text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define APB_CTRL_RET_ICACHE_ENABLE (BIT(31))
#define APB_CTRL_RET_ICACHE_ENABLE_M (BIT(31))
#define APB_CTRL_RET_ICACHE_ENABLE_V 0x1
#define APB_CTRL_RET_ICACHE_ENABLE_S 31
/* APB_CTRL_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
/*description: .*/
#define APB_CTRL_RET_ICACHE_START_POINT ... | 2,081 |
*/
#define APB_CTRL_RET_DCACHE_ENABLE (BIT(31))
#define APB_CTRL_RET_DCACHE_ENABLE_M (BIT(31))
#define APB_CTRL_RET_DCACHE_ENABLE_V 0x1
#define APB_CTRL_RET_DCACHE_ENABLE_S 31
/* APB_CTRL_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
/*description: .*/
#define APB_CTRL_RET_DCACHE_START_POINT ... | 2,081 |
*/
#define APB_CTRL_RETENTION_INV_CFG 0xFFFFFFFF
#define APB_CTRL_RETENTION_INV_CFG_M ((APB_CTRL_RETENTION_INV_CFG_V)<<(APB_CTRL_RETENTION_INV_CFG_S))
#define APB_CTRL_RETENTION_INV_CFG_V 0xFFFFFFFF
#define APB_CTRL_RETENTION_INV_CFG_S 0
#define APB_CTRL_RETENTION_CTRL5_REG (DR_REG_APB_CTRL_BASE + 0xC8)... | 2,081 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
Configuration Set ID: 1
*/
/* 3.1 Basic Config Parameters */
#define OTG_MODE 0
#define OTG_ARCHITECTURE 2
#define OTG_SINGLE_POINT 1
#define OTG_ENABLE_LPM 0
#define OTG_EN_DED_TX_FIFO 1
#define OTG_EN_DESC_DMA... | 2,082 |
6 Additional Configuration Options Parameters */
#define OTG_TRANS_COUNT_WIDTH 16
#define OTG_PACKET_COUNT_WIDTH 7
#define OTG_RM_OPT_FEATURES 1
#define OTG_EN_PWROPT 1
#define OTG_SYNC_RESET_TYPE 0
#define OTG_EN_IDDIG_FILTER 1
#define OTG_EN_VBUSVALID_FILTER 1
#def... | 2,082 |
10 UTMI-To-UTMI Bridge Component Parameters */
#define U2UB_EN 0
#ifdef __cplusplus
}
#endif
| 2,082 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,084 |
The data in dfifo will not lost..*/
#define USB_WRAP_DFIFO_FORCE_PU (BIT(22))
#define USB_WRAP_DFIFO_FORCE_PU_M (BIT(22))
#define USB_WRAP_DFIFO_FORCE_PU_V 0x1
#define USB_WRAP_DFIFO_FORCE_PU_S 22
/* USB_WRAP_PHY_TX_EDGE_SEL : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: Select phy tx signal output clock ... | 2,084 |
*/
#define USB_WRAP_USB_PAD_ENABLE (BIT(18))
#define USB_WRAP_USB_PAD_ENABLE_M (BIT(18))
#define USB_WRAP_USB_PAD_ENABLE_V 0x1
#define USB_WRAP_USB_PAD_ENABLE_S 18
/* USB_WRAP_PULLUP_VALUE : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: Controlle pullup value.*/
#define USB_WRAP_PULLUP_VALUE (BIT(17))
#d... | 2,084 |
*/
#define USB_WRAP_DP_PULLDOWN (BIT(14))
#define USB_WRAP_DP_PULLDOWN_M (BIT(14))
#define USB_WRAP_DP_PULLDOWN_V 0x1
#define USB_WRAP_DP_PULLDOWN_S 14
/* USB_WRAP_DP_PULLUP : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Controlle USB D+ pullup.*/
#define USB_WRAP_DP_PULLUP (BIT(13))
#define USB_WRAP_DP... | 2,084 |
8V to 1.04V, step 80mV.*/
#define USB_WRAP_VREFL 0x00000003
#define USB_WRAP_VREFL_M ((USB_WRAP_VREFL_V)<<(USB_WRAP_VREFL_S))
#define USB_WRAP_VREFL_V 0x3
#define USB_WRAP_VREFL_S 9
/* USB_WRAP_VREFH : R/W ;bitpos:[8:7] ;default: 2'b0 ; */
/*description: Control single-end input high threshold,1.76V to 2V, step 8... | 2,084 |
*/
#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4))
#define USB_WRAP_DBNCE_FLTR_BYPASS_M (BIT(4))
#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x1
#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4
/* USB_WRAP_DFIFO_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Force the dfifo to go into low power mode. The data in dfifo ... | 2,084 |
.*/
#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0))
#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (BIT(0))
#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x1
#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0
#define USB_WRAP_TEST_CONF_REG (DR_REG_USB_WRAP_BASE + 0x4)
/* USB_WRAP_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; *... | 2,084 |
*/
#define USB_WRAP_TEST_TX_DM (BIT(3))
#define USB_WRAP_TEST_TX_DM_M (BIT(3))
#define USB_WRAP_TEST_TX_DM_V 0x1
#define USB_WRAP_TEST_TX_DM_S 3
/* USB_WRAP_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: USB D+ tx value in test.*/
#define USB_WRAP_TEST_TX_DP (BIT(2))
#define USB_WRAP_TEST_TX_D... | 2,084 |
*/
#define USB_WRAP_DATE 0xFFFFFFFF
#define USB_WRAP_DATE_M ((USB_WRAP_DATE_V)<<(USB_WRAP_DATE_S))
#define USB_WRAP_DATE_V 0xFFFFFFFF
#define USB_WRAP_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_USB_WRAP_REG_H_ */
| 2,084 |
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 2,085 |
/*
*/
#pragma once
/**
#define I2C_DIG_REG 0x6D
#define I2C_DIG_REG_HOSTID 1
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
#define I2C_DIG_REG_ENX_RTC_DREG 4
#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
#define I2C_DIG_REG_ENX_RTC_DREG_LS... | 2,087 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,089 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,090 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,091 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,092 |
1: enable 0: disable. .*/
#define SPI_MEM_FLASH_READ (BIT(31))
#define SPI_MEM_FLASH_READ_M (BIT(31))
#define SPI_MEM_FLASH_READ_V 0x1
#define SPI_MEM_FLASH_READ_S 31
/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
/*description: Write flash enable. Write enable command will be sent when the bit... | 2,092 |
Read ID command will be sent when the bit is set. The bit will b
e cleared once the operation done. 1: enable 0: disable. .*/
#define SPI_MEM_FLASH_RDID (BIT(28))
#define SPI_MEM_FLASH_RDID_M (BIT(28))
#define SPI_MEM_FLASH_RDID_V 0x1
#define SPI_MEM_FLASH_RDID_S 28
/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;d... | 2,092 |
Page program operat
ion will be triggered when the bit is set. The bit will be cleared once the ope
ration done .1: enable 0: disable. .*/
#define SPI_MEM_FLASH_PP (BIT(25))
#define SPI_MEM_FLASH_PP_M (BIT(25))
#define SPI_MEM_FLASH_PP_V 0x1
#define SPI_MEM_FLASH_PP_S 25
/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24... | 2,092 |
Chip erase operation will be triggered when the bit is set. T
he bit will be cleared once the operation done.1: enable 0: disable. .*/
#define SPI_MEM_FLASH_CE (BIT(22))
#define SPI_MEM_FLASH_CE_M (BIT(22))
#define SPI_MEM_FLASH_CE_V 0x1
#define SPI_MEM_FLASH_CE_S 22
/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;de... | 2,092 |
The bit will be cleared once the operat
ion done.1: enable 0: disable. .*/
#define SPI_MEM_FLASH_HPM (BIT(19))
#define SPI_MEM_FLASH_HPM_M (BIT(19))
#define SPI_MEM_FLASH_HPM_V 0x1
#define SPI_MEM_FLASH_HPM_S 19
/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
/*description: User define command enable. ... | 2,092 |
other then the bit0-bit23 is the memory
address, the bit24-bit31 are the byte length of a transfer..*/
#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF
#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF
#define SPI_MEM_USR_ADDR_VALUE_S 0... | 2,092 |
1: enable 0: d
isable. .*/
#define SPI_MEM_WRSR_2B (BIT(22))
#define SPI_MEM_WRSR_2B_M (BIT(22))
#define SPI_MEM_WRSR_2B_V 0x1
#define SPI_MEM_WRSR_2B_S 22
/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. .*/
#de... | 2,092 |
*/
#define SPI_MEM_Q_POL (BIT(18))
#define SPI_MEM_Q_POL_M (BIT(18))
#define SPI_MEM_Q_POL_V 0x1
#define SPI_MEM_Q_POL_S 18
/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
/*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with
spi_mem_flash_res bit. 1: enable 0:... | 2,092 |
1: enable 0:disabl
e.*/
#define SPI_MEM_TX_CRC_EN (BIT(11))
#define SPI_MEM_TX_CRC_EN_M (BIT(11))
#define SPI_MEM_TX_CRC_EN_V 0x1
#define SPI_MEM_TX_CRC_EN_S 11
/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. A... | 2,092 |
.*/
#define SPI_MEM_FCMD_DUAL (BIT(7))
#define SPI_MEM_FCMD_DUAL_M (BIT(7))
#define SPI_MEM_FCMD_DUAL_V 0x1
#define SPI_MEM_FCMD_DUAL_S 7
/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase..*/
#define SPI_MEM_FADDR_OCT (BIT(6))
#defin... | 2,092 |
.*/
#define SPI_MEM_FDUMMY_OUT (BIT(3))
#define SPI_MEM_FDUMMY_OUT_M (BIT(3))
#define SPI_MEM_FDUMMY_OUT_V 0x1
#define SPI_MEM_FDUMMY_OUT_S 3
#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC)
/* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: SPI0 RX FIFO reset signal. Se... | 2,092 |
0: SPI Bus clock (SPI_CLK) is off when CS ina
ctive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delaye
d two cycles after SPI_CS inactive 3: SPI_CLK is always on..*/
#define SPI_MEM_CLK_MODE 0x00000003
#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
#define SPI_MEM_C... | 2,092 |
.*/
#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14))
#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14))
#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1
#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14
/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: 1: MSPI skips page corner when accesses flash. 0: N... | 2,092 |
These bits are combined with SPI_ME
M_CS_HOLD bit..*/
#define SPI_MEM_CS_HOLD_TIME 0x0000001F
#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
#define SPI_MEM_CS_HOLD_TIME_V 0x1F
#define SPI_MEM_CS_HOLD_TIME_S 5
/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
/... | 2,092 |
*/
#define SPI_MEM_CLKCNT_N 0x000000FF
#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
#define SPI_MEM_CLKCNT_N_V 0xFF
#define SPI_MEM_CLKCNT_N_S 16
/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
/*description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1)..*/
#defin... | 2,092 |
.*/
#define SPI_MEM_USR_ADDR (BIT(30))
#define SPI_MEM_USR_ADDR_M (BIT(30))
#define SPI_MEM_USR_ADDR_V 0x1
#define SPI_MEM_USR_ADDR_S 30
/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set this bit to enable enable the DUMMY phase of an operation..*/
#define SPI_MEM_USR_DUMMY (BIT(29... | 2,092 |
.*/
#define SPI_MEM_USR_DUMMY_IDLE (BIT(26))
#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26))
#define SPI_MEM_USR_DUMMY_IDLE_V 0x1
#define SPI_MEM_USR_DUMMY_IDLE_S 26
/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_M... | 2,092 |
.*/
#define SPI_MEM_FWRITE_QIO (BIT(15))
#define SPI_MEM_FWRITE_QIO_M (BIT(15))
#define SPI_MEM_FWRITE_QIO_V 0x1
#define SPI_MEM_FWRITE_QIO_S 15
/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation..*/
#define SPI_ME... | 2,092 |
.*/
#define SPI_MEM_CK_OUT_EDGE (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_M (BIT(9))
#define SPI_MEM_CK_OUT_EDGE_V 0x1
#define SPI_MEM_CK_OUT_EDGE_S 9
/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
#define SPI_MEM_CS_SETUP (BI... | 2,092 |
.*/
#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F
#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F
#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0
#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)
/* SPI_MEM_US... | 2,092 |
The register value shall be (bit_num-1)..*/
#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF
#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF
#define SPI_MEM_USR_MOSI_DBITLEN_S 0
#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI... | 2,092 |
.*/
#define SPI_MEM_STATUS 0x0000FFFF
#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
#define SPI_MEM_STATUS_V 0xFFFF
#define SPI_MEM_STATUS_S 0
#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x30)
/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: The... | 2,092 |
.*/
#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10))
#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10))
#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1
#define SPI_MEM_CS_KEEP_ACTIVE_S 10
/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI ... | 2,092 |
.*/
#define SPI_MEM_CS1_DIS (BIT(1))
#define SPI_MEM_CS1_DIS_M (BIT(1))
#define SPI_MEM_CS1_DIS_V 0x1
#define SPI_MEM_CS1_DIS_S 1
/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) co
nnected to SPI_CS is in low lev... | 2,092 |
.*/
#define SPI_MEM_FADDR_QUAD (BIT(8))
#define SPI_MEM_FADDR_QUAD_M (BIT(8))
#define SPI_MEM_FADDR_QUAD_V 0x1
#define SPI_MEM_FADDR_QUAD_S 8
/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phas
e..*/
#define SP... | 2,092 |
.*/
#define SPI_MEM_FDOUT_DUAL (BIT(4))
#define SPI_MEM_FDOUT_DUAL_M (BIT(4))
#define SPI_MEM_FDOUT_DUAL_V 0x1
#define SPI_MEM_FDOUT_DUAL_S 4
/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase
..*/
#define SPI_... | 2,092 |
The value of SPI_MEM_
USR_ADDR_BITLEN should be 31..*/
#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1))
#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1))
#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1
#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1
/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set thi... | 2,092 |
.*/
#define SPI_MEM_SRAM_OCT (BIT(21))
#define SPI_MEM_SRAM_OCT_M (BIT(21))
#define SPI_MEM_SRAM_OCT_V 0x1
#define SPI_MEM_SRAM_OCT_S 21
/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
/*description: 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALU
E. 0: The v... | 2,092 |
.*/
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6
/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
... | 2,092 |
.*/
#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3))
#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3))
#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1
#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3
/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer..*/
#de... | 2,092 |
.*/
#define SPI_MEM_SDUMMY_OUT (BIT(22))
#define SPI_MEM_SDUMMY_OUT_M (BIT(22))
#define SPI_MEM_SDUMMY_OUT_V 0x1
#define SPI_MEM_SDUMMY_OUT_S 22
/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase..*/
#define SPI_MEM_SCM... | 2,092 |
.*/
#define SPI_MEM_SDIN_OCT (BIT(18))
#define SPI_MEM_SDIN_OCT_M (BIT(18))
#define SPI_MEM_SDIN_OCT_V 0x1
#define SPI_MEM_SDIN_OCT_S 18
/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase..*/
#define SPI_MEM_SCMD_QUAD ... | 2,092 |
.*/
#define SPI_MEM_SDIN_QUAD (BIT(14))
#define SPI_MEM_SDIN_QUAD_M (BIT(14))
#define SPI_MEM_SDIN_QUAD_V 0x1
#define SPI_MEM_SDIN_QUAD_S 14
/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase..*/
#define SPI_MEM_SCMD_D... | 2,092 |
.*/
#define SPI_MEM_SDIN_DUAL (BIT(10))
#define SPI_MEM_SDIN_DUAL_M (BIT(10))
#define SPI_MEM_SDIN_DUAL_V 0x1
#define SPI_MEM_SDIN_DUAL_S 10
/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
/*description: Mode bits when SPI0 accesses to Ext_RAM..*/
#define SPI_MEM_SWB_MODE 0x000000FF
#define SPI_MEM... | 2,092 |
The register val
ue shall be (bit_num-1)..*/
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF
#define SPI_MEM_CACHE_SRAM_USR... | 2,092 |
The register va
lue shall be (bit_num-1)..*/
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF
#define SPI_MEM_CACHE_SRAM_USR... | 2,092 |
.*/
#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31))
#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31))
#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1
#define SPI_MEM_SCLK_EQU_SYSCLK_S 31
/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
/*description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCL... | 2,092 |
0: idle state(IDLE), 1: preparation state(PREP
), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DI
N), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)..*/
#define SPI_MEM_ST 0x00000007
#define SPI_MEM_ST_M ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S))
#define SPI_MEM_ST_V 0x7
#... | 2,092 |
*/
#define SPI_MEM_BUF2 0xFFFFFFFF
#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
#define SPI_MEM_BUF2_V 0xFFFFFFFF
#define SPI_MEM_BUF2_S 0
#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64)
/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer.*/
#def... | 2,092 |
*/
#define SPI_MEM_BUF6 0xFFFFFFFF
#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
#define SPI_MEM_BUF6_V 0xFFFFFFFF
#define SPI_MEM_BUF6_S 0
#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74)
/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer.*/
#def... | 2,092 |
*/
#define SPI_MEM_BUF10 0xFFFFFFFF
#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
#define SPI_MEM_BUF10_V 0xFFFFFFFF
#define SPI_MEM_BUF10_S 0
#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84)
/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer... | 2,092 |
*/
#define SPI_MEM_BUF14 0xFFFFFFFF
#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
#define SPI_MEM_BUF14_V 0xFFFFFFFF
#define SPI_MEM_BUF14_S 0
#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94)
/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: data buffer... | 2,092 |
.*/
#define SPI_MEM_WAITI_CMD 0x000000FF
#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
#define SPI_MEM_WAITI_CMD_V 0xFF
#define SPI_MEM_WAITI_CMD_S 2
/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to enable DUMMY phase in auto wait flash idle ... | 2,092 |
0: Not separate..*/
#define SPI_MEM_PESR_IDLE_EN (BIT(5))
#define SPI_MEM_PESR_IDLE_EN_M (BIT(5))
#define SPI_MEM_PESR_IDLE_EN_V 0x1
#define SPI_MEM_PESR_IDLE_EN_S 5
/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to enable PES transfer trigger PES transfer option..*/
#def... | 2,092 |
The bit will be cleared once the operation done.1: enable 0: d
isable. .*/
#define SPI_MEM_FLASH_PES (BIT(1))
#define SPI_MEM_FLASH_PES_M (BIT(1))
#define SPI_MEM_FLASH_PES_V 0x1
#define SPI_MEM_FLASH_PES_S 1
/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */
/*description: program erase resume bit... | 2,092 |
.*/
#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF
#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF
#define SPI_MEM_FLASH_PER_COMMAND_S 1
/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this b... | 2,092 |
1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
#define SPI_MEM_FLASH_PER_DLY_256 (BIT(5))
#define SPI_MEM_FLASH_PER_DLY_256_M (BIT(5))
#define SPI_MEM_FLASH_PER_DLY_256_... | 2,092 |
.*/
#define SPI_MEM_FLASH_RES_DLY_256 (BIT(3))
#define SPI_MEM_FLASH_RES_DLY_256_M (BIT(3))
#define SPI_MEM_FLASH_RES_DLY_256_V 0x1
#define SPI_MEM_FLASH_RES_DLY_256_S 3
/* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK c... | 2,092 |
Active when S
PI_MEM_TIMING_CALI bit is set..*/
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7
#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2
/* SPI_MEM_TIMING_CALI : ... | 2,092 |
0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles
at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK
positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
EM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negat
ive edge. 4: Delay for... | 2,092 |
3: Delay for (SPI
_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
cles at HCLK negative edge and one cycle at MSPI_CORE_CLK ... | 2,092 |
5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_DIN6_MODE 0x00000007
#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
#define SPI_MEM_DIN6_MODE_V 0x7
#define SPI_MEM_DIN6_MODE_S 18
/* SPI_MEM_DIN5_MODE : R... | 2,092 |
0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
gative edge. 4: Delay... | 2,092 |
3: Delay for (SPI_
MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg
ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
les at HCLK negative edge and one cycle at MSPI_CORE_CLK n... | 2,092 |
5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_DIN2_MODE 0x00000007
#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
#define SPI_MEM_DIN2_MODE_V 0x7
#define SPI_MEM_DIN2_MODE_S 6
/* SPI_MEM_DIN1_MODE : R/... | 2,092 |
0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a
t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK
positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega
tive edge. 4: Delay... | 2,092 |
.*/
#define SPI_MEM_DIN7_NUM 0x00000003
#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
#define SPI_MEM_DIN7_NUM_V 0x3
#define SPI_MEM_DIN7_NUM_S 14
/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: SPI_IO6 input delay number..*/
#define SPI_MEM_DIN6_NUM 0x000... | 2,092 |
.*/
#define SPI_MEM_DIN3_NUM 0x00000003
#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
#define SPI_MEM_DIN3_NUM_V 0x3
#define SPI_MEM_DIN3_NUM_S 6
/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: SPI_WP input delay number..*/
#define SPI_MEM_DIN2_NUM 0x0000000... | 2,092 |
0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
tive edge..*/
#define SPI_MEM_DOUTS_MODE (BIT(8))
#define SPI_MEM_DOUTS_MODE_M (BIT(8))
#define SPI_MEM_DOUTS_MODE_V 0x1
#define SPI_MEM_DOUTS_MODE_S 8
/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
/*description: SPI_IO7 output delay mode. 0: No... | 2,092 |
.*/
#define SPI_MEM_DOUT5_MODE (BIT(5))
#define SPI_MEM_DOUT5_MODE_M (BIT(5))
#define SPI_MEM_DOUT5_MODE_V 0x1
#define SPI_MEM_DOUT5_MODE_S 5
/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
/*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
tive edge..*/
#d... | 2,092 |
0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
ve edge..*/
#define SPI_MEM_DOUT1_MODE (BIT(1))
#define SPI_MEM_DOUT1_MODE_M (BIT(1))
#define SPI_MEM_DOUT1_MODE_V 0x1
#define SPI_MEM_DOUT1_MODE_S 1
/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: SPI_D output delay mode. 0: No d... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1))
#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1))
#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1
#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1
/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to power on HCLK. When PLL is p... | 2,092 |
3: Delay for (SPI
_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
gative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and
one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cy
cles at HCLK negative edge and one cycle at MSPI_CORE_CLK ... | 2,092 |
5: Delay for (SPI_SMEM_DIN$n_NUM+
1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007
#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S))
#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7
#define SP... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007
#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S))
#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7
#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18
/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
/*descrip... | 2,092 |
0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
negative edge. 4: Del... | 2,092 |
3: Delay for (SP
I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK... | 2,092 |
5: Delay for (SPI_SMEM_DIN$n_NUM+1
) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007
#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S))
#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7
#define SP... | 2,092 |
0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
egative edge. 4: Del... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S))
#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14
/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: S... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S))
#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8
/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
/*description: SPI_... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003
#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S))
#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3
#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2
/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: SPI_... | 2,092 |
0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
tive edge..*/
#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7))
#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7))
#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1
#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7
/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
/*... | 2,092 |
0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
tive edge..*/
#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4))
#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4))
#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1
#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4
/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
/*... | 2,092 |
0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
ve edge..*/
#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1))
#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1))
#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1
#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1
/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*... | 2,092 |
.*/
#define SPI_MEM_ECC_ERR_INT_NUM 0x000000FF
#define SPI_MEM_ECC_ERR_INT_NUM_M ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S))
#define SPI_MEM_ECC_ERR_INT_NUM_V 0xFF
#define SPI_MEM_ECC_ERR_INT_NUM_S 0
#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD0)
/* SPI_MEM_ECC_ERR_ADDR ... | 2,092 |
It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/
#define SPI_MEM_ECC_ERR_CNT 0x000000FF
#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
#define SPI_MEM_ECC_ERR_CNT_V 0xFF
#define SPI_MEM_ECC_ERR_CNT_S 17
/* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0... | 2,092 |
The value ranges from
0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_ME
M_ECC_ERR_INT_CLR bit..*/
#define SPI_MEM_ECC_DATA_ERR_BIT 0x0000007F
#define SPI_MEM_ECC_DATA_ERR_BIT_M ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S))
#define SPI_MEM_ECC_DATA_ERR_BIT_V 0x7F
#defi... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN (BIT(24))
#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M (BIT(24))
#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V 0x1
#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S 24
/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: Set this bit to enable M... | 2,092 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.