text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
.*/
#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007
#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S))
#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7
#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12
/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F
#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S))
#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F
#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2
/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1... | 2,092 |
.*/
#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30))
#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30))
#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1
#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30
/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set this bit to enable octa_ram address o... | 2,092 |
.*/
#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27))
#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27))
#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1
#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27
/* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: Set this bit to enabl... | 2,092 |
.*/
#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24))
#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24))
#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1
#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24
/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FM... | 2,092 |
.*/
#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F
#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S))
#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F
#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14
/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bit... | 2,092 |
.*/
#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F
#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S))
#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F
#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5
/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;defaul... | 2,092 |
.*/
#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2))
#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2))
#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1
#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2
/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set the bit to enable variable dummy cycle in... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30))
#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30))
#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1
#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30
/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: Set this bit to enable octa_ram address o... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27))
#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27))
#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1
#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27
/* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: Set this bit to enabl... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24))
#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24))
#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1
#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24
/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SM... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F
#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S))
#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F
#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14
/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bit... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S))
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F
#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5
/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;defaul... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2))
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2))
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1
#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2
/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set the bit to enable variable dummy cycle in... | 2,092 |
1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_
CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the freq
uency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_C
LK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. .*/
#define ... | 2,092 |
.*/
#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(3))
#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(3))
#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1
#define SPI_MEM_BROWN_OUT_INT_ENA_S 3
/* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt... | 2,092 |
SPI_MEM_ECC_ERR_ADDR and SPI_ME
M_ECC_ERR_CNT will be cleared by the pulse of this bit..*/
#define SPI_MEM_ECC_ERR_INT_CLR (BIT(4))
#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(4))
#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1
#define SPI_MEM_ECC_ERR_INT_CLR_S 4
/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; *... | 2,092 |
.*/
#define SPI_MEM_PES_END_INT_CLR (BIT(1))
#define SPI_MEM_PES_END_INT_CLR_M (BIT(1))
#define SPI_MEM_PES_END_INT_CLR_V 0x1
#define SPI_MEM_PES_END_INT_CLR_S 1
/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
#define SPI_MEM_PER_E... | 2,092 |
When APB_CTRL_FECC_ERR_INT_EN
and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total erro
r times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_C
TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN
are cleared, this bit will not be triggered..... | 2,092 |
1: Triggered when SPI1 tr
ansfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/
PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Other
s..*/
#define SPI_MEM_TOTAL_TRANS_END_INT_RAW (BIT(2))
#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M (BIT(2))
#define SPI_MEM_TOTAL... | 2,092 |
0: Others..*/
#define SPI_MEM_PER_END_INT_RAW (BIT(0))
#define SPI_MEM_PER_END_INT_RAW_M (BIT(0))
#define SPI_MEM_PER_END_INT_RAW_V 0x1
#define SPI_MEM_PER_END_INT_RAW_S 0
#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xFC)
/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*descrip... | 2,092 |
.*/
#define SPI_MEM_PES_END_INT_ST (BIT(1))
#define SPI_MEM_PES_END_INT_ST_M (BIT(1))
#define SPI_MEM_PES_END_INT_ST_V 0x1
#define SPI_MEM_PES_END_INT_ST_S 1
/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
#define SPI_MEM_PER_END_I... | 2,092 |
0: The
driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK
PAD..*/
#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN (BIT(4))
#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M (BIT(4))
#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V 0x1
#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S 4
/* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV... | 2,092 |
.*/
#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV 0x00000003
#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S))
#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V 0x3
#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_M... | 2,092 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,093 |
*/
#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1))
#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1))
#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V 0x1
#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S 1
/* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_CONTROL_COR... | 2,093 |
*/
#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7))
#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7))
#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1
#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7
/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6))... | 2,093 |
*/
#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F
#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF
#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4
/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*descriptio... | 2,093 |
*/
#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0))
#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0))
#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1
#define SYSTEM_LSLP_MEM_PD_MASK_S 0
#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18)
/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
/*description: .*/
#d... | 2,093 |
*/
#define SYSTEM_APB_SARADC_CLK_EN (BIT(28))
#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28))
#define SYSTEM_APB_SARADC_CLK_EN_V 0x1
#define SYSTEM_APB_SARADC_CLK_EN_S 28
/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27))
#define SYSTEM_SPI... | 2,093 |
*/
#define SYSTEM_USB_CLK_EN (BIT(23))
#define SYSTEM_USB_CLK_EN_M (BIT(23))
#define SYSTEM_USB_CLK_EN_V 0x1
#define SYSTEM_USB_CLK_EN_S 23
/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22))
#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22))
#d... | 2,093 |
*/
#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18))
#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18))
#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1
#define SYSTEM_I2C_EXT1_CLK_EN_S 18
/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_PWM0_CLK_EN (BIT(17))
#define SYSTEM_PWM0_CLK_EN_M (BIT... | 2,093 |
*/
#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13))
#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13))
#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1
#define SYSTEM_TIMERGROUP_CLK_EN_S 13
/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_UHCI1_CLK_EN (BIT(12))
#define SYSTEM_UHCI1_CLK... | 2,093 |
*/
#define SYSTEM_UHCI0_CLK_EN (BIT(8))
#define SYSTEM_UHCI0_CLK_EN_M (BIT(8))
#define SYSTEM_UHCI0_CLK_EN_V 0x1
#define SYSTEM_UHCI0_CLK_EN_S 8
/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7))
#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7))
... | 2,093 |
*/
#define SYSTEM_WDG_CLK_EN (BIT(3))
#define SYSTEM_WDG_CLK_EN_M (BIT(3))
#define SYSTEM_WDG_CLK_EN_V 0x1
#define SYSTEM_WDG_CLK_EN_S 3
/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_UART_CLK_EN (BIT(2))
#define SYSTEM_UART_CLK_EN_M (BIT(2))
#define SYSTEM_UART_... | 2,093 |
*/
#define SYSTEM_UART2_CLK_EN (BIT(9))
#define SYSTEM_UART2_CLK_EN_M (BIT(9))
#define SYSTEM_UART2_CLK_EN_V 0x1
#define SYSTEM_UART2_CLK_EN_S 9
/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_LCD_CAM_CLK_EN (BIT(8))
#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8))
#de... | 2,093 |
*/
#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4))
#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4))
#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_DS_CLK_EN_S 4
/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3))
#define SYSTEM_CRYPTO_R... | 2,093 |
*/
#define SYSTEM_PERI_BACKUP_CLK_EN (BIT(0))
#define SYSTEM_PERI_BACKUP_CLK_EN_M (BIT(0))
#define SYSTEM_PERI_BACKUP_CLK_EN_V 0x1
#define SYSTEM_PERI_BACKUP_CLK_EN_S 0
#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20)
/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: .... | 2,093 |
*/
#define SYSTEM_APB_SARADC_RST (BIT(28))
#define SYSTEM_APB_SARADC_RST_M (BIT(28))
#define SYSTEM_APB_SARADC_RST_V 0x1
#define SYSTEM_APB_SARADC_RST_S 28
/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_SPI3_DMA_RST (BIT(27))
#define SYSTEM_SPI3_DMA_RST_M (BIT(... | 2,093 |
*/
#define SYSTEM_USB_RST (BIT(23))
#define SYSTEM_USB_RST_M (BIT(23))
#define SYSTEM_USB_RST_V 0x1
#define SYSTEM_USB_RST_S 23
/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_SPI2_DMA_RST (BIT(22))
#define SYSTEM_SPI2_DMA_RST_M (BIT(22))
#define SYSTEM_SPI2_DMA... | 2,093 |
*/
#define SYSTEM_I2C_EXT1_RST (BIT(18))
#define SYSTEM_I2C_EXT1_RST_M (BIT(18))
#define SYSTEM_I2C_EXT1_RST_V 0x1
#define SYSTEM_I2C_EXT1_RST_S 18
/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_PWM0_RST (BIT(17))
#define SYSTEM_PWM0_RST_M (BIT(17))
#define SYSTEM_... | 2,093 |
*/
#define SYSTEM_TIMERGROUP_RST (BIT(13))
#define SYSTEM_TIMERGROUP_RST_M (BIT(13))
#define SYSTEM_TIMERGROUP_RST_V 0x1
#define SYSTEM_TIMERGROUP_RST_S 13
/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_UHCI1_RST (BIT(12))
#define SYSTEM_UHCI1_RST_M (BIT(12))
#def... | 2,093 |
*/
#define SYSTEM_UHCI0_RST (BIT(8))
#define SYSTEM_UHCI0_RST_M (BIT(8))
#define SYSTEM_UHCI0_RST_V 0x1
#define SYSTEM_UHCI0_RST_S 8
/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_I2C_EXT0_RST (BIT(7))
#define SYSTEM_I2C_EXT0_RST_M (BIT(7))
#define SYSTEM_I2C_EX... | 2,093 |
*/
#define SYSTEM_WDG_RST (BIT(3))
#define SYSTEM_WDG_RST_M (BIT(3))
#define SYSTEM_WDG_RST_V 0x1
#define SYSTEM_WDG_RST_S 3
/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_UART_RST (BIT(2))
#define SYSTEM_UART_RST_M (BIT(2))
#define SYSTEM_UART_RST_V 0x1
#define SY... | 2,093 |
*/
#define SYSTEM_UART2_RST (BIT(9))
#define SYSTEM_UART2_RST_M (BIT(9))
#define SYSTEM_UART2_RST_V 0x1
#define SYSTEM_UART2_RST_S 9
/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_LCD_CAM_RST (BIT(8))
#define SYSTEM_LCD_CAM_RST_M (BIT(8))
#define SYSTEM_LCD_CAM_R... | 2,093 |
*/
#define SYSTEM_CRYPTO_DS_RST (BIT(4))
#define SYSTEM_CRYPTO_DS_RST_M (BIT(4))
#define SYSTEM_CRYPTO_DS_RST_V 0x1
#define SYSTEM_CRYPTO_DS_RST_S 4
/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_CRYPTO_RSA_RST (BIT(3))
#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3))... | 2,093 |
*/
#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF
#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_NUM_S 0
#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x2C)
/* SYSTEM_LPCLK_RTC_EN : R/W ;b... | 2,093 |
*/
#define SYSTEM_LPCLK_SEL_8M (BIT(25))
#define SYSTEM_LPCLK_SEL_8M_M (BIT(25))
#define SYSTEM_LPCLK_SEL_8M_V 0x1
#define SYSTEM_LPCLK_SEL_8M_S 25
/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24))
#define SYSTEM_LPCLK_SEL_RTC_SLO... | 2,093 |
*/
#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x34)
/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ;... | 2,093 |
*/
#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0))
#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0
#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x40)
/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*descr... | 2,093 |
*/
#define SYSTEM_EDMA_RESET (BIT(1))
#define SYSTEM_EDMA_RESET_M (BIT(1))
#define SYSTEM_EDMA_RESET_V 0x1
#define SYSTEM_EDMA_RESET_S 1
/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: .*/
#define SYSTEM_EDMA_CLK_ON (BIT(0))
#define SYSTEM_EDMA_CLK_ON_M (BIT(0))
#define SYSTEM_EDMA_... | 2,093 |
*/
#define SYSTEM_ICACHE_CLK_ON (BIT(0))
#define SYSTEM_ICACHE_CLK_ON_M (BIT(0))
#define SYSTEM_ICACHE_CLK_ON_V 0x1
#define SYSTEM_ICACHE_CLK_ON_S 0
#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x4C)
/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default:... | 2,093 |
*/
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0))
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x50)
/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos... | 2,093 |
*/
#define SYSTEM_RTC_MEM_CRC_START (BIT(8))
#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8))
#define SYSTEM_RTC_MEM_CRC_START_V 0x1
#define SYSTEM_RTC_MEM_CRC_START_S 8
#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x54)
/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*descrip... | 2,093 |
*/
#define SYSTEM_CLK_EN (BIT(0))
#define SYSTEM_CLK_EN_M (BIT(0))
#define SYSTEM_CLK_EN_V 0x1
#define SYSTEM_CLK_EN_S 0
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x60)
/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
/*description: .*/
#define SYSTEM_CLK_DIV_EN (BIT(19))
#define... | 2,093 |
*/
#define SYSTEM_PRE_DIV_CNT 0x000003FF
#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
#define SYSTEM_PRE_DIV_CNT_V 0x3FF
#define SYSTEM_PRE_DIV_CNT_S 0
#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x64)
/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
/... | 2,093 |
*/
#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4))
#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4))
#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1
#define SYSTEM_MEM_ERR_CNT_CLR_S 4
/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
/*description: .*/
#define SYSTEM_MEM_PATH_LEN 0x0000000F
#define SYSTEM_MEM_PATH_LEN_M ((... | 2,093 |
*/
#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F
#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F
#define SYSTEM_COMB_PATH_LEN_LVT_S 0
#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x6C)
/* SYSTEM_COMB_PVT_... | 2,093 |
*/
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6
/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define SYSTEM_COMB_ERR_CNT_CLR_HVT ... | 2,093 |
*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0
#define SYSTEM_COMB... | 2,093 |
*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0
#define SYSTEM_COMB... | 2,093 |
*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0
#define SYSTEM_COMB... | 2,093 |
*/
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0
#define SYSTEM_COMB... | 2,093 |
/*
*/
#pragma once
#define ADC1_GPIO1_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 4
#define ADC1_GPIO5_CHA... | 2,094 |
/*
*/
// The long term plan is to have a single soc_caps.h for all peripherals.
// During the refactoring and multichip support development process, we
// separate these information into periph_caps.h for each peripheral and
// include them here to avoid developing conflicts.
/*
*/
#pragma once
/* COMMON CAPS */
... | 2,096 |
> 3)
#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/* I/D Cache tag memory retention hardware parameters */
#define SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WI... | 2,096 |
5
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/* TIMER GROUP CAPS */
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_G... | 2,096 |
< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART... | 2,096 |
<Compatible to the old version of IDF */
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_TAGMEM_PD (1)... | 2,096 |
< Support to connect an external low frequency crystal */
/* eFuse CAPS*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
#define SOC_EFUSE_HARD_DIS_JTAG 1
#define SOC_EFUSE_DIS_USB_JTAG 1
#define SOC_EFUSE_SOFT_DIS_JTAG 1
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
#define SOC_EFUSE_DIS_ICACHE... | 2,096 |
< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (1) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/* SDMMC CAPS */
/* Card detect, write protect, interrupt use GPIO Matrix on all chips.
*/
#define SOC_SDMMC_USE_GPIO_MATRIX 1
#define SOC_SDMMC_NUM_SLOTS 2
/* Indicat... | 2,096 |
< Support CSI */
#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
#define SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW (1) /*!< Support delta early time for rf phy on/off */
#define SOC_WIFI_PHY_NEEDS_USB_WORKAROUND (1) /*!< SoC has WiFi and USB PHYs interference, needs a workaround */
... | 2,096 |
0: external XTAL_32K*/
uint32_t reserved24 : 6;
uint32_t ctr_lv : 1; /*0: power down XTAL at high level*/
uint32_t ctr_en : 1;
};
uint32_t val;
} ext_xtl_conf;
union {
struct {... | 2,097 |
Clear vld before set reg_ck8m_div_sel*/
uint32_t ck8m_div : 2; /*CK8M_D256_OUT divider. 00: div128*/
uint32_t enb_ck8m : 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div : 1; /*1: CK8M_D256_OUT is actu... | 2,097 |
0: XTAL div 2*/
uint32_t ana_clk_rtc_sel : 2;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reserved0 : 22;
uint32_t rtc_ana_clk_div_vld : 1; /*used to sync div bus. clear vld before set r... | 2,097 |
0: no res*/
uint32_t sdio_en_initi : 1; /*0 to set init[1:0]=0*/
uint32_t sdio_dcurlim : 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
uint32_t sdio_modecurlim : 1; /*select current limit mode*/
... | 2,097 |
Only active when reg_sdio_force = 1*/
uint32_t drefh_sdio : 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
uint32_t xpd_sdio : 1;
};
uint32_t val;
} sdio_conf;
union {
struct {
uint3... | 2,097 |
8v or lower )*/
uint32_t rtculator_force_pu : 1;
};
uint32_t val;
} rtc;
union {
struct {
uint32_t rtc_fastmem_force_noiso : 1; /*Fast RTC memory force no ISO*/
uint32_t rtc_fastmem_force_iso : 1; /*Fast RTC memory f... | 2,097 |
Switch rtc main state*/
uint32_t rtc_touch_state_slp : 1; /*touch is in sleep state*/
uint32_t rtc_touch_state_done : 1; /*touch is done*/
uint32_t rtc_cocpu_state_start : 1; /*ulp/cocpu should start to work*/
uint32_t rtc_cocpu_sta... | 2,097 |
*/
uint32_t cocpu_sw_int_trigger : 1; /*trigger cocpu register interrupt*/
uint32_t cocpu_clkgate_en : 1;
uint32_t reserved28 : 4;
};
uint32_t val;
} cocpu_ctrl;
union {
struct {
uint32_t ... | 2,097 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,099 |
The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: ... | 2,099 |
Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the op... | 2,099 |
1: enable 0: disable. */
uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdid : 1; /*Read JEDEC I... | 2,099 |
The bit will be cleared once the operation done. 1: enable 0: disable. */
};
uint32_t val;
} cmd;
uint32_t addr;
union {
struct {
uint32_t reserved0 : 3; /*reserved*/
uint32_t fdummy_out : 1; /*In the DUMMY phase... | 2,099 |
*/
uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t... | 2,099 |
1: enable 0: disable. */
uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */
uint32_t wrsr_2b : 1; /*Two bytes data will be written to status register when it is set. 1: enable 0: disable. *... | 2,099 |
*/
uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.*/
uint32_t reserved2 : 18; /*reserved*/
uint32_t rxfifo_rst : 1; ... | 2,099 |
*/
uint32_t ecc_skip_page_corner : 1; /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
... | 2,099 |
*/
uint32_t clkcnt_n : 8; /*When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t clk_equ_sysclk : 1; /*When SPI0 accesses flash, set this bit in 1... | 2,099 |
*/
uint32_t fwrite_quad : 1; /*Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.*/
uint32_t fwrite_dio : 1; /*Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.*/
uint32_t fwrite_qio ... | 2,099 |
*/
uint32_t usr_miso : 1; /*Set this bit to enable enable the DIN phase of a read-data operation.*/
uint32_t usr_dummy : 1; /*Set this bit to enable enable the DUMMY phase of an operation.*/
uint32_t usr_addr : ... | 2,099 |
*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_command_bitlen : 4; /*The length in bits of CMD phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_b... | 2,099 |
*/
uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit.*/
uint32_t reserved24 : 8; /*reserved*/
};
uint32_t val;
} rd_status;
uint32_t ext_addr;
union {
str... | 2,099 |
*/
uint32_t ck_idle_edge : 1; /*1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle */
uint32_t cs_keep_active : 1; /*SPI_CS line keep low when the bit is set.*/
uint32_t auto_per : 1; /*Set this bit to ... | 2,099 |
0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.*/
uint32_t fdin_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.*/
uint32_t fdout_du... | 2,099 |
The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.*/
uint32_t usr_sram_dio : 1; /*Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.*/
uint32_t usr_sram_qio : 1; /*Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.*/
... | 2,099 |
The register value shall be (bit_num-1).*/
uint32_t usr_wcmd : 1; /*1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.*/
uint32_t sram_oct : 1; /*Set the bit to enable OPI mode in all SPI0 Ext... | 2,099 |
*/
uint32_t sdin_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.*/
uint32_t sdout_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.*/
uint32_t saddr_dual ... | 2,099 |
*/
uint32_t sdin_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.*/
uint32_t sdout_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.*/
uint32_t saddr_oct ... | 2,099 |
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