text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_rd_cmd_bitlen : 4; /*When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_drd_cmd;
union {
s... | 2,099 |
*/
uint32_t cnt_n : 8; /*When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t equ_sysclk : 1; /*When SPI0 accesses to Ext_RAM, set th... | 2,099 |
*/
uint32_t waiti_dummy : 1; /*Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).*/
uint32_t waiti_cmd : 8; /*The command value of auto wait flash idle transfer(RDSR).*/
uint32_t waiti_dummy_cyclelen : ... | 2,099 |
*/
uint32_t flash_per_wait_en : 1; /*Set this bit to add delay time after program erase resume(PER) is sent.*/
uint32_t flash_pes_wait_en : 1; /*Set this bit to add delay time after program erase suspend(PES) command is sent.*/
uint32_t pes_per_en ... | 2,099 |
*/
uint32_t reserved17 : 15; /*reserved*/
};
uint32_t val;
} flash_sus_ctrl;
union {
struct {
uint32_t flash_sus : 1; /*The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is se... | 2,099 |
0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
uint32_t flash_per_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS... | 2,099 |
Otherwise, the frequency equals to that of XTAL.*/
uint32_t timing_cali : 1; /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
uint32_t extra_dummy_cyclelen : 3; /*Extra SPI_CLK cycles added in DUMMY phase for timing compe... | 2,099 |
5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1)... | 2,099 |
3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK nega... | 2,099 |
0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for... | 2,099 |
5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+... | 2,099 |
3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK nega... | 2,099 |
*/
uint32_t din1_num : 2; /*SPI_Q input delay number.*/
uint32_t din2_num : 2; /*SPI_WP input delay number.*/
uint32_t din3_num : 2; /*SPI_HD input delay number.*/
uint32_t din4_num ... | 2,099 |
*/
uint32_t dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
... | 2,099 |
0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint3... | 2,099 |
0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay ... | 2,099 |
5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NU... | 2,099 |
3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK n... | 2,099 |
0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay ... | 2,099 |
5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_N... | 2,099 |
3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK nega... | 2,099 |
*/
uint32_t smem_din6_num : 2; /*SPI_IO6 input delay number.*/
uint32_t smem_din7_num : 2; /*SPI_IO7 input delay number.*/
uint32_t smem_dins_num : 2; /*SPI_DQS input delay number.*/
uint32_t reserved18 ... | 2,099 |
*/
uint32_t smem_dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
... | 2,099 |
*/
uint32_t fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} ecc_ctrl;
uint32_t ecc_err_addr;
union {
... | 2,099 |
It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
uint32_t ecc_err_cnt : 8; /*This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */
uint32_t reserved25 :... | 2,099 |
These bits are combined with SPI_MEM_CS_HOLD bit.*/
uint32_t smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.*/
uint32_t smem_ecc_skip_page_corner : 1; /*1: MSPI skips page co... | 2,099 |
*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} spi_smem_ac;
union {
struct {
uint32_t fmem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/
uint32_t fmem_var_dummy : 1; /*Set th... | 2,099 |
*/
uint32_t fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.*/
uint32_t fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/
uint32_t f... | 2,099 |
*/
uint32_t fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 acce... | 2,099 |
*/
uint32_t smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t smem_ddr_cmd_dis : 1; /*the bit... | 2,099 |
0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
uint32_t smem_ddr_dqs_loop_mode : 1; /*When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this... | 2,099 |
.*/
uint32_t smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
uint32_t smem_hyperbus_ca : 1; /*Set this bit to enab... | 2,099 |
1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. */
... | 2,099 |
*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t per_end_int_clr : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_int_clr : ... | 2,099 |
1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
uint32_t pes_end_int_raw : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
... | 2,099 |
When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times... | 2,099 |
*/
uint32_t total_trans_end_int_st : 1; /*The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
uint32_t brown_out_int_st : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t ecc_err_int_st : 1; /*The status bit fo... | 2,099 |
*/
uint32_t fmem_spiclk_fun_drv : 2; /*The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash.*/
uint32_t reg_spiclk_pad_drv_ctl_en : 1; /*SPI_CLK PAD driver control signal. ... | 2,099 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
// ESP32S3 does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32... | 2,100 |
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,101 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,102 |
*/
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_SARADC_XPD_SAR_FORCE_S 27
/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input d... | 2,102 |
*/
#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24
/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG A... | 2,102 |
*/
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_SARADC_SAR_CLK_DIV_S 7
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: .*/
#define APB_SARADC_SA... | 2,102 |
*/
#define APB_SARADC_START (BIT(1))
#define APB_SARADC_START_M (BIT(1))
#define APB_SARADC_START_V 0x1
#define APB_SARADC_START_S 1
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define APB_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_START_FORCE_M (BIT(0))
#define APB_... | 2,102 |
*/
#define APB_SARADC_TIMER_SEL (BIT(11))
#define APB_SARADC_TIMER_SEL_M (BIT(11))
#define APB_SARADC_TIMER_SEL_V 0x1
#define APB_SARADC_TIMER_SEL_S 11
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/
#define APB_SARADC_SAR2_INV ... | 2,102 |
*/
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; ... | 2,102 |
*/
#define APB_SARADC_STANDBY_WAIT 0x000000FF
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
#define APB_SARADC_STANDBY_WAIT_V 0xFF
#define APB_SARADC_STANDBY_WAIT_S 16
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: .*/
#define APB_SAR... | 2,102 |
*/
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_S 0
#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/* APB_SARADC_SAR1_P... | 2,102 |
*/
#define APB_SARADC_SAR1_PATT_TAB3 0x00FFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S))
#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_S 0
#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x24)
/* A... | 2,102 |
*/
#define APB_SARADC_SAR2_PATT_TAB2 0x00FFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S))
#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_S 0
#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x30)
/* A... | 2,102 |
*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi pri... | 2,102 |
*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;... | 2,102 |
*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enableapb controller.*/
#d... | 2,102 |
*/
#define APB_SARADC_FILTER_CHANNEL1 0x0000001F
#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
#define APB_SARADC_FILTER_CHANNEL1_V 0x1F
#define APB_SARADC_FILTER_CHANNEL1_S 14
#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE ... | 2,102 |
*/
#define APB_SARADC_THRES0_HIGH 0x00001FFF
#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
#define APB_SARADC_THRES0_HIGH_V 0x1FFF
#define APB_SARADC_THRES0_HIGH_S 5
/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
/*description: .*/
#define APB_SAR... | 2,102 |
*/
#define APB_SARADC_THRES1_HIGH 0x00001FFF
#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
#define APB_SARADC_THRES1_HIGH_V 0x1FFF
#define APB_SARADC_THRES1_HIGH_S 5
/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
/*description: .*/
#define APB_SAR... | 2,102 |
*/
#define APB_SARADC_THRES2_EN (BIT(29))
#define APB_SARADC_THRES2_EN_M (BIT(29))
#define APB_SARADC_THRES2_EN_V 0x1
#define APB_SARADC_THRES2_EN_S 29
/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: .*/
#define APB_SARADC_THRES3_EN (BIT(28))
#define APB_SARADC_THRES3_EN_M (BIT(2... | 2,102 |
*/
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define APB_SARADC_THRES0_HIGH_INT_ENA... | 2,102 |
*/
#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ENA_S 26
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x60)
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;de... | 2,102 |
*/
#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: .*/
#define APB_SARADC_THRES0_LOW_IN... | 2,102 |
*/
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define APB_SARADC_THRES0_HIGH_INT_ST (BI... | 2,102 |
*/
#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ST_S 26
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x68)
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;defaul... | 2,102 |
*/
#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
/*description: .*/
#define APB_SARADC_THRES0_LOW_IN... | 2,102 |
*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
/*description: the dma_in_suc_eof gen when sample cnt = ... | 2,102 |
*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (BIT(20))
#define APB_SARADC_CLK_EN_V 0x1
#define APB_SARADC_CLK_EN_S 20
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
/*description: Fractional clock divider denominator value.*/
#define APB_SARADC_CLKM_DIV_A 0x0000003F
#d... | 2,102 |
*/
#define APB_SARADC_ADC2_DATA 0x0001FFFF
#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
#define APB_SARADC_ADC2_DATA_V 0x1FFFF
#define APB_SARADC_ADC2_DATA_S 0
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC)
/* APB_SARADC_APB_CTRL_DATE : R/W ;... | 2,102 |
fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
_Static_assert(sizeof(UART1.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
_Static_assert(sizeof(UART2.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
#endif
#ifdef __cplusplus
}
#endif
| 2,103 |
0: XPD HALL is controlled by FSM in ULP-coprocessor*/
uint32_t hall_phase : 1; /*Reverse phase of hall sensor*/
uint32_t hall_phase_force : 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
};
... | 2,104 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32S3.
#pragma once
//UART channels
#define UART_GPIO43_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 43
#define UART_GPIO44_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 44
#define UA... | 2,105 |
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
*/
#pragma once
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
/** SYSTEM TIMER CLK CONTROL REGISTER */
/** Type of conf register
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32... | 2,106 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
#include
/* Register Layout */
/* The TWAI peripheral's registers are 8bits, however the ESP32-S3 can only access
*/
typedef volatile struct twai_dev_s {
//Configuration and Control Registers
union {
struct {
uint... | 2,107 |
2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; ... | 2,107 |
8 Miss Status */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti... | 2,107 |
0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4:... | 2,107 |
7 Sampling*/
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; ... | 2,107 |
8 CLKOUT enable/disable */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");... | 2,107 |
/*
*/
#ifndef _SOC_INTERRUPT_REG_H_
#define _SOC_INTERRUPT_REG_H_
#include "soc/interrupt_core0_reg.h"
#include "soc/interrupt_core1_reg.h"
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /*_SOC_INTERRUPT_REG_H_ */
| 2,108 |
/*
*/
#ifndef _SOC_APB_SARADC_STRUCT_H_
#define _SOC_APB_SARADC_STRUCT_H_
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force : 1;
uint32_t start : 1;
... | 2,111 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,112 |
*/
#define UHCI_CLK_EN (BIT(11))
#define UHCI_CLK_EN_M (BIT(11))
#define UHCI_CLK_EN_V 0x1
#define UHCI_CLK_EN_S 11
/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: .*/
#define UHCI_ENCODE_CRC_EN (BIT(10))
#define UHCI_ENCODE_CRC_EN_M (BIT(10))
#define UHCI_ENCODE_CRC_EN_V 0x1
#def... | 2,112 |
*/
#define UHCI_HEAD_EN (BIT(6))
#define UHCI_HEAD_EN_M (BIT(6))
#define UHCI_HEAD_EN_V 0x1
#define UHCI_HEAD_EN_S 6
/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: .*/
#define UHCI_SEPER_EN (BIT(5))
#define UHCI_SEPER_EN_M (BIT(5))
#define UHCI_SEPER_EN_V 0x1
#define UHCI_SEPER_EN_S 5... | 2,112 |
*/
#define UHCI_TX_RST (BIT(0))
#define UHCI_TX_RST_M (BIT(0))
#define UHCI_TX_RST_V 0x1
#define UHCI_TX_RST_S 0
#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4)
/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL1_INT_RAW (BIT(8))
#define UHCI... | 2,112 |
*/
#define UHCI_SEND_A_Q_INT_RAW (BIT(5))
#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5))
#define UHCI_SEND_A_Q_INT_RAW_V 0x1
#define UHCI_SEND_A_Q_INT_RAW_S 5
/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_SEND_S_Q_INT_RAW (BIT(4))
#define UHCI_SEND_S_Q_INT_RAW_M (BIT(... | 2,112 |
*/
#define UHCI_RX_START_INT_RAW (BIT(0))
#define UHCI_RX_START_INT_RAW_M (BIT(0))
#define UHCI_RX_START_INT_RAW_V 0x1
#define UHCI_RX_START_INT_RAW_S 0
#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8)
/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_C... | 2,112 |
*/
#define UHCI_SEND_A_Q_INT_ST (BIT(5))
#define UHCI_SEND_A_Q_INT_ST_M (BIT(5))
#define UHCI_SEND_A_Q_INT_ST_V 0x1
#define UHCI_SEND_A_Q_INT_ST_S 5
/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_SEND_S_Q_INT_ST (BIT(4))
#define UHCI_SEND_S_Q_INT_ST_M (BIT(4))
#de... | 2,112 |
*/
#define UHCI_RX_START_INT_ST (BIT(0))
#define UHCI_RX_START_INT_ST_M (BIT(0))
#define UHCI_RX_START_INT_ST_V 0x1
#define UHCI_RX_START_INT_ST_S 0
#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC)
/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CT... | 2,112 |
*/
#define UHCI_SEND_A_Q_INT_ENA (BIT(5))
#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5))
#define UHCI_SEND_A_Q_INT_ENA_V 0x1
#define UHCI_SEND_A_Q_INT_ENA_S 5
/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_SEND_S_Q_INT_ENA (BIT(4))
#define UHCI_SEND_S_Q_INT_ENA_M (BIT... | 2,112 |
*/
#define UHCI_RX_START_INT_ENA (BIT(0))
#define UHCI_RX_START_INT_ENA_M (BIT(0))
#define UHCI_RX_START_INT_ENA_V 0x1
#define UHCI_RX_START_INT_ENA_S 0
#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10)
/* UHCI_APP_CTRL1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_AP... | 2,112 |
*/
#define UHCI_SEND_A_Q_INT_CLR (BIT(5))
#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5))
#define UHCI_SEND_A_Q_INT_CLR_V 0x1
#define UHCI_SEND_A_Q_INT_CLR_S 5
/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_SEND_S_Q_INT_CLR (BIT(4))
#define UHCI_SEND_S_Q_INT_CLR_M (BIT(... | 2,112 |
*/
#define UHCI_RX_START_INT_CLR (BIT(0))
#define UHCI_RX_START_INT_CLR_M (BIT(0))
#define UHCI_RX_START_INT_CLR_V 0x1
#define UHCI_RX_START_INT_CLR_S 0
#define UHCI_APP_INT_SET_REG(i) (REG_UHCI_BASE(i) + 0x14)
/* UHCI_APP_CTRL1_INT_SET : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define UHC... | 2,112 |
*/
#define UHCI_WAIT_SW_START (BIT(7))
#define UHCI_WAIT_SW_START_M (BIT(7))
#define UHCI_WAIT_SW_START_V 0x1
#define UHCI_WAIT_SW_START_S 7
/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: .*/
#define UHCI_TX_ACK_NUM_RE (BIT(5))
#define UHCI_TX_ACK_NUM_RE_M (BIT(5))
#define UHCI_TX_... | 2,112 |
*/
#define UHCI_CHECK_SEQ_EN (BIT(1))
#define UHCI_CHECK_SEQ_EN_M (BIT(1))
#define UHCI_CHECK_SEQ_EN_V 0x1
#define UHCI_CHECK_SEQ_EN_S 1
/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: .*/
#define UHCI_CHECK_SUM_EN (BIT(0))
#define UHCI_CHECK_SUM_EN_M (BIT(0))
#define UHCI_CHECK_SUM_... | 2,112 |
*/
#define UHCI_ENCODE_STATE 0x00000007
#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
#define UHCI_ENCODE_STATE_V 0x7
#define UHCI_ENCODE_STATE_S 0
#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24)
/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*descript... | 2,112 |
*/
#define UHCI_TX_13_ESC_EN (BIT(3))
#define UHCI_TX_13_ESC_EN_M (BIT(3))
#define UHCI_TX_13_ESC_EN_V 0x1
#define UHCI_TX_13_ESC_EN_S 3
/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_TX_11_ESC_EN (BIT(2))
#define UHCI_TX_11_ESC_EN_M (BIT(2))
#define UHCI_TX_11_ESC_... | 2,112 |
*/
#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007
#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7
#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
/*description: .*/
#de... | 2,112 |
*/
#define UHCI_TXFIFO_TIMEOUT 0x000000FF
#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
#define UHCI_TXFIFO_TIMEOUT_V 0xFF
#define UHCI_TXFIFO_TIMEOUT_S 0
#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x2C)
/* UHCI_ACK_NUM_LOAD : WO ;bitpos:[3] ;default: 1'b1 ; */
/*... | 2,112 |
*/
#define UHCI_ALWAYS_SEND_EN (BIT(7))
#define UHCI_ALWAYS_SEND_EN_M (BIT(7))
#define UHCI_ALWAYS_SEND_EN_V 0x1
#define UHCI_ALWAYS_SEND_EN_S 7
/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
/*description: .*/
#define UHCI_ALWAYS_SEND_NUM 0x00000007
#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWA... | 2,112 |
*/
#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q0_WORD0_S 0
#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x3C)
/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ... | 2,112 |
*/
#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q1_WORD1_S 0
#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x48)
/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ... | 2,112 |
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