text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q3_WORD0_S 0
#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x54)
/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ... | 2,112 |
*/
#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q4_WORD1_S 0
#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x60)
/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ... | 2,112 |
*/
#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q6_WORD0_S 0
#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x6C)
/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ... | 2,112 |
*/
#define UHCI_SEPER_CHAR 0x000000FF
#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
#define UHCI_SEPER_CHAR_V 0xFF
#define UHCI_SEPER_CHAR_S 0
#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x74)
/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
/*description: .... | 2,112 |
*/
#define UHCI_ESC_SEQ1_CHAR1 0x000000FF
#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
#define UHCI_ESC_SEQ1_CHAR1_V 0xFF
#define UHCI_ESC_SEQ1_CHAR1_S 16
/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
/*description: .*/
#define UHCI_ESC_SEQ1_CHAR0 0x000000... | 2,112 |
*/
#define UHCI_ESC_SEQ2_CHAR0 0x000000FF
#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
#define UHCI_ESC_SEQ2_CHAR0_V 0xFF
#define UHCI_ESC_SEQ2_CHAR0_S 8
/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
/*description: .*/
#define UHCI_ESC_SEQ2 0x000000FF
#define UHC... | 2,112 |
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,113 |
/*
*/
#pragma once
/**
*/
#define I2C_ULP_IR_FORCE_CODE 5
#define I2C_ULP_IR_FORCE_CODE_MSB 6
#define I2C_ULP_IR_FORCE_CODE_LSB 6
//register for OCode
#define I2C_ULP_EXT_CODE 6
#define I2C_ULP_EXT_CODE_MSB 7
#define I2C_ULP_EXT_CODE_LSB 0
| 2,114 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*descri... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11))
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : R... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#def... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
#define ASSIST_DEBUG_CORE_0_INTERRUPT_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9))
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#def... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*descri... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10))
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*descri... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
#define ASSIST_... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
#define ASSIST_... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
#define ASSIST_DEBUG_CORE_0... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_REG (DR_REG_ASSIST_D... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + ... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_RCD_RECORDING (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_M (BIT(0))
#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_V 0x1
#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_S 0
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
/* ASSIST_DEBUG_CORE_0... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S 0
#define ASSIST_DEBUG_CORE_0... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S))
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S 0
#define A... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitp... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25))
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitp... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(22))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(22))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 22
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000FFFF
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xFFFF
#define ASSIST_DEBUG_CORE_0_DR... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11))
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_S 11
/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA : R... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA (BIT(8))
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M (BIT(8))
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V 0x1
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S 8
/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#de... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA (BIT(4))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M (BIT(4))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S 4
/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA (BIT(0))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M (BIT(0))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S 0
#define ASSIST_DEBUG_CORE_1_INTERRUPT_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW (BIT(9))
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M (BIT(9))
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V 0x1
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S 9
/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#defi... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW (BIT(5))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M (BIT(5))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S 5
/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW (BIT(1))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M (BIT(1))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S 1
/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*descrip... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10))
#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1
#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_S 10
/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W ;bitpos:... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS (BIT(6))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M (BIT(6))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S 6
/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS (BIT(2))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M (BIT(2))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S 2
/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*descri... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11))
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1
#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_S 11
/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR : R... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR (BIT(8))
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M (BIT(8))
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V 0x1
#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S 8
/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#de... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR (BIT(4))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M (BIT(4))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S 4
/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR (BIT(0))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M (BIT(0))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V 0x1
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S 0
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S))
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S 0
#define ASSIST_... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S))
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S 0
#define ASSIST_DEBUG_CORE_1... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_AREA_PC 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_AREA_PC_M ((ASSIST_DEBUG_CORE_1_AREA_PC_V)<<(ASSIST_DEBUG_CORE_1_AREA_PC_S))
#define ASSIST_DEBUG_CORE_1_AREA_PC_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_AREA_PC_S 0
#define ASSIST_DEBUG_CORE_1_AREA_SP_REG (DR_REG_ASSIST_DEBUG... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_SP_MIN 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_SP_MIN_M ((ASSIST_DEBUG_CORE_1_SP_MIN_V)<<(ASSIST_DEBUG_CORE_1_SP_MIN_S))
#define ASSIST_DEBUG_CORE_1_SP_MIN_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_SP_MIN_S 0
#define ASSIST_DEBUG_CORE_1_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE +... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE (BIT(0))
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_M (BIT(0))
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_V 0x1
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_S 0
#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG (DR_REG_ASSIST_DEBUG_BASE + 0xDC)
/* ASSIST_D... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS 0x000000FF
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S))
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V 0xFF
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S 0
#define ASSIST_DEBUG_... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S))
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S 0
#define A... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S))
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S 0
#define A... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 (BIT(24))
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M (BIT(24))
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V 0x1
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S 24
/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 (BIT(24))
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M (BIT(24))
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V 0x1
#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S 24
/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 0x003FFFFF
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S))
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V 0x3FFFFF
#define ASSIST_DEBUG_CORE_1_DRAM0_RECO... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S))
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 0x0000FFFF
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S))
#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V 0xFFFF
#define ASSIST_DEBUG_CORE_1_DR... | 2,115 |
*/
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF
#define ASSIST_DEBUG_COR... | 2,115 |
*/
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(6))
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(6))
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 6
/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[5:3] ;default: 3'b0 ; */
/*description: .*/
#define ASSIST_DEBUG_LOG_MODE ... | 2,115 |
*/
#define ASSIST_DEBUG_LOG_DATA_1 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_DATA_1_M ((ASSIST_DEBUG_LOG_DATA_1_V)<<(ASSIST_DEBUG_LOG_DATA_1_S))
#define ASSIST_DEBUG_LOG_DATA_1_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_DATA_1_S 0
#define ASSIST_DEBUG_LOG_DATA_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x134)
/* ASSIST_DEB... | 2,115 |
*/
#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF
#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF
#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0
#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x140)
/*... | 2,115 |
*/
#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF
#define ASSIST_DEBUG_LOG_MEM_START_S 0
#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0... | 2,115 |
*/
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0))
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0))
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0
#define ASSIST_DEBUG_REG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
/* ASSIST_DEBUG_REG_DATE : R/W ;bitpos:[27:0] ... | 2,115 |
/*
*/
#pragma once
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sdmmc_desc_s {
struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1... | 2,119 |
} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
#ifndef __cplusplus
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
#endif
typedef struct sdmmc_dev_t {
volatile union {
struct {
... | 2,119 |
uint32_t ddr: 16; ///< bit N enables DDR mode for card N
};
} uhs; ///< UHS related settings
volatile union {
struct {
uint32_t cards: 2; ///< bit N resets card N, active low
uint32_t reserved: 30;
};
} rst_n;... | 2,119 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/* USB IN EP Register block type */
typedef struct usb_in_ep_reg {
volatile uint32_t diepctl;
uint32_t reserved;
volatile uint32_t diepint;
uint32_t reserved1;
volatile uint32_t dieptsiz;
volatile uint32_t diepdma;
vola... | 2,120 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,122 |
*/
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
uint32_t reserved25 : 7; /*reserved... | 2,122 |
Can be configured in CONF state.*/
uint32_t faddr_oct : 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be confi... | 2,122 |
1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_oct : 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved17 : 1; /*reserved*/
... | 2,122 |
Can be configured in CONF state.*/
uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} ctrl;... | 2,122 |
Can be configured in CONF state.*/
uint32_t reserved22 : 9; /*reserved*/
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
};
uint... | 2,122 |
0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1:... | 2,122 |
Can be configured in CONF state.*/
uint32_t fwrite_oct : 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which mean... | 2,122 |
*/
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can... | 2,122 |
Can be configured in CONF state.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
uint32_t rese... | 2,122 |
The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/
uint32_t reserved16 ... | 2,122 |
The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} ms_dlen;
union {
struct {
... | 2,122 |
*/
uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca... | 2,122 |
*/
uint32_t data_dtr_en : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
uint32_t addr_dtr_en : ... | 2,122 |
Can be configured in CONF state.*/
uint32_t reserved25 : 4; /*reserved*/
uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/
uint32_t cs_keep_active ... | 2,122 |
Can be configured in CONF state.*/
uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
... | 2,122 |
Can be configured in CONF state.*/
uint32_t din6_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
... | 2,122 |
.. Can be configured in CONF state.*/
uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din2_num : 2; /*the input sig... | 2,122 |
.. Can be configured in CONF state.*/
uint32_t din6_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din7_num : 2; /*the input sig... | 2,122 |
Can be configured in CONF state.*/
uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout3_mode ... | 2,122 |
*/
uint32_t dout6_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout7_mode : 1; /*The out... | 2,122 |
1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
uint32_t infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
uint32_t reserved2 ... | 2,122 |
0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
uint32_t reserved22 : 5; /*reserved*/
uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/
ui... | 2,122 |
*/
uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi : 1; /*The enable bit for S... | 2,122 |
*/
uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done : 1; /*The enable bit for ... | 2,122 |
*/
uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t v... | 2,122 |
*/
uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/
uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_I... | 2,122 |
*/
uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MS... | 2,122 |
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