text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
0: Others. */
uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */
uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI int... | 2,122 |
0: Others.*/
uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA trans... | 2,122 |
0: others.*/
uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ... | 2,122 |
*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_I... | 2,122 |
*/
uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7... | 2,122 |
*/
uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_D... | 2,122 |
*/
uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_st;
union {
struct {
uint32_t infifo_full_err_int_set : ... | 2,122 |
*/
uint32_t cmda_int_set : 1; /*The software set bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done_int_set : 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done_int_set : 1; /*The software set... | 2,122 |
*/
uint32_t cmd_err_int_set : 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The... | 2,122 |
0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first e... | 2,122 |
0: others*/
uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-writ... | 2,122 |
0: This is not seg-trans mode.*/
uint32_t reserved29 : 3; /*reserved*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */
... | 2,122 |
*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t GPSPI2;
extern spi_dev_t GPSPI3;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SPI_STRUCT_H_ */
| 2,122 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_PKG_VERSION_ESP32S3 0 // QFN56
#define EFUSE_PKG_VERSION_ESP32S3PICO 1 // LGA56
/** EFUSE_RD_MAC_SPI_SYS_2_REG register
*/
// #define EFUSE_RD_MAC_SPI_SYS_2_REG (DR... | 2,123 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_TOUCH_SHIELD_CHANNEL (14) /*!< The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) */
#define SOC_TOUCH_DENOISE_CHANNEL (0) /*!< T0 is an internal channel that does not have a corresponding external GPIO.
... | 2,126 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/*
*/
typedef union {
struct {
uint32_t cat0 : 2; /**< category bits - level 2 */
uint32_t cat1 : 2; /**< category bits - level 3 */
uint32_t cat2 : 2; /**< category bits - level 4 */
uint32_t... | 2,127 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 2,129 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 2,130 |
// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows.
#define SPI2_FUNC_NUM 4
#define SPI2_IOMUX_PIN_NUM_HD 9
#define SPI2_IOMUX_PIN_NUM_CS 10
#define SPI2_IOMUX_PIN_NUM_MOSI 11
#define SPI2_IOMUX_PIN_N... | 2,130 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_C... | 2,132 |
/*
*/
/*
*/
#pragma once
#include "soc/usb_pins.h"
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
#include "soc/sdmmc_pins.h"
#include "soc/touch_sensor_pins.h"
| 2,133 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,134 |
/*
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xC)
/* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.... | 2,135 |
*/
#define I2S_RX_DONE_INT_RAW (BIT(0))
#define I2S_RX_DONE_INT_RAW_M (BIT(0))
#define I2S_RX_DONE_INT_RAW_V 0x1
#define I2S_RX_DONE_INT_RAW_S 0
#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The masked interrupt status bit f... | 2,135 |
*/
#define I2S_RX_DONE_INT_ST (BIT(0))
#define I2S_RX_DONE_INT_ST_M (BIT(0))
#define I2S_RX_DONE_INT_ST_V 0x1
#define I2S_RX_DONE_INT_ST_S 0
#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the i... | 2,135 |
*/
#define I2S_RX_DONE_INT_ENA (BIT(0))
#define I2S_RX_DONE_INT_ENA_M (BIT(0))
#define I2S_RX_DONE_INT_ENA_V 0x1
#define I2S_RX_DONE_INT_ENA_S 0
#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
/* I2S_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the i2s_tx... | 2,135 |
*/
#define I2S_RX_DONE_INT_CLR (BIT(0))
#define I2S_RX_DONE_INT_CLR_M (BIT(0))
#define I2S_RX_DONE_INT_CLR_V 0x1
#define I2S_RX_DONE_INT_CLR_S 0
#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
/*description: Configure the down sampl... | 2,135 |
0: Disable..*/
#define I2S_RX_TDM_EN (BIT(19))
#define I2S_RX_TDM_EN_M (BIT(19))
#define I2S_RX_TDM_EN_V 0x1
#define I2S_RX_TDM_EN_S 19
/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
/*description: I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
MSB is received first..... | 2,135 |
.*/
#define I2S_RX_24_FILL_EN (BIT(16))
#define I2S_RX_24_FILL_EN_M (BIT(16))
#define I2S_RX_24_FILL_EN_V 0x1
#define I2S_RX_24_FILL_EN_S 16
/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode..*/
#define I2S_RX_LEFT_ALIGN (BI... | 2,135 |
.*/
#define I2S_RX_CLKM_DIV_X 0x000001FF
#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V) a/2, the value o
f I2S_RX_CLKM_DIV_Y is (a%(a-b)). .*/
#define I2S_RX_CLKM_DIV_Y 0x000001FF
#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V) a/2, the value of I2S
_RX_CLKM_DIV_Z is (a-b). .*/
#define I2S_RX_CLKM_DIV_Z... | 2,135 |
.*/
#define I2S_TX_CLKM_DIV_Z 0x000001FF
#define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V)= 88000/2^i2s_lc_fifo_timeout_shift.*/
#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
#define I2S_LC_FIFO_TIMEOUT_SHIFT_V ... | 2,135 |
.*/
#define I2S_RX_EOF_NUM 0x00000FFF
#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
#define I2S_RX_EOF_NUM_V 0xFFF
#define I2S_RX_EOF_NUM_S 0
#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: The co... | 2,135 |
*/
#define I2S_DATE 0x0FFFFFFF
#define I2S_DATE_M ((I2S_DATE_V)<<(I2S_DATE_S))
#define I2S_DATE_V 0xFFFFFFF
#define I2S_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_I2S_REG_H_ */
| 2,135 |
/*
*/
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#warning "apb_ctrl_struct is deprecated due to duplicated with syscon_struct, please use syscon_struct instead, they are same"
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
... | 2,136 |
*/
uint32_t reserved1 : 31;
};
uint32_t val;
} ext_mem_writeback_bypass;
union {
struct {
uint32_t flash_ace0_attr : 9;
uint32_t reserved9 : 23;
};
uint32_t val;
} flash... | 2,136 |
0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size : 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22 : 10; /*reserved*/
};
... | 2,136 |
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 2,137 |
*/
#define SENS_SAR1_DATA_INV (BIT(28))
#define SENS_SAR1_DATA_INV_M (BIT(28))
#define SENS_SAR1_DATA_INV_V 0x1
#define SENS_SAR1_DATA_INV_S 28
/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
/*description: .*/
#define SENS_SAR1_SAMPLE_NUM 0x000000FF
#define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR... | 2,137 |
*/
#define SENS_SAR1_READER_STATUS 0xFFFFFFFF
#define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S))
#define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF
#define SENS_SAR1_READER_STATUS_S 0
#define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x8)
/* SENS_AMP_SHORT_REF_GND_... | 2,137 |
*/
#define SENS_AMP_RST_FB_FORCE 0x00000003
#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S))
#define SENS_AMP_RST_FB_FORCE_V 0x3
#define SENS_AMP_RST_FB_FORCE_S 26
/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
/*description: .*/
#define SENS_FORCE_XPD_AMP ... | 2,137 |
*/
#define SENS_MEAS1_START_FORCE (BIT(18))
#define SENS_MEAS1_START_FORCE_M (BIT(18))
#define SENS_MEAS1_START_FORCE_V 0x1
#define SENS_MEAS1_START_FORCE_S 18
/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: SAR ADC1 controller (in RTC) starts conversion.*/
#define SENS_MEAS1_START_S... | 2,137 |
*/
#define SENS_SAR1_DIG_FORCE (BIT(31))
#define SENS_SAR1_DIG_FORCE_M (BIT(31))
#define SENS_SAR1_DIG_FORCE_V 0x1
#define SENS_SAR1_DIG_FORCE_S 31
#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x14)
/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
/*description: 2-bit attenuation f... | 2,137 |
*/
#define SENS_SAR_AMP_WAIT3 0x0000FFFF
#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S))
#define SENS_SAR_AMP_WAIT3_V 0xFFFF
#define SENS_SAR_AMP_WAIT3_S 16
/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define SENS_SAR_RSTB_FSM_IDLE (BIT(6))
#... | 2,137 |
*/
#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3))
#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3))
#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1
#define SENS_AMP_SHORT_REF_FSM_IDLE_S 3
/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define SENS_AMP_RST_FB_FSM_IDLE (BIT(2))
#define... | 2,137 |
*/
#define SENS_SAR_RSTB_FSM 0x0000000F
#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S))
#define SENS_SAR_RSTB_FSM_V 0xF
#define SENS_SAR_RSTB_FSM_S 24
/* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */
/*description: .*/
#define SENS_XPD_SAR_FSM 0x0000000F
#define SENS_... | 2,137 |
*/
#define SENS_AMP_RST_FB_FSM 0x0000000F
#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S))
#define SENS_AMP_RST_FB_FSM_V 0xF
#define SENS_AMP_RST_FB_FSM_S 8
/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */
/*description: .*/
#define SENS_XPD_SAR_AMP_FSM 0x00000... | 2,137 |
*/
#define SENS_SAR2_DATA_INV (BIT(29))
#define SENS_SAR2_DATA_INV_M (BIT(29))
#define SENS_SAR2_DATA_INV_V 0x1
#define SENS_SAR2_DATA_INV_S 29
/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
/*description: .*/
#define SENS_SAR2_SAMPLE_NUM 0x000000FF
#define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR... | 2,137 |
*/
#define SENS_SAR2_CLK_DIV 0x000000FF
#define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S))
#define SENS_SAR2_CLK_DIV_V 0xFF
#define SENS_SAR2_CLK_DIV_S 0
#define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x28)
/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ;... | 2,137 |
*/
#define SENS_SAR2_STANDBY_WAIT 0x000000FF
#define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V)<<(SENS_SAR2_STANDBY_WAIT_S))
#define SENS_SAR2_STANDBY_WAIT_V 0xFF
#define SENS_SAR2_STANDBY_WAIT_S 8
/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
/*description: .*/
#define SENS_SAR2_RSTB_... | 2,137 |
*/
#define SENS_SAR2_PWDET_CAL_EN (BIT(3))
#define SENS_SAR2_PWDET_CAL_EN_M (BIT(3))
#define SENS_SAR2_PWDET_CAL_EN_V 0x1
#define SENS_SAR2_PWDET_CAL_EN_S 3
/* SENS_SAR2_CNTL_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: saradc2_cntl_fsm.*/
#define SENS_SAR2_CNTL_STATE 0x00000007
#define SENS_SAR... | 2,137 |
*/
#define SENS_MEAS2_START_FORCE (BIT(18))
#define SENS_MEAS2_START_FORCE_M (BIT(18))
#define SENS_MEAS2_START_FORCE_V 0x1
#define SENS_MEAS2_START_FORCE_S 18
/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: SAR ADC2 controller (in RTC) starts conversion.*/
#define SENS_MEAS2_START_S... | 2,137 |
*/
#define SENS_SAR2_RTC_FORCE (BIT(31))
#define SENS_SAR2_RTC_FORCE_M (BIT(31))
#define SENS_SAR2_RTC_FORCE_V 0x1
#define SENS_SAR2_RTC_FORCE_S 31
/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */
/*description: SAR2_PWDET_CCT.*/
#define SENS_SAR2_PWDET_CCT 0x00000007
#define SENS_SAR2_PWDET_CC... | 2,137 |
*/
#define SENS_FORCE_XPD_SAR 0x00000003
#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S))
#define SENS_FORCE_XPD_SAR_V 0x3
#define SENS_FORCE_XPD_SAR_S 29
#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x40)
/* SENS_SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h... | 2,137 |
*/
#define SENS_I2C_SLAVE_ADDR2 0x000007FF
#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S))
#define SENS_I2C_SLAVE_ADDR2_V 0x7FF
#define SENS_I2C_SLAVE_ADDR2_S 11
/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
/*description: .*/
#define SENS_I2C_SLAVE_ADDR3 ... | 2,137 |
*/
#define SENS_I2C_SLAVE_ADDR6 0x000007FF
#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S))
#define SENS_I2C_SLAVE_ADDR6_V 0x7FF
#define SENS_I2C_SLAVE_ADDR6_S 11
/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
/*description: .*/
#define SENS_I2C_SLAVE_ADDR7 ... | 2,137 |
*/
#define SENS_TSENS_POWER_UP (BIT(22))
#define SENS_TSENS_POWER_UP_M (BIT(22))
#define SENS_TSENS_POWER_UP_V 0x1
#define SENS_TSENS_POWER_UP_S 22
/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
/*description: temperature sensor clock divider.*/
#define SENS_TSENS_CLK_DIV 0x000000FF
#define SE... | 2,137 |
*/
#define SENS_TSENS_READY (BIT(8))
#define SENS_TSENS_READY_M (BIT(8))
#define SENS_TSENS_READY_V 0x1
#define SENS_TSENS_READY_S 8
/* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: temperature sensor data out.*/
#define SENS_TSENS_OUT 0x000000FF
#define SENS_TSENS_OUT_M ((SENS_TSENS_OU... | 2,137 |
*/
#define SENS_TSENS_XPD_WAIT 0x00000FFF
#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S))
#define SENS_TSENS_XPD_WAIT_V 0xFFF
#define SENS_TSENS_XPD_WAIT_S 0
#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x58)
/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: ... | 2,137 |
*/
#define SENS_TOUCH_APPROACH_PAD0 0x0000000F
#define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V)<<(SENS_TOUCH_APPROACH_PAD0_S))
#define SENS_TOUCH_APPROACH_PAD0_V 0xF
#define SENS_TOUCH_APPROACH_PAD0_S 28
/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hf ; */
/*description: indicate ... | 2,137 |
*/
#define SENS_TOUCH_UNIT_END (BIT(19))
#define SENS_TOUCH_UNIT_END_M (BIT(19))
#define SENS_TOUCH_UNIT_END_V 0x1
#define SENS_TOUCH_UNIT_END_S 19
/* SENS_TOUCH_DENOISE_END : RO ;bitpos:[18] ;default: 1'd0 ; */
/*description: touch_denoise_done.*/
#define SENS_TOUCH_DENOISE_END (BIT(18))
#define SENS_TOUCH_DE... | 2,137 |
*/
#define SENS_TOUCH_OUTEN 0x00007FFF
#define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V)<<(SENS_TOUCH_OUTEN_S))
#define SENS_TOUCH_OUTEN_V 0x7FFF
#define SENS_TOUCH_OUTEN_S 0
#define SENS_SAR_TOUCH_DENOISE_REG (DR_REG_SENS_BASE + 0x60)
/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'b0 ; */
/... | 2,137 |
*/
#define SENS_TOUCH_OUT_TH2 0x003FFFFF
#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S))
#define SENS_TOUCH_OUT_TH2_V 0x3FFFFF
#define SENS_TOUCH_OUT_TH2_S 0
#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x6C)
/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'... | 2,137 |
*/
#define SENS_TOUCH_OUT_TH5 0x003FFFFF
#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S))
#define SENS_TOUCH_OUT_TH5_V 0x3FFFFF
#define SENS_TOUCH_OUT_TH5_S 0
#define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x78)
/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'... | 2,137 |
*/
#define SENS_TOUCH_OUT_TH8 0x003FFFFF
#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S))
#define SENS_TOUCH_OUT_TH8_V 0x3FFFFF
#define SENS_TOUCH_OUT_TH8_S 0
#define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x84)
/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'... | 2,137 |
*/
#define SENS_TOUCH_OUT_TH11 0x003FFFFF
#define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V)<<(SENS_TOUCH_OUT_TH11_S))
#define SENS_TOUCH_OUT_TH11_V 0x3FFFFF
#define SENS_TOUCH_OUT_TH11_S 0
#define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x90)
/* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;defa... | 2,137 |
*/
#define SENS_TOUCH_OUT_TH14 0x003FFFFF
#define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V)<<(SENS_TOUCH_OUT_TH14_S))
#define SENS_TOUCH_OUT_TH14_V 0x3FFFFF
#define SENS_TOUCH_OUT_TH14_S 0
#define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x9C)
/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default... | 2,137 |
*/
#define SENS_TOUCH_SCAN_CURR 0x0000000F
#define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V)<<(SENS_TOUCH_SCAN_CURR_S))
#define SENS_TOUCH_SCAN_CURR_V 0xF
#define SENS_TOUCH_SCAN_CURR_S 22
/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: the counter for touch pad 0.*/
#def... | 2,137 |
*/
#define SENS_TOUCH_PAD1_DATA 0x003FFFFF
#define SENS_TOUCH_PAD1_DATA_M ((SENS_TOUCH_PAD1_DATA_V)<<(SENS_TOUCH_PAD1_DATA_S))
#define SENS_TOUCH_PAD1_DATA_V 0x3FFFFF
#define SENS_TOUCH_PAD1_DATA_S 0
#define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0xA8)
/* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[3... | 2,137 |
*/
#define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007
#define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V)<<(SENS_TOUCH_PAD3_DEBOUNCE_S))
#define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7
#define SENS_TOUCH_PAD3_DEBOUNCE_S 29
/* SENS_TOUCH_PAD3_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#define SE... | 2,137 |
*/
#define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007
#define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V)<<(SENS_TOUCH_PAD5_DEBOUNCE_S))
#define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7
#define SENS_TOUCH_PAD5_DEBOUNCE_S 29
/* SENS_TOUCH_PAD5_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#define SE... | 2,137 |
*/
#define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007
#define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V)<<(SENS_TOUCH_PAD7_DEBOUNCE_S))
#define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7
#define SENS_TOUCH_PAD7_DEBOUNCE_S 29
/* SENS_TOUCH_PAD7_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#define SE... | 2,137 |
*/
#define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007
#define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V)<<(SENS_TOUCH_PAD9_DEBOUNCE_S))
#define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7
#define SENS_TOUCH_PAD9_DEBOUNCE_S 29
/* SENS_TOUCH_PAD9_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#define SE... | 2,137 |
*/
#define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007
#define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V)<<(SENS_TOUCH_PAD11_DEBOUNCE_S))
#define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7
#define SENS_TOUCH_PAD11_DEBOUNCE_S 29
/* SENS_TOUCH_PAD11_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#de... | 2,137 |
*/
#define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007
#define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V)<<(SENS_TOUCH_PAD13_DEBOUNCE_S))
#define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7
#define SENS_TOUCH_PAD13_DEBOUNCE_S 29
/* SENS_TOUCH_PAD13_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#de... | 2,137 |
*/
#define SENS_TOUCH_SLP_DEBOUNCE 0x00000007
#define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V)<<(SENS_TOUCH_SLP_DEBOUNCE_S))
#define SENS_TOUCH_SLP_DEBOUNCE_V 0x7
#define SENS_TOUCH_SLP_DEBOUNCE_S 29
/* SENS_TOUCH_SLP_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: .*/
#define SENS_TOUC... | 2,137 |
*/
#define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF
#define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V)<<(SENS_TOUCH_APPROACH_PAD1_CNT_S))
#define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF
#define SENS_TOUCH_APPROACH_PAD1_CNT_S 8
/* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */... | 2,137 |
*/
#define SENS_COCPU_TRAP (BIT(29))
#define SENS_COCPU_TRAP_M (BIT(29))
#define SENS_COCPU_TRAP_V 0x1
#define SENS_COCPU_TRAP_S 29
/* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: check cocpu whether in interrupt state.*/
#define SENS_COCPU_EOI (BIT(28))
#define SENS_COCPU_EOI_M (BIT(28... | 2,137 |
*/
#define SENS_COCPU_DBG_TRIGGER (BIT(25))
#define SENS_COCPU_DBG_TRIGGER_M (BIT(25))
#define SENS_COCPU_DBG_TRIGGER_V 0x1
#define SENS_COCPU_DBG_TRIGGER_S 25
#define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0xE8)
/* SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
/*descr... | 2,137 |
*/
#define SENS_COCPU_SWD_INT_RAW (BIT(8))
#define SENS_COCPU_SWD_INT_RAW_M (BIT(8))
#define SENS_COCPU_SWD_INT_RAW_V 0x1
#define SENS_COCPU_SWD_INT_RAW_S 8
/* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: int from software.*/
#define SENS_COCPU_SW_INT_RAW (BIT(7))
#define SENS_COCP... | 2,137 |
*/
#define SENS_COCPU_SARADC2_INT_RAW (BIT(4))
#define SENS_COCPU_SARADC2_INT_RAW_M (BIT(4))
#define SENS_COCPU_SARADC2_INT_RAW_V 0x1
#define SENS_COCPU_SARADC2_INT_RAW_S 4
/* SENS_COCPU_SARADC1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: int from saradc1.*/
#define SENS_COCPU_SARADC1_INT_RAW (... | 2,137 |
*/
#define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0))
#define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0))
#define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1
#define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0
#define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0xEC)
/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[11] ;... | 2,137 |
*/
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA (BIT(9))
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_M (BIT(9))
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V 0x1
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S 9
/* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SWD_INT_ENA ... | 2,137 |
*/
#define SENS_COCPU_TSENS_INT_ENA (BIT(5))
#define SENS_COCPU_TSENS_INT_ENA_M (BIT(5))
#define SENS_COCPU_TSENS_INT_ENA_V 0x1
#define SENS_COCPU_TSENS_INT_ENA_S 5
/* SENS_COCPU_SARADC2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SARADC2_INT_ENA (BIT(4))
#define SENS_CO... | 2,137 |
*/
#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1))
#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1))
#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1
#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1
/* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_TOUC... | 2,137 |
*/
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST (BIT(9))
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_M (BIT(9))
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V 0x1
#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S 9
/* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SWD_INT_ST (BIT(8)... | 2,137 |
*/
#define SENS_COCPU_TSENS_INT_ST (BIT(5))
#define SENS_COCPU_TSENS_INT_ST_M (BIT(5))
#define SENS_COCPU_TSENS_INT_ST_V 0x1
#define SENS_COCPU_TSENS_INT_ST_S 5
/* SENS_COCPU_SARADC2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SARADC2_INT_ST (BIT(4))
#define SENS_COCPU_SAR... | 2,137 |
*/
#define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1))
#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1))
#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1
#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1
/* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_TOUCH_DONE... | 2,137 |
*/
#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR (BIT(9))
#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_M (BIT(9))
#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V 0x1
#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S 9
/* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SWD_INT_CLR (... | 2,137 |
*/
#define SENS_COCPU_TSENS_INT_CLR (BIT(5))
#define SENS_COCPU_TSENS_INT_CLR_M (BIT(5))
#define SENS_COCPU_TSENS_INT_CLR_V 0x1
#define SENS_COCPU_TSENS_INT_CLR_S 5
/* SENS_COCPU_SARADC2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SARADC2_INT_CLR (BIT(4))
#define SENS_COC... | 2,137 |
*/
#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1))
#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1))
#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1
#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1
/* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_TOUCH... | 2,137 |
*/
#define SENS_COCPU_MEM_RDY (BIT(14))
#define SENS_COCPU_MEM_RDY_M (BIT(14))
#define SENS_COCPU_MEM_RDY_V 0x1
#define SENS_COCPU_MEM_RDY_S 14
/* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: cocpu mem valid output.*/
#define SENS_COCPU_MEM_VLD (BIT(13))
#define SENS_COCPU_MEM_VLD_M ... | 2,137 |
*/
#define SENS_HALL_PHASE (BIT(30))
#define SENS_HALL_PHASE_M (BIT(30))
#define SENS_HALL_PHASE_V 0x1
#define SENS_HALL_PHASE_S 30
/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */
/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coproce
ssor.*/
#define SENS_XPD... | 2,137 |
*/
#define SENS_IOMUX_CLK_EN (BIT(31))
#define SENS_IOMUX_CLK_EN_M (BIT(31))
#define SENS_IOMUX_CLK_EN_V 0x1
#define SENS_IOMUX_CLK_EN_S 31
/* SENS_SARADC_CLK_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define SENS_SARADC_CLK_EN (BIT(30))
#define SENS_SARADC_CLK_EN_M (BIT(30))
#define SENS_S... | 2,137 |
*/
#define SENS_TSENS_RESET (BIT(29))
#define SENS_TSENS_RESET_M (BIT(29))
#define SENS_TSENS_RESET_V 0x1
#define SENS_TSENS_RESET_S 29
/* SENS_RTC_I2C_RESET : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: .*/
#define SENS_RTC_I2C_RESET (BIT(27))
#define SENS_RTC_I2C_RESET_M (BIT(27))
#define SENS_RTC_I... | 2,137 |
*/
#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(10))
#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(10))
#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1
#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 10
/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bit... | 2,137 |
*/
#define SENS_COCPU_START_INT_ENA_W1TS (BIT(6))
#define SENS_COCPU_START_INT_ENA_W1TS_M (BIT(6))
#define SENS_COCPU_START_INT_ENA_W1TS_V 0x1
#define SENS_COCPU_START_INT_ENA_W1TS_S 6
/* SENS_COCPU_TSENS_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_TSENS_INT_ENA_W1TS ... | 2,137 |
*/
#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(2))
#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(2))
#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1
#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S 2
/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#de... | 2,137 |
*/
#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(11))
#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(11))
#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1
#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 11
/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ;... | 2,137 |
*/
#define SENS_COCPU_SWD_INT_ENA_W1TC (BIT(8))
#define SENS_COCPU_SWD_INT_ENA_W1TC_M (BIT(8))
#define SENS_COCPU_SWD_INT_ENA_W1TC_V 0x1
#define SENS_COCPU_SWD_INT_ENA_W1TC_S 8
/* SENS_COCPU_SW_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SW_INT_ENA_W1TC (BIT(7))
#def... | 2,137 |
*/
#define SENS_COCPU_SARADC2_INT_ENA_W1TC (BIT(4))
#define SENS_COCPU_SARADC2_INT_ENA_W1TC_M (BIT(4))
#define SENS_COCPU_SARADC2_INT_ENA_W1TC_V 0x1
#define SENS_COCPU_SARADC2_INT_ENA_W1TC_S 4
/* SENS_COCPU_SARADC1_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define SENS_COCPU_SARADC1_INT... | 2,137 |
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