content stringlengths 1 1.04M ⌀ |
|---|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
|
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(2 downto 0);
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(3 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(3 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(2 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "0000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "000";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel2 <= "10";
sel3 <= "11";
Reg2En <= '1';
Reg3En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
sel1 <= "10";
Reg0En <= '1';
Reg1En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "111"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "101" then -- RoundNrVar = 5 (101x, 1010 and 1011)
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
if RoundNrVar = "010" then -- RoundNrVar = 3 (011x, 1010 and 1011 will be done)
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := CRYPT;
Busy <= '1';
end if;
when TAG =>
if RoundNrVar = "101" then -- RoundNrVar = 5 (101x, 1010 and 1011)
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_c_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_c_e-e.vhd,v 1.1 2004/04/06 10:49:52 wig Exp $
-- $Date: 2004/04/06 10:49:52 $
-- $Log: inst_c_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:49:52 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_c_e
--
entity inst_c_e is
-- Generics:
-- No Generated Generics for Entity inst_c_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_c_e
end inst_c_e;
--
-- End of Generated Entity inst_c_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : %version
-- \ \ Application : MIG
-- / / Filename : v6_data_gen.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:43 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Virtex6
-- Design Name : DDR2/DDR3
-- Purpose : This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Virtex 6 family.
-- Reference :
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity v6_data_gen is
generic (
EYE_TEST : string := "FALSE";
ADDR_WIDTH : integer := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : integer := 6;
DWIDTH : integer := 288;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 72;
COLUMN_WIDTH : integer := 10;
SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
user_burst_cnt : in std_logic_vector(6 downto 0);
fifo_rdy_i : in std_logic;
data_o : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
);
end entity v6_data_gen;
architecture trans of v6_data_gen is
component data_prbs_gen is
generic (
EYE_TEST : string := "FALSE";
PRBS_WIDTH : integer := 32;
SEED_WIDTH : integer := 32
);
port (
clk_i : in std_logic;
clk_en : in std_logic;
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
prbs_seed_init : in std_logic;
prbs_seed_i : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
prbs_o : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
);
end component;
constant ALL_0 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
signal prbs_data : std_logic_vector(31 downto 0);
signal acounts : std_logic_vector(35 downto 0);
signal adata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal hdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal ndata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w1data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal w0data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal tstpts : std_logic_vector(7 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal sel_w1gen_logic : std_logic;
--signal BLANK : std_logic_vector(7 downto 0);
--signal SHIFT_0 : std_logic_vector(7 downto 0);
--signal SHIFT_1 : std_logic_vector(7 downto 0);
--signal SHIFT_2 : std_logic_vector(7 downto 0);
--signal SHIFT_3 : std_logic_vector(7 downto 0);
--signal SHIFT_4 : std_logic_vector(7 downto 0);
--signal SHIFT_5 : std_logic_vector(7 downto 0);
--signal SHIFT_6 : std_logic_vector(7 downto 0);
--signal SHIFT_7 : std_logic_vector(7 downto 0);
signal sel_victimline_r : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
signal data_clk_en : std_logic;
signal full_prbs_data : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal h_prbsdata : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
signal i : integer;
signal j : integer;
signal data_mode_rr_a : std_logic_vector(3 downto 0);
signal data_mode_rr_b : std_logic_vector(3 downto 0);
signal data_mode_rr_c : std_logic_vector(3 downto 0);
signal prbs_seed_i : std_logic_vector(31 downto 0);
function concat ( in1 : integer;
in2 : std_logic_vector) return std_logic_vector is
variable rang : integer := in2'length;
variable temp : std_logic_vector(in1*rang-1 downto 0);
begin
for i in 0 to in1-1 loop
temp(rang*(i+1)-1 downto rang*i) := in2;
end loop;
return temp;
end function;
function Data_Gen ( int : integer
) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
end if;
return data_bus;
end function;
function Data_GenW0 ( int : integer) return std_logic_vector is
variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
variable j : integer;
begin
j := int/2;
if((int mod 2) = 1) then
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
else
data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
end if;
return data_bus;
end function;
begin
data_o <= data;
full_prbs_data <= concat(DWIDTH/32,prbs_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_mode_rr_a <= data_mode_i;
data_mode_rr_b <= data_mode_i;
data_mode_rr_c <= data_mode_i;
end if;
end process;
process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
begin
case data_mode_rr_a is
when "0000" =>
data <= h_prbsdata;
when "0001" => -- "0001" = fixed data
data <= fixed_data_i;
when "0010" => -- "0010" = address as data
data <= adata;
when "0011" => -- "0011" = hammer
data <= hdata;
when "0100" => -- "0100" = neighbour
data <= ndata;
when "0101" => -- "0101" = walking 1's
data <= w1data;
when "0110" => -- "0110" = walking 0's
data <= w1data;
when "0111" => -- "0111" = prbs
data <= full_prbs_data;
when others =>
data <= (others => '0');
end case;
end process;
-- process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
-- begin
-- case data_mode_rr_a is
-- when "0000" =>
-- data <= h_prbsdata;
-- when "0001" => -- "0001" = fixed data
-- data <= fixed_data_i;
-- when "0010" => -- "0010" = address as data
-- data <= adata;
-- when "0011" => -- "0011" = hammer
-- data <= hdata;
-- when "0100" => -- "0100" = neighbour
-- data <= ndata;
-- when "0111" => -- "0111" = prbs
-- data <= full_prbs_data;
-- when others =>
-- data <= w1data;
-- end case;
-- end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
sel_w1gen_logic <= '1';
else
sel_w1gen_logic <= '0';
end if;
end if;
end process;
WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(3) is
when '0' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when '1' =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(4 downto 3) is
when "00" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "01" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "10" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "11" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 3) is
when "00000" | "00110" | "01100" |
"10010" | "11000" | "11110" =>
-- when "10010" | "11000"=>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "00111" | "01101" |
"10011" | "11001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "01000" | "01110" | --2,8,14,20,26
"10100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "01001" | "01111" | --3,9,15,21,27
"10101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "01010" | "10000" |
"10110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "01011" | "10001" |
"10111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if; -- cmd_startC
end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
end if; -- clk
end process;
end generate;
WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(6 downto 4) is
when "000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(7);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_48_PATTERN :
if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(7 downto 4) is
when "0000" | "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
--
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_56_PATTERN:
if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" | "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" | "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
--
WALKING_ONE_64_PATTERN :
if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(8 downto 5) is
when "0000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "0001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "0010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "0011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "0100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "0101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "0110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "0111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "1000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "1001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "1010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "1011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "1100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "1101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "1110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "1111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_72_PATTERN :
if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_80_PATTERN :
if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_88_PATTERN:
if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_96_PATTERN:
if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_104_PATTERN:
if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_112_PATTERN:
if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_120_PATTERN:
if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(9 downto 5) is
when "00000" | "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" | "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_128_PATTERN:
if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(10 downto 6) is
when "00000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "00001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "00010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "00011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "00100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "00101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "00110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "00111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "01000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "01001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "01010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "01011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "01100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "01101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "01110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "01111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "10000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "10001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "10010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "10011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "10100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "10101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "10110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "10111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "11000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "11001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "11010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "11011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "11100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "11101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "11110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "11111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_136_PATTERN:
if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
WALKING_ONE_144_PATTERN:
if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( fifo_rdy_i = '1' or cmd_startC = '1') then
if (cmd_startC = '1') then
if (sel_w1gen_logic = '1') then
case addr_i(11 downto 6) is
when "000000" | "100100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(0);
else
w1data <= Data_GenW0(0);
end if;
when "000001" | "100101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(1);
else
w1data <= Data_GenW0(1);
end if;
when "000010" | "100110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(2);
else
w1data <= Data_GenW0(2);
end if;
when "000011" | "100111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(3);
else
w1data <= Data_GenW0(3);
end if;
when "000100" | "101000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(4);
else
w1data <= Data_GenW0(4);
end if;
when "000101" | "101001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(5);
else
w1data <= Data_GenW0(5);
end if;
when "000110" | "101010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(6);
else
w1data <= Data_GenW0(6);
end if;
when "000111" | "101011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(7);
else
w1data <= Data_GenW0(7);
end if;
when "001000" | "101100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(8);
else
w1data <= Data_GenW0(8);
end if;
when "001001" | "101101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(9);
else
w1data <= Data_GenW0(9);
end if;
when "001010" | "101110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(10);
else
w1data <= Data_GenW0(10);
end if;
when "001011" | "101111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(11);
else
w1data <= Data_GenW0(11);
end if;
when "001100" | "110000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(12);
else
w1data <= Data_GenW0(12);
end if;
when "001101" | "110001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(13);
else
w1data <= Data_GenW0(13);
end if;
when "001110" | "110010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(14);
else
w1data <= Data_GenW0(14);
end if;
when "001111" | "110011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(15);
else
w1data <= Data_GenW0(15);
end if;
when "010000" | "110100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(16);
else
w1data <= Data_GenW0(16);
end if;
when "010001" | "110101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(17);
else
w1data <= Data_GenW0(17);
end if;
when "010010" | "110110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(18);
else
w1data <= Data_GenW0(18);
end if;
when "010011" | "110111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(19);
else
w1data <= Data_GenW0(19);
end if;
when "010100" | "111000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(20);
else
w1data <= Data_GenW0(20);
end if;
when "010101" | "111001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(21);
else
w1data <= Data_GenW0(21);
end if;
when "010110" | "111010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(22);
else
w1data <= Data_GenW0(22);
end if;
when "010111" | "111011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(23);
else
w1data <= Data_GenW0(23);
end if;
when "011000" | "111100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(24);
else
w1data <= Data_GenW0(24);
end if;
when "011001" | "111101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(25);
else
w1data <= Data_GenW0(25);
end if;
when "011010" | "111110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(26);
else
w1data <= Data_GenW0(26);
end if;
when "011011" | "111111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(27);
else
w1data <= Data_GenW0(27);
end if;
when "011100" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(28);
else
w1data <= Data_GenW0(28);
end if;
when "011101" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(29);
else
w1data <= Data_GenW0(29);
end if;
when "011110" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(30);
else
w1data <= Data_GenW0(30);
end if;
when "011111" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(31);
else
w1data <= Data_GenW0(31);
end if;
when "100000" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(32);
else
w1data <= Data_GenW0(32);
end if;
when "100001" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(33);
else
w1data <= Data_GenW0(33);
end if;
when "100010" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(34);
else
w1data <= Data_GenW0(34);
end if;
when "100011" =>
if (data_mode_i = "0101") then
w1data <= Data_Gen(35);
else
w1data <= Data_GenW0(35);
end if;
when others =>
w1data <= (others => '0');
end case;
end if;
elsif (MEM_BURST_LEN = 8) then
w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
end if;
end if;
end if;
end process;
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
hdata(i) <= '1';
elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
hdata(i) <= '1';
elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
hdata(i) <= '0';
else
hdata(i) <= '1';
end if;
end loop;
end if;
end process;
process (w1data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
process (full_prbs_data, hdata)
begin
for i in 0 to 4 * NUM_DQ_PINS - 1 loop
if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
else
h_prbsdata(i) <= hdata(i);
end if;
end loop;
end process;
addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
acounts <= ("0000" & addr_i);
elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
if (NUM_DQ_PINS = 8 ) then
acounts <= acounts + X"000000004";
elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
acounts <= acounts + X"000000008";
elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
acounts <= acounts + X"000000010";
elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
acounts <= acounts + X"000000020";
elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
acounts <= acounts + X"000000040";
end if;
end if;
end if;
end process;
adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
end generate;
-- When doing eye_test, traffic gen only does write and want to
-- keep the prbs random and address is fixed at a location.
d_clk_en1 : if (EYE_TEST = "TRUE") generate
data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end generate;
d_clk_en2 : if (EYE_TEST = "FALSE") generate
data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
end generate;
prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
data_prbs_gen_inst : data_prbs_gen
generic map (
PRBS_WIDTH => 32,
SEED_WIDTH => 32,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i,
clk_en => data_clk_en,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => prbs_seed_i,
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of mul_seq is
begin
mul : entity work.mul_seq_inferred(rtl)
generic map (
latency => latency,
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
clk => clk,
rstn => rstn,
en => en,
unsgnd => unsgnd,
src1 => src1,
src2 => src2,
valid => valid,
result => result
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity comparator_n is
generic ( N : positive := 8 );
port (
x, y : in std_logic_vector ( N downto 1 );
gt, eq : out std_logic
);
end entity comparator_n;
architecture comparator_n_impl of comparator_n is
begin
gt <= '1' when x > y else '0';
eq <= '1' when x = y else '0';
end architecture comparator_n_impl; |
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'left = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'left = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
type small is range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'left = 1 report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity misc_logic is
end entity misc_logic;
-- end not in book
use work.MVL4.all;
architecture gate_level of misc_logic is
signal src1, src1_enable : MVL4_ulogic;
signal src2, src2_enable : MVL4_ulogic;
signal selected_val : MVL4_logic;
-- . . .
begin
src1_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src1, enable => src1_enable, y => selected_val );
src2_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src2, enable => src2_enable, y => selected_val );
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns;
src1 <= '0'; src2 <= '1'; wait for 10 ns;
src1_enable <= '1'; wait for 10 ns;
src1 <= 'Z'; wait for 10 ns;
src1 <= '1'; wait for 10 ns;
src1_enable <= '0'; wait for 10 ns;
src2_enable <= '1'; wait for 10 ns;
src2 <= 'Z'; wait for 10 ns;
src2 <= '0'; wait for 10 ns;
src2_enable <= '0'; wait for 10 ns;
src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns;
src1 <= '0'; wait for 10 ns;
src1 <= 'X'; wait for 10 ns;
src1 <= '1'; src2 <= '1'; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture gate_level;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity misc_logic is
end entity misc_logic;
-- end not in book
use work.MVL4.all;
architecture gate_level of misc_logic is
signal src1, src1_enable : MVL4_ulogic;
signal src2, src2_enable : MVL4_ulogic;
signal selected_val : MVL4_logic;
-- . . .
begin
src1_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src1, enable => src1_enable, y => selected_val );
src2_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src2, enable => src2_enable, y => selected_val );
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns;
src1 <= '0'; src2 <= '1'; wait for 10 ns;
src1_enable <= '1'; wait for 10 ns;
src1 <= 'Z'; wait for 10 ns;
src1 <= '1'; wait for 10 ns;
src1_enable <= '0'; wait for 10 ns;
src2_enable <= '1'; wait for 10 ns;
src2 <= 'Z'; wait for 10 ns;
src2 <= '0'; wait for 10 ns;
src2_enable <= '0'; wait for 10 ns;
src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns;
src1 <= '0'; wait for 10 ns;
src1 <= 'X'; wait for 10 ns;
src1 <= '1'; src2 <= '1'; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture gate_level;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity misc_logic is
end entity misc_logic;
-- end not in book
use work.MVL4.all;
architecture gate_level of misc_logic is
signal src1, src1_enable : MVL4_ulogic;
signal src2, src2_enable : MVL4_ulogic;
signal selected_val : MVL4_logic;
-- . . .
begin
src1_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src1, enable => src1_enable, y => selected_val );
src2_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src2, enable => src2_enable, y => selected_val );
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns;
src1 <= '0'; src2 <= '1'; wait for 10 ns;
src1_enable <= '1'; wait for 10 ns;
src1 <= 'Z'; wait for 10 ns;
src1 <= '1'; wait for 10 ns;
src1_enable <= '0'; wait for 10 ns;
src2_enable <= '1'; wait for 10 ns;
src2 <= 'Z'; wait for 10 ns;
src2 <= '0'; wait for 10 ns;
src2_enable <= '0'; wait for 10 ns;
src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns;
src1 <= '0'; wait for 10 ns;
src1 <= 'X'; wait for 10 ns;
src1 <= '1'; src2 <= '1'; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture gate_level;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RdT3NHqn9crEVoGlVr/u5ifJrhZxCKMuq2cHsTARQRG6jVMPRhnzggQLQXUT46IUMAW9jvMJWPX+
qzSQ7DlaGA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
l9TkRhWuYPTmqesd6suV9XTZ3VPfFaaViocpyDrxYTu6WhcA8LTA87s6O1fxFWBaEe8ejVSh+dTA
fBTywaIzD6Pvwo3SIGqcoQWG1G8b/htFi3vTrcGzHFADrN6npxmURYicoBu7Nysaz2rVS+kDvvX/
6SMxBDGJxHNluTNfOfs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EYceV5QU4O0db9jGqBW6Zcxisvt12NgTmxxrS1V5Q7j/IhW6/quWxSq+g7EI/XdNj9QPE2IdcmH8
bVya8/qTjy0A1QX35nSxt7vTYedqNu465tC31d1gSZv/kTgwsiyLuwqEcX2XuPWtCtU9zZUhL7Il
2Kq2+W4nCCLCCcSveJad3fvCE0PHRxk26bWkXFVplZnodSz+o7HsyhlK+Dw9uZTzUAGDTcQexyg/
VwoE33FFwg3xrLtrFC3Yc+3Ci12lIOk6ox+EPKylAG3O6vdvhh/wk8fHyecQH+6mWOiDaL6mxNMD
p3c6FL9knpouY9hrFEFnkws/CVeEi955aL7iIA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
3P75IPAwFXq454ffDtSQEIRGo8/c1f61zDZVhqmKoQIPM+JnMNBWMJMtPhUFK8B/KMinqWmjw1FL
ujZLDJkbxQr6L3chtq241i3WX0GZZqzPlPtq6NgqtQc1dZYQ/6plKFwo1kFI0G0+aaXXA/Rg0my4
yCUW2cdGH1FiPkrfTTk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
U4A9VXASlEerYBMwLLMRq0uqBbuc5L+YMSRJVGgWzFToJIpoFNrOwRzqQ/AO3+K4R2EXLYMNSBSP
TdIkdh3GVx/DOJPGABU+jakJcGrmbxCsdTRe36ySkMAGm2PEBhWN5d0rJ1+mMJyR9fUAt4PqJgDT
geENJYB9LMuhHISLxMsPfmR4lwsP5W/mhqo1gOUBVrUg2ZhKO7le4N2V++ce3O1PFfF8e2ud2jGz
Kjy4RN9oYsttt1uvpKVvgY4hHqfYh3YOP284g5YDCjhAhGfLmTOjl9XXOb4fI6D0/XqL4aNNVhRE
1EOYYgYjpK7fQX3V0Yh9HmUHi+Jp2BWIjI5uyw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18352)
`protect data_block
OfMEHIw2C6kHzUz2JuaPPgsgi7BVcTnNyP5GYjhbGsmlBAGTEte9kmxdZW+Mu61HLpiiTJ43ulSL
aEAOHqO16BXbUe8CnCetzl2iOBbDTOxu5W6G2mDyY33bp5MfzSTIRKhNpslJ67RKzxFo+as/OI0r
SQofrrMl+ndXhCbCkxXGQgHwZC/CfUp0iJmmfN50KY1R+4jcwsbccLCgqlQRxssP1YdNX8H7C9u0
mL5MIv/tVpBb36m91dbeA9akm5Ls+mo30UYHQ/1p9gaJiMqkEw+ttpvq8fE2fHI4qZPfCrq0xSzS
TxODbVYfsSb571GIB+xKw5/UocYcJkBiUzYxgWK8yBpbmz+9E/v2gRGZUojG98lo22tJjazqkBJV
mRf3UqKcwcuIXaRVBkQAFXmb1tqSG5LLc7ocQ3p9I9ayPoyFPlKXlfHYczW9EvnBViaogv3Fbb1U
0aB6thXqRhCbLkSqGQ82u+5jyLzca2nmBgSw8ZKglsVCV8RBlwFTl0lHGNv9Spd6JHl32ffTJCnv
wUBSDMM8ZJuBjNzXxx8hfkmoXyNiUPs9iXTqJZe3VIMktwvCaIhzxBFXeC9k8mEIo7u3kcvO6vmH
MtYypa+loHTMvDcwzM79OlGv3W5E5DcvM0dfrvG3uefsRiTMAJEh9Mc4N0X8WdmamFPKaWrFJovX
pHMTEKfZ7w6BesNqsWTh9NTfGyiwgmmg1sc+efk2KlCgfsexm0OA2NEA8KLtSia7pk0GWEjwgpLx
TmWcG1GvwMHUPmNlltU2d4Sp75JRh2BirNMMIoxzDg97ctzxFrsKaETalgAIKD2RhbVfR5t99Gcz
JNMlFbScP20fX+/82cWisK245VAnz+fuiEd7dToNa9C5BhjJ8GSrlOgdwh+cJopwZba8bxm6V5ZN
spfYGdTkHyHAOIG32YqmMLQkF0+s/M26Kg/e8WEgSRaO5uo4f7nt4BTfGX1roR4i+wIO1KBK5+BN
RlaX1ySKt9RIKjB13KDUTmLMWkGQD9imG0DGOawlZIjNt1j2wHjx2Nf95hFgBePrwn/lMUGqdXU5
HB3YxE3mOPNigKvJ/ZU8RyPtGpAwBcwWK1dnUkMpKsvfRzmw6f0jU6HpKsT1kSkVABTmNkBSmHSO
GjV74CdBE+HzGud8jUToZVGyvU/Y0/ALAZLgeQALECLp+57NnC/fmKbHkgOrjthnfRTYYkVk0Pg5
wDcM1VhF2slH6Lax7IizTAlkvKhOEpi45AtfxT1ifINkxYNaGw41wIxhlOykvSRBO3RCVFM4v9G2
gT6wv4Ywc8POW8YNF4oFD5L5UCHrpIGFSDWRy4MybAknhL/B69ULGI/D1a+RopAozLsBrkIvf7vj
5dozf9/5mK1NJC+KY+s8goXoQPi7sew/T8l7izCgdTE6bMZMEz0mgIYzI+rcIdj/Ie2FVZmeMlJD
VNUGC6LaypE0ZygPPNjWCnRC8M1vdRwjUZK1RkQmBMMwvXMfIF1eQU6sdDs13/VuVTz1ilIGiQZA
p3l3A5H7MfMCXy7VrY5iNEBckRGqjbn4eSr/DxnAQL7Ej8+Ypun4DiVesv6sEm16vI1yOEucXlne
iC5o82rF8DW/rinfZZzT2iljQ2aB4mk77ZsDXtZh6m7XK1vFbLgey08n51Dk9b/btseeu9dENvFj
+SCKR4J0Uf/bLjn4GoGqz2kynDWcYvD+sTJtRZKtVFYLE3pJYSg7b+b9aUWtEjY4r5lXEoUd7Br/
ghLTYXi2HQZaL0UMMT9A5Rxk6/kzvTU6ymDNq6DsGHwUzQPCabVIL+aH/u2ZGvsgWejcKJ7EH8Yk
op9YOtNfcXcNxs7WypRvkukyX/Qcx5JBZoJ/pfxR6KkIL1eySdjD4Wc1YPP4hGpWxMHiCaWCJN0d
1NTyldbQfY7meAOSpDT1CDMv7oBqRVQlD/Wz1epfZbsJ9936SO1bhf7tuYKd4TFkNSN+YngnASiZ
oeEU+ZXEQmZTKwHaZ3XhsZxwYd+SmoyJ2F5hei72R/xfLbY/AzXuNbI5rHBo09XCG2YbP0enyMY7
MQUDB33lZcYsoEet+8YhdeT4U120N0LoThWHreEldex3DZAMjltW0vlTp03HURkg5Cg2t9nNK9aN
fR88rFwxeiCrG2mIcC4RS50CHm/wW+LuD+slBeSCUNb/0xtDleOxgH31jBgw4XRR/mG8w3o2pbs9
MokdAmrlHM1bu4hoCTrqaiMlkGagPTz/pR6mOd9O3ewVC3DrAGGMxuDUafFDicDBxCJBptIv0cWA
LV71llgl84ukQKJT7QsPRpVg5DsZaigDdhnLbF9ttSaZ9/7BYS74LWFTS2nrS5lQqUeQGJbSVel9
0F2q0tUbtJOqKzx25Slt9jFffJUyaWTxyQHaIui6Qie5e8ycOGIPY76gfFSdWcdTNyr9hj98YcHI
goZ83cHRaEHZ6iTQaA/YNFnCS7yoL9dbkv2mk4NJ8/rr41hMbPooaVT406sQ7OBVHcHgth3+/Fxx
UkTsZqo4d1DCIBzLLe5WHyI7k9k0CnnWAWfQ9Mw7gJJCT+7BL50fbEXaUURW5PtmW61d68p/pzAf
tcHcSP9ZTKs+vM20SdT/2Kq2UF82wMzDZa7DF3GEOhdeG84rWoppPhPIF4I3l2uQLR2xDbC9892q
9HrBQB6Gk2j1GQCZVz7lkWb69v6XQG+Giw+7iSAhaliIvquDj5o2gteYy31y3qSY1fvYoAjvnFSp
BuxtFRLXsd8EwdZE5JtgpY7em6FSyL3N4/uFXjSDWvXrFc65Be9h3uk9Rd/1lZjXCJQgNdSyKO6D
Hc3xJ98+YarsqCRpcfwzSvVyca3NjW/ly47bGWry0hB+/7VbmFMBxG+J3RZIOkO60zQKO9pJBtUJ
tjBAJZ8Lr+E+uPQQRbNupYEQljnTFhY6T1Uu2MsmNN7bJ13QGq15jFxfnFtvd6e90/JfeVGF0ICZ
xDCxzvlIRrj/fjdAZyoKsdX2abhompr+Fn6xNqIgPE/GDXb8IlwB22v62coiZVKIOcY1PStQ+C5f
Dm/6kgyTvV/t+BtsfnlIeMFdmLUWlZgzPn7E/k0Go5mYo6IQa6ILuCsVrb0qbd4841OxHLV4M6RP
/Ii0vrN+Kphb4G0j6gqwZig7EmOwJ6T7wJzArXjmEguFxi/kxfsJ6NuiJ00Ib3Eu5CuI75ghKb1o
xcw5SrBL2JvUF6UbNemoKKI+fKZvTbzFFevunhU+TmaElFfaCxiUJ1Q16WKZHuWfh8gF4J9vjJMW
dmP8Popgev2+gAuVQTjKOFx43POqWxICCMdPFmMw2tTF+TfKfbg//vArIbRTlOPEcZwvydKtci8b
mrDScqj/SX3VoV6z1yyq+a8KIoS+RYrDnIn5lvJ6m1ZkgFqzUR+Qe0fbFCwK7li8d9x31vOLTZe6
hQT2HIWrg3+lvFkZJcMwhB4PgkzHGwCjcPntoL/+9kOXhiIWggGwuLfXlkYVBgRuFrqvlC4esl5x
MGyUgjSmNF67lIDz1WZczqeAuxBgmLEFjfoibeqd9Gs3wNCnaIzQ3u5wi3DwI+G5osaC1utJeJ14
PFSAFkARpombTtWLY3IH5Guq4Fh25UtV+1JLLbXOf+wvOvxyxl05oFn5b/5VFfOGdVNdGdJ/Z9P0
WJJbX6A4wfURqqYGQgENe7gQ8DXwcbH829PhRF2BQmRK1P0PsO3qz9Z21Gn1zQgUSDW5Qb/fH5Xj
YxEpxJ4OMFublZrLw7nqI17fHKAtlDc8XJqttvq99vLMp9UYgq1cmy1AvbdKK0e/nmFfYBiQnlNJ
LZBFWB9cW94Bf7la7ReGLOCvLVQmEObsI15PcOO9kQ8J5+4y5EhBqtmkMRQpRmjmoP4A/V2ikJBE
uObhrObMWL0mCx1pMJO6TfxQkzC5UPF0W4XypdMRVbFmPG9BamuhBpKr2Jxqc7G4OpvLfKPhtqt/
BKrczvGmbgw5T4m0AUCOyqCBxQktmQo0RvZrPNTJ1Yk/9foI9+mIondHyy4oGe6S7eVPieFAA7bY
ALedNqOL9Nl6EBqKVT/XRDJ1eee76Z61HKc4ot4Ay1IQW1Sr7b4xjXiiiAKZfd85RJ6SSKCtmklj
RD6ibZjecR2FdcWUcH56iAbvWXKF92Voo+sSHXYD5GoxGs8Oy8epfJPIpFqFTJtNnt5G8/wngsor
w7dc/AmIsBaZsFN95lJTByf19n+He9NYYAXJz2sn+90sJmcSlEnoMnXu9z5+9sJAvcFFJY1ifk8i
1xzDspnsaq1CWkX1UN1qCo+i7OW02FLPywgD7sxaNhxgRrLO5wpvbG7h4eU3q3Aimn9dedL9oFvU
F2sqbsZEY2sZcuQ9eyG/4N8ZvPYt102HTwUMJbWSudTtbK75eaHZm4O249gC3A+872QYhs9UsZTP
opRPF2dMEzHBdwVOjaLoT2sHp/RPJsjgSQY+c2MrWLJHKHlCYUesEFQQN7E437xEwlLRo8lSjw+f
4QEwwxDDjM1pQ5cyY+WyM/egAwNJoyFwcDGAQ2ZI6bXlnPz0TOkYOIb9JQD5JvyFrZ4Acdn6n+qu
KBqw0uWKxPxKlUnXVwB9miRnRKxVbzCHOL/bpyWfQTW8pudmZzBiauO6OOb4eLMQUNQGcTnExHG8
Ksm5Kp206mCdLorsgzQmjyph6i0ApPvxBotSi1cSze8jmJCO7VFLBk39C8qK3ncSjbyfQXb81jef
gpCoOPZPnG6UOEJoUgh544etbIAbRJzuO0YZhHybrNGWpTY1clhmwmplXD4Vjf37isYoJOTW/2Rm
c+rlOA6RJ8DASiE9cf39iMbJTw+KISZ2foC2ZYWDr3qIY0pOiX17AY2cT+IbWKcl4fa6kVoWkdMy
xCgnoTx+KLpKVdPlTPeH5OoBv4XvqZqCwPkUJgyDiqVAdK/Fhyuk1nnsZKH0rFA23VndDKwWclBl
6/S7xddYYoNdRcogwvDAH2PD4tMBXS+ZU4+sd2/4BdRu5YXuwNZG05xCK2cIcvexgLNX0saXQTs5
3CpIS+gHRorwxX7+CsjKCaUsAqKahxV/iH7qPAMEYf/RNMTZJVmYXShLl8paoJPAJmKiJKRyXHRp
zuxbdrYlFr/SyaXYV1R7W32wMqWlQJKhdByHbvm9go3VaipPjnl0OIaWM6uL+sMg9klRxA6rRiWl
Cw0HErldMDFANLBp45LVwRqM2v+vOPy1xw0bs9KMVUgeNF+qH/ztMBVFjXfllcy74uHQDnJiSiU+
tZIEUFjbACeCfik4jiNyed+Ouf4wyLhRHz9LFXaTNAHqt0EJGyO3t9hgFIOWxsITTwtpGuvntRs8
AFVWYEgSCI3Bfwi9TWfiz1c9pokSqyUotoEmCll9mzUr9Icw2oUBkWVSMNI1sEjoDQbbgP6B3lxz
dViDAMFg5mstRdvhvufGBaFxQoQL13RIhi+ywRVH/Sc3RBnaDB0mvtl5YGChSykjBoEGCAlVNUH5
fKFEt+tlbs+IHSr/Gj6zc5fXlb10FkDONxY0HhM36fD/9J3ic0/vWiKu4a+npLegbuNRPFr+NMT7
za+tB7eivNj5cEVa3DvZpe939/Q1luBuWrlLH+RlI+T3pcVLvqnco49saX9aWWfXmVYzjJueUaGM
vHaUgvGFYk0lLIMBmHIgLdc/n05f780L7/LbP0eonmt92GmbgyurvHAZ6glHqJHeKo0oYqagVfOJ
l/p4xsNh+WTJM/FJeskdMc/t/xFzYcIXBmnBnvMSe6bFVuiKqKCGc/3fC2D5x8+7cBaMzkCnOcdv
tbmATFRZCjPmgKiLPJaKMh77ptUD9TEkc1hv6y4sktL1bdNqoYDDpFFa4fSoAYRcL06RNBLEZKss
PFIkeyaPc8eyOiXE6wWneJdfEeB/MSVHP9FFeuy5hxix3slpVXXyne9PJ3aoNKgpypr9SiVCZgQf
e96Y455PtwQrGPtCdXTRgqNUHkMdCPGyRAiLysoEQEQkWGb0t19KG9+oIbCgbxLPHnkpi+rNfECr
OZLZl7aKa4ASsurJ86QXiCMtqFBxylhaJQtLA5VLiQgEd3YvQHnZixPoGHYT6NXj0Qyk1uLr9cjP
tOJO7za2cscfoaWwPA+xsMHX3rb8cs6PiYc7CWi0sT6dlwbkZPavCg3CwLGLYnSZoKNNvIly1XgL
3wMPJqbOAUfCEWuWCBf/5g6wVtK9h7w5pU/zZAPDwm1iRf3SnL/znMs5Rhq+IIZQ7cB4239881H6
imsustX8zsOuewSA1D3rq8rBBhmf5pEHPzzEKoHuqpbKsugSRehywackhGDulFNhHBwLhKf6LUPV
7cXo45yUmPLYfAp/gmrDY4CPpXxcw4rM57Nnz/E5inp/jN3/QfOY75/xHRiNufcdt10sBL+3WYkt
fhNwEJpGS20leMm4+cU7jGkKv8kCh/cVJ0tEKWbBMKXpqiMLv6r6z0CExkfuDt5d6HtG6xRgwDYz
U6ndKA//A4ilaAuFOyJNX8QcgQlKcxwHgeNRnrzAf24TZWbnvkinF0Zs9VtfMbnfM1OAWlPCOlaQ
wTfkO1t8tSA/AEMBXjaVkRUs8Zqe/yIM9yT+Jxqp9DxHvj96ULZeNhOXJbu5gZzPXl3EWRS1FTLg
3HooNJsrJH413/3UEiXZosbuGPevLufM7fy5bFaovPLaGwwrYq9n4FEeHfu/pskjiLW2/GCgcwnc
wgo1c0apN7FnjDBDyo+BuIIOWQ/KPwKMXsr1E1ZSC4lqyMqpHkME6EXSsmDFDhrf7GBGFBnDhHb3
JvyeU77EI2fqbv9SlT/iUGkPXEKvkfnpUOihISk8jVyXF07OYv1/OUwIXwYodKztNXD8UXMYn7ue
fdwiGbIEiFL70SA7gdx4XaoNO2l5A4ESpwKhopKTOGrMkd7gkvMknmqp0yJgDFbloXIVGzDZBhSK
d5wfP9jTDe5mnKc3FyKhrM4fvxlLXIsHghebq0/p+zxXrpZ7+N54A6+jEG/bRxI4rXQeblg1sPQJ
lqeJ0rO7lRjUUqdht4O6IbXozXcTPKG/1KWXjlAwpLEmFYRtmvQui2iVE/8LtlbJ+irjEgI/RBkK
1SLX2ezohcGEyh1pAN0CZYg6FGSpwOb0nRADs0czypDfFnX2e9ETHZqUUZcFrmOehUbwJPXgn7YW
DCC6CeiOXJPt6n7IOUFmEqacaGWc4h+mzuRLo93AfBaKg0Id0AY59FghR4ij4iBn323nu2P4c41q
VtWkiMh8WdALpIgKK5inp38rrJjVUTDn8Za+9SUeWqmAT7/xdNvtpCSXwdPkdNxM8p8B9+N38tgG
3FZFGKZATTD+6cz/RjyONHtG5y8Rt+CfK3HRS7i/qPJJFmXdA/1CKWLGLyXBPT6/jXbuA+5Waowq
CY76+7C+Dc3EamwODSfZXK6AWM1ONLPwISe3/r53DlZG6NuaeewfWBlCeBCi4MQLB76m5POn/jnt
7U0REhe2+yiE6/Ns7iG5fY1Bl5Vkn2JJ5qkdOQR0UF8UYCUWBpJXPbAoMLf4wirWTHoJBBTOwmjq
6CEBoQOV9OQ/ky5MViV7xHYaZ++Ng7YBgoQmzGMJhAOZ58h5cN62oq/fozsoH2e52gZPN/qlPz0Y
4FJXP6c/NGVyThv3najn/+m5S7Uyjl/qtEKPu9YLM/FKv2kLm1EcOKG5vSoX+ZN3LqYuFJeuW6jn
8Nzg/njm69zLZIMGuMgbuRp4ZN1Udaeg7S4H8H3QkzEkU1IHnMmnesDKfuzP2jNNeUSCdPbiPDo6
a2lpw+0FLcsWzEi/oHp50T4g9uyypdmjn3RTynb/8xqQbFKTG1QHZV51aaRUpJ6BsDr1qVpD4wy2
amzaiAwF/K/D2l4ucZdCmRHr0axKpEHo+yCYl3Lt6IHePXfLMnW1Sy6zz0wSS3AOd2L2H9trs4vI
ufE+QVOt+Ni7dY9YKEWD28dlafSWfBJQuXDsSu38vz5HEXFpeEstf8VvAvX9wwFJS2q3zqRk6iMe
B6BtbEi0APjkfq53W80boGGIUW3Ey4I/tN5YbWX1s32h8i3SldAgKrb+6TwtVBIt66gomS/0VJix
MPwa4cIBwUJVRf0C2jSwY6UYzCxfbA7kduotKa4+X6CPl7gZCowzXxr7nj+9LsS8LMThRzDg8aaf
xLkIihfhBxiIzOOX+DF0rI4U+1AwFnW2pI0XcwJGweIBWRri8jG8yBoVJsSoyQo7ouK0zBp6fEcP
CCuejcRFAC46cmUPSEPCUXh49rG+70JAq0q5+ZIK13PUi2BsemopN7aldjt00VcF36urfX0nduMD
ySicSW3K9YLL361uC4cRX3O59oOKCSZVgCPIq2lUDapsiVBh4/2csZrW2pRlY7yOuGzvIZJbA0JL
u4Y5iEsHmjo2mEH5RPOsAdcpYauwaBKj0sWD7m+Xuo5BMVkMnFl0DvLHdxaOg9q3eqkmJYRs1E/K
h9+XyqjXP3234ZVZb4Vr0Hr4yFCgwyjQQHURHGNWe0zxwjO50jM7BqyY78sQOtnckAjCut6YoO2p
J1YhQwhMKitX1PDe0SLXiXcB98TxzGq1HBgiBW3vQg5JsotUfck0kh7C1iiTjjXvPmIBw4F2ehRc
Bs7rPj5U2mD6qWZ3PSgymuldNTXw/j1UA4kj3EKnSpigL5zZk2WHX2m3IWRNKi25Re4wty2HcdyL
7lS4KM4hPePebQwAN3r8K2+r+jrrpWovY70jFB2NWDfz9l9x9NdcaHqnl7Zo47h5MulLvp8P/QWO
QiNl6bX7GH1LUcVVpF1ZunvoU+kUxz78cmU2OMCHR+myOJzb2VHssw2FPMAnq86f0tbKWtNeT35p
R9WqPwIoZdL3tLQzIaxe3cYiIfdhwr9uhb3u1sVlnbZGlHZSLX8MDzXkaUKYYj7txxQfBO4p7cCj
80AdSOZNO1+R77E7ZEu2Bt3ZqzlHv5iu0KUF0umGYl/EszoTXx1z5c9mnjbJ+qP99qfn9G8qxaoB
iryYfVpCzpKSopGbsvVoOLtDJvE8wNF4tAqg6hwcKfN3BBF+JzD+WaLZnQByN69mmo5SsN6j4hbU
ZS7bbrQKej5OpOGErpN4PJYuNvONFjSiAQl2sL65JgxW/3Rc8V5VNi9s0XZJ69zfsCZyKaBH2pHO
auyvze13S2+2LK/rCgkdrzvZZzCfh6GX1z56lKGh3v8e/tv769y8QSG1gF9kUCYcTnaZmR/vK9F+
1kJb27ZrhXYFyvX0BJRXZMqSVaRj7RtsP1jlBDJJLK+tU2sFCX+kda8b9fKyHLIEluKs/xWgTpx9
bonWnF93Z+i6Uydz7gNbbku4FWBPEP2HcGRANrUC6eNHuUlWa2PXZlZ4QQgbWi8d5itmyi30U6Qn
DClqazY6nhB+rFvmbmWQZhi1889rsWoMozwLB9GxhXfGu20H8u17bxmaJbNJ+fCxrp5pMetzrU4J
MvdrSXkQ5FJVlA1CNZfPLkgPCk9ZSG7XdBfDZszwPDPlP5yL06QUEQOAHIArQDc0aA6Q9TLo7TRt
sBhI0WpcNo0fqicE2GJNIYsLNKiBVl6j/PSrGWF+8eaDayQyqzkZXyt45uCKuq8EqmvRmwfDuUYF
Pq3EwRnxxbG6DMvX2Qf85tWxmG7dZvmd40CHJsvRkfzUu5sZu2CJ+uyL9DWWncLYAy53m4n4ydB2
qo0hbT0HcdhhVkEpsTcDcra69vB9MeRauYsAUHU9kloEcRiYOwCpbvzMfNA1KezTwp1QMpACHBtI
wlEWKUmC7zLc8uXyHdpbgebGbMZz7fLD1f1RrDD2CWnBp4WuDHpPO4Qu5ySrcyVWArqyDMIB0Mf8
uXYcrPzJxZ0UtHWZ/mMBEu4Pkcdr3BohuXhqwmR8ThE0rDa+9YiegsTyDJBrXGBcXzqJWj8PWK5Q
MsfNVDOMjZftGkIl5IFfhnrPKdjE3T+XhJswf6eT08LyTMAyjq+GxRqrNfRL3smh6664+C7rQ/m1
3TcbaTojAg97Scm6NPVC1l0U13a1KLu8Q6HyIdZV7wCpUKop/eVAzDt6mskLVZJhfKYlJVQEfLPU
nlOsDkb5GKLnklokmVzoVvJjizIbxKxzx7OlfbhmX/pxnQqMZX/ndqtAyKk3XM1eIVuFWkLWjE26
P8eUntNybiyFJ6t3sLn+2RuPSkETax9t0kzZfI1Uv9xOnoclmoJadJtKn/YtpeCGNTpsx8gMs1cN
996P3jCMuamftXtOECYbC/izfbhMPSywrauKdo7ILDg2zoLOkusLxfd1FOWrJ10s98mI1DfVhQxM
L4YcSySNtigAwp7+cWGI+HIJGkg6FfpA984vEeTqYFXh0ZhNHzr048AAuObecgSkPQ0+25rdmZsl
JDxa9h7Q8JCPke4wQ3OR7KCTY2fdKEwkHztpi3x32wq1oCkQz+0DLgKLi9sPn0/PMtt5Gn6/sDKk
CSMVimwpe9TzXBaSsoDgtWBsxpiDS1J5eEE2+4qG9XPE4/ZIx5lS45eeKTJ2SjatkXQNnIK8eLNg
ZEgqmbzUKjg4ciW1csqjDqK9TCt9bi/HIcLpuuRZf27cVPUJB+ZY4b2t7u0BT3m5R8a+sres0cMB
PHX4xtvlHnzwOa2T9LwrsogZIevDfm/2yFSmKPCKn671pRLpfuY4pChKqrbrj66L8I5RgKgD4t9k
7VFGLG9Y7fu2OUTPxb603XDXyWvA3tS3FfuHDCcA1s4I4qShxG6j5ZfLZCWDHq9EZMO7dULw3Typ
bjD+jqps0p+SpUyY+aUy55z6o0Q5S9jtOISPjZy7uRY14n7EsCpGHxQ4uGY8yZJwFD+9CYuGnopZ
eL1bEoHvC9ZhME3IW7gvEgUk9d+bJgZ/ECerDBV0Cb6BG0kqYK3WGi35ch2wnC8R5Xi0tTvL2ope
mkDmuPjrUYq0IorBvd/OypTBd09mtNKi+wx9OLqi3lmPqIMnynWFy/dbv2r7w5RX9WoHhWj9cNqv
OC8q1jKndQlRZT+/w2A3n/n9nxQha+IOtOBzzwvLBDIABcy5bsFSJVdz1XDi1c09GPKE5VNFxWZ6
DgY0xv/aMxF3Wup7p5rSjlRVw0IMcsS19lFiPi2Bc9+TXBMS2czu/s8hlQ4UaAVn/KgvQbx1MDIQ
LbWI0dpBQOEbEGocrdgu5QJQh6HimneXCHECOdPlbS42g7Dw8/o10Bx/mr1LwqCjtGsGzhrR89Ze
VWh2EIWPkMcHWm5SalzkMBVcuNMaoaidX2PoGD4Qw0a7b/auyHOzwFpQqw3+rOMV7P01fgNffJkT
lztzloxYXS3FRUfAZLg7m6Ra+8EW8xLu/4IAeYI4KT6IeuFLJ9osk/h8EO+aFVR+wO3MMyP68d4W
fMZbdGoiOCwhE59WELDb/ZxSwvw1dMkVPNozVX10uB0yJLbz8PhzqARmIQ+ourxUByoTUB8fX1qm
+1StAehfl8Dv1aH7Rc1iYj7/twFbbzN2oHD8TYLQThOMpFliubpRZCognS2hY1cd/0MPSEqOOWRc
KOO2UCJJsOIcUKdKd4MlX0swX6AmiTsvCKXeixZvhXQL3+6hFFPacXWkw15ZkDUNfrTZO57ahEzG
UvLqQpEXa6zqYP1kNyMWQbzLc1ifzXWLWpCP5LvNtoMJO0syUVanub3NVnFGUjZfrs1zb07/Wi5A
RCrkWKYL5+TP+ULlJU1nEangUDjg+ZaasU8oljcqmJi/fvQlxutD54ZnY2lOeh92geJnXEcbS0tC
Zy2fjGx1WrK5TxRm3TOwpP2Hyx8ZZEJylKCd2oh0Q9rGRt7fJM70NcFNPNXmt6bPJy/vcBpOA7/Z
zvbI0zyTTfsYTlmJhszeTR3hK6S3SHMRlx24ZqItPk0FF9oWw5zXsPxj36XwEZcja+HLiWuSjd0/
R8ZjiYvKuFeAqQ2rU/wZuF8Tinwd/V5fUG5WQVdlNOWGhGc0Fjs0huWQaZoWiTsNQML6OBP7Qo/X
pukZwH7dvbLdvUEWH0Wwf3AK7TYR83ITqiHCuCe5vElZ4FCZQv/MVxqrNninD95EktsLvD3VKJR2
uxM6wHLRawJH0T58vnHI/NO8daQnM+2eRu3BlGgWTAAn7S+oh534xo4uZ2Ugb9248AA2eKR3fpd+
+Rl8+kUVj/cK21bo1psdRkuojLjXEGGPJrpp5Ysi+d+mF/yombt4bTlwPk+vSfY7bKHzuMtMRqRU
u+z4KwvC96rn01zNbIh4O0zh5y11knkKrEZ64TFpvBzCSCYUaMCSKx06982OrnwGejd6ay7tuQcr
H//n0te/1ZO/XYMaORmDInYH/yqMEnQsyCWRB36JBpW2OhmsJAWbVYimRgf7Ne6+0ejEfRKnPT8+
laGEsuA0an7lU75zNeFDhNefk1qTHhlcOls+JGkjKbYLRNNPa6gFiukecjS7/iwoobcezTczGwJu
GoGBdNN3ZZEAdgUo278pD+BYyi4hbQ6zW13sjc5axFDevu68xDuO13M0burUjcdN3S6SAoG2m4r0
oY+4kWZx663Riam1/Libh1B26FyFGhU0GHt0sKRHEr8HqD3UJsAzy3HpJghgfOnP86Oz/G6Cj6UP
jcrhScRlmGiYTnlszF+1gqo2URRYV7mLP/+Uc/EuUdgmHFIVnUU1IvXhgPn53DUgPJzXgOIaIqDA
Kmww7auU/0yKsayZghipDjo5BDlF784G/Wx9Wafo+aKS8xPowP9bYB0FS3LYN4WDrDvGHT9IE9N6
wIZazLr8gVys7VQkp1FruAULmVIvlA1x42AJo92FC06vB30focIAq6yCYHiZXQ69JNu3LhpWUOZl
EwswNNK327Z8A9rsOqloyBv6R7OFSV9KqmBGS8+n/XTA3D5Xm1AsiIvAgGj2q71M9A90UzWjfnaF
RZndGDsn5hs2wTa5s1EMoS1Ny/33MRqDdYywfHcre12GkS3GrmulufbGvDDPegtIlGHizeiIBP7i
+kIxyfAzI8LYpTJuuNBzFpn25DjscxWihy3UgB3SuNvo10Mx0rpOTQrPLa5ZTrQtw4athi1dDzR+
0nhNVEZ6d4AefpQJ9FY2vVKGgsIcNjTyvcBrF3/XeJV8lceAhwin1Za4YfmQul3GSr9XH0AfoJTD
CDHVUzePL0BA/22AzbD7Yr7XyyPbfd0JilWmkZsz97eKY+SoQLeZ4CLxao4q2Tqa3fsh0GAg2BSm
9d1yfZsnZEXJ5eLCQmWXnkVpehE94eZ9yit34uWzljHTiVuLycp0ht06ASaZwETnvDbz5r4xwErP
Jed8pVtFDM7TZ2d7nlXj7mZS4wb7+9fB6V1B9Vx3FSZ71vdDBJWXTwuGcSfcRtHVA1BVAbBq0ZHN
XNQGvFhFUTWVtr0rOVHUWGqGMMWmRaJyzujELOMfcU1BhSMp8y19oQkVP5CR6cfOZUVaCiEpbcRS
H0r0+XlzCudX6701vXF+JZVjMSyIZ06oWjANs/JGFRMaOF3uBJSETENWCDWJibkdc6jloVj6A7Ve
JP7e7ID4t6H7clyWUwapiavcflmW/DLB7p/yenIkyWv569lFL0byaHkitg4gMObtnSLcDJLOOoqP
Jy+Mv30NL/tNGtWBZdyTMk88HZZZ2i2Z82mlONIHf5v0QoMDS/NVJhCO8ReXrSCrYKaYtr0KFTL+
S08zNFbiWHlH4fYUwM9PRUeI+LAnoT1hR3+4y60djB89L9EfXF36ZDYTkB90wj07ocVVp1q+BxOt
1Yni5dPVsWMEv7x8L4Ke/vKoRSevsAPOccdkNbJh+yK+VzFa69c32qdsZMycX5NizkyJNko+eo6v
4I7eA3O+f6MuxEtrB/kUxDoRVMNqT3NGAJhF2axFeoLDkF0ZxQ9Tk7H6OBbvmbTd954GY9kI9UDz
TWLREQb6aVxafz6vKkKm4rOeOCd8oE4mwXRujWQGMs8DxXp2xIfx3Q0IajyCOZ4RFDlKlKCcX3jR
2E582PaDki+hpknumVp2MhVIReG/V8uqNAebkWRX9YPSdsEdMjhNpR/7EOSiVpK/7c1Lh6BtwZ+/
cjz8PDoZWE2qvmvQbn2QBYn7jQdlteiTg4Y/f0+Mkkw8EqvrUaBqpBoMu6wYf4XhtRSPIIRQmwEh
9Mb6zHyxr7MfFYmq5j+N0nsJbK2UD5QXexr281v3ZBaL6E5gHD9PcJOgzoqu2jMtyZPMttI1zWDF
KMVg9DO9oz7zPToarPzrcOydqlTsGc72uZtx+2Vssg9DQC3giMLqNqo29dNibC2nIk8nW4r1f/zt
0GuEbTLb4+gDl7w4JldHHYixngfQ+vhXKZk/Cwi4S4fyFYckV75bvzRF8snRFAbNQJNWVoQkKRmi
/Osp4AqPomTN+vcKH00ZhgWga2ppZ8wsB1pCruf/PyHR084IMi+ZA6EgXSaSQdshiZFUm0W1dUE0
UufWyEaL0DsI+kJ7d26to7DQ9bunSuM+6jcEViG8potXDItIbd94NiUZdQsqfopSUWKYvTDlq3nv
13YI+F3SW/9gvDl6zVOKdQok5hKSLaujTSBf3chylSzntpay20wgUzJu5NbHHFufdKhwxqQ+ZQwb
Su/qRKwD/9bzTSs3ADxydQTzf9x9BYMnmGUT80+DINwfC2DsHXLRM6aukg8cOP3Oq6+y2IAnx4jd
WZyN8BPTV0F8NRrTxjcvnntAsiRbL6trHo+nnn6UIPha2/9QTbrkVyuORrL4mEjkKf9FfQzFz5dH
cSTUPMSm3WEJydfaZzxrK0KiK9d2UlNDcmh2SJa57s7GG4wb0W2BJRkSootM1nSVkE7omaJTXudG
EDTwTsJDaG14Zu7RY+HV1JLDVmjc+TUVAsIvtRC5XJUQLbFTadAkzEl8/j5u50VcoNoGKiiRhE+w
qYC8P1mJwgiG7MJh91y3Br81HcAoJhjSMgZk0HkbOCbhmXhbEUZEUWtWtoWZjTMRGPOsG4eAAGwX
jITxxuOMbEdr1JtGJ+4WQhLwwkyUPoTLMp3tfmU8zg47b4AibJhB+4VBYw6pj9u5eZBt+ewuzo65
y5ZfwC4HstR8R5Cj0NQS+orG7/SI9GH7DDqulertAWFIn3NNDD2ZMEqMt67jv1bQE6cAObHWjoZp
sgaDWPI1Fx9X308HbUho4CtN0c5ILVi8tIvTTb89EfbO7X1NdRJJcD3WA4IhjYtEaVbKJ0N9LKyS
s5Qk/IxeyyK7tMIjRAjQo1mV/0Ylb3+aacYE4YjTt4LCf+hOs+rYFoR0nyhGkFdUSQWevJCjdhbP
Qt2nwntHc0LO3rnsMa2pmka3eSKVmDM7PUc0uao+ACz07iVlsEf4hDrySQZEVmrFarJkQZxuTaUQ
CxgSYU+zr5zkx2LLEdLTUwp1NpCouSvZ4sPOLMaoxFhgUkn+K/fCiLqk7X72VsOjIRwUe63lIUUq
I+tJQo1P7krUBSwC5au9YcUQzokQuvwmVOKHJrC/oFveIEgws4t/cQUew2x5/jEZWIBAxAKXpqbF
AbbMHICRuWIsTM8Qvn+DbnHci43oC8iYk7VUqpeMwIo6NeKdTghY9dqL/UNLX5Ni5+r3zxrzldgn
11BDiJiEK8SXNu0o8T8dNgNTwJ+3VuZ4ilYq946aebY2FUWjXTS0CN3mmjFfqplyLR5xmVnvuQnl
UiZan88yR2Mv2T3EhAdS6zRP59gQLFYRsQOGIU8tp5G3qqtBRvJbsp5bHRLHh7a8kz4c3vTBC1fL
AzooPnyl7YQZF1oqV4oCyprS+qHakGvKJ65mf7TF/2IUosN+8j5n3qfx0+Qb5iS+SYsfID3dRs+A
YfUo+Cj7ZBkmKGu+HZJ5HY7C0Qx0ZjtkR0WF4B1F8LoptikBRo8pX4Ph+qFHUTb/CMlu3CRQsOyI
zqvJa0+APkshBnQW57ClYoI+2onevmNyZXoBv5Q81V8dlQkewEkHxHgBevGLkeo6DR4SYgpbxzQl
KUNNQG8CzSCK2bpuoP/OnpUYRaL1BiQJ/EOc5WQu3TVmzVf3efALoQZ/RjHW1Y8liu/Spzrqa/9+
ua2GfCjSOiA8RFSDt+eJzpOFdxFahuSTuAfvkuPSOOD4ZW6uI61evM2+XJjfiLT+piI6imt4fKBI
gLvGxAErSpTz+dQ/ZsdEpWXkTIEcPQtMm9owZplKmS/F9FaKCxQAPftYk5ot1YHakaEjiPaLECKH
+HMCS0NSkJPaoc8FSIh3HgOTXO7Vw7LeTxd+tt7LJYHcokhlcaGdX8YJ9l8f2N0kPaR4ClFUBST6
43fXskreX27DUUvkTpf0sbkEazth2j2teyK32RZPfq8Hn5BM2zwpUWd/7YFIW0u8EzdnUKd0HI6C
5lfWvb3jnpDD8hf/RdhLw49wN+a67H1ME9HmK6yjlPaMLgsO5fvDcPPcMN966Izf2vCK6akFRjlv
qNNpt1XEe13pDbW0BqrZoia+Q+c62pavbIohqLgB1vrfvvbRgSUs3LKt7DcIwi42x6ldVvWqgkWt
8cJzWZla7MQJTbTDzSoQXmDfSpxIkrP7ZGKaasE3+tNTCUAJvoHMiZsrae36PUnyvtp5L4+0+iJP
i07i0OFlrNjj2jVi7Tyh35BL0soBEkxwPTYDm4vuXVpMPPwvH/xlRK7zwbqXfgB1WGIeEu/IWx4g
KCqSyBzz+2OEW2QFsoilN5HkKw+KTNeB6jRObhyQR40x0IVo3WOxUe9WgtEkVrBrAfg4U0E7S4nD
mcq8w2857gOrSIhkqnVyT/QtJil+iGTWbtza21ngBqdVebAZId2GYGafttI8xz4ecMubBM4IHfdJ
Uv6YbZl7jucnD5QUQIhl/yNs5k3xhPkpgJD09Cq+dg0bpLn22ZUlhCoszYTv8k4WsliT1jKSiIjJ
Qky4j6Suct7wwCvfLTn1PdvK8K9Jysl1GwYZoVPmFZoA4oBcbu/eno5LL+1yAk/4J/Sw3Qy2Njky
aenyEhNjUBDgW9vCvHPFKIpdEk9RcIQFIdGp6svNBiJCSz0CtA9XOzmA1IT0XEJmcgqNDXpR3eEj
vRmCbMi4KcRiPCCyTgPxBuqQjyRithLDmZk268U5wVDWXlerQjLhFStR2klKwuYRGTngysUA5smM
X/Z0D+2xXiZp/zXm9VdBLmxLKNon8e++8mfvWiNjWHCtgW4o8QQblGYTUQN80Y02TLQChWXIRdag
Fzv8RWY4S87K9L26YNUXCJ8JgN/UxqIJHB7v55MPyEDQ9db+ABrOeJtYpeg51POOesdl5MLymmTw
6ruz7E8s0OWO7lfbTPDJW96y9tICPTMt7d1D/n0pnp0MUGQUOJ+CUoeH+E6sa1IboAeHNWcX7p8X
4OLBMV8hC82A9mPS59P9A6OpFlnfUU7puIAO1IStjzD2M6ROgpysU4t4U5hjRs5sGNr3PKBTs6rk
vQkJNeLaBYc+D7m3wAta3JvCnLAn2AazLjkiCrrB7ZlkPlj/YuhdoXjx1ode6o8vqxHNbBINKAQG
SWjUtIhxgE/lMRAJMtrtvqq71XjHKlr0fbIkQa3gkqyibwDd+iQa4Vdgy+0FTMj19kbsod9c24Z7
kgk9k7LfrWErD7vlMPZSR0UTdqpS7tUApK1ro/42tIrR7b2b8oInQdLekzm7M3eEZKAtKbtvaDtX
yh1rehAKKN8Acc+NEoY5YhU+NbW4dnt5Xw5fxX2zECUcZ83sG+uPscWuMUjPwyt+SbJmK70BJka0
HJSu8BR5MQBJ0hqbG1Dl1pHWavP3U5/vnT50N8wzBxc1qYM+1LA4PzdAjnlIGptsgqLMmQiJSjGr
SuQ0cgOloQrEfNCvmJCx8hLaQIfs6gZASjnRtNqSGsrsu54/wOGTVPFaDI99GSLwW1tepUEgum1y
u9k8CFc+EilkcrPL0exWX54my2zyz2z2+hgXgnSRoSQR7JKsLEg1hOO5O86p4ECxg0tuEK37jZc0
8id4+BeUz9Bsu3lmMwU4ga4TDbY4sUHm7VVfoVpOXYMsSBoIha+OiaIWJRfbBpaD6UvO494RkhMu
/vhhOZZmBmCTerX/VqozQJM8YqSh1fryEFysdEP8GjiBD885njFDZyAp+q6f/cgRl/v7dNuSxF3g
3RbAb23+CE/j8skU1Pg2TfZCQ1flJ17ayYaMjuoJTcjVAyLOtEyfHb4eZeZ9tRrfsr/TglR5nWNo
dEWrkq88JCeJikc/bA250nNbvXElmlrrG7VIMG5LYE0rOi0bNXvV++cm2DPO9xSY6aPhCaoYrx7A
bQZMYTpOZ7JRNP91BjfPNn8P5RAQnU+PZpNvyVSAuu7MlzfGEcmpXGstJqkLejAEw29Isyiw3tDe
JfzLrDjD6UXbBAUPMSCNKq3TZIrWr8t9S1GO1bURNMNndXtqm64zBpkuclxu1aVUPILfQ4gCud/7
2v/h4bw1GoEm3SrZIA4LgqGV5NZIKOwv3HWxXA68XPvLjczQsw6K1xZWhvxwsXULLnpnbCe7qfbZ
vIRd8CZOfCr7J5sFgEPx+hu6WuwH0bSJiqyme19wb2gvThU24T1kJRKH1kMi74QmPkkt/jn74dE+
Bnj3sxl64xGcRsLBSH8xit1ZqVUttyD+JZGzySnprPczPJs0231sNaAkJ9Lpd8QMdddwAFrYG1B4
hKuBe4tydIRcdCVaZTGeNaF8AcfxoLNen7pNNoC/HFznSB7hkqlLTLRC7iDHSylvQ/mPbECh04eU
t8258OJ+tEXMw3pDjac266RDFU7hDCUGtT+27iDzWaY1RHjeVZEVO7W3YtfnrTsQ6BjxOQVZc6Sv
oIgxy/VDf4hUmOxJyE30sR9jaU6ij/eBu8qHtZAun/esi84shKQGwD+8xyscuU7O0yBP0JXLaS6a
6QnTzChy89TwvkHsqoxZi8/Wsn2sbWpJVq/yoJt6OhowDY936sxMpVuYDHQhL0bhl5NpGS7G46tf
qTP+V58jz0P7unq47wSHgDpjahjy5R13/2AorbYEYfZq9TWkOSwft8MABl+YCan/IBHHT5yRH7tt
TUyVIY+e22014ObvI+Iy8ESedba9krgo5aqDj+WCbnoPPtTxjiIZ40w3f5ybVS9XFnOb+yqLj8zz
KK79WG5PR4tb+rPdMDaWI8OAxL/avJ8je3/hdBEcmsGfbWER/vO7RGo5HAR+5O3lasQoX34qzOgg
bdEwlcJdWr9AQcCgtfYkSo+TLLegiFF6//OTq7DCVXv6Yv6OtZ94OYwL+bLnPsjgfLZ3lgdtwE57
p4maJTKXrZkHgEtoxBFVCLWNjsjspPqfR27WjOUpRKrSYgJXeiOClVFf4fzS7H7cg+dMSQUeUI03
/0lb/9lbve8JItRbfkhOlN5KjZdGZWcoIvwYtDrA1rw1vZi8m3L+QOhW4n4ovdhh4UP+xSSaKShu
2vPpvdeMa124a6bOfwmsDX6w4D5u+2c9tJqrpZU18XaE2VrGvd4ROl5Fg6Rel4xOUnDSmyjy1poG
BRyj1dfKtl7cNcpl5ku+UVDr8iRikL0l35w3taQsgtN616KA/Lr276KTi81AoV0mQJATF5HJ2797
1sT7sng5j/jvzrVeqo4E2/T09yZ1O6DK5+TH+gS/3CGg8+EGDFtZvBj3GRCPzlsbc+2cZiM6CNJJ
fTJgkA1FXUDZ1cqqsqSGvjdSfgejH6pTnn++1J2wDx1Mg7lnihUmgjJA/8iLmeaVOSguEXZARw8S
eakCASqbSz678pJJTaSFQx1QXht4LjcMp5MuV1wEc6X1EuywXC/f1YU617WRsodX3dT8xQSkoGJZ
P1D+hTTUZkKy5DU7cUaL+xH6JRjAA3g9ZpMiIXnU2b/haFSSN2SkM/wh31IW/7DhfWEY7qYZtc3K
oHjogXAHzQistfuYbs2mj0/w9xpMbvrKoqX33qyOX/F+dkPmLSlIvGiYhsF03ga5BaX70DcdWdw5
MQHShilc7AVqWgT3fEYAbwXILDdfyelDBXHKVzkk2xoqneSe+Px2d3Wm8ScJDeDqpmzgo4Fti6zX
zrpiJusRhzBzxd1KvnKdm8jRrZtqsTukejFq7Njh4D4aptYpQhVIywBQ+ZSTz663wJgRAJ3Ib5Af
IWWu2+bQEB66O32iBIvBYLEI6YcN9H2LNmmaMnmotSa+8nfFPnK2Q++2axoMgSU1Vpn7Txoup642
QqrAmzH/BRbz3IFH51cw268eBTnokqyG36LxgduhiMcFgXK1LY+7M95zND6aOcomNgqYtxrWdiRI
8lqtGC6daKi7xJZvxC/JvFw+r10HdAw1iNiprFoIRU7vpCU5zne5g77ta+IlMOIhGVMH88+Aec18
4XwB/aRHL4KiBDxqFAcugHUDzfvms9LX3VnJ8BCi9vR9w/F7YMLU7Xsp9ENp2H/mOpP1kyO9uPKR
X7L3pQaRQ5z+jBpb47eBLMBBBqNbtPFQoz0aJ3PHTL/7hvmHaJGaRRiVVLoAPdSQAdAh318nqbAF
nDxG8pfrMd2+38KU7IJQbxlxnXBVTP8+FU4l6pauO2e+pFzJQdUegD2DjRyb7vL198VeIFunOyeI
ENTpRSXrDTiHrJRhddEvYY8NCUd90xhj6kzouerEZptK6sRppC+oPTbmJ2EczqMWSVAsDF/Oe7sh
rzGr9vdQvSKyetq4+ACJT6CakuwFIVR/HvFaC/tKVH7sfLG+Umqk/KGdOQ5beYsl5PLekJMMrg9j
nuO3EQPDgvcjzROfTc3ECE1nmv38+oldgiJTCbvj19dvh/DPUVrJ8+o7X4dVQugfat7ktu5+FrRb
xGidno5/FvEB7M9juxHODybVXJ33JeAXdo/2M41qZXG0U5JgHz3nwgRFIugrPEVa9QB+5RabwDst
vLCRh1KFBt7O+ZBb7aBv3/5QnUXA9hT5Tn9BHO5/H4Ym0IodcnflPurVQmAw9VGM7g1wpX9MgcNc
/H2XTPlZlI0FD8xLWMu11Lqadh7gYCE4c+lWv+FkJ88nWjD10YlQqNs0djFVPIdHMIfzR4yFdzYP
N0JcXfzUM7tyY6vWgb4356vvjJJbi7jGmeZ2sxd7tmuErs+1A1dF8h+NjMu1KnMWfi3XjpRJL5he
ZGdzFBsWx487VS3I+a0XR7tRM72NQGC3rptIFW4q9cgaNcjEzCpMdStLZBNeSpSJfp7C1yt9qeYO
OY+/d4AC6h5F6vayLv4mpwIfvAuuBGCot4M1B5/UQQcgGIxr/SvBD+tB+5tr9S5ygNIUeG60nFlN
rzzEEx7qLx2sTH+v5F1KyFVxmNK1GCI6/1mgAdt3SpDc/F97NcByDVBbUp1CM564/UyPYc578HKu
YCxKE1GMCz1hVGmGVv3CV/q5UFaa8xOrKmOIyKtruSjyOw5b9e0XDkd16/i02YLPNxEYPG/HN1hp
RNCdgG79umWT1A6rhzs1M7JqAFm5LWakTiIKPCoOLU4SNc6ppQkHmfzCoelPLg03OjGrBN55//uz
LL931PhBrOM0iNJzaqzPN3GRzWy4YS+2YnxcO3h1tVO11kWUvcOmDUuBJCYE6qNBxes51EK6L6sy
FvRyKq5UcQ8d4xOiIdglGBB/KnDHvXpBJ4gZ979bhv190Nlxg5gdJFeSV6/sSh3D/UcQUgZGn7Ra
TtbEdE02H/EkF0hR+cBI3WSxC11R5iD9nAjeLqYMJY9q62BNAO8JLDOP9hI8djl7ok+xM7dHQB0x
u43CmtlYyEjmnAYJIE0VjVVR6YjYT52C6GrI2KKZaCpPVhTCpkT+jAirFfoXaJLgchL7j9xORRGY
TqnFqrccEFl0nPJyQ5zC6X7qu5yKDECUps3oPnICmDH1OaDtmjw5SCooxH0EpT17KkBSlxuR17c0
9lhcOLt6wAAAEqM9U+usVkouP6dTqWQBRLgrvemiYWyBK81P4U5FkxGJiELt5d7lN2YZ3AyPFkxP
aZ3VQ8Yv3LTKhBGaG0VdhQ22ru5trK9etg7w/YG/57gwKM4SOHgjGxuoHcq5PwjOYCOuBPTwsA2D
PV4g6a/JSVXUKnNgqJ764EkwM3txB7GsC+XLJ/gxTf8RFQCWSMeTcamdRqz3TkuGNVWNOImr0pit
ORwCHbOy28HrWbf3scW2MO38pI2ymbo4xe+DLEdpVWYeaFyCB9A6igwUU26r9MresrDwS9vPaw1k
z4F9ALDLsyGAdQWMU4DspZvF1NAPaoRbYFBHUrCeSEDicBJqTH6sjDIzflNKeWw1ohDpZa9Z4wbp
qS9TKjso6BLJeyAfR3ogsmZ4L2jDv6aB+S2J409WaaxfuWofxuqEs12uWeQf0RvsuQfwqA7lXHAO
cXenF68bMQ453+73YSTYFGJuxtgrLBkFhCgq8XSd9FHVP8D0DhEHl8OrXMjFlFQMgbiWWLjvjpxM
L3NRtJx4Gzq419UvpQDqlfoNSlXlrE9AweJyzy3RrR1UJaz+Po7txNVCKJhJZds94fgNSjbKAhRT
GzkbjRqz057MzwvBw5qtA94nfJI+FmLgd8lM3ynO9L2Ff8nGwKcvEOneAl2adYRKnXs1GxzrSqnS
lmczy+yr30DNOIdSOZcVCIloWY/5iDcEZPU0SnsGRWkqKZtufhOfkd79DpnvY2OL7RQqFUptWpUm
0oxlRdTJWP8n2hRZIacIZKiOpb2HRqwvINDzzemYP0yUld8+pfqJJroi3q9DuYojLORQLKJaGNdM
VlliHzrxT/mRQ3vVYeCcGER7MZ2fjpYM+De3grKbRskbU0Xnvvog+Iqgd+/xClqoY+ClqD4WvmnJ
Kjh6ASCbYOIYXpCi1Z+x6K9zhtD9n8KzhboRkXWxrA0wDsCizwpk0GN9j7iJKqup4lgca92eTaL+
wXZLuTBZ4iX0VIG/JFlqB+IFqUjNTq6QA8tcGcnBqjqkA61otp9oRkmgdwBENE8YnP7gfx7+9i8K
4FKEh+pJZnfyNq2Zpd6fsB3y1ASbV0S9dah7MVeM7cyy2T8bC+mQm+CGRv3WmLnJg1X1SzvAplno
W96DNBfFPFTfmtOLOEld8y875xFcubiuK4Rz9XCo0EzDxJn6Km8ASsyh8JfEcYNgFPPIBxYOi2vL
2dhb1lTiWCM14LqqQucPBKnTPlzeVV0fwBILBJn9NNbU/q/158xGSgt5dqBCKmEpdhqsLjF1k1fy
TrfY71YtmGUGJakFMT1xJlbbqCTvM87l9XgNgUIDQl1muKItCE5ZOoI4XCVK94Nh84jo9gMZ542f
0USfy33/zW6vUSnr7e+BJgT56FqJ/UHt9ez29WXxqNzAg57DmHS55HpKmx2XQdalvmUaBDTFIhmo
tPwkLbbkOC4jUjLCBOTPYoRwuyCq7qmUR+RPKntRH1ZNqw4KawLiFX/s2Gh8aKLcuCO0rIfLBybz
H0QCfAHGbTZQvIyxxqKtESS1Ka2Vv+ZHle8dbda6L1UUJO3ga1jgYRb5mqVawV3VRREUBcp1yKuk
jjIFvhVjbHDIqoS86JAOhSqXqfjl5cFbyxQEDGy75EGLG410/b+Ipe3YHMOjQTW74t7pxA0AKZee
HKk3HUspWjm6rXzU3WdOlrEvLyUWrk3oPMxsBX4wMKkN48zVxizXWQ+u61s0SVIotpm5ali3aIDP
Rg/vsTOon8SlaxYIOY3WUKyl1Jl8zbU3WKV+zP3v8StZQ6JAi+IPjDOJoRIXFLUQTiYPocRVsJ0c
Z3bmDvFTY3gft5T6QUGmTpgQVjmjiv5MBG4uqthzn+7Re7oSMDmLgQ+a7W0idTJBZkC8T7XJJrV7
M9iY6Mi2t2z9p97fH3g2Q0ONKMcPqPSCcXcdou2xr2RUD+h3paZOOKxb5zbLffzMvpvpvP/LVP6D
qyYGwImvX354hZFgQjip2tvmR97Lyh81gMD1GK8ST651vaRpQzLVE4OSyTRheVOwRFIcsqdg2nfq
s8g596wKQmHGQb0uHjFL3hJsDOm+PlNyuUjEZC+DqUOzurAyhm0mXR76kbYfGYtijaNsgNWJaDB6
8GEjfFz1QALeB50CZzR+jL7hwxSRaLOWLUmTshYIzyaiDBTMq9g3rOPswR1OpOXwXXfp/e+a4dDa
vDMwPZr7APNPkHDoq4kxMiPESoLD/AtuKjsXSvacv5aD4iQ7eV+ddnGezOKsP1/huMHtQl7iQpyQ
wipIy1q3gEhim53msEs/NQDbQU7YBBbJEyo793FHrokZCG8WJM/LnpGcinBogaO3Sa/NLJ6ata/F
sBNmfpq5pW5TjUFfNx2j8iJiXDg5QQMUif/mGLeumwfrZIP8+bwrGCHs45smoKVS7DsHcGuZxJjw
lCXadtgBvyQc3NuWzunmKeiXtEY2ljey1UpqlavQO6CoCvUvXqGmRQuzBwcCDNNyyKFVo/kBjGCa
gc81763AfkE+DKkUHEB2tWnEQKpgD1HHOpTQMz/MKrnS1+GKVls3LeLlFPrlyX75y1Nm8Fo14Hj3
avfP8TCR3RsWPTxNqBQzOY6wseqzDVT83hsvF9OxxX8IK/dD0WWTdqCTTRktHK7CLpkpp019M45J
QsVxvZMhzE2n5Hu0jMimBcUlHTmyWTSv8PMVG+vz//WZye7Bmsv+5UraNYtJRTYQJGpdqypPOQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RdT3NHqn9crEVoGlVr/u5ifJrhZxCKMuq2cHsTARQRG6jVMPRhnzggQLQXUT46IUMAW9jvMJWPX+
qzSQ7DlaGA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
l9TkRhWuYPTmqesd6suV9XTZ3VPfFaaViocpyDrxYTu6WhcA8LTA87s6O1fxFWBaEe8ejVSh+dTA
fBTywaIzD6Pvwo3SIGqcoQWG1G8b/htFi3vTrcGzHFADrN6npxmURYicoBu7Nysaz2rVS+kDvvX/
6SMxBDGJxHNluTNfOfs=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
EYceV5QU4O0db9jGqBW6Zcxisvt12NgTmxxrS1V5Q7j/IhW6/quWxSq+g7EI/XdNj9QPE2IdcmH8
bVya8/qTjy0A1QX35nSxt7vTYedqNu465tC31d1gSZv/kTgwsiyLuwqEcX2XuPWtCtU9zZUhL7Il
2Kq2+W4nCCLCCcSveJad3fvCE0PHRxk26bWkXFVplZnodSz+o7HsyhlK+Dw9uZTzUAGDTcQexyg/
VwoE33FFwg3xrLtrFC3Yc+3Ci12lIOk6ox+EPKylAG3O6vdvhh/wk8fHyecQH+6mWOiDaL6mxNMD
p3c6FL9knpouY9hrFEFnkws/CVeEi955aL7iIA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
3P75IPAwFXq454ffDtSQEIRGo8/c1f61zDZVhqmKoQIPM+JnMNBWMJMtPhUFK8B/KMinqWmjw1FL
ujZLDJkbxQr6L3chtq241i3WX0GZZqzPlPtq6NgqtQc1dZYQ/6plKFwo1kFI0G0+aaXXA/Rg0my4
yCUW2cdGH1FiPkrfTTk=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
U4A9VXASlEerYBMwLLMRq0uqBbuc5L+YMSRJVGgWzFToJIpoFNrOwRzqQ/AO3+K4R2EXLYMNSBSP
TdIkdh3GVx/DOJPGABU+jakJcGrmbxCsdTRe36ySkMAGm2PEBhWN5d0rJ1+mMJyR9fUAt4PqJgDT
geENJYB9LMuhHISLxMsPfmR4lwsP5W/mhqo1gOUBVrUg2ZhKO7le4N2V++ce3O1PFfF8e2ud2jGz
Kjy4RN9oYsttt1uvpKVvgY4hHqfYh3YOP284g5YDCjhAhGfLmTOjl9XXOb4fI6D0/XqL4aNNVhRE
1EOYYgYjpK7fQX3V0Yh9HmUHi+Jp2BWIjI5uyw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18352)
`protect data_block
OfMEHIw2C6kHzUz2JuaPPgsgi7BVcTnNyP5GYjhbGsmlBAGTEte9kmxdZW+Mu61HLpiiTJ43ulSL
aEAOHqO16BXbUe8CnCetzl2iOBbDTOxu5W6G2mDyY33bp5MfzSTIRKhNpslJ67RKzxFo+as/OI0r
SQofrrMl+ndXhCbCkxXGQgHwZC/CfUp0iJmmfN50KY1R+4jcwsbccLCgqlQRxssP1YdNX8H7C9u0
mL5MIv/tVpBb36m91dbeA9akm5Ls+mo30UYHQ/1p9gaJiMqkEw+ttpvq8fE2fHI4qZPfCrq0xSzS
TxODbVYfsSb571GIB+xKw5/UocYcJkBiUzYxgWK8yBpbmz+9E/v2gRGZUojG98lo22tJjazqkBJV
mRf3UqKcwcuIXaRVBkQAFXmb1tqSG5LLc7ocQ3p9I9ayPoyFPlKXlfHYczW9EvnBViaogv3Fbb1U
0aB6thXqRhCbLkSqGQ82u+5jyLzca2nmBgSw8ZKglsVCV8RBlwFTl0lHGNv9Spd6JHl32ffTJCnv
wUBSDMM8ZJuBjNzXxx8hfkmoXyNiUPs9iXTqJZe3VIMktwvCaIhzxBFXeC9k8mEIo7u3kcvO6vmH
MtYypa+loHTMvDcwzM79OlGv3W5E5DcvM0dfrvG3uefsRiTMAJEh9Mc4N0X8WdmamFPKaWrFJovX
pHMTEKfZ7w6BesNqsWTh9NTfGyiwgmmg1sc+efk2KlCgfsexm0OA2NEA8KLtSia7pk0GWEjwgpLx
TmWcG1GvwMHUPmNlltU2d4Sp75JRh2BirNMMIoxzDg97ctzxFrsKaETalgAIKD2RhbVfR5t99Gcz
JNMlFbScP20fX+/82cWisK245VAnz+fuiEd7dToNa9C5BhjJ8GSrlOgdwh+cJopwZba8bxm6V5ZN
spfYGdTkHyHAOIG32YqmMLQkF0+s/M26Kg/e8WEgSRaO5uo4f7nt4BTfGX1roR4i+wIO1KBK5+BN
RlaX1ySKt9RIKjB13KDUTmLMWkGQD9imG0DGOawlZIjNt1j2wHjx2Nf95hFgBePrwn/lMUGqdXU5
HB3YxE3mOPNigKvJ/ZU8RyPtGpAwBcwWK1dnUkMpKsvfRzmw6f0jU6HpKsT1kSkVABTmNkBSmHSO
GjV74CdBE+HzGud8jUToZVGyvU/Y0/ALAZLgeQALECLp+57NnC/fmKbHkgOrjthnfRTYYkVk0Pg5
wDcM1VhF2slH6Lax7IizTAlkvKhOEpi45AtfxT1ifINkxYNaGw41wIxhlOykvSRBO3RCVFM4v9G2
gT6wv4Ywc8POW8YNF4oFD5L5UCHrpIGFSDWRy4MybAknhL/B69ULGI/D1a+RopAozLsBrkIvf7vj
5dozf9/5mK1NJC+KY+s8goXoQPi7sew/T8l7izCgdTE6bMZMEz0mgIYzI+rcIdj/Ie2FVZmeMlJD
VNUGC6LaypE0ZygPPNjWCnRC8M1vdRwjUZK1RkQmBMMwvXMfIF1eQU6sdDs13/VuVTz1ilIGiQZA
p3l3A5H7MfMCXy7VrY5iNEBckRGqjbn4eSr/DxnAQL7Ej8+Ypun4DiVesv6sEm16vI1yOEucXlne
iC5o82rF8DW/rinfZZzT2iljQ2aB4mk77ZsDXtZh6m7XK1vFbLgey08n51Dk9b/btseeu9dENvFj
+SCKR4J0Uf/bLjn4GoGqz2kynDWcYvD+sTJtRZKtVFYLE3pJYSg7b+b9aUWtEjY4r5lXEoUd7Br/
ghLTYXi2HQZaL0UMMT9A5Rxk6/kzvTU6ymDNq6DsGHwUzQPCabVIL+aH/u2ZGvsgWejcKJ7EH8Yk
op9YOtNfcXcNxs7WypRvkukyX/Qcx5JBZoJ/pfxR6KkIL1eySdjD4Wc1YPP4hGpWxMHiCaWCJN0d
1NTyldbQfY7meAOSpDT1CDMv7oBqRVQlD/Wz1epfZbsJ9936SO1bhf7tuYKd4TFkNSN+YngnASiZ
oeEU+ZXEQmZTKwHaZ3XhsZxwYd+SmoyJ2F5hei72R/xfLbY/AzXuNbI5rHBo09XCG2YbP0enyMY7
MQUDB33lZcYsoEet+8YhdeT4U120N0LoThWHreEldex3DZAMjltW0vlTp03HURkg5Cg2t9nNK9aN
fR88rFwxeiCrG2mIcC4RS50CHm/wW+LuD+slBeSCUNb/0xtDleOxgH31jBgw4XRR/mG8w3o2pbs9
MokdAmrlHM1bu4hoCTrqaiMlkGagPTz/pR6mOd9O3ewVC3DrAGGMxuDUafFDicDBxCJBptIv0cWA
LV71llgl84ukQKJT7QsPRpVg5DsZaigDdhnLbF9ttSaZ9/7BYS74LWFTS2nrS5lQqUeQGJbSVel9
0F2q0tUbtJOqKzx25Slt9jFffJUyaWTxyQHaIui6Qie5e8ycOGIPY76gfFSdWcdTNyr9hj98YcHI
goZ83cHRaEHZ6iTQaA/YNFnCS7yoL9dbkv2mk4NJ8/rr41hMbPooaVT406sQ7OBVHcHgth3+/Fxx
UkTsZqo4d1DCIBzLLe5WHyI7k9k0CnnWAWfQ9Mw7gJJCT+7BL50fbEXaUURW5PtmW61d68p/pzAf
tcHcSP9ZTKs+vM20SdT/2Kq2UF82wMzDZa7DF3GEOhdeG84rWoppPhPIF4I3l2uQLR2xDbC9892q
9HrBQB6Gk2j1GQCZVz7lkWb69v6XQG+Giw+7iSAhaliIvquDj5o2gteYy31y3qSY1fvYoAjvnFSp
BuxtFRLXsd8EwdZE5JtgpY7em6FSyL3N4/uFXjSDWvXrFc65Be9h3uk9Rd/1lZjXCJQgNdSyKO6D
Hc3xJ98+YarsqCRpcfwzSvVyca3NjW/ly47bGWry0hB+/7VbmFMBxG+J3RZIOkO60zQKO9pJBtUJ
tjBAJZ8Lr+E+uPQQRbNupYEQljnTFhY6T1Uu2MsmNN7bJ13QGq15jFxfnFtvd6e90/JfeVGF0ICZ
xDCxzvlIRrj/fjdAZyoKsdX2abhompr+Fn6xNqIgPE/GDXb8IlwB22v62coiZVKIOcY1PStQ+C5f
Dm/6kgyTvV/t+BtsfnlIeMFdmLUWlZgzPn7E/k0Go5mYo6IQa6ILuCsVrb0qbd4841OxHLV4M6RP
/Ii0vrN+Kphb4G0j6gqwZig7EmOwJ6T7wJzArXjmEguFxi/kxfsJ6NuiJ00Ib3Eu5CuI75ghKb1o
xcw5SrBL2JvUF6UbNemoKKI+fKZvTbzFFevunhU+TmaElFfaCxiUJ1Q16WKZHuWfh8gF4J9vjJMW
dmP8Popgev2+gAuVQTjKOFx43POqWxICCMdPFmMw2tTF+TfKfbg//vArIbRTlOPEcZwvydKtci8b
mrDScqj/SX3VoV6z1yyq+a8KIoS+RYrDnIn5lvJ6m1ZkgFqzUR+Qe0fbFCwK7li8d9x31vOLTZe6
hQT2HIWrg3+lvFkZJcMwhB4PgkzHGwCjcPntoL/+9kOXhiIWggGwuLfXlkYVBgRuFrqvlC4esl5x
MGyUgjSmNF67lIDz1WZczqeAuxBgmLEFjfoibeqd9Gs3wNCnaIzQ3u5wi3DwI+G5osaC1utJeJ14
PFSAFkARpombTtWLY3IH5Guq4Fh25UtV+1JLLbXOf+wvOvxyxl05oFn5b/5VFfOGdVNdGdJ/Z9P0
WJJbX6A4wfURqqYGQgENe7gQ8DXwcbH829PhRF2BQmRK1P0PsO3qz9Z21Gn1zQgUSDW5Qb/fH5Xj
YxEpxJ4OMFublZrLw7nqI17fHKAtlDc8XJqttvq99vLMp9UYgq1cmy1AvbdKK0e/nmFfYBiQnlNJ
LZBFWB9cW94Bf7la7ReGLOCvLVQmEObsI15PcOO9kQ8J5+4y5EhBqtmkMRQpRmjmoP4A/V2ikJBE
uObhrObMWL0mCx1pMJO6TfxQkzC5UPF0W4XypdMRVbFmPG9BamuhBpKr2Jxqc7G4OpvLfKPhtqt/
BKrczvGmbgw5T4m0AUCOyqCBxQktmQo0RvZrPNTJ1Yk/9foI9+mIondHyy4oGe6S7eVPieFAA7bY
ALedNqOL9Nl6EBqKVT/XRDJ1eee76Z61HKc4ot4Ay1IQW1Sr7b4xjXiiiAKZfd85RJ6SSKCtmklj
RD6ibZjecR2FdcWUcH56iAbvWXKF92Voo+sSHXYD5GoxGs8Oy8epfJPIpFqFTJtNnt5G8/wngsor
w7dc/AmIsBaZsFN95lJTByf19n+He9NYYAXJz2sn+90sJmcSlEnoMnXu9z5+9sJAvcFFJY1ifk8i
1xzDspnsaq1CWkX1UN1qCo+i7OW02FLPywgD7sxaNhxgRrLO5wpvbG7h4eU3q3Aimn9dedL9oFvU
F2sqbsZEY2sZcuQ9eyG/4N8ZvPYt102HTwUMJbWSudTtbK75eaHZm4O249gC3A+872QYhs9UsZTP
opRPF2dMEzHBdwVOjaLoT2sHp/RPJsjgSQY+c2MrWLJHKHlCYUesEFQQN7E437xEwlLRo8lSjw+f
4QEwwxDDjM1pQ5cyY+WyM/egAwNJoyFwcDGAQ2ZI6bXlnPz0TOkYOIb9JQD5JvyFrZ4Acdn6n+qu
KBqw0uWKxPxKlUnXVwB9miRnRKxVbzCHOL/bpyWfQTW8pudmZzBiauO6OOb4eLMQUNQGcTnExHG8
Ksm5Kp206mCdLorsgzQmjyph6i0ApPvxBotSi1cSze8jmJCO7VFLBk39C8qK3ncSjbyfQXb81jef
gpCoOPZPnG6UOEJoUgh544etbIAbRJzuO0YZhHybrNGWpTY1clhmwmplXD4Vjf37isYoJOTW/2Rm
c+rlOA6RJ8DASiE9cf39iMbJTw+KISZ2foC2ZYWDr3qIY0pOiX17AY2cT+IbWKcl4fa6kVoWkdMy
xCgnoTx+KLpKVdPlTPeH5OoBv4XvqZqCwPkUJgyDiqVAdK/Fhyuk1nnsZKH0rFA23VndDKwWclBl
6/S7xddYYoNdRcogwvDAH2PD4tMBXS+ZU4+sd2/4BdRu5YXuwNZG05xCK2cIcvexgLNX0saXQTs5
3CpIS+gHRorwxX7+CsjKCaUsAqKahxV/iH7qPAMEYf/RNMTZJVmYXShLl8paoJPAJmKiJKRyXHRp
zuxbdrYlFr/SyaXYV1R7W32wMqWlQJKhdByHbvm9go3VaipPjnl0OIaWM6uL+sMg9klRxA6rRiWl
Cw0HErldMDFANLBp45LVwRqM2v+vOPy1xw0bs9KMVUgeNF+qH/ztMBVFjXfllcy74uHQDnJiSiU+
tZIEUFjbACeCfik4jiNyed+Ouf4wyLhRHz9LFXaTNAHqt0EJGyO3t9hgFIOWxsITTwtpGuvntRs8
AFVWYEgSCI3Bfwi9TWfiz1c9pokSqyUotoEmCll9mzUr9Icw2oUBkWVSMNI1sEjoDQbbgP6B3lxz
dViDAMFg5mstRdvhvufGBaFxQoQL13RIhi+ywRVH/Sc3RBnaDB0mvtl5YGChSykjBoEGCAlVNUH5
fKFEt+tlbs+IHSr/Gj6zc5fXlb10FkDONxY0HhM36fD/9J3ic0/vWiKu4a+npLegbuNRPFr+NMT7
za+tB7eivNj5cEVa3DvZpe939/Q1luBuWrlLH+RlI+T3pcVLvqnco49saX9aWWfXmVYzjJueUaGM
vHaUgvGFYk0lLIMBmHIgLdc/n05f780L7/LbP0eonmt92GmbgyurvHAZ6glHqJHeKo0oYqagVfOJ
l/p4xsNh+WTJM/FJeskdMc/t/xFzYcIXBmnBnvMSe6bFVuiKqKCGc/3fC2D5x8+7cBaMzkCnOcdv
tbmATFRZCjPmgKiLPJaKMh77ptUD9TEkc1hv6y4sktL1bdNqoYDDpFFa4fSoAYRcL06RNBLEZKss
PFIkeyaPc8eyOiXE6wWneJdfEeB/MSVHP9FFeuy5hxix3slpVXXyne9PJ3aoNKgpypr9SiVCZgQf
e96Y455PtwQrGPtCdXTRgqNUHkMdCPGyRAiLysoEQEQkWGb0t19KG9+oIbCgbxLPHnkpi+rNfECr
OZLZl7aKa4ASsurJ86QXiCMtqFBxylhaJQtLA5VLiQgEd3YvQHnZixPoGHYT6NXj0Qyk1uLr9cjP
tOJO7za2cscfoaWwPA+xsMHX3rb8cs6PiYc7CWi0sT6dlwbkZPavCg3CwLGLYnSZoKNNvIly1XgL
3wMPJqbOAUfCEWuWCBf/5g6wVtK9h7w5pU/zZAPDwm1iRf3SnL/znMs5Rhq+IIZQ7cB4239881H6
imsustX8zsOuewSA1D3rq8rBBhmf5pEHPzzEKoHuqpbKsugSRehywackhGDulFNhHBwLhKf6LUPV
7cXo45yUmPLYfAp/gmrDY4CPpXxcw4rM57Nnz/E5inp/jN3/QfOY75/xHRiNufcdt10sBL+3WYkt
fhNwEJpGS20leMm4+cU7jGkKv8kCh/cVJ0tEKWbBMKXpqiMLv6r6z0CExkfuDt5d6HtG6xRgwDYz
U6ndKA//A4ilaAuFOyJNX8QcgQlKcxwHgeNRnrzAf24TZWbnvkinF0Zs9VtfMbnfM1OAWlPCOlaQ
wTfkO1t8tSA/AEMBXjaVkRUs8Zqe/yIM9yT+Jxqp9DxHvj96ULZeNhOXJbu5gZzPXl3EWRS1FTLg
3HooNJsrJH413/3UEiXZosbuGPevLufM7fy5bFaovPLaGwwrYq9n4FEeHfu/pskjiLW2/GCgcwnc
wgo1c0apN7FnjDBDyo+BuIIOWQ/KPwKMXsr1E1ZSC4lqyMqpHkME6EXSsmDFDhrf7GBGFBnDhHb3
JvyeU77EI2fqbv9SlT/iUGkPXEKvkfnpUOihISk8jVyXF07OYv1/OUwIXwYodKztNXD8UXMYn7ue
fdwiGbIEiFL70SA7gdx4XaoNO2l5A4ESpwKhopKTOGrMkd7gkvMknmqp0yJgDFbloXIVGzDZBhSK
d5wfP9jTDe5mnKc3FyKhrM4fvxlLXIsHghebq0/p+zxXrpZ7+N54A6+jEG/bRxI4rXQeblg1sPQJ
lqeJ0rO7lRjUUqdht4O6IbXozXcTPKG/1KWXjlAwpLEmFYRtmvQui2iVE/8LtlbJ+irjEgI/RBkK
1SLX2ezohcGEyh1pAN0CZYg6FGSpwOb0nRADs0czypDfFnX2e9ETHZqUUZcFrmOehUbwJPXgn7YW
DCC6CeiOXJPt6n7IOUFmEqacaGWc4h+mzuRLo93AfBaKg0Id0AY59FghR4ij4iBn323nu2P4c41q
VtWkiMh8WdALpIgKK5inp38rrJjVUTDn8Za+9SUeWqmAT7/xdNvtpCSXwdPkdNxM8p8B9+N38tgG
3FZFGKZATTD+6cz/RjyONHtG5y8Rt+CfK3HRS7i/qPJJFmXdA/1CKWLGLyXBPT6/jXbuA+5Waowq
CY76+7C+Dc3EamwODSfZXK6AWM1ONLPwISe3/r53DlZG6NuaeewfWBlCeBCi4MQLB76m5POn/jnt
7U0REhe2+yiE6/Ns7iG5fY1Bl5Vkn2JJ5qkdOQR0UF8UYCUWBpJXPbAoMLf4wirWTHoJBBTOwmjq
6CEBoQOV9OQ/ky5MViV7xHYaZ++Ng7YBgoQmzGMJhAOZ58h5cN62oq/fozsoH2e52gZPN/qlPz0Y
4FJXP6c/NGVyThv3najn/+m5S7Uyjl/qtEKPu9YLM/FKv2kLm1EcOKG5vSoX+ZN3LqYuFJeuW6jn
8Nzg/njm69zLZIMGuMgbuRp4ZN1Udaeg7S4H8H3QkzEkU1IHnMmnesDKfuzP2jNNeUSCdPbiPDo6
a2lpw+0FLcsWzEi/oHp50T4g9uyypdmjn3RTynb/8xqQbFKTG1QHZV51aaRUpJ6BsDr1qVpD4wy2
amzaiAwF/K/D2l4ucZdCmRHr0axKpEHo+yCYl3Lt6IHePXfLMnW1Sy6zz0wSS3AOd2L2H9trs4vI
ufE+QVOt+Ni7dY9YKEWD28dlafSWfBJQuXDsSu38vz5HEXFpeEstf8VvAvX9wwFJS2q3zqRk6iMe
B6BtbEi0APjkfq53W80boGGIUW3Ey4I/tN5YbWX1s32h8i3SldAgKrb+6TwtVBIt66gomS/0VJix
MPwa4cIBwUJVRf0C2jSwY6UYzCxfbA7kduotKa4+X6CPl7gZCowzXxr7nj+9LsS8LMThRzDg8aaf
xLkIihfhBxiIzOOX+DF0rI4U+1AwFnW2pI0XcwJGweIBWRri8jG8yBoVJsSoyQo7ouK0zBp6fEcP
CCuejcRFAC46cmUPSEPCUXh49rG+70JAq0q5+ZIK13PUi2BsemopN7aldjt00VcF36urfX0nduMD
ySicSW3K9YLL361uC4cRX3O59oOKCSZVgCPIq2lUDapsiVBh4/2csZrW2pRlY7yOuGzvIZJbA0JL
u4Y5iEsHmjo2mEH5RPOsAdcpYauwaBKj0sWD7m+Xuo5BMVkMnFl0DvLHdxaOg9q3eqkmJYRs1E/K
h9+XyqjXP3234ZVZb4Vr0Hr4yFCgwyjQQHURHGNWe0zxwjO50jM7BqyY78sQOtnckAjCut6YoO2p
J1YhQwhMKitX1PDe0SLXiXcB98TxzGq1HBgiBW3vQg5JsotUfck0kh7C1iiTjjXvPmIBw4F2ehRc
Bs7rPj5U2mD6qWZ3PSgymuldNTXw/j1UA4kj3EKnSpigL5zZk2WHX2m3IWRNKi25Re4wty2HcdyL
7lS4KM4hPePebQwAN3r8K2+r+jrrpWovY70jFB2NWDfz9l9x9NdcaHqnl7Zo47h5MulLvp8P/QWO
QiNl6bX7GH1LUcVVpF1ZunvoU+kUxz78cmU2OMCHR+myOJzb2VHssw2FPMAnq86f0tbKWtNeT35p
R9WqPwIoZdL3tLQzIaxe3cYiIfdhwr9uhb3u1sVlnbZGlHZSLX8MDzXkaUKYYj7txxQfBO4p7cCj
80AdSOZNO1+R77E7ZEu2Bt3ZqzlHv5iu0KUF0umGYl/EszoTXx1z5c9mnjbJ+qP99qfn9G8qxaoB
iryYfVpCzpKSopGbsvVoOLtDJvE8wNF4tAqg6hwcKfN3BBF+JzD+WaLZnQByN69mmo5SsN6j4hbU
ZS7bbrQKej5OpOGErpN4PJYuNvONFjSiAQl2sL65JgxW/3Rc8V5VNi9s0XZJ69zfsCZyKaBH2pHO
auyvze13S2+2LK/rCgkdrzvZZzCfh6GX1z56lKGh3v8e/tv769y8QSG1gF9kUCYcTnaZmR/vK9F+
1kJb27ZrhXYFyvX0BJRXZMqSVaRj7RtsP1jlBDJJLK+tU2sFCX+kda8b9fKyHLIEluKs/xWgTpx9
bonWnF93Z+i6Uydz7gNbbku4FWBPEP2HcGRANrUC6eNHuUlWa2PXZlZ4QQgbWi8d5itmyi30U6Qn
DClqazY6nhB+rFvmbmWQZhi1889rsWoMozwLB9GxhXfGu20H8u17bxmaJbNJ+fCxrp5pMetzrU4J
MvdrSXkQ5FJVlA1CNZfPLkgPCk9ZSG7XdBfDZszwPDPlP5yL06QUEQOAHIArQDc0aA6Q9TLo7TRt
sBhI0WpcNo0fqicE2GJNIYsLNKiBVl6j/PSrGWF+8eaDayQyqzkZXyt45uCKuq8EqmvRmwfDuUYF
Pq3EwRnxxbG6DMvX2Qf85tWxmG7dZvmd40CHJsvRkfzUu5sZu2CJ+uyL9DWWncLYAy53m4n4ydB2
qo0hbT0HcdhhVkEpsTcDcra69vB9MeRauYsAUHU9kloEcRiYOwCpbvzMfNA1KezTwp1QMpACHBtI
wlEWKUmC7zLc8uXyHdpbgebGbMZz7fLD1f1RrDD2CWnBp4WuDHpPO4Qu5ySrcyVWArqyDMIB0Mf8
uXYcrPzJxZ0UtHWZ/mMBEu4Pkcdr3BohuXhqwmR8ThE0rDa+9YiegsTyDJBrXGBcXzqJWj8PWK5Q
MsfNVDOMjZftGkIl5IFfhnrPKdjE3T+XhJswf6eT08LyTMAyjq+GxRqrNfRL3smh6664+C7rQ/m1
3TcbaTojAg97Scm6NPVC1l0U13a1KLu8Q6HyIdZV7wCpUKop/eVAzDt6mskLVZJhfKYlJVQEfLPU
nlOsDkb5GKLnklokmVzoVvJjizIbxKxzx7OlfbhmX/pxnQqMZX/ndqtAyKk3XM1eIVuFWkLWjE26
P8eUntNybiyFJ6t3sLn+2RuPSkETax9t0kzZfI1Uv9xOnoclmoJadJtKn/YtpeCGNTpsx8gMs1cN
996P3jCMuamftXtOECYbC/izfbhMPSywrauKdo7ILDg2zoLOkusLxfd1FOWrJ10s98mI1DfVhQxM
L4YcSySNtigAwp7+cWGI+HIJGkg6FfpA984vEeTqYFXh0ZhNHzr048AAuObecgSkPQ0+25rdmZsl
JDxa9h7Q8JCPke4wQ3OR7KCTY2fdKEwkHztpi3x32wq1oCkQz+0DLgKLi9sPn0/PMtt5Gn6/sDKk
CSMVimwpe9TzXBaSsoDgtWBsxpiDS1J5eEE2+4qG9XPE4/ZIx5lS45eeKTJ2SjatkXQNnIK8eLNg
ZEgqmbzUKjg4ciW1csqjDqK9TCt9bi/HIcLpuuRZf27cVPUJB+ZY4b2t7u0BT3m5R8a+sres0cMB
PHX4xtvlHnzwOa2T9LwrsogZIevDfm/2yFSmKPCKn671pRLpfuY4pChKqrbrj66L8I5RgKgD4t9k
7VFGLG9Y7fu2OUTPxb603XDXyWvA3tS3FfuHDCcA1s4I4qShxG6j5ZfLZCWDHq9EZMO7dULw3Typ
bjD+jqps0p+SpUyY+aUy55z6o0Q5S9jtOISPjZy7uRY14n7EsCpGHxQ4uGY8yZJwFD+9CYuGnopZ
eL1bEoHvC9ZhME3IW7gvEgUk9d+bJgZ/ECerDBV0Cb6BG0kqYK3WGi35ch2wnC8R5Xi0tTvL2ope
mkDmuPjrUYq0IorBvd/OypTBd09mtNKi+wx9OLqi3lmPqIMnynWFy/dbv2r7w5RX9WoHhWj9cNqv
OC8q1jKndQlRZT+/w2A3n/n9nxQha+IOtOBzzwvLBDIABcy5bsFSJVdz1XDi1c09GPKE5VNFxWZ6
DgY0xv/aMxF3Wup7p5rSjlRVw0IMcsS19lFiPi2Bc9+TXBMS2czu/s8hlQ4UaAVn/KgvQbx1MDIQ
LbWI0dpBQOEbEGocrdgu5QJQh6HimneXCHECOdPlbS42g7Dw8/o10Bx/mr1LwqCjtGsGzhrR89Ze
VWh2EIWPkMcHWm5SalzkMBVcuNMaoaidX2PoGD4Qw0a7b/auyHOzwFpQqw3+rOMV7P01fgNffJkT
lztzloxYXS3FRUfAZLg7m6Ra+8EW8xLu/4IAeYI4KT6IeuFLJ9osk/h8EO+aFVR+wO3MMyP68d4W
fMZbdGoiOCwhE59WELDb/ZxSwvw1dMkVPNozVX10uB0yJLbz8PhzqARmIQ+ourxUByoTUB8fX1qm
+1StAehfl8Dv1aH7Rc1iYj7/twFbbzN2oHD8TYLQThOMpFliubpRZCognS2hY1cd/0MPSEqOOWRc
KOO2UCJJsOIcUKdKd4MlX0swX6AmiTsvCKXeixZvhXQL3+6hFFPacXWkw15ZkDUNfrTZO57ahEzG
UvLqQpEXa6zqYP1kNyMWQbzLc1ifzXWLWpCP5LvNtoMJO0syUVanub3NVnFGUjZfrs1zb07/Wi5A
RCrkWKYL5+TP+ULlJU1nEangUDjg+ZaasU8oljcqmJi/fvQlxutD54ZnY2lOeh92geJnXEcbS0tC
Zy2fjGx1WrK5TxRm3TOwpP2Hyx8ZZEJylKCd2oh0Q9rGRt7fJM70NcFNPNXmt6bPJy/vcBpOA7/Z
zvbI0zyTTfsYTlmJhszeTR3hK6S3SHMRlx24ZqItPk0FF9oWw5zXsPxj36XwEZcja+HLiWuSjd0/
R8ZjiYvKuFeAqQ2rU/wZuF8Tinwd/V5fUG5WQVdlNOWGhGc0Fjs0huWQaZoWiTsNQML6OBP7Qo/X
pukZwH7dvbLdvUEWH0Wwf3AK7TYR83ITqiHCuCe5vElZ4FCZQv/MVxqrNninD95EktsLvD3VKJR2
uxM6wHLRawJH0T58vnHI/NO8daQnM+2eRu3BlGgWTAAn7S+oh534xo4uZ2Ugb9248AA2eKR3fpd+
+Rl8+kUVj/cK21bo1psdRkuojLjXEGGPJrpp5Ysi+d+mF/yombt4bTlwPk+vSfY7bKHzuMtMRqRU
u+z4KwvC96rn01zNbIh4O0zh5y11knkKrEZ64TFpvBzCSCYUaMCSKx06982OrnwGejd6ay7tuQcr
H//n0te/1ZO/XYMaORmDInYH/yqMEnQsyCWRB36JBpW2OhmsJAWbVYimRgf7Ne6+0ejEfRKnPT8+
laGEsuA0an7lU75zNeFDhNefk1qTHhlcOls+JGkjKbYLRNNPa6gFiukecjS7/iwoobcezTczGwJu
GoGBdNN3ZZEAdgUo278pD+BYyi4hbQ6zW13sjc5axFDevu68xDuO13M0burUjcdN3S6SAoG2m4r0
oY+4kWZx663Riam1/Libh1B26FyFGhU0GHt0sKRHEr8HqD3UJsAzy3HpJghgfOnP86Oz/G6Cj6UP
jcrhScRlmGiYTnlszF+1gqo2URRYV7mLP/+Uc/EuUdgmHFIVnUU1IvXhgPn53DUgPJzXgOIaIqDA
Kmww7auU/0yKsayZghipDjo5BDlF784G/Wx9Wafo+aKS8xPowP9bYB0FS3LYN4WDrDvGHT9IE9N6
wIZazLr8gVys7VQkp1FruAULmVIvlA1x42AJo92FC06vB30focIAq6yCYHiZXQ69JNu3LhpWUOZl
EwswNNK327Z8A9rsOqloyBv6R7OFSV9KqmBGS8+n/XTA3D5Xm1AsiIvAgGj2q71M9A90UzWjfnaF
RZndGDsn5hs2wTa5s1EMoS1Ny/33MRqDdYywfHcre12GkS3GrmulufbGvDDPegtIlGHizeiIBP7i
+kIxyfAzI8LYpTJuuNBzFpn25DjscxWihy3UgB3SuNvo10Mx0rpOTQrPLa5ZTrQtw4athi1dDzR+
0nhNVEZ6d4AefpQJ9FY2vVKGgsIcNjTyvcBrF3/XeJV8lceAhwin1Za4YfmQul3GSr9XH0AfoJTD
CDHVUzePL0BA/22AzbD7Yr7XyyPbfd0JilWmkZsz97eKY+SoQLeZ4CLxao4q2Tqa3fsh0GAg2BSm
9d1yfZsnZEXJ5eLCQmWXnkVpehE94eZ9yit34uWzljHTiVuLycp0ht06ASaZwETnvDbz5r4xwErP
Jed8pVtFDM7TZ2d7nlXj7mZS4wb7+9fB6V1B9Vx3FSZ71vdDBJWXTwuGcSfcRtHVA1BVAbBq0ZHN
XNQGvFhFUTWVtr0rOVHUWGqGMMWmRaJyzujELOMfcU1BhSMp8y19oQkVP5CR6cfOZUVaCiEpbcRS
H0r0+XlzCudX6701vXF+JZVjMSyIZ06oWjANs/JGFRMaOF3uBJSETENWCDWJibkdc6jloVj6A7Ve
JP7e7ID4t6H7clyWUwapiavcflmW/DLB7p/yenIkyWv569lFL0byaHkitg4gMObtnSLcDJLOOoqP
Jy+Mv30NL/tNGtWBZdyTMk88HZZZ2i2Z82mlONIHf5v0QoMDS/NVJhCO8ReXrSCrYKaYtr0KFTL+
S08zNFbiWHlH4fYUwM9PRUeI+LAnoT1hR3+4y60djB89L9EfXF36ZDYTkB90wj07ocVVp1q+BxOt
1Yni5dPVsWMEv7x8L4Ke/vKoRSevsAPOccdkNbJh+yK+VzFa69c32qdsZMycX5NizkyJNko+eo6v
4I7eA3O+f6MuxEtrB/kUxDoRVMNqT3NGAJhF2axFeoLDkF0ZxQ9Tk7H6OBbvmbTd954GY9kI9UDz
TWLREQb6aVxafz6vKkKm4rOeOCd8oE4mwXRujWQGMs8DxXp2xIfx3Q0IajyCOZ4RFDlKlKCcX3jR
2E582PaDki+hpknumVp2MhVIReG/V8uqNAebkWRX9YPSdsEdMjhNpR/7EOSiVpK/7c1Lh6BtwZ+/
cjz8PDoZWE2qvmvQbn2QBYn7jQdlteiTg4Y/f0+Mkkw8EqvrUaBqpBoMu6wYf4XhtRSPIIRQmwEh
9Mb6zHyxr7MfFYmq5j+N0nsJbK2UD5QXexr281v3ZBaL6E5gHD9PcJOgzoqu2jMtyZPMttI1zWDF
KMVg9DO9oz7zPToarPzrcOydqlTsGc72uZtx+2Vssg9DQC3giMLqNqo29dNibC2nIk8nW4r1f/zt
0GuEbTLb4+gDl7w4JldHHYixngfQ+vhXKZk/Cwi4S4fyFYckV75bvzRF8snRFAbNQJNWVoQkKRmi
/Osp4AqPomTN+vcKH00ZhgWga2ppZ8wsB1pCruf/PyHR084IMi+ZA6EgXSaSQdshiZFUm0W1dUE0
UufWyEaL0DsI+kJ7d26to7DQ9bunSuM+6jcEViG8potXDItIbd94NiUZdQsqfopSUWKYvTDlq3nv
13YI+F3SW/9gvDl6zVOKdQok5hKSLaujTSBf3chylSzntpay20wgUzJu5NbHHFufdKhwxqQ+ZQwb
Su/qRKwD/9bzTSs3ADxydQTzf9x9BYMnmGUT80+DINwfC2DsHXLRM6aukg8cOP3Oq6+y2IAnx4jd
WZyN8BPTV0F8NRrTxjcvnntAsiRbL6trHo+nnn6UIPha2/9QTbrkVyuORrL4mEjkKf9FfQzFz5dH
cSTUPMSm3WEJydfaZzxrK0KiK9d2UlNDcmh2SJa57s7GG4wb0W2BJRkSootM1nSVkE7omaJTXudG
EDTwTsJDaG14Zu7RY+HV1JLDVmjc+TUVAsIvtRC5XJUQLbFTadAkzEl8/j5u50VcoNoGKiiRhE+w
qYC8P1mJwgiG7MJh91y3Br81HcAoJhjSMgZk0HkbOCbhmXhbEUZEUWtWtoWZjTMRGPOsG4eAAGwX
jITxxuOMbEdr1JtGJ+4WQhLwwkyUPoTLMp3tfmU8zg47b4AibJhB+4VBYw6pj9u5eZBt+ewuzo65
y5ZfwC4HstR8R5Cj0NQS+orG7/SI9GH7DDqulertAWFIn3NNDD2ZMEqMt67jv1bQE6cAObHWjoZp
sgaDWPI1Fx9X308HbUho4CtN0c5ILVi8tIvTTb89EfbO7X1NdRJJcD3WA4IhjYtEaVbKJ0N9LKyS
s5Qk/IxeyyK7tMIjRAjQo1mV/0Ylb3+aacYE4YjTt4LCf+hOs+rYFoR0nyhGkFdUSQWevJCjdhbP
Qt2nwntHc0LO3rnsMa2pmka3eSKVmDM7PUc0uao+ACz07iVlsEf4hDrySQZEVmrFarJkQZxuTaUQ
CxgSYU+zr5zkx2LLEdLTUwp1NpCouSvZ4sPOLMaoxFhgUkn+K/fCiLqk7X72VsOjIRwUe63lIUUq
I+tJQo1P7krUBSwC5au9YcUQzokQuvwmVOKHJrC/oFveIEgws4t/cQUew2x5/jEZWIBAxAKXpqbF
AbbMHICRuWIsTM8Qvn+DbnHci43oC8iYk7VUqpeMwIo6NeKdTghY9dqL/UNLX5Ni5+r3zxrzldgn
11BDiJiEK8SXNu0o8T8dNgNTwJ+3VuZ4ilYq946aebY2FUWjXTS0CN3mmjFfqplyLR5xmVnvuQnl
UiZan88yR2Mv2T3EhAdS6zRP59gQLFYRsQOGIU8tp5G3qqtBRvJbsp5bHRLHh7a8kz4c3vTBC1fL
AzooPnyl7YQZF1oqV4oCyprS+qHakGvKJ65mf7TF/2IUosN+8j5n3qfx0+Qb5iS+SYsfID3dRs+A
YfUo+Cj7ZBkmKGu+HZJ5HY7C0Qx0ZjtkR0WF4B1F8LoptikBRo8pX4Ph+qFHUTb/CMlu3CRQsOyI
zqvJa0+APkshBnQW57ClYoI+2onevmNyZXoBv5Q81V8dlQkewEkHxHgBevGLkeo6DR4SYgpbxzQl
KUNNQG8CzSCK2bpuoP/OnpUYRaL1BiQJ/EOc5WQu3TVmzVf3efALoQZ/RjHW1Y8liu/Spzrqa/9+
ua2GfCjSOiA8RFSDt+eJzpOFdxFahuSTuAfvkuPSOOD4ZW6uI61evM2+XJjfiLT+piI6imt4fKBI
gLvGxAErSpTz+dQ/ZsdEpWXkTIEcPQtMm9owZplKmS/F9FaKCxQAPftYk5ot1YHakaEjiPaLECKH
+HMCS0NSkJPaoc8FSIh3HgOTXO7Vw7LeTxd+tt7LJYHcokhlcaGdX8YJ9l8f2N0kPaR4ClFUBST6
43fXskreX27DUUvkTpf0sbkEazth2j2teyK32RZPfq8Hn5BM2zwpUWd/7YFIW0u8EzdnUKd0HI6C
5lfWvb3jnpDD8hf/RdhLw49wN+a67H1ME9HmK6yjlPaMLgsO5fvDcPPcMN966Izf2vCK6akFRjlv
qNNpt1XEe13pDbW0BqrZoia+Q+c62pavbIohqLgB1vrfvvbRgSUs3LKt7DcIwi42x6ldVvWqgkWt
8cJzWZla7MQJTbTDzSoQXmDfSpxIkrP7ZGKaasE3+tNTCUAJvoHMiZsrae36PUnyvtp5L4+0+iJP
i07i0OFlrNjj2jVi7Tyh35BL0soBEkxwPTYDm4vuXVpMPPwvH/xlRK7zwbqXfgB1WGIeEu/IWx4g
KCqSyBzz+2OEW2QFsoilN5HkKw+KTNeB6jRObhyQR40x0IVo3WOxUe9WgtEkVrBrAfg4U0E7S4nD
mcq8w2857gOrSIhkqnVyT/QtJil+iGTWbtza21ngBqdVebAZId2GYGafttI8xz4ecMubBM4IHfdJ
Uv6YbZl7jucnD5QUQIhl/yNs5k3xhPkpgJD09Cq+dg0bpLn22ZUlhCoszYTv8k4WsliT1jKSiIjJ
Qky4j6Suct7wwCvfLTn1PdvK8K9Jysl1GwYZoVPmFZoA4oBcbu/eno5LL+1yAk/4J/Sw3Qy2Njky
aenyEhNjUBDgW9vCvHPFKIpdEk9RcIQFIdGp6svNBiJCSz0CtA9XOzmA1IT0XEJmcgqNDXpR3eEj
vRmCbMi4KcRiPCCyTgPxBuqQjyRithLDmZk268U5wVDWXlerQjLhFStR2klKwuYRGTngysUA5smM
X/Z0D+2xXiZp/zXm9VdBLmxLKNon8e++8mfvWiNjWHCtgW4o8QQblGYTUQN80Y02TLQChWXIRdag
Fzv8RWY4S87K9L26YNUXCJ8JgN/UxqIJHB7v55MPyEDQ9db+ABrOeJtYpeg51POOesdl5MLymmTw
6ruz7E8s0OWO7lfbTPDJW96y9tICPTMt7d1D/n0pnp0MUGQUOJ+CUoeH+E6sa1IboAeHNWcX7p8X
4OLBMV8hC82A9mPS59P9A6OpFlnfUU7puIAO1IStjzD2M6ROgpysU4t4U5hjRs5sGNr3PKBTs6rk
vQkJNeLaBYc+D7m3wAta3JvCnLAn2AazLjkiCrrB7ZlkPlj/YuhdoXjx1ode6o8vqxHNbBINKAQG
SWjUtIhxgE/lMRAJMtrtvqq71XjHKlr0fbIkQa3gkqyibwDd+iQa4Vdgy+0FTMj19kbsod9c24Z7
kgk9k7LfrWErD7vlMPZSR0UTdqpS7tUApK1ro/42tIrR7b2b8oInQdLekzm7M3eEZKAtKbtvaDtX
yh1rehAKKN8Acc+NEoY5YhU+NbW4dnt5Xw5fxX2zECUcZ83sG+uPscWuMUjPwyt+SbJmK70BJka0
HJSu8BR5MQBJ0hqbG1Dl1pHWavP3U5/vnT50N8wzBxc1qYM+1LA4PzdAjnlIGptsgqLMmQiJSjGr
SuQ0cgOloQrEfNCvmJCx8hLaQIfs6gZASjnRtNqSGsrsu54/wOGTVPFaDI99GSLwW1tepUEgum1y
u9k8CFc+EilkcrPL0exWX54my2zyz2z2+hgXgnSRoSQR7JKsLEg1hOO5O86p4ECxg0tuEK37jZc0
8id4+BeUz9Bsu3lmMwU4ga4TDbY4sUHm7VVfoVpOXYMsSBoIha+OiaIWJRfbBpaD6UvO494RkhMu
/vhhOZZmBmCTerX/VqozQJM8YqSh1fryEFysdEP8GjiBD885njFDZyAp+q6f/cgRl/v7dNuSxF3g
3RbAb23+CE/j8skU1Pg2TfZCQ1flJ17ayYaMjuoJTcjVAyLOtEyfHb4eZeZ9tRrfsr/TglR5nWNo
dEWrkq88JCeJikc/bA250nNbvXElmlrrG7VIMG5LYE0rOi0bNXvV++cm2DPO9xSY6aPhCaoYrx7A
bQZMYTpOZ7JRNP91BjfPNn8P5RAQnU+PZpNvyVSAuu7MlzfGEcmpXGstJqkLejAEw29Isyiw3tDe
JfzLrDjD6UXbBAUPMSCNKq3TZIrWr8t9S1GO1bURNMNndXtqm64zBpkuclxu1aVUPILfQ4gCud/7
2v/h4bw1GoEm3SrZIA4LgqGV5NZIKOwv3HWxXA68XPvLjczQsw6K1xZWhvxwsXULLnpnbCe7qfbZ
vIRd8CZOfCr7J5sFgEPx+hu6WuwH0bSJiqyme19wb2gvThU24T1kJRKH1kMi74QmPkkt/jn74dE+
Bnj3sxl64xGcRsLBSH8xit1ZqVUttyD+JZGzySnprPczPJs0231sNaAkJ9Lpd8QMdddwAFrYG1B4
hKuBe4tydIRcdCVaZTGeNaF8AcfxoLNen7pNNoC/HFznSB7hkqlLTLRC7iDHSylvQ/mPbECh04eU
t8258OJ+tEXMw3pDjac266RDFU7hDCUGtT+27iDzWaY1RHjeVZEVO7W3YtfnrTsQ6BjxOQVZc6Sv
oIgxy/VDf4hUmOxJyE30sR9jaU6ij/eBu8qHtZAun/esi84shKQGwD+8xyscuU7O0yBP0JXLaS6a
6QnTzChy89TwvkHsqoxZi8/Wsn2sbWpJVq/yoJt6OhowDY936sxMpVuYDHQhL0bhl5NpGS7G46tf
qTP+V58jz0P7unq47wSHgDpjahjy5R13/2AorbYEYfZq9TWkOSwft8MABl+YCan/IBHHT5yRH7tt
TUyVIY+e22014ObvI+Iy8ESedba9krgo5aqDj+WCbnoPPtTxjiIZ40w3f5ybVS9XFnOb+yqLj8zz
KK79WG5PR4tb+rPdMDaWI8OAxL/avJ8je3/hdBEcmsGfbWER/vO7RGo5HAR+5O3lasQoX34qzOgg
bdEwlcJdWr9AQcCgtfYkSo+TLLegiFF6//OTq7DCVXv6Yv6OtZ94OYwL+bLnPsjgfLZ3lgdtwE57
p4maJTKXrZkHgEtoxBFVCLWNjsjspPqfR27WjOUpRKrSYgJXeiOClVFf4fzS7H7cg+dMSQUeUI03
/0lb/9lbve8JItRbfkhOlN5KjZdGZWcoIvwYtDrA1rw1vZi8m3L+QOhW4n4ovdhh4UP+xSSaKShu
2vPpvdeMa124a6bOfwmsDX6w4D5u+2c9tJqrpZU18XaE2VrGvd4ROl5Fg6Rel4xOUnDSmyjy1poG
BRyj1dfKtl7cNcpl5ku+UVDr8iRikL0l35w3taQsgtN616KA/Lr276KTi81AoV0mQJATF5HJ2797
1sT7sng5j/jvzrVeqo4E2/T09yZ1O6DK5+TH+gS/3CGg8+EGDFtZvBj3GRCPzlsbc+2cZiM6CNJJ
fTJgkA1FXUDZ1cqqsqSGvjdSfgejH6pTnn++1J2wDx1Mg7lnihUmgjJA/8iLmeaVOSguEXZARw8S
eakCASqbSz678pJJTaSFQx1QXht4LjcMp5MuV1wEc6X1EuywXC/f1YU617WRsodX3dT8xQSkoGJZ
P1D+hTTUZkKy5DU7cUaL+xH6JRjAA3g9ZpMiIXnU2b/haFSSN2SkM/wh31IW/7DhfWEY7qYZtc3K
oHjogXAHzQistfuYbs2mj0/w9xpMbvrKoqX33qyOX/F+dkPmLSlIvGiYhsF03ga5BaX70DcdWdw5
MQHShilc7AVqWgT3fEYAbwXILDdfyelDBXHKVzkk2xoqneSe+Px2d3Wm8ScJDeDqpmzgo4Fti6zX
zrpiJusRhzBzxd1KvnKdm8jRrZtqsTukejFq7Njh4D4aptYpQhVIywBQ+ZSTz663wJgRAJ3Ib5Af
IWWu2+bQEB66O32iBIvBYLEI6YcN9H2LNmmaMnmotSa+8nfFPnK2Q++2axoMgSU1Vpn7Txoup642
QqrAmzH/BRbz3IFH51cw268eBTnokqyG36LxgduhiMcFgXK1LY+7M95zND6aOcomNgqYtxrWdiRI
8lqtGC6daKi7xJZvxC/JvFw+r10HdAw1iNiprFoIRU7vpCU5zne5g77ta+IlMOIhGVMH88+Aec18
4XwB/aRHL4KiBDxqFAcugHUDzfvms9LX3VnJ8BCi9vR9w/F7YMLU7Xsp9ENp2H/mOpP1kyO9uPKR
X7L3pQaRQ5z+jBpb47eBLMBBBqNbtPFQoz0aJ3PHTL/7hvmHaJGaRRiVVLoAPdSQAdAh318nqbAF
nDxG8pfrMd2+38KU7IJQbxlxnXBVTP8+FU4l6pauO2e+pFzJQdUegD2DjRyb7vL198VeIFunOyeI
ENTpRSXrDTiHrJRhddEvYY8NCUd90xhj6kzouerEZptK6sRppC+oPTbmJ2EczqMWSVAsDF/Oe7sh
rzGr9vdQvSKyetq4+ACJT6CakuwFIVR/HvFaC/tKVH7sfLG+Umqk/KGdOQ5beYsl5PLekJMMrg9j
nuO3EQPDgvcjzROfTc3ECE1nmv38+oldgiJTCbvj19dvh/DPUVrJ8+o7X4dVQugfat7ktu5+FrRb
xGidno5/FvEB7M9juxHODybVXJ33JeAXdo/2M41qZXG0U5JgHz3nwgRFIugrPEVa9QB+5RabwDst
vLCRh1KFBt7O+ZBb7aBv3/5QnUXA9hT5Tn9BHO5/H4Ym0IodcnflPurVQmAw9VGM7g1wpX9MgcNc
/H2XTPlZlI0FD8xLWMu11Lqadh7gYCE4c+lWv+FkJ88nWjD10YlQqNs0djFVPIdHMIfzR4yFdzYP
N0JcXfzUM7tyY6vWgb4356vvjJJbi7jGmeZ2sxd7tmuErs+1A1dF8h+NjMu1KnMWfi3XjpRJL5he
ZGdzFBsWx487VS3I+a0XR7tRM72NQGC3rptIFW4q9cgaNcjEzCpMdStLZBNeSpSJfp7C1yt9qeYO
OY+/d4AC6h5F6vayLv4mpwIfvAuuBGCot4M1B5/UQQcgGIxr/SvBD+tB+5tr9S5ygNIUeG60nFlN
rzzEEx7qLx2sTH+v5F1KyFVxmNK1GCI6/1mgAdt3SpDc/F97NcByDVBbUp1CM564/UyPYc578HKu
YCxKE1GMCz1hVGmGVv3CV/q5UFaa8xOrKmOIyKtruSjyOw5b9e0XDkd16/i02YLPNxEYPG/HN1hp
RNCdgG79umWT1A6rhzs1M7JqAFm5LWakTiIKPCoOLU4SNc6ppQkHmfzCoelPLg03OjGrBN55//uz
LL931PhBrOM0iNJzaqzPN3GRzWy4YS+2YnxcO3h1tVO11kWUvcOmDUuBJCYE6qNBxes51EK6L6sy
FvRyKq5UcQ8d4xOiIdglGBB/KnDHvXpBJ4gZ979bhv190Nlxg5gdJFeSV6/sSh3D/UcQUgZGn7Ra
TtbEdE02H/EkF0hR+cBI3WSxC11R5iD9nAjeLqYMJY9q62BNAO8JLDOP9hI8djl7ok+xM7dHQB0x
u43CmtlYyEjmnAYJIE0VjVVR6YjYT52C6GrI2KKZaCpPVhTCpkT+jAirFfoXaJLgchL7j9xORRGY
TqnFqrccEFl0nPJyQ5zC6X7qu5yKDECUps3oPnICmDH1OaDtmjw5SCooxH0EpT17KkBSlxuR17c0
9lhcOLt6wAAAEqM9U+usVkouP6dTqWQBRLgrvemiYWyBK81P4U5FkxGJiELt5d7lN2YZ3AyPFkxP
aZ3VQ8Yv3LTKhBGaG0VdhQ22ru5trK9etg7w/YG/57gwKM4SOHgjGxuoHcq5PwjOYCOuBPTwsA2D
PV4g6a/JSVXUKnNgqJ764EkwM3txB7GsC+XLJ/gxTf8RFQCWSMeTcamdRqz3TkuGNVWNOImr0pit
ORwCHbOy28HrWbf3scW2MO38pI2ymbo4xe+DLEdpVWYeaFyCB9A6igwUU26r9MresrDwS9vPaw1k
z4F9ALDLsyGAdQWMU4DspZvF1NAPaoRbYFBHUrCeSEDicBJqTH6sjDIzflNKeWw1ohDpZa9Z4wbp
qS9TKjso6BLJeyAfR3ogsmZ4L2jDv6aB+S2J409WaaxfuWofxuqEs12uWeQf0RvsuQfwqA7lXHAO
cXenF68bMQ453+73YSTYFGJuxtgrLBkFhCgq8XSd9FHVP8D0DhEHl8OrXMjFlFQMgbiWWLjvjpxM
L3NRtJx4Gzq419UvpQDqlfoNSlXlrE9AweJyzy3RrR1UJaz+Po7txNVCKJhJZds94fgNSjbKAhRT
GzkbjRqz057MzwvBw5qtA94nfJI+FmLgd8lM3ynO9L2Ff8nGwKcvEOneAl2adYRKnXs1GxzrSqnS
lmczy+yr30DNOIdSOZcVCIloWY/5iDcEZPU0SnsGRWkqKZtufhOfkd79DpnvY2OL7RQqFUptWpUm
0oxlRdTJWP8n2hRZIacIZKiOpb2HRqwvINDzzemYP0yUld8+pfqJJroi3q9DuYojLORQLKJaGNdM
VlliHzrxT/mRQ3vVYeCcGER7MZ2fjpYM+De3grKbRskbU0Xnvvog+Iqgd+/xClqoY+ClqD4WvmnJ
Kjh6ASCbYOIYXpCi1Z+x6K9zhtD9n8KzhboRkXWxrA0wDsCizwpk0GN9j7iJKqup4lgca92eTaL+
wXZLuTBZ4iX0VIG/JFlqB+IFqUjNTq6QA8tcGcnBqjqkA61otp9oRkmgdwBENE8YnP7gfx7+9i8K
4FKEh+pJZnfyNq2Zpd6fsB3y1ASbV0S9dah7MVeM7cyy2T8bC+mQm+CGRv3WmLnJg1X1SzvAplno
W96DNBfFPFTfmtOLOEld8y875xFcubiuK4Rz9XCo0EzDxJn6Km8ASsyh8JfEcYNgFPPIBxYOi2vL
2dhb1lTiWCM14LqqQucPBKnTPlzeVV0fwBILBJn9NNbU/q/158xGSgt5dqBCKmEpdhqsLjF1k1fy
TrfY71YtmGUGJakFMT1xJlbbqCTvM87l9XgNgUIDQl1muKItCE5ZOoI4XCVK94Nh84jo9gMZ542f
0USfy33/zW6vUSnr7e+BJgT56FqJ/UHt9ez29WXxqNzAg57DmHS55HpKmx2XQdalvmUaBDTFIhmo
tPwkLbbkOC4jUjLCBOTPYoRwuyCq7qmUR+RPKntRH1ZNqw4KawLiFX/s2Gh8aKLcuCO0rIfLBybz
H0QCfAHGbTZQvIyxxqKtESS1Ka2Vv+ZHle8dbda6L1UUJO3ga1jgYRb5mqVawV3VRREUBcp1yKuk
jjIFvhVjbHDIqoS86JAOhSqXqfjl5cFbyxQEDGy75EGLG410/b+Ipe3YHMOjQTW74t7pxA0AKZee
HKk3HUspWjm6rXzU3WdOlrEvLyUWrk3oPMxsBX4wMKkN48zVxizXWQ+u61s0SVIotpm5ali3aIDP
Rg/vsTOon8SlaxYIOY3WUKyl1Jl8zbU3WKV+zP3v8StZQ6JAi+IPjDOJoRIXFLUQTiYPocRVsJ0c
Z3bmDvFTY3gft5T6QUGmTpgQVjmjiv5MBG4uqthzn+7Re7oSMDmLgQ+a7W0idTJBZkC8T7XJJrV7
M9iY6Mi2t2z9p97fH3g2Q0ONKMcPqPSCcXcdou2xr2RUD+h3paZOOKxb5zbLffzMvpvpvP/LVP6D
qyYGwImvX354hZFgQjip2tvmR97Lyh81gMD1GK8ST651vaRpQzLVE4OSyTRheVOwRFIcsqdg2nfq
s8g596wKQmHGQb0uHjFL3hJsDOm+PlNyuUjEZC+DqUOzurAyhm0mXR76kbYfGYtijaNsgNWJaDB6
8GEjfFz1QALeB50CZzR+jL7hwxSRaLOWLUmTshYIzyaiDBTMq9g3rOPswR1OpOXwXXfp/e+a4dDa
vDMwPZr7APNPkHDoq4kxMiPESoLD/AtuKjsXSvacv5aD4iQ7eV+ddnGezOKsP1/huMHtQl7iQpyQ
wipIy1q3gEhim53msEs/NQDbQU7YBBbJEyo793FHrokZCG8WJM/LnpGcinBogaO3Sa/NLJ6ata/F
sBNmfpq5pW5TjUFfNx2j8iJiXDg5QQMUif/mGLeumwfrZIP8+bwrGCHs45smoKVS7DsHcGuZxJjw
lCXadtgBvyQc3NuWzunmKeiXtEY2ljey1UpqlavQO6CoCvUvXqGmRQuzBwcCDNNyyKFVo/kBjGCa
gc81763AfkE+DKkUHEB2tWnEQKpgD1HHOpTQMz/MKrnS1+GKVls3LeLlFPrlyX75y1Nm8Fo14Hj3
avfP8TCR3RsWPTxNqBQzOY6wseqzDVT83hsvF9OxxX8IK/dD0WWTdqCTTRktHK7CLpkpp019M45J
QsVxvZMhzE2n5Hu0jMimBcUlHTmyWTSv8PMVG+vz//WZye7Bmsv+5UraNYtJRTYQJGpdqypPOQ==
`protect end_protected
|
--------------------------------------------------------------------------------
-- Title : new Wishbone Slave
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : wbs_new.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2015-03-10
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- Wishbone slave module to receive read and write requests from Wishbone
-- master and to return read data via completion
-- Due to different FIFO data port widths (32bit for WB, 64bit for RX & TX)
-- storing or deleting dummy packets is necessary on the WB side.
-- 1. RX storing 64bit wide -> delete 1 dummy packet on WB side
-- 2. store 1 dummy packet on WB side so that TX can read 64bit (otherwise
-- fifo_empty will not indicate 32bit contents to TX side)
-- CPLD := completion with data
-- CDC := clock domain crossing
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- * wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity z091_01_wb_slave is
generic(
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100"; -- = 1020 DW, one place spare for put_stuffing
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- Rx Module
rx_fifo_c_empty : in std_logic;
rx_fifo_c_out : in std_logic_vector(31 downto 0);
rx_fifo_c_rd_enable : out std_logic;
-- Tx Module
tx_fifo_wr_head_full : in std_logic;
tx_fifo_w_data_full : in std_logic;
tx_fifo_w_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(4 downto 0);
tx_fifo_wr_head_clr : out std_logic;
tx_fifo_wr_head_enable : out std_logic;
tx_fifo_wr_head_in : out std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : out std_logic;
tx_fifo_w_data_enable : out std_logic;
tx_fifo_w_data_in : out std_logic_vector(31 downto 0);
max_read : in std_logic_vector(2 downto 0);
-- error
error_ecrc_err : in std_logic;
error_timeout : in std_logic
);
end entity z091_01_wb_slave;
architecture z091_01_wb_slave_arch of z091_01_wb_slave is
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
WAIT_ON_FIFO, IDLE, HEADER_TO_FIFO, WR_TRANS, RD_TRANS, GET_RD_HEADER,
DROP_DATA
);
signal state : fsm_state;
-- internal signals -----------------------------------------------------------
signal tx_fifo_wr_head_en_int : std_logic; -- internal enable
signal cnt_len : std_logic_vector(9 downto 0); -- packet counter
signal cpl_return_len : std_logic_vector(9 downto 0); -- count amount of CPL data
signal put_header : std_logic; -- valid signal for put_h0_h1
signal put_h0_h1 : std_logic; -- qualify which kind of header to store
-- 0: put h0, 1: put h1
signal get_header : std_logic; -- get header info from CPLD
signal wbs_adr_int : std_logic_vector(31 downto 0); -- store wbs_adr
signal first_DW_int : std_logic_vector(3 downto 0); -- store first_DW byte enable
signal last_DW_int : std_logic_vector(3 downto 0); -- store last_DW byte enable
signal length_int : std_logic_vector(9 downto 0); -- store length returned with CPLD
signal max_read_len : std_logic_vector(9 downto 0); -- max read length for RD_TRANS
signal wr_req : std_logic; -- active while write request
signal rd_req : std_logic; -- active while read request
signal wr_burst : std_logic; -- active if burst write
signal rd_burst : std_logic; -- active if burst read
signal max_wr_len_reached : std_logic; -- break if cnt_len will wrap thus 1024DW were written to FIFO
signal multi_cpl : std_logic; -- asserted if read returned in multiple cycles
signal rd_trans_done : std_logic; -- store if WB transaction is finished
signal len_is_1024DW : std_logic; -- if asserted length is 1024
-- 1024DW is encoded as len=0 thus
-- needed to distinguish from reset value
signal compare_to_4k_len : std_logic; -- enable 4k honoring
signal to_4k_len : std_logic_vector(9 downto 0); -- DW counter which holds amount of DWs until next 4k boundary
signal requested_len : std_logic_vector(9 downto 0); -- save requested length for reads
signal act_read_size : std_logic_vector(9 downto 0); -- actual read size composed in IDLE state
-- registered signals
signal max_read_q : std_logic_vector(2 downto 0); -- used for CDC synchronization
signal max_read_qq : std_logic_vector(2 downto 0); -- used for CDC synchronization
signal put_header_q : std_logic;
signal get_header_q : std_logic; -- define 4 stages of header aquisition
signal get_header_qq : std_logic;
signal get_header_qqq : std_logic;
signal first_rd_cycle : std_logic; -- first cycle in RD_TRANS
signal wbs_tga_q : std_logic; -- registered copy of wbs_tga
-------------------------------------------------------------------------------
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
----------------------------------------
-- assign static connections for ports
----------------------------------------
wbs_err <= error_ecrc_err or error_timeout;
tx_fifo_w_data_in <= wbs_dat_i;
wbs_dat_o <= rx_fifo_c_out;
-----------------------
-- decode max_read_qq
-----------------------
with max_read_qq select
max_read_len <= "0001000000" when "001",
"0010000000" when "010",
"0100000000" when "011",
"1000000000" when "100",
"0000000000" when "101",
"0000100000" when others;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
--------------------------------------------
-- register different signals using wb_clk
--------------------------------------------
reg_proc : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
tx_fifo_wr_head_enable <= '0';
max_read_q <= (others => '0');
max_read_qq <= (others => '0');
put_header_q <= '0';
get_header_q <= '0';
get_header_qq <= '0';
get_header_qqq <= '0';
first_rd_cycle <= '0';
wbs_tga_q <= '0';
elsif wb_clk'event and wb_clk = '1' then
tx_fifo_wr_head_enable <= tx_fifo_wr_head_en_int;
max_read_q <= max_read;
max_read_qq <= max_read_q;
put_header_q <= put_header;
get_header_q <= get_header;
get_header_qq <= get_header_q;
get_header_qqq <= get_header_qq;
first_rd_cycle <= get_header_qqq;
if state = HEADER_TO_FIFO then
wbs_tga_q <= wbs_tga;
end if;
end if;
end process reg_proc;
---------------------------
-- manage FSM transitions
---------------------------
fsm_transout : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
-- ports
tx_fifo_wr_head_clr <= '1';
tx_fifo_w_data_clr <= '1';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
-- internal signals
wbs_adr_int <= (others => '0');
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
elsif wb_clk'event and wb_clk = '1' then
case state is
when IDLE =>
-- ports
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
-- internal signals
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
------------------------------
-- wait until active request
------------------------------
if wbs_cyc = '1' and wbs_stb = '1' then
wbs_adr_int <= wbs_adr;
first_DW_int <= wbs_sel;
----------------------------------------------------------------------------------------
-- calculate length to 4k boundary:
-- wbs_adr[12] denotes 4k boundary which is 0x1000
-- maximum transfer length is 1024DW = 1024 *4B = 4096B := 0x1000
-- => if wbs_adr[11:0] = 0b000 then all lenghts are ok
-- otherwise calculate length offset to next 4k boundary, use to_4k_len as DW counter
-- subtracting wbs_adr from the next 4k boundary results in a byte value
-- -> use 1024 instead of 4096 to calculated DW counter instead of byte counter
-- ! manage first_DW_be and last_DW_be accordingly
----------------------------------------------------------------------------------------
if wbs_adr(11 downto 0) = x"000" then
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
else
compare_to_4k_len <= '1';
to_4k_len <= std_logic_vector(to_unsigned((1024 - to_integer(unsigned(wbs_adr(11 downto 2)))), 10));
end if;
if wbs_we = '0' and wbs_cti = "010" then
rd_burst <= '1';
else
rd_burst <= '0';
end if;
-----------------------------------------------------------------------------------
-- if write request and TX data FIFO full or
-- read request and TX header FIFO full then
-- wait until FIFO is empty again
-- for both read and write requests the header FIFO must have at least 2 DW space
-- (here 3 for easier checking)
-----------------------------------------------------------------------------------
if (wbs_we = '1' and (tx_fifo_w_data_full = '1' or tx_fifo_w_data_usedw > RESUME_FIFO_ACCESS or
tx_fifo_wr_head_full = '1' or tx_fifo_wr_head_usedw(4 downto 2) = "111")) or
(wbs_we = '0' and (tx_fifo_wr_head_full = '1' or tx_fifo_wr_head_usedw(4 downto 2) = "111")) then
state <= WAIT_ON_FIFO;
elsif wbs_we = '1' and tx_fifo_w_data_full = '0' then
tx_fifo_w_data_enable <= '1';
wbs_ack <= '1';
wr_req <= '1';
cnt_len <= ONE_10B;
state <= WR_TRANS;
elsif wbs_we = '0' and tx_fifo_wr_head_full = '0' then
tx_fifo_wr_head_en_int <= '1';
rd_req <= '1';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
else
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
end if;
when HEADER_TO_FIFO =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '1';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= '0';
put_header <= '1';
put_h0_h1 <= '1';
multi_cpl <= '0'; -- new read startet thus reset
first_DW_int <= first_DW_int;
last_DW_int <= last_DW_int;
cpl_return_len <= (others => '0'); -- requesting new packet thus clear cpl_return_len
rd_trans_done <= '0';
len_is_1024DW <= '0';
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
-- NOTE: this setting is not always true as this state can now be entered for wr_burst as
-- well but it has no influence on write bursts so it will remain unchanged
if wbs_cti = "010" then
rd_burst <= '1';
else
rd_burst <= '0';
end if;
----------------------------------------------------------
-- update address information for reads because multiple
-- read cycles without transition to IDLE are possible
----------------------------------------------------------
if put_header = '1' and put_header_q = '0' and rd_req = '1' then
wbs_adr_int <= wbs_adr;
else
wbs_adr_int <= wbs_adr_int;
end if;
------------------------------------------------------------------------------------
-- don't clear cnt_len for writes because this info must be stored to header first
------------------------------------------------------------------------------------
if wr_req = '1' then
cnt_len <= cnt_len;
else
-- cnt_len is not used for RD headers so it may be cleared here
cnt_len <= (others => '0');
end if;
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif put_h0_h1 = '1' then
tx_fifo_wr_head_en_int <= '0';
put_header <= '0';
put_h0_h1 <= '0';
----------------------------------------------------------------
-- 1. if max write length was reached split packet by writing
-- header and start new PCIe packet thus return to WR_TRANS
-- 2. for reads write request header first then go to RD_TRANS
-- for multiple returned CPLDs this state should not
-- be entered
-- 3. if neither write nor read request then FIFO was full
-- during start of WB transaction thus return to IDLE
----------------------------------------------------------------
if rd_req = '1' then
max_wr_len_reached <= '0';
state <= GET_RD_HEADER;
elsif wr_req = '1' and max_wr_len_reached = '1' then
max_wr_len_reached <= '0';
tx_fifo_w_data_enable <= '1';
wbs_ack <= '1';
first_DW_int <= x"F"; -- set value for next wr cycle
state <= WR_TRANS;
else
wr_req <= '0';
rd_req <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
rd_trans_done <= '0';
len_is_1024DW <= '0';
cpl_return_len <= (others => '0');
state <= IDLE;
end if;
else
state <= HEADER_TO_FIFO;
end if;
when RD_TRANS =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '0';
rd_burst <= rd_burst;
wr_burst <= '0';
max_wr_len_reached <= '0';
first_DW_int <= first_DW_int; -- unused for read requests
last_DW_int <= last_DW_int; -- unused for read requests
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
cpl_return_len <= cpl_return_len;
len_is_1024DW <= len_is_1024DW;
--------------------------------------------------------------------------------
-- there are several possible transitions:
-- 1. CPLD length is the same as PCIE_REQUEST_LENGTH
-- 1a. aligned address and even length => no action
-- 1b. aligned address and odd length => drop 1 dummy packet from RX FIFO
-- 1c. not aligned address and even length => drop 1 dummy packet from RX FIFO
-- 1d. not aligned address and odd length => no action
-- 2. CPLD length is smaller than PCIE_REQUEST_LENGTH (multiple CPLDs)
-- 2a. return to GET_RD_HEADER and wait for next packet
-- 2b. don't write a new header to TX header FIFO
-- 2c. manage address and length as described in 1.
-- 3. WBM finishes transfer while more data packets are in RX FIFO
-- 3a. drop data until PCIE_REQUEST_LENGTH is reached
-- 3b. remember that every split completion has its own header info included
--------------------------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif rx_fifo_c_empty = '1' and cnt_len < length_int then
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
state <= WAIT_ON_FIFO;
-------------------------
-- single read requests
-------------------------
elsif wbs_cti = ZERO_03B or (wbs_cti = FULL_03B and rd_burst = '0') then
-------------------------------------------------------------
-- aligned single requests always include a dummy packet
-- not aligned single requests never include a dummy packet
-- I/O completions are always aligned
-------------------------------------------------------------
wbs_ack <= '0';
rd_trans_done <= '1';
if wbs_tga_q = '0' and wbs_adr_int(2) = '1' then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
else
rx_fifo_c_rd_enable <= '1';
state <= DROP_DATA;
end if;
-----------------
-- end of burst
-----------------
elsif wbs_cti = FULL_03B and rd_burst = '1' then
wbs_ack <= '0';
rd_trans_done <= '1';
-------------------------------------------------------------------
-- requested length is reached and data is transferred completely
-- drop dummy packet for aligned & odd or !aligned & even
-------------------------------------------------------------------
if cpl_return_len = requested_len and cnt_len = length_int then
if (wbs_adr_int(2) = '0' and length_int(0) = '0') or
(wbs_adr_int(2) = '1' and length_int(0) = '1') then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
end if;
---------------------------------------------------------------------------
-- drop all outstanding CPLDs but capture header thus go to GET_RD_HEADER
-- from there we'll go to DROP_DATA again
---------------------------------------------------------------------------
elsif cpl_return_len < requested_len and cnt_len = length_int then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
---------------------------------
-- drop all outstanding packets
---------------------------------
else
state <= DROP_DATA;
end if;
-----------------------
-- burst still active
-----------------------
else
-----------------------------------------------------------------------------
-- when first_rd_cycle is asserted and cnt_len =0 this is a 1024DW transfer
-- -> remain in RD_TRANS
-- in case of PCIE_REQUEST_LENGTH = 1024 and full transfer then
-- cpl_return_len =0 and cpl_return_len = cnt_len would be true right
-- and we would transition to IDLE too early
-----------------------------------------------------------------------------
if first_rd_cycle = '1' and cnt_len = ZERO_10B then
state <= RD_TRANS;
elsif cnt_len = length_int and cpl_return_len = requested_len then
wbs_ack <= '0';
------------------------------------------
-- check if dummy packet must be removed
------------------------------------------
if (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
else
----------------------------------------------------------------------------------------
-- calculate length to 4k boundary:
-- wbs_adr[12] denotes 4k boundary which is 0x1000
-- maximum transfer length is 1024DW = 1024 *4B = 4096B := 0x1000
-- => if wbs_adr[11:0] = 0b000 then all lenghts are ok
-- otherwise calculate length offset to next 4k boundary, use to_4k_len as DW counter
-- subtracting wbs_adr from the next 4k boundary results in a byte value
-- -> use 1024 instead of 4096 to calculated DW counter instead of byte counter
-- ! manage first_DW_be and last_DW_be accordingly
-- wbs_adr is the last transferred address here so to_4k_len must be reduced by 4bytes
----------------------------------------------------------------------------------------
--if wbs_adr(11 downto 0) = x"000" then
if (unsigned(wbs_adr(11 downto 0)) + to_unsigned(4,12)) = x"000" then
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
else
compare_to_4k_len <= '1';
to_4k_len <= std_logic_vector(to_unsigned((1024 - to_integer(unsigned(wbs_adr(11 downto 2))) -1), 10));
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
elsif cnt_len = length_int and cpl_return_len < requested_len then
wbs_ack <= '0';
if (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
else
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
end if;
else
state <= RD_TRANS;
end if;
end if;
when WR_TRANS =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '1';
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '1';
rd_req <= '0';
multi_cpl <= '0';
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
wbs_adr_int <= wbs_adr_int;
first_DW_int <= first_DW_int;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
if cnt_len = FULL_10B then
max_wr_len_reached <= '1';
else
max_wr_len_reached <= '0';
end if;
-------------------------------------------------------------
-- stop transfer upon error timeout
-- if TX data FIFO is full suspend until space is available
-- cti = "000" and cti = "111" signal end of transfer thus
-- put header to FIFO
-- cti = "010" states ongoing burst thus stay here
-- if max wr length is reached put header to FIFO
-------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif tx_fifo_w_data_usedw >= SUSPEND_FIFO_ACCESS then
if cnt_len(0) = '1' then
tx_fifo_w_data_enable <= '1';
else
tx_fifo_w_data_enable <= '0';
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
-- full FIFO and last packet of transfer could coincide and would not be covered here so use wbs_sel instead of 0xF
-- if cnt_len = 0x1 then last_DW_int must be 0x0 as single transfers only contain first_DW_int
if cnt_len = ONE_10B then
last_DW_int <= x"0";
else
last_DW_int <= wbs_sel;
end if;
state <= HEADER_TO_FIFO;
elsif wbs_cti = "010" then
wr_burst <= '1';
if max_wr_len_reached = '1' or (compare_to_4k_len = '1' and cnt_len = to_4k_len) then
-- store dummy packet if to_4k_len is not even, max_wr_len_reached should result in even length
if cnt_len(0) = '1' then
tx_fifo_w_data_enable <= '1';
else
tx_fifo_w_data_enable <= '0';
end if;
-- if cnt_len = 0x1 then last_DW_int must be 0x0 as single transfers only contain first_DW_int
if cnt_len = ONE_10B then
last_DW_int <= x"0";
else
last_DW_int <= x"F";
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
else
state <= WR_TRANS;
end if;
else
wr_burst <= '0';
---------------------------------------------------------
-- odd lengths need one dummy packet so that 64bit side
-- can take the data from the FIFO
---------------------------------------------------------
if cnt_len(0) = '1' then
tx_fifo_w_data_enable <= '1';
else
tx_fifo_w_data_enable <= '0';
end if;
----------------------------------------
-- for single writes last_DW must be 0
----------------------------------------
--TODO ITEM cti=111 is a valid equivalent for cti=000 for single!
-- idea: use signal which is set if cti=010 and which remains active (e.g. registered) to qualify cti=111 as either
-- single (extra signal=0) or burst (extra signal=1)
if wbs_cti = FULL_03B and wr_burst = '1' then
last_DW_int <= wbs_sel;
else
last_DW_int <= (others => '0');
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
when WAIT_ON_FIFO =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= wr_burst;
max_wr_len_reached <= '0';
multi_cpl <= multi_cpl;
first_DW_int <= first_DW_int;
cnt_len <= cnt_len;
cpl_return_len <= cpl_return_len;
rd_trans_done <= rd_trans_done;
len_is_1024DW <= len_is_1024DW;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
---------------------------------------------------------
-- if wr_req and rd_req =0 then previous state was IDLE
-- else return to RD_TRANS or WR_TRANS respectively
---------------------------------------------------------
--------------------------------------------------------
-- for writes several FIFO states occur:
-- 1. from IDLE because TX data FIFO is full
-- wr_req is still 0 as this is set during WR_TRANS
-- 2. from WR_TRANS because data FIFO is full
-- this is managed by SUSPEND_FIFO_ACCESS and
-- RESUME_FIFO_ACCESS and wr_req = 1
--------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif wr_req = '1' and tx_fifo_w_data_full = '0' and tx_fifo_w_data_usedw <= RESUME_FIFO_ACCESS then
tx_fifo_w_data_enable <= '1';
wbs_ack <= '1';
state <= WR_TRANS;
------------------------------------------------------------------
-- for reads several FIFO states occur:
-- 1. from IDLE because TX header FIFO is full
-- rd_req is still 0 as this is set during HEADER_TO_FIFO
-- 2. from RD_TRANS because RX FIFO is empty
-- rd_req = 1
-- 2a. because PCIE_REQUEST_LENGTH is transferred
-- multi_cpl= 0
-- 2b. because root splits PCIE_REQUEST_LENGTH into several CPLD
-- multi_cpl= 1
-- 2c. because WBM requests more than PCIE_REQUEST_LENGTH
-- cnt_len = PCIE_REQUEST_LENGTH and wbs_cti /= 111
------------------------------------------------------------------
elsif rd_req = '1' and multi_cpl = '0' and tx_fifo_wr_head_full = '0' then
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
state <= RD_TRANS;
elsif rd_req = '1' and multi_cpl = '1' and rx_fifo_c_empty = '0' then
state <= GET_RD_HEADER;
elsif wr_req = '0' and rd_req = '0' and tx_fifo_w_data_full = '0' and tx_fifo_w_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_wr_head_full = '0' then
state <= IDLE;
else
state <= WAIT_ON_FIFO;
end if;
when GET_RD_HEADER =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
wbs_ack <= '0';
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '0';
rd_req <= '1';
wr_burst <= '0';
max_wr_len_reached <= '0';
first_DW_int <= first_DW_int;
cnt_len <= ONE_10B;
rd_trans_done <= rd_trans_done;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
------------------------------------------------------------------------
-- update internal address for multiple CPLDs to manage FIFO correctly
-- shifting length_int left by 2 is the same as *4
-- update wbs_adr_int on last valid cycle of length_int which is
-- before any header updates thus check for all get_headers=0
------------------------------------------------------------------------
if multi_cpl = '1' and rx_fifo_c_empty = '0' and get_header = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
wbs_adr_int <= std_logic_vector(unsigned(wbs_adr_int) + unsigned(length_int(7 downto 0) & "00"));
else
wbs_adr_int <= wbs_adr_int;
end if;
if rx_fifo_c_empty = '0' then
rx_fifo_c_rd_enable <= '1';
else
rx_fifo_c_rd_enable <= '0';
end if;
-----------------------------------------------------------------------------------
-- as multiple completions can occur add actual transfer length to cpl_return_len
-----------------------------------------------------------------------------------
if get_header = '1' then
cpl_return_len <= std_logic_vector(unsigned(cpl_return_len) + unsigned(length_int));
end if;
if get_header = '1' and get_header_q = '0' then
get_header <= '0';
elsif rx_fifo_c_empty = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
get_header <= '1';
end if;
------------------------------------------
-- capture if multiple CPLD will be send
-- relevant for bursts only
------------------------------------------
--if get_header_q = '1' and rd_burst = '1' and cpl_return_len < requested_len then
if get_header_q = '1' and rd_burst = '1' and (
(requested_len /= ZERO_10B and cpl_return_len < requested_len) or
(requested_len = ZERO_10B and cpl_return_len > requested_len)) then
multi_cpl <= '1';
end if;
--------------------------------------
-- 1024DW is encoded as length_int=0
-- decode to enable comparison with
-- cnt_len in RD_TRANS as cnt_len
-- has 0 as reset value
--------------------------------------
if get_header_q = '1' and length_int = ZERO_10B then
len_is_1024DW <= '1';
elsif get_header_q = '1' and length_int > ZERO_10B then
len_is_1024DW <= '0';
else
len_is_1024DW <= len_is_1024DW;
end if;
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
----------------------------------------------
-- WB transaction done but outstanding CPLDs
-- -> burst only
----------------------------------------------
elsif multi_cpl = '1' and rd_trans_done = '1' and ((wbs_adr_int(2) = '0' and get_header_qqq = '1') or (wbs_adr_int(2) = '1' and get_header_qq = '1')) then
state <= DROP_DATA;
------------------------------------------------------------
-- RX FIFO contains 4 header packets if address is aligned
-- else 3 header packets
-- I/O completions always return with lower address =0
-- thus they are always aligned!
------------------------------------------------------------
elsif (wbs_tga_q = '0' and ((wbs_adr_int(2) = '0' and get_header_qqq = '1') or (wbs_adr_int(2) = '1' and get_header_qq = '1'))) or
(wbs_tga_q = '1' and get_header_qqq = '1') then
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
state <= RD_TRANS;
else
state <= GET_RD_HEADER;
end if;
when DROP_DATA =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '0';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= wr_burst;
max_wr_len_reached <= '0';
multi_cpl <= multi_cpl;
first_DW_int <= first_DW_int;
last_DW_int <= last_DW_int;
cpl_return_len <= cpl_return_len;
rd_trans_done <= rd_trans_done;
len_is_1024DW <= len_is_1024DW;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
-----------------------------------------------------
-- remain in DROP_DATA and don't go to WAIT ON FIFO
-- if FIFO is not ready
-----------------------------------------------------
if rx_fifo_c_empty = '0' then
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
end if;
-------------------------------------------------------------------------------------
-- for I/O completions just drop one packet then go to IDLE
-- for single transmission return to IDLE when all data packets are taken from FIFO
-- for multiple CPLDs
-- 1. drop dummy data packet at the end of RD_TRANS before GET_RD_HEADER
-- 2. drop data packets because WB transaction is done including possible
-- dummy packet
-- as cnt_len now starts with 1 cnt_len can have the value cnt_len +1 = length_int
-- thus use >= for comparison
-------------------------------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif wbs_tga_q = '1' then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
------------------------------
-- no dummy packet to remove
------------------------------
elsif cnt_len = length_int and (
(wbs_adr_int(2) = '0' and length_int(0) = '0') or
(wbs_adr_int(2) = '1' and length_int(0) = '1') ) then
if multi_cpl = '0' or (multi_cpl = '1' and cpl_return_len = requested_len) then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif multi_cpl = '1' and cpl_return_len < requested_len then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
else
state <= DROP_DATA;
end if;
---------------------------
-- dummy packet to remove
---------------------------
elsif cnt_len > length_int and (
(wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') ) then
if multi_cpl = '0' or (multi_cpl = '1' and cpl_return_len = requested_len) then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif multi_cpl = '1' and cpl_return_len < requested_len then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
else
state <= DROP_DATA;
end if;
-------------------------------------
-- length to remove not reached yet
-------------------------------------
else
state <= DROP_DATA;
end if;
-- coverage off
when others =>
-- synthesis translate_off
wbs_ack <= '0';
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
report "wrong state encoding in process fsm_transout of z091_01_wb_slave.vhd" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
end process fsm_transout;
-------------------------------------------------------------------------------
wbs_data : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
requested_len <= (others => '0');
tx_fifo_wr_head_in <= (others => '0');
length_int <= (others => '0');
act_read_size <= (others => '0');
elsif wb_clk'event and wb_clk = '1' then
-------------------------------------------------------------------------------------
-- compose the actual maximum read size out of PCIE_REQUEST_LENGTH and max_read_len
-- CAUTION: max_read_len may not change during an ongoing burst!
-------------------------------------------------------------------------------------
if max_read_len = "0000000000" then
act_read_size <= PCIE_REQUEST_LENGTH;
elsif PCIE_REQUEST_LENGTH > max_read_len or PCIE_REQUEST_LENGTH = "0000000000" then
act_read_size <= max_read_len;
else
act_read_size <= PCIE_REQUEST_LENGTH;
end if;
-------------------------------------------------
-- assemble write request specific header parts
-------------------------------------------------
if(put_header = '1' and put_h0_h1 = '0' and wr_req = '1') then
requested_len <= (others => '0');
tx_fifo_wr_head_in(31) <= '1';
--------------------------------------------------
-- write request is done when header is composed
-- thus use registered copy of tga
--------------------------------------------------
if(wbs_tga = '0') then -- memory
tx_fifo_wr_head_in(30) <= '1';
tx_fifo_wr_head_in(29) <= '1';
else -- I/O
tx_fifo_wr_head_in(30) <= '0';
tx_fifo_wr_head_in(29) <= '0';
end if;
tx_fifo_wr_head_in(28 downto 18) <= "00000000000";
tx_fifo_wr_head_in(17 downto 14) <= first_DW_int;
tx_fifo_wr_head_in(13 downto 10) <= last_DW_int;
---------------------------------------------------------------------------------
-- cnt_len counts to one more while transitioning to next state thus subtract 1
---------------------------------------------------------------------------------
tx_fifo_wr_head_in(9 downto 0) <= std_logic_vector(unsigned(cnt_len) - to_unsigned(1,10));
------------------------------------------------
-- assemble read request specific header parts
------------------------------------------------
elsif(put_header = '1' and put_h0_h1 = '0' and rd_req = '1') then
tx_fifo_wr_head_in(31) <= '0';
tx_fifo_wr_head_in(30) <= '0';
if(wbs_tga = '0') then -- memory
tx_fifo_wr_head_in(29) <= '1';
else -- I/O
tx_fifo_wr_head_in(29) <= '0';
end if;
tx_fifo_wr_head_in(28 downto 18) <= "00000000000";
---------------------------------------
-- always request all bytes for reads
-- WBM will chose later
---------------------------------------
tx_fifo_wr_head_in(17 downto 14) <= x"F"; -- first_DW
---------------------------------------------------------------------------------------------------------------------------
-- if PCIE_REQUEST_LENGTH is max (=0), max_read_len is either =0 too then maximum size is allowed or max_read_len is /= 0
-- then max_read_len must be used -> using max_read_len for both cases is always correct
-- otherwise PCIE_REQUEST_LENGTH is only allowed if <= max_read_len
-- all values may not exceed to_4k_len if it has to be obeyed which is denoted by compare_to_4k_len
---------------------------------------------------------------------------------------------------------------------------
if wbs_cti = "000" or wbs_cti = "111" then
requested_len <= "0000000001";
tx_fifo_wr_head_in(9 downto 0) <= "0000000001";
--------------------------------
-- for single read last_DW =0!
--------------------------------
tx_fifo_wr_head_in(13 downto 10) <= x"0"; -- last_DW
else
tx_fifo_wr_head_in(13 downto 10) <= x"F"; -- last_DW
if compare_to_4k_len = '1' then
if act_read_size <= to_4k_len then
tx_fifo_wr_head_in(9 downto 0) <= act_read_size;
requested_len <= act_read_size;
else
requested_len <= to_4k_len;
tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
end if;
else
tx_fifo_wr_head_in(9 downto 0) <= act_read_size;
requested_len <= act_read_size;
end if;
--if compare_to_4k_len = '1' and to_4k_len /= "0000000000" then
-- if PCIE_REQUEST_LENGTH <= max_read_len and PCIE_REQUEST_LENGTH <= to_4k_len then
-- requested_len <= PCIE_REQUEST_LENGTH;
-- tx_fifo_wr_head_in(9 downto 0) <= PCIE_REQUEST_LENGTH;
-- elsif PCIE_REQUEST_LENGTH <= max_read_len and PCIE_REQUEST_LENGTH > to_4k_len then
-- requested_len <= to_4k_len;
-- tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
-- elsif PCIE_REQUEST_LENGTH > max_read_len and max_read_len > to_4k_len then
-- requested_len <= to_4k_len;
-- tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
-- else
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- end if;
--else
-- if(PCIE_REQUEST_LENGTH = "0000000000") then
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- elsif(PCIE_REQUEST_LENGTH <= max_read_len or max_read_len = "0000000000") then
-- requested_len <= PCIE_REQUEST_LENGTH;
-- tx_fifo_wr_head_in(9 downto 0) <= PCIE_REQUEST_LENGTH;
-- else
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- end if;
--end if;
end if;
------------------------------------------------------------------------------
-- length is for both read and write requests at the same position in header
------------------------------------------------------------------------------
elsif(put_header = '1' and put_h0_h1 = '1') then
requested_len <= requested_len;
tx_fifo_wr_head_in <= wbs_adr_int(31 downto 2) & "00";
end if;
-------------------------------------------
-- store length of this completion packet
-------------------------------------------
if state = GET_RD_HEADER and rx_fifo_c_empty = '0' and get_header = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
length_int <= rx_fifo_c_out(9 downto 0);
end if;
end if;
end process wbs_data;
end architecture z091_01_wb_slave_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.ALL;
USE ieee.vital_primitives.ALL;
library fmf;
use fmf.gen_utils.all;
use fmf.conversions.all;
package flash is
component s25fl064a
generic (
tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
tipd_SI : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tsetup_SI_SCK : VitalDelayType := UnitDelay;
tsetup_CSNeg_SCK : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay;
tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay;
thold_SI_SCK : VitalDelayType := UnitDelay;
thold_CSNeg_SCK : VitalDelayType := UnitDelay;
thold_HOLDNeg_SCK : VitalDelayType := UnitDelay;
thold_WNeg_CSNeg : VitalDelayType := UnitDelay;
tpw_SCK_posedge : VitalDelayType := UnitDelay;
tpw_SCK_negedge : VitalDelayType := UnitDelay;
tpw_CSNeg_posedge : VitalDelayType := UnitDelay;
tperiod_SCK_rd : VitalDelayType := UnitDelay;
tperiod_SCK_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 3 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 384 sec;
tdevice_WR : VitalDelayType := 60 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES : VitalDelayType := 30 us;
tdevice_PU : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "s25fl064a.mem";
UserPreload : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
SCK : IN std_ulogic := 'U';
SI : IN std_ulogic := 'U';
CSNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
SO : OUT std_ulogic := 'U'
);
end component;
component m25p80
generic (
tipd_C : VitalDelayType01 := VitalZeroDelay01;
tipd_D : VitalDelayType01 := VitalZeroDelay01;
tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_C_Q : VitalDelayType01 := UnitDelay01;
tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tsetup_D_C : VitalDelayType := UnitDelay;
tsetup_SNeg_C : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_C : VitalDelayType := UnitDelay;
tsetup_C_HOLDNeg : VitalDelayType := UnitDelay;
tsetup_WNeg_SNeg : VitalDelayType := UnitDelay;
thold_D_C : VitalDelayType := UnitDelay;
thold_SNeg_C : VitalDelayType := UnitDelay;
thold_HOLDNeg_C : VitalDelayType := UnitDelay;
thold_C_HOLDNeg : VitalDelayType := UnitDelay;
thold_WNeg_SNeg : VitalDelayType := UnitDelay;
tpw_C_posedge : VitalDelayType := UnitDelay;
tpw_C_negedge : VitalDelayType := UnitDelay;
tpw_SNeg_posedge : VitalDelayType := UnitDelay;
tperiod_C_rd : VitalDelayType := UnitDelay;
tperiod_C_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 5 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 20 sec;
tdevice_WR : VitalDelayType := 15 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES1 : VitalDelayType := 3 us;
tdevice_RES2 : VitalDelayType := 1.8 us;
tdevice_VSL : VitalDelayType := 10 us;
tdevice_PUW : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "m25p80.mem";
UserPreload : BOOLEAN := FALSE;
DebugInfo : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
C : IN std_ulogic := 'U';
D : IN std_ulogic := 'U';
SNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
Q : OUT std_ulogic := 'U'
);
end component;
end flash;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.ALL;
USE ieee.vital_primitives.ALL;
library fmf;
use fmf.gen_utils.all;
use fmf.conversions.all;
package flash is
component s25fl064a
generic (
tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
tipd_SI : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tsetup_SI_SCK : VitalDelayType := UnitDelay;
tsetup_CSNeg_SCK : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay;
tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay;
thold_SI_SCK : VitalDelayType := UnitDelay;
thold_CSNeg_SCK : VitalDelayType := UnitDelay;
thold_HOLDNeg_SCK : VitalDelayType := UnitDelay;
thold_WNeg_CSNeg : VitalDelayType := UnitDelay;
tpw_SCK_posedge : VitalDelayType := UnitDelay;
tpw_SCK_negedge : VitalDelayType := UnitDelay;
tpw_CSNeg_posedge : VitalDelayType := UnitDelay;
tperiod_SCK_rd : VitalDelayType := UnitDelay;
tperiod_SCK_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 3 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 384 sec;
tdevice_WR : VitalDelayType := 60 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES : VitalDelayType := 30 us;
tdevice_PU : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "s25fl064a.mem";
UserPreload : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
SCK : IN std_ulogic := 'U';
SI : IN std_ulogic := 'U';
CSNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
SO : OUT std_ulogic := 'U'
);
end component;
component m25p80
generic (
tipd_C : VitalDelayType01 := VitalZeroDelay01;
tipd_D : VitalDelayType01 := VitalZeroDelay01;
tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_C_Q : VitalDelayType01 := UnitDelay01;
tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tsetup_D_C : VitalDelayType := UnitDelay;
tsetup_SNeg_C : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_C : VitalDelayType := UnitDelay;
tsetup_C_HOLDNeg : VitalDelayType := UnitDelay;
tsetup_WNeg_SNeg : VitalDelayType := UnitDelay;
thold_D_C : VitalDelayType := UnitDelay;
thold_SNeg_C : VitalDelayType := UnitDelay;
thold_HOLDNeg_C : VitalDelayType := UnitDelay;
thold_C_HOLDNeg : VitalDelayType := UnitDelay;
thold_WNeg_SNeg : VitalDelayType := UnitDelay;
tpw_C_posedge : VitalDelayType := UnitDelay;
tpw_C_negedge : VitalDelayType := UnitDelay;
tpw_SNeg_posedge : VitalDelayType := UnitDelay;
tperiod_C_rd : VitalDelayType := UnitDelay;
tperiod_C_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 5 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 20 sec;
tdevice_WR : VitalDelayType := 15 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES1 : VitalDelayType := 3 us;
tdevice_RES2 : VitalDelayType := 1.8 us;
tdevice_VSL : VitalDelayType := 10 us;
tdevice_PUW : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "m25p80.mem";
UserPreload : BOOLEAN := FALSE;
DebugInfo : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
C : IN std_ulogic := 'U';
D : IN std_ulogic := 'U';
SNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
Q : OUT std_ulogic := 'U'
);
end component;
end flash;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.ALL;
USE ieee.vital_primitives.ALL;
library fmf;
use fmf.gen_utils.all;
use fmf.conversions.all;
package flash is
component s25fl064a
generic (
tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
tipd_SI : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;
tsetup_SI_SCK : VitalDelayType := UnitDelay;
tsetup_CSNeg_SCK : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay;
tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay;
thold_SI_SCK : VitalDelayType := UnitDelay;
thold_CSNeg_SCK : VitalDelayType := UnitDelay;
thold_HOLDNeg_SCK : VitalDelayType := UnitDelay;
thold_WNeg_CSNeg : VitalDelayType := UnitDelay;
tpw_SCK_posedge : VitalDelayType := UnitDelay;
tpw_SCK_negedge : VitalDelayType := UnitDelay;
tpw_CSNeg_posedge : VitalDelayType := UnitDelay;
tperiod_SCK_rd : VitalDelayType := UnitDelay;
tperiod_SCK_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 3 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 384 sec;
tdevice_WR : VitalDelayType := 60 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES : VitalDelayType := 30 us;
tdevice_PU : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "s25fl064a.mem";
UserPreload : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
SCK : IN std_ulogic := 'U';
SI : IN std_ulogic := 'U';
CSNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
SO : OUT std_ulogic := 'U'
);
end component;
component m25p80
generic (
tipd_C : VitalDelayType01 := VitalZeroDelay01;
tipd_D : VitalDelayType01 := VitalZeroDelay01;
tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tpd_C_Q : VitalDelayType01 := UnitDelay01;
tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;
tsetup_D_C : VitalDelayType := UnitDelay;
tsetup_SNeg_C : VitalDelayType := UnitDelay;
tsetup_HOLDNeg_C : VitalDelayType := UnitDelay;
tsetup_C_HOLDNeg : VitalDelayType := UnitDelay;
tsetup_WNeg_SNeg : VitalDelayType := UnitDelay;
thold_D_C : VitalDelayType := UnitDelay;
thold_SNeg_C : VitalDelayType := UnitDelay;
thold_HOLDNeg_C : VitalDelayType := UnitDelay;
thold_C_HOLDNeg : VitalDelayType := UnitDelay;
thold_WNeg_SNeg : VitalDelayType := UnitDelay;
tpw_C_posedge : VitalDelayType := UnitDelay;
tpw_C_negedge : VitalDelayType := UnitDelay;
tpw_SNeg_posedge : VitalDelayType := UnitDelay;
tperiod_C_rd : VitalDelayType := UnitDelay;
tperiod_C_fast_rd : VitalDelayType := UnitDelay;
tdevice_PP : VitalDelayType := 5 ms;
tdevice_SE : VitalDelayType := 3 sec;
tdevice_BE : VitalDelayType := 20 sec;
tdevice_WR : VitalDelayType := 15 ms;
tdevice_DP : VitalDelayType := 3 us;
tdevice_RES1 : VitalDelayType := 3 us;
tdevice_RES2 : VitalDelayType := 1.8 us;
tdevice_VSL : VitalDelayType := 10 us;
tdevice_PUW : VitalDelayType := 10 ms;
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
mem_file_name : STRING := "m25p80.mem";
UserPreload : BOOLEAN := FALSE;
DebugInfo : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
TimingModel : STRING := DefaultTimingModel
);
port (
C : IN std_ulogic := 'U';
D : IN std_ulogic := 'U';
SNeg : IN std_ulogic := 'U';
HOLDNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
Q : OUT std_ulogic := 'U'
);
end component;
end flash;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.MVL4.all;
entity tri_state_buffer is
port ( a, enable : in MVL4_ulogic; y : out MVL4_ulogic );
end entity tri_state_buffer;
--------------------------------------------------
architecture behavioral of tri_state_buffer is
begin
y <= 'Z' when enable = '0' else
a when enable = '1' and (a = '0' or a = '1') else
'X';
end architecture behavioral;
|
--========================================================================================================================
-- Copyright (c) 2016 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif_pkg
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package irqc_pif_pkg is
-- Change this to a generic when generic in packages is allowed (VHDL 2008)
constant C_NUM_SOURCES : integer := 6; -- 1 <= C_NUM_SOURCES <= Data width
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_IRR : integer := 0;
constant C_ADDR_IER : integer := 1;
constant C_ADDR_ITR : integer := 2;
constant C_ADDR_ICR : integer := 3;
constant C_ADDR_IPR : integer := 4;
constant C_ADDR_IRQ2CPU_ENA : integer := 5;
constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
-- Signals from pif to core
type t_p2c is record
rw_ier : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_itr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_icr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_irq2cpu_ena : std_logic;
awt_irq2cpu_disable : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_irr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_ipr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_irq2cpu_allowed : std_logic;
end record t_c2p;
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rd : std_logic; -- to dut
wr : std_logic; -- to dut
wdata : std_logic_vector; -- to dut
ready : std_logic; -- from dut
rdata : std_logic_vector; -- from dut
end record;
------------------------------------------
-- init_sbi_if_signals
------------------------------------------
-- - This function returns an SBI interface with initialized signals.
-- - All SBI input signals are initialized to 0
-- - All SBI output signals are initialized to Z
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if;
end package irqc_pif_pkg;
package body irqc_pif_pkg is
---------------------------------------------------------------------------------
-- initialize sbi to dut signals
---------------------------------------------------------------------------------
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if is
variable result : t_sbi_if( addr(addr_width - 1 downto 0),
wdata(data_width - 1 downto 0),
rdata(data_width - 1 downto 0));
begin
result.cs := '0';
result.rd := '0';
result.wr := '0';
result.addr := (others => '0');
result.wdata := (others => '0');
result.ready := 'Z';
result.rdata := (others => 'Z');
return result;
end function;
end package body irqc_pif_pkg;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY TestBenchAutomated IS
-- Generics passed in
generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
END TestBenchAutomated;
ARCHITECTURE behavior OF TestBenchAutomated IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TopLevelM_M
generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
PORT(
clk : IN std_logic;
next_in : IN std_logic; --User input
rst_in : IN std_logic; --User input
OUTPUT : OUT SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0) --Calculated DATA output
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal next_in : std_logic := '0';
signal rst_in : std_logic := '0';
--Outputs
signal OUTPUT : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
--Variable to be used in assert section
type Vector is record
OUTPUT_test : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
end record;
type VectorArray is array (natural range <>) of Vector;
constant Vectors : VectorArray := (
-- Values to be compaired to calculated output
(OUTPUT_test =>"000000110000"), -- 48
(OUTPUT_test =>"000011110110"), -- 246
(OUTPUT_test =>"000101001000"), -- 382 <--- Purposefully incorrect value, Should be '000100001000' = 264
(OUTPUT_test =>"111111010011"), -- -45
(OUTPUT_test =>"111101001100"), -- -180
(OUTPUT_test =>"111111001111"), -- -49
(OUTPUT_test =>"000000101011"), -- 43 Purposefully incorrect value, Should be '000010101011' = 171
(OUTPUT_test =>"000000010011"), -- 19
(OUTPUT_test =>"111111100101"), -- -27
(OUTPUT_test =>"111110111011"), -- -69
(OUTPUT_test =>"111110111011"), -- -69
(OUTPUT_test =>"000000101101"), -- 45
(OUTPUT_test =>"111011011110"), -- -290
(OUTPUT_test =>"000001010110"), -- 86
(OUTPUT_test =>"000011110010"), -- 242
(OUTPUT_test =>"000000111110"), -- 125
(OUTPUT_test =>"111111001001"), -- -55
(OUTPUT_test =>"000100010101"), -- 277
(OUTPUT_test =>"111111100011"), -- -29
(OUTPUT_test =>"111101111101"));-- -131
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TopLevelM_M PORT MAP (
clk => clk,
next_in => next_in,
rst_in => rst_in,
OUTPUT => OUTPUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Process to simulate user input and to check output is correct
Test :process
variable i : integer;
begin
wait for 100 ns;
rst_in <= '1';
wait for clk_period*3;
rst_in <= '0';
--Loops through enough times to cover matrix and more to show it freezes in S_Wait state
for i in 0 to 50 loop
for i in Vectors'range loop
next_in <= '1';
wait for clk_period*5;
next_in <= '0';
wait for clk_period*4; --Appropriate amount of clock cycles needed for calculations to be displayed at output
--Check the output is the same as expected
assert OUTPUT = Vectors(i).OUTPUT_test
report "Incorrect Output on vector line" & integer'image(i) &
lf & "Expected:" & integer'image(i)(to_integer((Vectors(i).OUTPUT_test))) --& lf &
--"But got" & integer'image(i)(to_integer(signed(OUTPUT)))
severity error;
end loop;
end loop;
wait;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY TestBenchAutomated IS
-- Generics passed in
generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
END TestBenchAutomated;
ARCHITECTURE behavior OF TestBenchAutomated IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TopLevelM_M
generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
PORT(
clk : IN std_logic;
next_in : IN std_logic; --User input
rst_in : IN std_logic; --User input
OUTPUT : OUT SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0) --Calculated DATA output
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal next_in : std_logic := '0';
signal rst_in : std_logic := '0';
--Outputs
signal OUTPUT : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
--Variable to be used in assert section
type Vector is record
OUTPUT_test : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
end record;
type VectorArray is array (natural range <>) of Vector;
constant Vectors : VectorArray := (
-- Values to be compaired to calculated output
(OUTPUT_test =>"000000110000"), -- 48
(OUTPUT_test =>"000011110110"), -- 246
(OUTPUT_test =>"000101001000"), -- 382 <--- Purposefully incorrect value, Should be '000100001000' = 264
(OUTPUT_test =>"111111010011"), -- -45
(OUTPUT_test =>"111101001100"), -- -180
(OUTPUT_test =>"111111001111"), -- -49
(OUTPUT_test =>"000000101011"), -- 43 Purposefully incorrect value, Should be '000010101011' = 171
(OUTPUT_test =>"000000010011"), -- 19
(OUTPUT_test =>"111111100101"), -- -27
(OUTPUT_test =>"111110111011"), -- -69
(OUTPUT_test =>"111110111011"), -- -69
(OUTPUT_test =>"000000101101"), -- 45
(OUTPUT_test =>"111011011110"), -- -290
(OUTPUT_test =>"000001010110"), -- 86
(OUTPUT_test =>"000011110010"), -- 242
(OUTPUT_test =>"000000111110"), -- 125
(OUTPUT_test =>"111111001001"), -- -55
(OUTPUT_test =>"000100010101"), -- 277
(OUTPUT_test =>"111111100011"), -- -29
(OUTPUT_test =>"111101111101"));-- -131
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TopLevelM_M PORT MAP (
clk => clk,
next_in => next_in,
rst_in => rst_in,
OUTPUT => OUTPUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Process to simulate user input and to check output is correct
Test :process
variable i : integer;
begin
wait for 100 ns;
rst_in <= '1';
wait for clk_period*3;
rst_in <= '0';
--Loops through enough times to cover matrix and more to show it freezes in S_Wait state
for i in 0 to 50 loop
for i in Vectors'range loop
next_in <= '1';
wait for clk_period*5;
next_in <= '0';
wait for clk_period*4; --Appropriate amount of clock cycles needed for calculations to be displayed at output
--Check the output is the same as expected
assert OUTPUT = Vectors(i).OUTPUT_test
report "Incorrect Output on vector line" & integer'image(i) &
lf & "Expected:" & integer'image(i)(to_integer((Vectors(i).OUTPUT_test))) --& lf &
--"But got" & integer'image(i)(to_integer(signed(OUTPUT)))
severity error;
end loop;
end loop;
wait;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY TestBenchAutomated IS
-- Generics passed in
generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
END TestBenchAutomated;
ARCHITECTURE behavior OF TestBenchAutomated IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TopLevelM_M
generic (m: integer := 3; n: integer := 5; h: integer := 4; DATA_SIZE: integer :=5);
PORT(
clk : IN std_logic;
next_in : IN std_logic; --User input
rst_in : IN std_logic; --User input
OUTPUT : OUT SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0) --Calculated DATA output
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal next_in : std_logic := '0';
signal rst_in : std_logic := '0';
--Outputs
signal OUTPUT : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
--Variable to be used in assert section
type Vector is record
OUTPUT_test : SIGNED((DATA_SIZE+DATA_SIZE)+(m-1)-1 downto 0);
end record;
type VectorArray is array (natural range <>) of Vector;
constant Vectors : VectorArray := (
-- Values to be compaired to calculated output
(OUTPUT_test =>"000000110000"), -- 48
(OUTPUT_test =>"000011110110"), -- 246
(OUTPUT_test =>"000101001000"), -- 382 <--- Purposefully incorrect value, Should be '000100001000' = 264
(OUTPUT_test =>"111111010011"), -- -45
(OUTPUT_test =>"111101001100"), -- -180
(OUTPUT_test =>"111111001111"), -- -49
(OUTPUT_test =>"000000101011"), -- 43 Purposefully incorrect value, Should be '000010101011' = 171
(OUTPUT_test =>"000000010011"), -- 19
(OUTPUT_test =>"111111100101"), -- -27
(OUTPUT_test =>"111110111011"), -- -69
(OUTPUT_test =>"111110111011"), -- -69
(OUTPUT_test =>"000000101101"), -- 45
(OUTPUT_test =>"111011011110"), -- -290
(OUTPUT_test =>"000001010110"), -- 86
(OUTPUT_test =>"000011110010"), -- 242
(OUTPUT_test =>"000000111110"), -- 125
(OUTPUT_test =>"111111001001"), -- -55
(OUTPUT_test =>"000100010101"), -- 277
(OUTPUT_test =>"111111100011"), -- -29
(OUTPUT_test =>"111101111101"));-- -131
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TopLevelM_M PORT MAP (
clk => clk,
next_in => next_in,
rst_in => rst_in,
OUTPUT => OUTPUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Process to simulate user input and to check output is correct
Test :process
variable i : integer;
begin
wait for 100 ns;
rst_in <= '1';
wait for clk_period*3;
rst_in <= '0';
--Loops through enough times to cover matrix and more to show it freezes in S_Wait state
for i in 0 to 50 loop
for i in Vectors'range loop
next_in <= '1';
wait for clk_period*5;
next_in <= '0';
wait for clk_period*4; --Appropriate amount of clock cycles needed for calculations to be displayed at output
--Check the output is the same as expected
assert OUTPUT = Vectors(i).OUTPUT_test
report "Incorrect Output on vector line" & integer'image(i) &
lf & "Expected:" & integer'image(i)(to_integer((Vectors(i).OUTPUT_test))) --& lf &
--"But got" & integer'image(i)(to_integer(signed(OUTPUT)))
severity error;
end loop;
end loop;
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:59:29 02/23/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_top.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: topModule
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT topModule
PORT(
CLK : IN std_logic;
GPIO0 : OUT std_logic;
GPIO1 : OUT std_logic;
RX : IN std_logic;
TX : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RX : std_logic := '1';
--Outputs
signal GPIO0 : std_logic;
signal GPIO1 : std_logic;
signal TX : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
constant bit_period : time := 8.68 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: topModule PORT MAP (
CLK => CLK,
GPIO0 => GPIO0,
GPIO1 => GPIO1,
RX => RX,
TX => TX
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait for 10 us;
-- send '0000000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11111111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11110000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '00001111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '10101010'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 200 us;
end process;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity edge_enhance is
Port ( clk : in STD_LOGIC;
enable_feature : in std_logic;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank : in std_logic;
in_hsync : in std_logic;
in_vsync : in std_logic;
in_red : in std_logic_vector(7 downto 0);
in_green : in std_logic_vector(7 downto 0);
in_blue : in std_logic_vector(7 downto 0);
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : out std_logic;
out_hsync : out std_logic;
out_vsync : out std_logic;
out_red : out std_logic_vector(7 downto 0);
out_green : out std_logic_vector(7 downto 0);
out_blue : out std_logic_vector(7 downto 0));
end edge_enhance;
architecture Behavioral of edge_enhance is
component line_delay is
Port ( clk : in STD_LOGIC;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_blank : in std_logic;
in_hsync : in std_logic;
in_vsync : in std_logic;
in_red : in std_logic_vector(7 downto 0);
in_green : in std_logic_vector(7 downto 0);
in_blue : in std_logic_vector(7 downto 0);
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : out std_logic;
out_hsync : out std_logic;
out_vsync : out std_logic;
out_red : out std_logic_vector(7 downto 0);
out_green : out std_logic_vector(7 downto 0);
out_blue : out std_logic_vector(7 downto 0));
end component;
type a_bits is array(0 to 8) of std_logic;
type a_component is array(0 to 8) of std_logic_vector(7 downto 0);
signal blanks : a_bits;
signal hsyncs : a_bits;
signal vsyncs : a_bits;
signal reds : a_component;
signal greens : a_component;
signal blues : a_component;
signal sobel_1_blue : unsigned(12 downto 0) := (others => '0');
signal sobel_1_blue_x : unsigned(11 downto 0) := (others => '0');
signal sobel_1_blue_y : unsigned(11 downto 0) := (others => '0');
signal sobel_3_blue : unsigned(12 downto 0) := (others => '0');
signal sobel_2_blue_x : unsigned(11 downto 0) := (others => '0');
signal sobel_2_blue_y : unsigned(11 downto 0) := (others => '0');
signal sobel_1_green_left : unsigned(11 downto 0) := (others => '0');
signal sobel_1_green_right : unsigned(11 downto 0) := (others => '0');
signal sobel_1_blue_left : unsigned(11 downto 0) := (others => '0');
signal sobel_1_blue_right : unsigned(11 downto 0) := (others => '0');
signal test : std_logic_vector(7 downto 0) := (others => '0');
signal test2 : std_logic_vector(7 downto 0) := (others => '0');
begin
i_line_delay_2: line_delay Port map (
clk => clk,
in_blank => blanks(3),
in_hsync => hsyncs(3),
in_vsync => vsyncs(3),
in_red => reds(3),
in_green => greens(3),
in_blue => blues(3),
out_blank => blanks(6),
out_hsync => hsyncs(6),
out_vsync => vsyncs(6),
out_red => reds(6),
out_green => test2,
out_blue => test
);
process(clk)
begin
if rising_edge(clk) then
out_green <= test2;
out_blue <= test;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- axi_bram_ctrl_funcs.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_funcs.vhd
--
-- Description: Support functions for axi_bram_ctrl library modules.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
--
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/16/2011 v1.03a
-- ~~~~~~
-- Update ECC size on 128-bit data width configuration.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add MIG functions for Hsiao ECC.
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Add Find_ECC_Size function.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Add REDUCTION_OR function.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Recode Create_Size_Max with a case statement.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Remove Family_To_LUT_Size function.
-- Remove String_To_Family function.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package axi_bram_ctrl_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
SPARTAN3,
VIRTEX4,
VIRTEX5,
SPARTAN3E,
SPARTAN3A,
SPARTAN3AN,
SPARTAN3Adsp,
SPARTAN6,
VIRTEX6,
VIRTEX7,
KINTEX7,
-- pragma xilinx_rtl_on
RTL
);
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
-- function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN;
function log2(x : natural) return integer;
function Int_ECC_Size (i: integer) return integer;
function Find_ECC_Size (i: integer; j: integer) return integer;
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer;
function Create_Size_Max (i: integer) return std_logic_vector;
function REDUCTION_OR (A: in std_logic_vector) return std_logic;
function REDUCTION_XOR (A: in std_logic_vector) return std_logic;
function REDUCTION_NOR (A: in std_logic_vector) return std_logic;
function BOOLEAN_TO_STD_LOGIC (A: in BOOLEAN) return std_logic;
end package axi_bram_ctrl_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body axi_bram_ctrl_funcs is
-------------------------------------------------------------------------------
-- Function: Int_ECC_Size
-- Purpose: Determine internal size of ECC when enabled.
-------------------------------------------------------------------------------
function Int_ECC_Size (i: integer) return integer is
begin
--coverage off
if (i = 32) then
return 7; -- 7-bits ECC for 32-bit data
-- ECC port size fixed @ 8-bits
elsif (i = 64) then
return 8;
elsif (i = 128) then
return 9; -- Hsiao is 9-bits for 128-bit data.
else
return 0;
end if;
--coverage on
end Int_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Size
-- Purpose: Determine external size of ECC signals when enabled.
-------------------------------------------------------------------------------
function Find_ECC_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8; -- Keep at 8 for port size matchings
-- Only 7-bits ECC per 32-bit data
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 9;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Full_Bit_Size
-- Purpose: Determine external size of ECC signals when enabled in bytes.
-------------------------------------------------------------------------------
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8;
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 16;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Full_Bit_Size;
-------------------------------------------------------------------------------
-- Function: Create_Size_Max
-- Purpose: Create maximum value for AxSIZE based on AXI data bus width.
-------------------------------------------------------------------------------
function Create_Size_Max (i: integer)
return std_logic_vector is
variable size_vector : std_logic_vector (2 downto 0);
begin
case (i) is
when 32 => size_vector := "010"; -- 2h (4 bytes)
when 64 => size_vector := "011"; -- 3h (8 bytes)
when 128 => size_vector := "100"; -- 4h (16 bytes)
when 256 => size_vector := "101"; -- 5h (32 bytes)
when 512 => size_vector := "110"; -- 5h (32 bytes)
when 1024 => size_vector := "111"; -- 5h (32 bytes)
--coverage off
when others => size_vector := "000"; -- 0h
--coverage on
end case;
return (size_vector);
end function Create_Size_Max;
-------------------------------------------------------------------------------
-- Function: REDUCTION_OR
-- Purpose: New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_OR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_XOR
-- Purpose: Derived from MIG v3.7 ecc_gen module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_XOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp xor A(i);
end loop;
return tmp;
end function REDUCTION_XOR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_NOR
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_NOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return not tmp;
end function REDUCTION_NOR;
-------------------------------------------------------------------------------
-- Function: BOOLEAN_TO_STD_LOGIC
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function BOOLEAN_TO_STD_LOGIC (A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
-------------------------------------------------------------------------------
function LowerCase_Char(char : character) return character is
begin
--coverage off
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
--coverage on
end LowerCase_Char;
-------------------------------------------------------------------------------
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String ( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
--coverage off
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
--coverage on
RETURN equal;
END Equal_String;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of String_To_Family function.
--
--
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
-- begin -- function String_To_Family
--
-- --coverage off
--
-- if ((Select_RTL) or Equal_String(S, "rtl")) then
-- return RTL;
-- elsif Equal_String(S, "spartan3") or Equal_String(S, "aspartan3") then
-- return SPARTAN3;
-- elsif Equal_String(S, "spartan3E") or Equal_String(S, "aspartan3E") then
-- return SPARTAN3E;
-- elsif Equal_String(S, "spartan3A") or Equal_String(S, "aspartan3A") then
-- return SPARTAN3A;
-- elsif Equal_String(S, "spartan3AN") then
-- return SPARTAN3AN;
-- elsif Equal_String(S, "spartan3Adsp") or Equal_String(S, "aspartan3Adsp") then
-- return SPARTAN3Adsp;
-- elsif Equal_String(S, "spartan6") or Equal_String(S, "spartan6l") or
-- Equal_String(S, "qspartan6") or Equal_String(S, "aspartan6") or Equal_String(S, "qspartan6l") then
-- return SPARTAN6;
-- elsif Equal_String(S, "virtex4") or Equal_String(S, "qvirtex4")
-- or Equal_String(S, "qrvirtex4") then
-- return VIRTEX4;
-- elsif Equal_String(S, "virtex5") or Equal_String(S, "qrvirtex5") then
-- return VIRTEX5;
-- elsif Equal_String(S, "virtex6") or Equal_String(S, "virtex6l") or Equal_String(S, "qvirtex6") then
-- return VIRTEX6;
-- elsif Equal_String(S, "virtex7") then
-- return VIRTEX7;
-- elsif Equal_String(S, "kintex7") then
-- return KINTEX7;
--
-- --coverage on
--
-- else
-- -- assert (false) report "No known target family" severity failure;
-- return RTL;
-- end if;
--
-- end function String_To_Family;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of Family_To_LUT_Size function.
--
-- function Family_To_LUT_Size (Family : TARGET_FAMILY_TYPE) return integer is
-- begin
--
-- --coverage off
--
-- if (Family = SPARTAN3) or (Family = SPARTAN3E) or (Family = SPARTAN3A) or
-- (Family = SPARTAN3AN) or (Family = SPARTAN3Adsp) or (Family = VIRTEX4) then
-- return 4;
-- end if;
--
-- return 6;
--
-- --coverage on
--
-- end function Family_To_LUT_Size;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
--coverage off
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
--coverage on
end function log2;
-------------------------------------------------------------------------------
end package body axi_bram_ctrl_funcs;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_3 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_3;
ARCHITECTURE design_1_FIR_resized1_3_arch OF design_1_FIR_resized1_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_3_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_FIR_resized1_3_arch: ARCHITECTURE IS "fir_compiler_v7_2_6,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_FIR_resized1_3_arch : ARCHITECTURE IS "design_1_FIR_resized1_3,fir_compiler_v7_2_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_FIR_resized1_3_arch: ARCHITECTURE IS "design_1_FIR_resized1_3,fir_compiler_v7_2_6,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=design_1_FIR_resized1_3,C_COEF_FILE=design_1_FIR_resized1_3.mif,C_COEF_FILE_LINES=35,C_FILTER_TYPE=1,C_INTERP_RATE=1,C_DECIM_RATE=5,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=62,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=f" &
"ixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=7,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=24,C_DATA_IP_PATH_WIDTHS=24,C_DATA_PX_PATH_WIDTHS=24,C_DATA_WIDTH=24,C_COEF_PATH_WIDTHS=16,C_COEF_WIDTH=16,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_PX_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=42,C_OUTPUT_WIDTH=32,C_OUTPUT_PATH_WIDTHS=32,C_ACCUM_OP_PATH_WIDTHS=42,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_M" &
"ADDS=7,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=1,C_INPUT_RATE=1,C_OUTPUT_RATE=5,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=14,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONF" &
"IG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_3",
C_COEF_FILE => "design_1_FIR_resized1_3.mif",
C_COEF_FILE_LINES => 35,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 62,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "7",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "42",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "42",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 7,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 14,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_3_arch;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
--altera translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Test_Pattern_Generator is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0) := (others=>'0');
Avalon_MM_Slave_write : in std_logic := '0';
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0) := (others=>'0');
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic := '0';
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic := '0';
aclr : in std_logic := '0'
);
end entity Test_Pattern_Generator;
architecture rtl of Test_Pattern_Generator is
component Test_Pattern_Generator_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0) := (others=>'0');
Avalon_MM_Slave_write : in std_logic := '0';
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0) := (others=>'0');
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic := '0';
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic := '0';
aclr : in std_logic := '0'
);
end component Test_Pattern_Generator_GN;
begin
Test_Pattern_Generator_GN_0: if true generate
inst_Test_Pattern_Generator_GN_0: Test_Pattern_Generator_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
--altera translate_on
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1725.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n01i01725ent IS
END c12s06b01x00p04n01i01725ent;
ARCHITECTURE c12s06b01x00p04n01i01725arch OF c12s06b01x00p04n01i01725ent IS
signal clk : bit;
BEGIN
TESTING: PROCESS
BEGIN
--
-- The signal assignment below tries to make two
-- assignments at the same (current) time.
--
clk <= '0', '1';
assert FALSE
report "***FAILED TEST: c12s06b01x00p04n01i01725 - The signal assignment can not make two assignment at the same (current) time."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n01i01725arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1725.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n01i01725ent IS
END c12s06b01x00p04n01i01725ent;
ARCHITECTURE c12s06b01x00p04n01i01725arch OF c12s06b01x00p04n01i01725ent IS
signal clk : bit;
BEGIN
TESTING: PROCESS
BEGIN
--
-- The signal assignment below tries to make two
-- assignments at the same (current) time.
--
clk <= '0', '1';
assert FALSE
report "***FAILED TEST: c12s06b01x00p04n01i01725 - The signal assignment can not make two assignment at the same (current) time."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n01i01725arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1725.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n01i01725ent IS
END c12s06b01x00p04n01i01725ent;
ARCHITECTURE c12s06b01x00p04n01i01725arch OF c12s06b01x00p04n01i01725ent IS
signal clk : bit;
BEGIN
TESTING: PROCESS
BEGIN
--
-- The signal assignment below tries to make two
-- assignments at the same (current) time.
--
clk <= '0', '1';
assert FALSE
report "***FAILED TEST: c12s06b01x00p04n01i01725 - The signal assignment can not make two assignment at the same (current) time."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n01i01725arch;
|
architecture RTL of ENTITY_NAME is
begin
process
begin
FORCE_LABEL : sig1 := a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 := a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 := a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 := a + b - c, d + e;
FORCE_LABEL : sig1 := a + b - c;
FORCE_LABEL : sig2 := a;
sig2 := a;
end process;
end architecture RTL;
|
--------------------------------------------------------------------------------
-- Entity: extender
-- Date:2017-04-22
-- Author: Gideon
--
-- Description: This unit is meant to fit in an external PLD for I/O extension
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity extender_u64 is
port (
reset_n : in std_logic;
data : inout std_logic_vector(7 downto 0);
read : in std_logic;
write : in std_logic;
address : in unsigned(2 downto 0);
cia1_pa : inout std_logic_vector(7 downto 0);
cia1_pb : inout std_logic_vector(7 downto 0);
cia2_pa : inout std_logic_vector(7 downto 0);
cia2_pb : inout std_logic_vector(7 downto 0);
lightpen : out std_logic
);
end entity;
architecture arch of extender_u64 is
signal cia1_pa_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia1_pa_o : std_logic_vector(7 downto 0) := (others => '0');
signal cia1_pb_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia1_pb_o : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pa_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pa_o : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pb_t : std_logic_vector(7 downto 0) := (others => '0');
signal cia2_pb_o : std_logic_vector(7 downto 0) := (others => '0');
signal read_data : std_logic_vector(7 downto 0);
signal read_2pa : std_logic_vector(7 downto 0);
begin
-- CIA1 Port A and B have pull ups on the board (joy / keyboard: read pin)
-- CIA2 Port A:
-- 0: VA14 (should read '1' when input, else read output)
-- 1: VA15 (should read '1' when input, else read output)
-- 2: UserPort pin (needs pull up), read actual pin
-- 3: ATN Out (should read '1' when input, else read output)
-- 4: CLOCK Out (should read '1' when input, else read output)
-- 5: DATA Out (should read '1' when input, else read output)
-- 6: CLOCK In - connected to CLK pin of IEC bus, reads the correct value
-- 7: DATA In - connected to DATA pin of IEC bus, reads the correct value
-- CIA2 Port B:
-- 0: UserPort pin (needs pull up, read pin)
-- 1: UserPort pin (needs pull up, read pin)
-- 2: UserPort pin (needs pull up, read pin)
-- 3: UserPort pin (needs pull up, read pin)
-- 4: UserPort pin (needs pull up, read pin)
-- 5: UserPort pin (needs pull up, read pin)
-- 6: UserPort pin (needs pull up, read pin)
-- 7: UserPort pin (needs pull up, read pin)
read_2pa(0) <= cia2_pa_o(0) or not cia2_pa_t(0);
read_2pa(1) <= cia2_pa_o(1) or not cia2_pa_t(1);
read_2pa(2) <= cia2_pa(2);
read_2pa(3) <= cia2_pa_o(3) or not cia2_pa_t(3);
read_2pa(4) <= cia2_pa_o(4) or not cia2_pa_t(4);
read_2pa(5) <= cia2_pa_o(5) or not cia2_pa_t(5);
read_2pa(6) <= cia2_pa(6);
read_2pa(7) <= cia2_pa(7);
process(cia1_pa, cia1_pb, cia2_pa, read_2pa, address)
begin
case address is
when "000" =>
read_data <= cia1_pa;
when "001" =>
read_data <= cia1_pb;
-- when "010" =>
-- read_data <= cia1_pa_t;
-- when "011" =>
-- read_data <= cia1_pb_t;
when "100" =>
read_data <= read_2pa;
when "101" =>
read_data <= cia2_pa;
-- when "110" =>
-- read_data <= cia2_pa_t;
-- when "111" =>
-- read_data <= cia2_pb_t;
when others =>
read_data <= X"FF";
end case;
end process;
data <= read_data when read = '0' else "ZZZZZZZZ";
process(write, reset_n)
begin
if reset_n = '0' then
cia1_pa_t <= (others => '0');
cia1_pa_o <= (others => '0');
cia1_pb_t <= (others => '0');
cia1_pb_o <= (others => '0');
cia2_pa_t <= (others => '0');
cia2_pa_o <= (others => '0');
cia2_pb_t <= (others => '0');
cia2_pb_o <= (others => '0');
elsif rising_edge(write) then
case address is
when "000" => -- CIA1 PA
cia1_pa_o <= data;
when "001" => -- CIA1 PB
cia1_pb_o <= data;
when "010" => -- CIA1 PA DDR
cia1_pa_t <= data;
when "011" => -- CIA1 PB DDR
cia1_pb_t(5 downto 0) <= data(5 downto 0); -- we never drive the B ports, bit 6 and 7, the FPGA does
when "100" => -- CIA2 PA
cia2_pa_o <= data;
when "101" => -- CIA2 PB
cia2_pb_o <= data;
when "110" => -- CIA2 PA DDR
cia2_pa_t <= data;
when "111" => -- CIA2 PB DDR
cia2_pb_t(5 downto 0) <= data(5 downto 0); -- we never drive the B ports, bit 6 and 7, the FPGA does
when others =>
null;
end case;
end if;
end process;
r1: for i in 0 to 7 generate
cia1_pa(i) <= '0' when cia1_pa_o(i) = '0' and cia1_pa_t(i) = '1' else 'Z';
cia1_pb(i) <= '0' when cia1_pb_o(i) = '0' and cia1_pb_t(i) = '1' else 'Z';
end generate;
-- cia2_pa <= "ZZZZZZZZ";
cia2_pb <= "ZZZZZZZZ";
r2: for i in 0 to 7 generate
cia2_pa(i) <= cia2_pa_o(i) when cia2_pa_t(i) = '1' else 'Z';
-- cia2_pb(i) <= '0' when cia2_pb_o(i) = '0' and cia2_pb_t(i) = '1' else 'Z';
end generate;
lightpen <= cia1_pb(4);
end architecture;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_PB_Tracer_ILA.vhd
-- /___/ /\ Timestamp : Sat Jun 27 15:57:29 Mitteleuropäische Sommerzeit 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_PB_Tracer_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(62 downto 0);
TRIG0: in std_logic_vector(14 downto 0);
TRIG1: in std_logic_vector(7 downto 0);
TRIG2: in std_logic_vector(5 downto 0);
TRIG3: in std_logic_vector(15 downto 0);
TRIG_OUT: out std_logic);
END CSP_PB_Tracer_ILA;
ARCHITECTURE CSP_PB_Tracer_ILA_a OF CSP_PB_Tracer_ILA IS
BEGIN
END CSP_PB_Tracer_ILA_a;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_56 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_56;
architecture BEHAVIORAL of dcm_32_56 is
signal CLKFX_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
CLK2X_BUFG_INST : BUFG
port map (I => CLK2X_BUF, O => CLK2X_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 56.00 = 32.000 * 7/4
CLKFX_MULTIPLY => 7,
CLKFX_DIVIDE => 4,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_BUF,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
-- $Id: crc16.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: crc16 - syn
-- Description: 16bit CRC generator, use CCITT polynomial
-- x^16 + x^12 + x^5 + 1 (0x1021)
--
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-09-27 595 14.7 131013 xc6slx16-2 16 16 - 4
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-27 595 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.comlib.all;
entity crc16 is -- crc-16 generator, checker
generic (
INIT: slv16 := (others=>'0')); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv16 -- crc code
);
end crc16;
architecture syn of crc16 is
signal R_CRC : slv16 := INIT; -- state registers
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_CRC <= INIT;
else
if ENA = '1' then
R_CRC <= crc16_update(R_CRC, DI);
end if;
end if;
end if;
end process proc_regs;
CRC <= R_CRC;
end syn;
|
------------------------------------------------------------------------------
---- ----
---- I2C Master Core Package ----
---- ----
---- Internal file, can't be downloaded. ----
---- ----
---- Description: ----
---- I2C Master module. Implemented as a Wishbone Slave. (Wishbone to ----
---- I2C bridge?). Package for the code by Richard Herveille. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti gov ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2005 Salvador E. Tropea <salvador en inti gov ar> ----
---- Copyright (c) 2005 Instituto Nacional de Tecnolog Industrial ----
---- ----
---- Covered by the GPL license. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: I2C_Master (Package) ----
---- File name: i2c_master_pkg.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: i2c_mwb ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan II (XC2S100-5-PQ208) ----
---- Language: VHDL ----
---- Wishbone: SLAVE (rev B.2) ----
---- Synthesis tools: Xilinx Release 6.2.03i - xst G.31a ----
---- Simulation tools: GHDL [Sokcho edition] (0.1x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: i2c_master_pkg.vhdl,v $
-- Revision 1.10 2006/04/17 19:44:43 salvador
-- * Modified: License to GPL.
--
-- Revision 1.9 2005/05/20 14:39:05 salvador
-- * Modificado: Mejorado el indentado usando bakalint 0.3.7.
--
-- Revision 1.8 2005/05/18 14:50:19 salvador
-- * Modificado: Los encabezados de los archivos para que cumplan con nuestras
-- recomendaciones.
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package I2C_Master is
component I2C_MasterTop is
generic(
ARST_LVL : std_logic:='0'; -- asynchronous reset level
DEBUG : boolean:=false; -- enable debug registers
MUX_BETTER : boolean:=false; -- true if using MUX is better than using tri-states
FULL_SYNC : boolean:=false; -- true if you need full synchronous behavior, introduces 1 WS
FIXED_PRER : integer:=-1; -- assigning a value removes the PRER and uses it as pre-scaler
USE_IEN : boolean:=true -- false if interrupts are always enabled (masked in another component)
);
port(-- Wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in unsigned(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic:='1'; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end component I2C_MasterTop;
-- EXPORT CONSTANTS
constant I2C_CTR : std_logic_vector(7 downto 0):="00000000";
constant I2C_RXR : std_logic_vector(7 downto 0):="00000001";
constant I2C_TXR : std_logic_vector(7 downto 0):="00000001";
constant I2C_CR : std_logic_vector(7 downto 0):="00000010";
constant I2C_SR : std_logic_vector(7 downto 0):="00000010";
constant I2C_PRER_LO : std_logic_vector(7 downto 0):="00000011";
constant I2C_PRER_HI : std_logic_vector(7 downto 0):="00000100";
-- END EXPORT CONSTANTS
constant I2C_TXR_R : std_logic_vector(7 downto 0):="00000101"; -- undocumented / reserved output
constant I2C_CR_R : std_logic_vector(7 downto 0):="00000110"; -- undocumented / reserved output
constant I2C_XXX_R : std_logic_vector(7 downto 0):="00000111"; -- undocumented / reserved output
constant I2C_UCTR : unsigned(2 downto 0):="000";
constant I2C_URXR : unsigned(2 downto 0):="001";
constant I2C_UTXR : unsigned(2 downto 0):="001";
constant I2C_UCR : unsigned(2 downto 0):="010";
constant I2C_USR : unsigned(2 downto 0):="010";
constant I2C_UPRER_LO : unsigned(2 downto 0):="011";
constant I2C_UPRER_HI : unsigned(2 downto 0):="100";
constant I2C_UTXR_R : unsigned(2 downto 0):="101"; -- undocumented / reserved output
constant I2C_UCR_R : unsigned(2 downto 0):="110"; -- undocumented / reserved output
constant I2C_UXXX_R : unsigned(2 downto 0):="111"; -- undocumented / reserved output
end package I2C_Master;
|
-------------------------------------------------------------------------------
--
-- The Interface Timing Checker.
--
-- $Id: if_timing-c.vhd,v 1.1 2004-04-25 16:24:10 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration if_timing_behav_c0 of if_timing is
for behav
end for;
end if_timing_behav_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-- Generic size shift register for enabling the nodes inside the network
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY FSM_ENABLE_NODES IS
GENERIC (NODES : integer := 8;
ADDR : integer := 3);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
M_SET : IN std_logic;
ZERO : IN std_logic;
ONE : IN std_logic;
DIN : IN std_logic_vector(ADDR-1 downto 0);
SH_DONE : OUT std_logic;
DOUT : OUT std_logic_vector(NODES-1 downto 0));
END FSM_ENABLE_NODES;
ARCHITECTURE structural OF FSM_ENABLE_NODES IS
COMPONENT Generic_shift_register_enable IS
GENERIC (N : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
SHF_EN : IN std_logic;
DIN : IN std_logic;
DOUT : OUT std_logic_vector(N-1 downto 0));
END COMPONENT;
COMPONENT Generic_register IS
GENERIC (N : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N-1 downto 0));
END COMPONENT;
COMPONENT Generic_zero_comparator IS
GENERIC (N : integer);
PORT (
OP : IN std_logic_vector(N-1 downto 0);
EN : IN std_logic;
EQ : OUT std_logic);
END COMPONENT;
COMPONENT SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic);
END COMPONENT;
SIGNAL data_pin : std_logic_vector(ADDR-1 downto 0);
SIGNAL count : std_logic_vector(ADDR-1 downto 0);
SIGNAL count_minus_one : std_logic_vector(ADDR-1 downto 0);
SIGNAL zero1 : std_logic;
SIGNAL one1 : std_logic;
SIGNAL shift : std_logic;
SIGNAL shift_zero : std_logic;
SIGNAL shift_one : std_logic;
SIGNAL data_in : std_logic;
SIGNAL count_en : std_logic;
SIGNAL stop : std_logic;
SIGNAL one_end : std_logic;
type state_zero is (S0,S1,S2);
signal CR_ZERO, NX: state_zero;
type state_one is (T0,T1,T2,T3);
signal CR_ONE, TX: state_one;
BEGIN
-- zero synch latch
ZERO_LATCH : SYNC_LATCH
port map(
DIN => ZERO,
CLK => CLK,
RST => RST,
EN => EN,
DOUT => zero1);
-- one synch latch
ONE_LATCH : SYNC_LATCH
port map(
DIN => ONE,
CLK => CLK,
RST => RST,
EN => EN,
DOUT => one1);
-- hold the value to enable and disable the nodes
SR : Generic_shift_register_enable
generic map(NODES)
port map(
CLK => CLK,
RST => M_SET,
SHF_EN => shift,
DIN => data_in,
DOUT => DOUT);
-- hold the current number of ones to shift in
REG : Generic_register
generic map(ADDR)
port map(
CLK => CLK,
RST => RST,
EN => EN,
DIN => data_pin,
DOUT => count);
-- Initial counter value (MUX)
OR_GEN : for i in 0 to (ADDR-1) generate
data_pin(i) <= (count_minus_one(i) AND count_en) OR (DIN(i) AND NOT(count_en));
end generate;
-- decrease the value of the counter
count_minus_one <= count - 1;
-- check when to stop shifting ones
ZERO_COMP : Generic_zero_comparator
generic map(ADDR)
port map(
OP => count,
EN => EN,
EQ => stop);
-- FSMs to control the structure
process (CLK,RST)
begin
if (RST='1') then
CR_ZERO <= S0;
CR_ONE <= T0;
elsif (CLK'event and CLK='1') then
CR_ZERO <= NX;
CR_ONE <= TX;
end if;
end process;
process (CR_ZERO, zero1)
begin
case CR_ZERO is
when S0 =>
shift_zero <= '0';
if zero1 = '1' then
NX <= S1;
else
NX <= S0;
end if;
when S1 =>
shift_zero <= '1';
NX <= S2;
when S2 =>
shift_zero <= '0';
NX <= S0;
end case;
end process;
process (CR_ONE, one1, stop)
begin
case CR_ONE is
when T0 =>
count_en <= '0';
shift_one <= '0';
data_in <= '0';
one_end <= '1';
if one1 = '1' then
TX <= T1;
else
TX <= T0;
end if;
when T1 =>
count_en <= '1';
shift_one <= '0';
data_in <= '0';
one_end <= '0';
TX <= T2;
when T2 =>
count_en <= '1';
shift_one <= '1';
data_in <= '1';
one_end <= '0';
if stop = '1' then
TX <= T3;
else
TX <= T2;
end if;
when T3 =>
count_en <= '0';
shift_one <= '0';
data_in <= '0';
one_end <= '1';
TX <= T0;
end case;
end process;
shift <= shift_one OR shift_zero;
SH_DONE <= one_end;
END structural;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ddr2ram.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
clk_img : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end ddr2ram;
architecture arc of ddr2ram is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKOUT4_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
clk_img : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 8;
constant C3_CLKOUT3_DIVIDE : integer := 4;
constant C3_CLKOUT4_DIVIDE : integer := 25; -- img clock divider
constant C3_CLKFBOUT_MULT : integer := 25;
constant C3_DIVCLK_DIVIDE : integer := 4;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKOUT4_DIVIDE => C3_CLKOUT4_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
clk_img => clk_img,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p2_cmd_clk => c3_p2_cmd_clk,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_rd_clk => c3_p2_rd_clk,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
p3_cmd_clk => c3_p3_cmd_clk,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_wr_clk => c3_p3_wr_clk,
p3_wr_en => c3_p3_wr_en,
p3_wr_mask => c3_p3_wr_mask,
p3_wr_data => c3_p3_wr_data,
p3_wr_full => c3_p3_wr_full,
p3_wr_empty => c3_p3_wr_empty,
p3_wr_count => c3_p3_wr_count,
p3_wr_underrun => c3_p3_wr_underrun,
p3_wr_error => c3_p3_wr_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ddr2ram.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
clk_img : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end ddr2ram;
architecture arc of ddr2ram is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKOUT4_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
clk_img : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 8;
constant C3_CLKOUT3_DIVIDE : integer := 4;
constant C3_CLKOUT4_DIVIDE : integer := 25; -- img clock divider
constant C3_CLKFBOUT_MULT : integer := 25;
constant C3_DIVCLK_DIVIDE : integer := 4;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKOUT4_DIVIDE => C3_CLKOUT4_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
clk_img => clk_img,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p2_cmd_clk => c3_p2_cmd_clk,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_rd_clk => c3_p2_rd_clk,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
p3_cmd_clk => c3_p3_cmd_clk,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_wr_clk => c3_p3_wr_clk,
p3_wr_en => c3_p3_wr_en,
p3_wr_mask => c3_p3_wr_mask,
p3_wr_data => c3_p3_wr_data,
p3_wr_full => c3_p3_wr_full,
p3_wr_empty => c3_p3_wr_empty,
p3_wr_count => c3_p3_wr_count,
p3_wr_underrun => c3_p3_wr_underrun,
p3_wr_error => c3_p3_wr_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ddr2ram.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
clk_img : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end ddr2ram;
architecture arc of ddr2ram is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKOUT4_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
clk_img : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 8;
constant C3_CLKOUT3_DIVIDE : integer := 4;
constant C3_CLKOUT4_DIVIDE : integer := 25; -- img clock divider
constant C3_CLKFBOUT_MULT : integer := 25;
constant C3_DIVCLK_DIVIDE : integer := 4;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKOUT4_DIVIDE => C3_CLKOUT4_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
clk_img => clk_img,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p2_cmd_clk => c3_p2_cmd_clk,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_rd_clk => c3_p2_rd_clk,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
p3_cmd_clk => c3_p3_cmd_clk,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_wr_clk => c3_p3_wr_clk,
p3_wr_en => c3_p3_wr_en,
p3_wr_mask => c3_p3_wr_mask,
p3_wr_data => c3_p3_wr_data,
p3_wr_full => c3_p3_wr_full,
p3_wr_empty => c3_p3_wr_empty,
p3_wr_count => c3_p3_wr_count,
p3_wr_underrun => c3_p3_wr_underrun,
p3_wr_error => c3_p3_wr_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FIFO_testbench IS
END FIFO_testbench;
ARCHITECTURE behavior OF FIFO_testbench IS
-- inputs
SIGNAL clk : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC := '0';
SIGNAL wr_en : STD_LOGIC := '0';
SIGNAL wr_data : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_en : STD_LOGIC := '0';
-- outputs
SIGNAL rd_data : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL empty : STD_LOGIC;
SIGNAL full : STD_LOGIC;
-- clock period definitions
CONSTANT clk_period : TIME := 10 ns;
BEGIN
-- instantiate the Unit Under Test (UUT)
uut : ENTITY work.FIFO GENERIC
MAP (
RAM_WIDTH => 4,
RAM_DEPTH => 5
) PORT MAP
(
clk => clk,
rst => rst,
wr_en => wr_en,
wr_data => wr_data,
rd_en => rd_en,
rd_data => rd_data,
empty => empty,
full => full
);
-- clock process definitions
clk_process : PROCESS
BEGIN
clk <= '0';
WAIT FOR clk_period/2;
clk <= '1';
WAIT FOR clk_period/2;
END PROCESS;
-- stimulus process
stim_proc : PROCESS
BEGIN
-- hold reset state for 100 ns.
WAIT FOR 100 ns;
rst <= '1';
WAIT FOR clk_period * 10;
rst <= '0';
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "1100";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0011";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "1111";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0000";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0001";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "1010";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "1010";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
wr_data <= "1010";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
wr_data <= "0101";
wr_en <= '1';
WAIT FOR clk_period;
wr_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
rd_en <= '1';
WAIT FOR clk_period;
rd_en <= '0';
WAIT FOR clk_period;
WAIT;
END PROCESS;
END;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare6.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare6 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare6;
ARCHITECTURE SYN OF lpm_compare6 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(9 DOWNTO 0) <= "1000001011";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 10
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "523"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
-- Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
-- Retrieval info: CONNECT: @datab 0 0 10 0 523 0 0 10 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- $Id: sn_humanio_emu_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_emu_rbus - syn
-- Description: sn_humanio rbus emulator
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2017.1-2019,1; ghdl 0.34-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0 Initial version (derived from sn_humanio_rbus
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 000 stat r/-/- Status register
-- 15 emu r/-/- emulation (always 1)
-- 14:12 hdig r/-/- display size as (2**DCWIDTH)-1
-- 11:08 hled r/-/- led size as LWIDTH-1
-- 7:04 hbtn r/-/- button size as BWIDTH-1
-- 3:00 hswi r/-/- switch size as SWIDTH-1
--
-- 001 cntl r/w/- Control register
-- 4 dsp1_en r/-/- always 0
-- 3 dsp0_en r/-/- always 0
-- 2 dp_en r/-/- always 0
-- 1 led_en r/-/- always 0
-- 0 swi_en r/-/- always 1: SWI will be driven by rbus
--
-- 010 x:00 btn -/-/f w: will pulse BTN
-- 011 x:00 swi r/w/- SWI status
-- 100 x:00 led r/-/- LED status
-- 101 x:00 dp r/-/- DSP_DP status
-- 110 15:00 dsp0 r/-/- DSP_DAT lsb status
-- 111 15:00 dsp1 r/-/- DSP_DAT msb status
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_emu_rbus is -- sn_humanio rbus emulator
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings
BTN : out slv(BWIDTH-1 downto 0); -- button settings
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0) -- display decimal points
);
end sn_humanio_emu_rbus;
architecture syn of sn_humanio_emu_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv(SWIDTH-1 downto 0); -- rbus swi
btn : slv(BWIDTH-1 downto 0); -- rbus btn
led : slv(LWIDTH-1 downto 0); -- hio led
dsp_dat : slv(4*(2**DCWIDTH)-1 downto 0); -- hio dsp_dat
dsp_dp : slv((2**DCWIDTH)-1 downto 0); -- hio dsp_dp
end record regs_type;
constant swizero : slv(SWIDTH-1 downto 0) := (others=>'0');
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant ledzero : slv(LWIDTH-1 downto 0) := (others=>'0');
constant dpzero : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
constant datzero : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
swizero, -- swi
btnzero, -- btn
ledzero, -- led
datzero, -- dsp_dat
dpzero -- dsp_dp
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
constant stat_rbf_emu: integer := 15;
subtype stat_rbf_hdig is integer range 14 downto 12;
subtype stat_rbf_hled is integer range 11 downto 8;
subtype stat_rbf_hbtn is integer range 7 downto 4;
subtype stat_rbf_hswi is integer range 3 downto 0;
constant cntl_rbf_dsp1_en: integer := 4;
constant cntl_rbf_dsp0_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
constant rbaddr_stat: slv3 := "000"; -- 0 r/-/-
constant rbaddr_cntl: slv3 := "001"; -- 0 r/w/-
constant rbaddr_btn: slv3 := "010"; -- 1 -/-/f
constant rbaddr_swi: slv3 := "011"; -- 1 r/w/-
constant rbaddr_led: slv3 := "100"; -- 2 r/-/-
constant rbaddr_dp: slv3 := "101"; -- 3 r/-/-
constant rbaddr_dsp0: slv3 := "110"; -- 4 r/-/-
constant rbaddr_dsp1: slv3 := "111"; -- 5 r/-/-
subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16;
subtype dspdat_lsb is integer range 15 downto 0;
begin
assert SWIDTH<=16
report "assert (SWIDTH<=16)"
severity failure;
assert BWIDTH<=8
report "assert (BWIDTH<=8)"
severity failure;
assert LWIDTH<=16
report "assert (LWIDTH<=16)"
severity failure;
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- input registers
n.led := LED;
n.dsp_dat := DSP_DAT;
n.dsp_dp := DSP_DP;
-- clear btn register --> cause single cycle pulses
n.btn := (others=>'0');
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_emu) := '1';
irb_dout(stat_rbf_hdig) := slv(to_unsigned((2**DCWIDTH)-1,3));
irb_dout(stat_rbf_hled) := slv(to_unsigned(LWIDTH-1,4));
irb_dout(stat_rbf_hbtn) := slv(to_unsigned(BWIDTH-1,4));
irb_dout(stat_rbf_hswi) := slv(to_unsigned(SWIDTH-1,4));
if RB_MREQ.we = '1' then
irb_ack := '0';
end if;
when rbaddr_cntl =>
irb_dout(cntl_rbf_dsp1_en) := '0';
irb_dout(cntl_rbf_dsp0_en) := '0';
irb_dout(cntl_rbf_dp_en) := '0';
irb_dout(cntl_rbf_led_en) := '0';
irb_dout(cntl_rbf_swi_en) := '1';
when rbaddr_btn =>
irb_dout(r.btn'range) := r.btn;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(n.btn'range);
end if;
when rbaddr_swi =>
irb_dout(r.swi'range) := r.swi;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_led =>
irb_dout(r.led'range) := r.led;
when rbaddr_dp =>
irb_dout(r.dsp_dp'range) := r.dsp_dp;
when rbaddr_dsp0 =>
irb_dout := r.dsp_dat(dspdat_lsb);
when rbaddr_dsp1 =>
irb_dout := r.dsp_dat(dspdat_msb);
when others => null;
end case;
end if;
N_REGS <= n;
BTN <= R_REGS.btn;
SWI <= R_REGS.swi;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:06:25 05/22/2013
-- Design Name:
-- Module Name: JK_viva - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity JK_viva is
Port ( JK : in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC;
Qn : out STD_LOGIC;
CLK : in STD_LOGIC);
end JK_viva;
architecture Behavioral of JK_viva is
begin
process(s)
begin
if(clk'event and clk='1') then
case JK is
when "00" => null;
when "10" => Q <= '1' ; qn <= '0';
when "01" => q <= '0' ; Qn <= '1';
when "11" => Q <= not q ; Qn <= not Qn;
when others => null;
end case;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
-- end not in book
entity program_ROM is
port ( address : in std_ulogic_vector(14 downto 0);
data : out std_ulogic_vector(7 downto 0);
enable : in std_ulogic );
subtype instruction_byte is bit_vector(7 downto 0);
type program_array is array (0 to 2**14 - 1) of instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
-- not in book
others => X"00"
-- end not in book
-- . . .
);
end entity program_ROM;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
-- end not in book
entity program_ROM is
port ( address : in std_ulogic_vector(14 downto 0);
data : out std_ulogic_vector(7 downto 0);
enable : in std_ulogic );
subtype instruction_byte is bit_vector(7 downto 0);
type program_array is array (0 to 2**14 - 1) of instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
-- not in book
others => X"00"
-- end not in book
-- . . .
);
end entity program_ROM;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
-- end not in book
entity program_ROM is
port ( address : in std_ulogic_vector(14 downto 0);
data : out std_ulogic_vector(7 downto 0);
enable : in std_ulogic );
subtype instruction_byte is bit_vector(7 downto 0);
type program_array is array (0 to 2**14 - 1) of instruction_byte;
constant program : program_array
:= ( X"32", X"3F", X"03", -- LDA $3F03
X"71", X"23", -- BLT $23
-- not in book
others => X"00"
-- end not in book
-- . . .
);
end entity program_ROM;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_as7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2018.3; ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-12 1105 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 9; -- vco 900 MHz
constant sys_conf_clksys_outdivide : positive := 12; -- sys 75 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
-- NEED RESULT: ARCH00112.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00112.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00112.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00112: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00112: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00112: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00112: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00112: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00112: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00112
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00112(ARCH00112)
-- ENT00112_Test_Bench(ARCH00112_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00112 is
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00112.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00112" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00112" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00112" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00112.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00112" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00112" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00112" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00112.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00112" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00112" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00112" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00112 ;
--
architecture ARCH00112 of ENT00112 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
end process P3 ;
--
--
end ARCH00112 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00112_Test_Bench is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
end ENT00112_Test_Bench ;
--
architecture ARCH00112_Test_Bench of ENT00112_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00112 ( ARCH00112 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
) ;
end block L1 ;
end ARCH00112_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2222.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02222ent IS
END c07s02b06x00p01n01i02222ent;
ARCHITECTURE c07s02b06x00p01n01i02222arch OF c07s02b06x00p01n01i02222ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV rem '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02222 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02222arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2222.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02222ent IS
END c07s02b06x00p01n01i02222ent;
ARCHITECTURE c07s02b06x00p01n01i02222arch OF c07s02b06x00p01n01i02222ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV rem '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02222 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02222arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2222.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02222ent IS
END c07s02b06x00p01n01i02222ent;
ARCHITECTURE c07s02b06x00p01n01i02222arch OF c07s02b06x00p01n01i02222ent IS
BEGIN
TESTING: PROCESS
variable BITV : BIT := '0';
variable k : integer;
BEGIN
k := BITV rem '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02222 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02222arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity UART_RX is
Generic
(
DBIT : integer := 8; -- # Data BITS
SB_TICK : integer := 16 -- # Stop BITS Tick (1 -> 16, 1.5 -> 24, 2 -> 32)
);
Port
(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RX : in STD_LOGIC;
S_TICK : in STD_LOGIC;
RX_DONE_TICK : out STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (7 downto 0)
);
end UART_RX;
-------------------------------------------------------------------------
architecture Behavioral of UART_RX is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type;
signal s_reg, s_next: unsigned(3 downto 0);
signal n_reg, n_next: unsigned(2 downto 0);
signal b_reg, b_next: std_logic_vector(7 downto 0);
begin
-- FSMD state & data registers
process(CLK,RESET)
begin
if RESET='1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
elsif (CLK'event and CLK='1') then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end if;
end process;
-- Next-state logic & data path functional units/routing
process(state_reg,s_reg,n_reg,b_reg,S_TICK,RX)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
RX_DONE_TICK <='0';
case state_reg is
when idle =>
if RX='0' then
state_next <= start;
s_next <= (others=>'0');
end if;
when start =>
if (S_TICK = '1') then
if s_reg=7 then
state_next <= data;
s_next <= (others=>'0');
n_next <= (others=>'0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
if (S_TICK = '1') then
if s_reg=15 then
s_next <= (others=>'0');
b_next <= RX & b_reg(7 downto 1);
if n_reg=(DBIT-1) then
state_next <= stop;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
if (S_TICK = '1') then
RX_DONE_TICK <='1';
if s_reg=(SB_TICK-1) then
state_next <= idle;
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
DOUT <= b_reg;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_library_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 1 -- global switch - round all ieee<=>x conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 1; -- 1 = single x format (s32/13)
funcoutput : integer := 0; -- 1 = function (S'1'mantissa-2/10)
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32+(mantissa-22)*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (mantissa/10)
funcoutput : integer := 1 -- function output (S'1'mantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_inv2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_invsqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_sqr2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_exp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ln2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doublemult : integer := 0; -- global switch - '0' 54x54 = 8x18x18, '1' 54x54 = 9/10x18x18
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_abs2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
END hcc_library_package;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_ovfl-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of overflow_logic is
constant Tpd_in_out : time := 3 ns;
begin
ovf <= real_accumulator_ovf or imag_accumulator_ovf
or ( real_sum(21) xor real_sum(20) )
or ( real_sum(21) xor real_sum(19) )
or ( real_sum(21) xor real_sum(18) )
or ( real_sum(21) xor real_sum(17) )
or ( imag_sum(21) xor imag_sum(20) )
or ( imag_sum(21) xor imag_sum(19) )
or ( imag_sum(21) xor imag_sum(18) )
or ( imag_sum(21) xor imag_sum(17) ) after Tpd_in_out;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_ovfl-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of overflow_logic is
constant Tpd_in_out : time := 3 ns;
begin
ovf <= real_accumulator_ovf or imag_accumulator_ovf
or ( real_sum(21) xor real_sum(20) )
or ( real_sum(21) xor real_sum(19) )
or ( real_sum(21) xor real_sum(18) )
or ( real_sum(21) xor real_sum(17) )
or ( imag_sum(21) xor imag_sum(20) )
or ( imag_sum(21) xor imag_sum(19) )
or ( imag_sum(21) xor imag_sum(18) )
or ( imag_sum(21) xor imag_sum(17) ) after Tpd_in_out;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_ovfl-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of overflow_logic is
constant Tpd_in_out : time := 3 ns;
begin
ovf <= real_accumulator_ovf or imag_accumulator_ovf
or ( real_sum(21) xor real_sum(20) )
or ( real_sum(21) xor real_sum(19) )
or ( real_sum(21) xor real_sum(18) )
or ( real_sum(21) xor real_sum(17) )
or ( imag_sum(21) xor imag_sum(20) )
or ( imag_sum(21) xor imag_sum(19) )
or ( imag_sum(21) xor imag_sum(18) )
or ( imag_sum(21) xor imag_sum(17) ) after Tpd_in_out;
end architecture behavioral;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net4,
G => vbias4,
S => gnd
);
end simple;
|
---------------------------------------------------------------------
-- TITLE: DDR SDRAM Interface
-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 7/26/07
-- FILENAME: ddr_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Double Data Rate Sychronous Dynamic Random Access Memory Interface
--
-- For: 64 MB = MT46V32M16, 512Mb, 32Mb x 16 (default)
-- ROW = address(25 downto 13)
-- BANK = address(12 downto 11)
-- COL = address(10 downto 2)
--
-- Changes are needed for 32 MB = MT46V16M16, 256Mb, 16Mb x 16
-- ROW = address(24 downto 12) -- 25 ignored
-- BANK = address(11 downto 10)
-- COL = address(9 downto 2) --also change ddr_init.c
--
-- Changes are needed for 128 MB = MT46V64M16, 1Gb, 64Mb x 16
-- ROW = address(26 downto 14)
-- BANK = address(13 downto 12)
-- COL = address(11 downto 2) --also change ddr_init.c
--
-- Requires CAS latency=2; burst size=2.
-- Requires clk changes on rising_edge(clk_2x).
-- Requires active, address, byte_we, data_w stable throughout transfer.
-- DLL mode requires 77MHz. Non-DLL mode runs at 25 MHz.
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____write+++WRITE+++____________________________
-- SD_DQ ~~~~~~~~~~~~~~uuuullllUUUULLLL~~~~~~~~~~~~~~~~~~
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____read++++________________________read++++____
-- SD_DQ ~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~~~
-- SD_DQnDLL ~~~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~
-- pause ____------------------------________------------
--
-- Must run DdrInit() to initialize DDR chip.
-- Read Micron DDR SDRAM MT46V32M16 data sheet for more details.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity ddr_ctrl is
port(
clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end; --entity ddr
architecture logic of ddr_ctrl is
--Commands for bits RAS & CAS & WE
subtype command_type is std_logic_vector(2 downto 0);
constant COMMAND_LMR : command_type := "000";
constant COMMAND_AUTO_REFRESH : command_type := "001";
constant COMMAND_PRECHARGE : command_type := "010";
constant COMMAND_ACTIVE : command_type := "011";
constant COMMAND_WRITE : command_type := "100";
constant COMMAND_READ : command_type := "101";
constant COMMAND_TERMINATE : command_type := "110";
constant COMMAND_NOP : command_type := "111";
subtype ddr_state_type is std_logic_vector(3 downto 0);
constant STATE_POWER_ON : ddr_state_type := "0000";
constant STATE_IDLE : ddr_state_type := "0001";
constant STATE_ROW_ACTIVATE : ddr_state_type := "0010";
constant STATE_ROW_ACTIVE : ddr_state_type := "0011";
constant STATE_READ : ddr_state_type := "0100";
constant STATE_READ2 : ddr_state_type := "0101";
constant STATE_READ3 : ddr_state_type := "0110";
constant STATE_PRECHARGE : ddr_state_type := "0111";
constant STATE_PRECHARGE2 : ddr_state_type := "1000";
signal state_prev : ddr_state_type;
signal refresh_cnt : std_logic_vector(7 downto 0);
signal data_write2 : std_logic_vector(47 downto 0); --write pipeline
signal byte_we_reg2 : std_logic_vector(5 downto 0); --write pipeline
signal write_active : std_logic;
signal write_prev : std_logic;
signal cycle_count : std_logic_vector(2 downto 0); --half clocks since op
signal cycle_count2 : std_logic_vector(2 downto 0); --delayed by quarter clock
signal cke_reg : std_logic;
signal clk_p : std_logic;
signal bank_open : std_logic_vector(3 downto 0);
signal data_read : std_logic_vector(31 downto 0);
begin
ddr_proc: process(clk, clk_p, clk_2x, reset_in,
address, byte_we, data_w, active, no_start, no_stop,
SD_DQ, SD_UDQS, SD_LDQS,
state_prev, refresh_cnt,
byte_we_reg2, data_write2,
cycle_count, cycle_count2, write_prev,
write_active, cke_reg, bank_open,
data_read)
type address_array_type is array(3 downto 0) of std_logic_vector(12 downto 0);
variable address_row : address_array_type;
variable command : std_logic_vector(2 downto 0); --RAS & CAS & WE
variable bank_index : integer;
variable state_current : ddr_state_type;
begin
command := COMMAND_NOP;
bank_index := conv_integer(address(12 downto 11));
state_current := state_prev;
--DDR state machine to determine state_current and command
case state_prev is
when STATE_POWER_ON =>
if active = '1' then
if byte_we /= "0000" then
command := address(6 downto 4); --LMR="000"
else
state_current := STATE_IDLE; --read transistions to STATE_IDLE
end if;
end if;
when STATE_IDLE =>
if refresh_cnt(7) = '1' then
state_current := STATE_PRECHARGE;
command := COMMAND_AUTO_REFRESH;
elsif active = '1' and no_start = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
end if;
when STATE_ROW_ACTIVATE =>
state_current := STATE_ROW_ACTIVE;
when STATE_ROW_ACTIVE =>
if refresh_cnt(7) = '1' then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
elsif active = '1' and no_start = '0' then
if bank_open(bank_index) = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
elsif address(25 downto 13) /= address_row(bank_index) then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
else
if byte_we /= "0000" then
command := COMMAND_WRITE;
elsif write_prev = '0' then
state_current := STATE_READ;
command := COMMAND_READ;
end if;
end if;
end if;
when STATE_READ =>
state_current := STATE_READ2;
when STATE_READ2 =>
state_current := STATE_READ3;
when STATE_READ3 =>
if no_stop = '0' then
state_current := STATE_ROW_ACTIVE;
end if;
when STATE_PRECHARGE =>
state_current := STATE_PRECHARGE2;
when STATE_PRECHARGE2 =>
state_current := STATE_IDLE;
when others =>
state_current := STATE_IDLE;
end case; --state_prev
--rising_edge(clk) domain registers
if reset_in = '1' then
state_prev <= STATE_POWER_ON;
cke_reg <= '0';
refresh_cnt <= ZERO(7 downto 0);
write_prev <= '0';
write_active <= '0';
bank_open <= "0000";
elsif rising_edge(clk) then
if active = '1' then
cke_reg <= '1';
end if;
if command = COMMAND_WRITE then
write_prev <= '1';
elsif cycle_count2(2 downto 1) = "11" then
write_prev <= '0';
end if;
if command = COMMAND_WRITE then
write_active <= '1';
elsif cycle_count2 = "100" then
write_active <= '0';
end if;
if command = COMMAND_ACTIVE then
bank_open(bank_index) <= '1';
address_row(bank_index) := address(25 downto 13);
end if;
if command = COMMAND_PRECHARGE then
bank_open <= "0000";
end if;
if command = COMMAND_AUTO_REFRESH then
refresh_cnt <= ZERO(7 downto 0);
else
refresh_cnt <= refresh_cnt + 1;
end if;
state_prev <= state_current;
end if; --rising_edge(clk)
--rising_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count <= "000";
elsif rising_edge(clk_2x) then
--Cycle_count
if (command = COMMAND_READ or command = COMMAND_WRITE) and clk = '1' then
cycle_count <= "000";
elsif cycle_count /= "111" then
cycle_count <= cycle_count + 1;
end if;
clk_p <= clk; --earlier version of not clk
--Read data (DLL disabled)
if cycle_count = "100" then
data_read(31 downto 16) <= SD_DQ; --data
elsif cycle_count = "101" then
data_read(15 downto 0) <= SD_DQ;
end if;
end if;
--falling_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count2 <= "000";
data_write2 <= ZERO(15 downto 0) & ZERO;
byte_we_reg2 <= "000000";
elsif falling_edge(clk_2x) then
cycle_count2 <= cycle_count;
--Write pipeline
if clk = '0' then
data_write2 <= data_write2(31 downto 16) & data_w;
byte_we_reg2 <= byte_we_reg2(3 downto 2) & byte_we;
else
data_write2(47 downto 16) <= data_write2(31 downto 0);
byte_we_reg2(5 downto 2) <= byte_we_reg2(3 downto 0);
end if;
--Read data (DLL enabled)
--if cycle_count = "100" then
-- data_read(31 downto 16) <= SD_DQ; --data
--elsif cycle_count = "101" then
-- data_read(15 downto 0) <= SD_DQ;
--end if;
end if;
data_r <= data_read;
--Write data
if write_active = '1' then
SD_UDQS <= clk_p; --upper_data_strobe
SD_LDQS <= clk_p; --low_data_strobe
SD_DQ <= data_write2(47 downto 32); --data
SD_UDM <= not byte_we_reg2(5); --upper_byte_enable
SD_LDM <= not byte_we_reg2(4); --low_byte_enable
else
SD_UDQS <= 'Z'; --upper_data_strobe
SD_LDQS <= 'Z'; --low_data_strobe
SD_DQ <= "ZZZZZZZZZZZZZZZZ"; --data
SD_UDM <= 'Z';
SD_LDM <= 'Z';
end if;
--DDR control signals
SD_CK_P <= clk_p; --clock_positive
SD_CK_N <= not clk_p; --clock_negative
SD_CKE <= cke_reg; --clock_enable
SD_BA <= address(12 downto 11); --bank_address
if command = COMMAND_ACTIVE or state_current = STATE_POWER_ON then
SD_A <= address(25 downto 13); --address row
elsif command = COMMAND_READ or command = COMMAND_WRITE then
SD_A <= "000" & address(10 downto 2) & "0"; --address col
else
SD_A <= "0010000000000"; --PERCHARGE all banks
end if;
SD_CS <= not cke_reg; --chip_select
SD_RAS <= command(2); --row_address_strobe
SD_CAS <= command(1); --column_address_strobe
SD_WE <= command(0); --write_enable
if active = '1' and state_current /= STATE_POWER_ON and
command /= COMMAND_WRITE and state_prev /= STATE_READ3 then
pause <= '1';
else
pause <= '0';
end if;
end process; --ddr_proc
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: DDR SDRAM Interface
-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 7/26/07
-- FILENAME: ddr_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Double Data Rate Sychronous Dynamic Random Access Memory Interface
--
-- For: 64 MB = MT46V32M16, 512Mb, 32Mb x 16 (default)
-- ROW = address(25 downto 13)
-- BANK = address(12 downto 11)
-- COL = address(10 downto 2)
--
-- Changes are needed for 32 MB = MT46V16M16, 256Mb, 16Mb x 16
-- ROW = address(24 downto 12) -- 25 ignored
-- BANK = address(11 downto 10)
-- COL = address(9 downto 2) --also change ddr_init.c
--
-- Changes are needed for 128 MB = MT46V64M16, 1Gb, 64Mb x 16
-- ROW = address(26 downto 14)
-- BANK = address(13 downto 12)
-- COL = address(11 downto 2) --also change ddr_init.c
--
-- Requires CAS latency=2; burst size=2.
-- Requires clk changes on rising_edge(clk_2x).
-- Requires active, address, byte_we, data_w stable throughout transfer.
-- DLL mode requires 77MHz. Non-DLL mode runs at 25 MHz.
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____write+++WRITE+++____________________________
-- SD_DQ ~~~~~~~~~~~~~~uuuullllUUUULLLL~~~~~~~~~~~~~~~~~~
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____read++++________________________read++++____
-- SD_DQ ~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~~~
-- SD_DQnDLL ~~~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~
-- pause ____------------------------________------------
--
-- Must run DdrInit() to initialize DDR chip.
-- Read Micron DDR SDRAM MT46V32M16 data sheet for more details.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity ddr_ctrl is
port(
clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end; --entity ddr
architecture logic of ddr_ctrl is
--Commands for bits RAS & CAS & WE
subtype command_type is std_logic_vector(2 downto 0);
constant COMMAND_LMR : command_type := "000";
constant COMMAND_AUTO_REFRESH : command_type := "001";
constant COMMAND_PRECHARGE : command_type := "010";
constant COMMAND_ACTIVE : command_type := "011";
constant COMMAND_WRITE : command_type := "100";
constant COMMAND_READ : command_type := "101";
constant COMMAND_TERMINATE : command_type := "110";
constant COMMAND_NOP : command_type := "111";
subtype ddr_state_type is std_logic_vector(3 downto 0);
constant STATE_POWER_ON : ddr_state_type := "0000";
constant STATE_IDLE : ddr_state_type := "0001";
constant STATE_ROW_ACTIVATE : ddr_state_type := "0010";
constant STATE_ROW_ACTIVE : ddr_state_type := "0011";
constant STATE_READ : ddr_state_type := "0100";
constant STATE_READ2 : ddr_state_type := "0101";
constant STATE_READ3 : ddr_state_type := "0110";
constant STATE_PRECHARGE : ddr_state_type := "0111";
constant STATE_PRECHARGE2 : ddr_state_type := "1000";
signal state_prev : ddr_state_type;
signal refresh_cnt : std_logic_vector(7 downto 0);
signal data_write2 : std_logic_vector(47 downto 0); --write pipeline
signal byte_we_reg2 : std_logic_vector(5 downto 0); --write pipeline
signal write_active : std_logic;
signal write_prev : std_logic;
signal cycle_count : std_logic_vector(2 downto 0); --half clocks since op
signal cycle_count2 : std_logic_vector(2 downto 0); --delayed by quarter clock
signal cke_reg : std_logic;
signal clk_p : std_logic;
signal bank_open : std_logic_vector(3 downto 0);
signal data_read : std_logic_vector(31 downto 0);
begin
ddr_proc: process(clk, clk_p, clk_2x, reset_in,
address, byte_we, data_w, active, no_start, no_stop,
SD_DQ, SD_UDQS, SD_LDQS,
state_prev, refresh_cnt,
byte_we_reg2, data_write2,
cycle_count, cycle_count2, write_prev,
write_active, cke_reg, bank_open,
data_read)
type address_array_type is array(3 downto 0) of std_logic_vector(12 downto 0);
variable address_row : address_array_type;
variable command : std_logic_vector(2 downto 0); --RAS & CAS & WE
variable bank_index : integer;
variable state_current : ddr_state_type;
begin
command := COMMAND_NOP;
bank_index := conv_integer(address(12 downto 11));
state_current := state_prev;
--DDR state machine to determine state_current and command
case state_prev is
when STATE_POWER_ON =>
if active = '1' then
if byte_we /= "0000" then
command := address(6 downto 4); --LMR="000"
else
state_current := STATE_IDLE; --read transistions to STATE_IDLE
end if;
end if;
when STATE_IDLE =>
if refresh_cnt(7) = '1' then
state_current := STATE_PRECHARGE;
command := COMMAND_AUTO_REFRESH;
elsif active = '1' and no_start = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
end if;
when STATE_ROW_ACTIVATE =>
state_current := STATE_ROW_ACTIVE;
when STATE_ROW_ACTIVE =>
if refresh_cnt(7) = '1' then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
elsif active = '1' and no_start = '0' then
if bank_open(bank_index) = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
elsif address(25 downto 13) /= address_row(bank_index) then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
else
if byte_we /= "0000" then
command := COMMAND_WRITE;
elsif write_prev = '0' then
state_current := STATE_READ;
command := COMMAND_READ;
end if;
end if;
end if;
when STATE_READ =>
state_current := STATE_READ2;
when STATE_READ2 =>
state_current := STATE_READ3;
when STATE_READ3 =>
if no_stop = '0' then
state_current := STATE_ROW_ACTIVE;
end if;
when STATE_PRECHARGE =>
state_current := STATE_PRECHARGE2;
when STATE_PRECHARGE2 =>
state_current := STATE_IDLE;
when others =>
state_current := STATE_IDLE;
end case; --state_prev
--rising_edge(clk) domain registers
if reset_in = '1' then
state_prev <= STATE_POWER_ON;
cke_reg <= '0';
refresh_cnt <= ZERO(7 downto 0);
write_prev <= '0';
write_active <= '0';
bank_open <= "0000";
elsif rising_edge(clk) then
if active = '1' then
cke_reg <= '1';
end if;
if command = COMMAND_WRITE then
write_prev <= '1';
elsif cycle_count2(2 downto 1) = "11" then
write_prev <= '0';
end if;
if command = COMMAND_WRITE then
write_active <= '1';
elsif cycle_count2 = "100" then
write_active <= '0';
end if;
if command = COMMAND_ACTIVE then
bank_open(bank_index) <= '1';
address_row(bank_index) := address(25 downto 13);
end if;
if command = COMMAND_PRECHARGE then
bank_open <= "0000";
end if;
if command = COMMAND_AUTO_REFRESH then
refresh_cnt <= ZERO(7 downto 0);
else
refresh_cnt <= refresh_cnt + 1;
end if;
state_prev <= state_current;
end if; --rising_edge(clk)
--rising_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count <= "000";
elsif rising_edge(clk_2x) then
--Cycle_count
if (command = COMMAND_READ or command = COMMAND_WRITE) and clk = '1' then
cycle_count <= "000";
elsif cycle_count /= "111" then
cycle_count <= cycle_count + 1;
end if;
clk_p <= clk; --earlier version of not clk
--Read data (DLL disabled)
if cycle_count = "100" then
data_read(31 downto 16) <= SD_DQ; --data
elsif cycle_count = "101" then
data_read(15 downto 0) <= SD_DQ;
end if;
end if;
--falling_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count2 <= "000";
data_write2 <= ZERO(15 downto 0) & ZERO;
byte_we_reg2 <= "000000";
elsif falling_edge(clk_2x) then
cycle_count2 <= cycle_count;
--Write pipeline
if clk = '0' then
data_write2 <= data_write2(31 downto 16) & data_w;
byte_we_reg2 <= byte_we_reg2(3 downto 2) & byte_we;
else
data_write2(47 downto 16) <= data_write2(31 downto 0);
byte_we_reg2(5 downto 2) <= byte_we_reg2(3 downto 0);
end if;
--Read data (DLL enabled)
--if cycle_count = "100" then
-- data_read(31 downto 16) <= SD_DQ; --data
--elsif cycle_count = "101" then
-- data_read(15 downto 0) <= SD_DQ;
--end if;
end if;
data_r <= data_read;
--Write data
if write_active = '1' then
SD_UDQS <= clk_p; --upper_data_strobe
SD_LDQS <= clk_p; --low_data_strobe
SD_DQ <= data_write2(47 downto 32); --data
SD_UDM <= not byte_we_reg2(5); --upper_byte_enable
SD_LDM <= not byte_we_reg2(4); --low_byte_enable
else
SD_UDQS <= 'Z'; --upper_data_strobe
SD_LDQS <= 'Z'; --low_data_strobe
SD_DQ <= "ZZZZZZZZZZZZZZZZ"; --data
SD_UDM <= 'Z';
SD_LDM <= 'Z';
end if;
--DDR control signals
SD_CK_P <= clk_p; --clock_positive
SD_CK_N <= not clk_p; --clock_negative
SD_CKE <= cke_reg; --clock_enable
SD_BA <= address(12 downto 11); --bank_address
if command = COMMAND_ACTIVE or state_current = STATE_POWER_ON then
SD_A <= address(25 downto 13); --address row
elsif command = COMMAND_READ or command = COMMAND_WRITE then
SD_A <= "000" & address(10 downto 2) & "0"; --address col
else
SD_A <= "0010000000000"; --PERCHARGE all banks
end if;
SD_CS <= not cke_reg; --chip_select
SD_RAS <= command(2); --row_address_strobe
SD_CAS <= command(1); --column_address_strobe
SD_WE <= command(0); --write_enable
if active = '1' and state_current /= STATE_POWER_ON and
command /= COMMAND_WRITE and state_prev /= STATE_READ3 then
pause <= '1';
else
pause <= '0';
end if;
end process; --ddr_proc
end; --architecture logic
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.