content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc362.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00362ent IS
END c03s02b01x01p02n01i00362ent;
ARCHITECTURE c03s02b01x01p02n01i00362arch OF c03s02b01x01p02n01i00362ent IS
type MVL1 is ('0', '1');
type MVL2 is ('X', 'Z');
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for I in MVL1'LOW to MVL2'HIGH loop -- failure_here
end loop;
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00362 - Bounds are of different discrete types"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00362arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc362.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00362ent IS
END c03s02b01x01p02n01i00362ent;
ARCHITECTURE c03s02b01x01p02n01i00362arch OF c03s02b01x01p02n01i00362ent IS
type MVL1 is ('0', '1');
type MVL2 is ('X', 'Z');
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for I in MVL1'LOW to MVL2'HIGH loop -- failure_here
end loop;
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00362 - Bounds are of different discrete types"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00362arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc362.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00362ent IS
END c03s02b01x01p02n01i00362ent;
ARCHITECTURE c03s02b01x01p02n01i00362arch OF c03s02b01x01p02n01i00362ent IS
type MVL1 is ('0', '1');
type MVL2 is ('X', 'Z');
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for I in MVL1'LOW to MVL2'HIGH loop -- failure_here
end loop;
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00362 - Bounds are of different discrete types"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00362arch;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_UART_ILA.vhd
-- /___/ /\ Timestamp : Tue Jun 09 21:51:35 Mitteleuropäische Sommerzeit 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_UART_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(29 downto 0);
TRIG_OUT: out std_logic);
END CSP_UART_ILA;
ARCHITECTURE CSP_UART_ILA_a OF CSP_UART_ILA IS
BEGIN
END CSP_UART_ILA_a;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pciahbmst
-- File: pciahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity pciahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in pci_ahb_dma_in_type;
dmao : out pci_ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of pciahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable kblimit : std_logic; -- 1 kB limit indicator
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq; kblimit := '0';
haddr := dmai.address; hbusreq := dmai.start; hwdata := dmai.wdata;
newaddr := dmai.address(10 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(10 downto 0) + inc;
if (newaddr(10) xor haddr(10)) = '1' then kblimit := '1'; end if;
end if;
-- hburst := HBURST_SINGLE;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
-- hburst := HBURST_INCR;
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr(9 downto 0);
if dmai.busy = '1' then htrans := HTRANS_BUSY;
elsif kblimit = '1' then htrans := HTRANS_IDLE;
else htrans := HTRANS_SEQ; end if;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if rst = '0' then v.retry := '0'; v.active := '0'; end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= ahbdrivedata(dmai.wdata);
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= '0' & dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr(9 downto 0);
dmao.rdata <= ahbreadword(ahbi.hrdata);
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
entity psl is
end;
architecture behav of psl is
signal a, b, c : bit;
signal clk : bit;
subtype wf_type is bit_vector (0 to 7);
constant wave_a : wf_type := "10010100";
constant wave_b : wf_type := "01001010";
constant wave_c : wf_type := "00100101";
begin
process
begin
for i in wf_type'range loop
clk <= '0';
wait for 1 ns;
a <= wave_a (i);
b <= wave_b (i);
c <= wave_c (i);
clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;
-- psl default clock is (clk'event and clk = '1');
-- psl a1: assert always a |=> b;
-- psl a2: assert always a -> eventually! c;
-- psl c1: cover {a;b;c};
end behav;
|
entity psl is
end;
architecture behav of psl is
signal a, b, c : bit;
signal clk : bit;
subtype wf_type is bit_vector (0 to 7);
constant wave_a : wf_type := "10010100";
constant wave_b : wf_type := "01001010";
constant wave_c : wf_type := "00100101";
begin
process
begin
for i in wf_type'range loop
clk <= '0';
wait for 1 ns;
a <= wave_a (i);
b <= wave_b (i);
c <= wave_c (i);
clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;
-- psl default clock is (clk'event and clk = '1');
-- psl a1: assert always a |=> b;
-- psl a2: assert always a -> eventually! c;
-- psl c1: cover {a;b;c};
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gr1553b_stdlogic
-- File: gr1553b_stdlogic.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Wrapper for GR1553B with std_logic ports
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.gr1553b_pkg.all;
entity gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq : out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable : in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end;
architecture rtl of gr1553b_stdlogic is
signal gr1553b_txout: gr1553b_txout_type;
signal gr1553b_rxin: gr1553b_rxin_type;
signal mi: ahb_mst_in_type;
signal mo: ahb_mst_out_type;
signal si: apb_slv_in_type;
signal so: apb_slv_out_type;
signal auxin: gr1553b_auxin_type;
signal auxout: gr1553b_auxout_type;
begin
x: gr1553b
generic map (
hindex => 0,
pindex => 0,
paddr => 0,
pmask => 0,
pirq => 0,
bc_enable => bc_enable,
rt_enable => rt_enable,
bm_enable => bm_enable,
bc_timer => bc_timer,
bc_rtbusmask => bc_rtbusmask,
syncrst => syncrst,
extra_regkeys => extra_regkeys,
ahbendian => ahbendian
)
port map (
clk => clk,
rst => rst,
ahbmi => mi,
ahbmo => mo,
apbsi => si,
apbso => so,
codec_clk => codec_clk,
codec_rst => codec_rst,
txout => gr1553b_txout,
txout_fb => gr1553b_txout,
rxin => gr1553b_rxin,
auxin => auxin,
auxout => auxout
);
mi.hgrant(0) <= mi_hgrant;
mi.hgrant(1 to NAHBMST-1) <= (others => '0');
mi.hready <= mi_hready;
mi.hresp <= mi_hresp;
mi.hrdata <= ahbdrivedata(mi_hrdata);
mi.hirq <= (others => '0');
mi.testen <= '0';
mi.testrst <= '0';
mi.scanen <= '0';
mi.testoen <= '0';
mo_hbusreq <= mo.hbusreq;
mo_htrans <= mo.htrans;
mo_haddr <= mo.haddr;
mo_hwrite <= mo.hwrite;
mo_hsize <= mo.hsize;
mo_hburst <= mo.hburst;
mo_hwdata <= ahbreadword(mo.hwdata);
si.psel(0) <= si_psel;
si.psel(1 to NAPBSLV-1) <= (others => '0');
si.penable <= si_penable;
si.paddr <= x"000000" & si_paddr;
si.pwrite <= si_pwrite;
si.pwdata <= si_pwdata;
si.pirq <= (others => '0');
si.testen <= '0';
si.testrst <= '0';
si.scanen <= '0';
si.testoen <= '0';
so_prdata <= so.prdata;
so_pirq <= so.pirq(0);
auxin.extsync <= bcsync;
auxin.rtaddr <= rtaddr;
auxin.rtpar <= rtaddrp;
rtsync <= auxout.rtsync;
busreset <= auxout.busreset;
busainen <= gr1553b_txout.busA_rxen;
gr1553b_rxin.busA_rxP <= busainp;
gr1553b_rxin.busA_rxN <= busainn;
busaouten <= gr1553b_txout.busA_txen;
busaoutp <= gr1553b_txout.busA_txP;
busaoutn <= gr1553b_txout.busA_txN;
busBinen <= gr1553b_txout.busB_rxen;
gr1553b_rxin.busB_rxP <= busBinp;
gr1553b_rxin.busB_rxN <= busBinn;
busBouten <= gr1553b_txout.busB_txen;
busBoutp <= gr1553b_txout.busB_txP;
busBoutn <= gr1553b_txout.busB_txN;
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.RC5_PKG.ALL;
ENTITY rc5 IS
PORT (
clr, clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
enc : IN STD_LOGIC; -- Encryption or decryption?
key_vld : IN STD_LOGIC; -- Indicate the input is user key
data_vld : IN STD_LOGIC; -- Indicate the input is user data
din : IN STD_LOGIC_VECTOR(63 downto 0);
dout : OUT STD_LOGIC_VECTOR(63 downto 0);
data_rdy : OUT STD_LOGIC -- Indicate the output data is ready
);
END rc5;
ARCHITECTURE struct OF rc5 IS -- Structural description
signal skey : rc5_rom_26;
signal key_rdy : std_logic;
signal dout_enc : std_logic_vector(63 downto 0);
signal dout_dec : std_logic_vector(63 downto 0);
signal dec_rdy : std_logic;
signal enc_rdy : std_logic;
signal enc_clr : std_logic;
signal dec_clr : std_logic;
--Key will be attached to din twice
signal key : std_logic_vector(127 downto 0);
BEGIN
enc_clr <= clr AND enc;
dec_clr <= clr AND NOT enc;
key(127 downto 64) <= din;
key( 63 downto 0) <= din;
U1: rc5_key
PORT MAP(clr=>clr, clk=>clk, key=>key, key_vld=>key_vld, --Input
skey=>skey, key_rdy=>key_rdy); --Output
U2: rc5_enc
PORT MAP(clr=>enc_clr, clk=>clk, din=>din, di_vld=>data_vld, key_rdy=>key_rdy, skey=>skey, --Input
dout=>dout_enc, do_rdy=>enc_rdy); --Output
U3: rc5_dec
PORT MAP(clr=>dec_clr, clk=>clk, din=>din, di_vld=>data_vld, key_rdy=>key_rdy, skey=>skey, --Input
dout=>dout_dec, do_rdy=>dec_rdy); --Output
WITH enc SELECT
dout<=dout_enc WHEN '1',
dout_dec WHEN OTHERS;
WITH enc SELECT
data_rdy<=enc_rdy WHEN '1',
dec_rdy WHEN OTHERS;
END struct;
|
library verilog;
use verilog.vl_types.all;
entity tb_Servo is
generic(
CLK_FREQUENCY : integer := 50000000;
SPEED_MAX_PERIOD: real := 0.030000;
MAX_RAM_POS : integer := 256;
VALUE_SCALING : integer := 256
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of CLK_FREQUENCY : constant is 1;
attribute mti_svvh_generic_type of SPEED_MAX_PERIOD : constant is 1;
attribute mti_svvh_generic_type of MAX_RAM_POS : constant is 1;
attribute mti_svvh_generic_type of VALUE_SCALING : constant is 1;
end tb_Servo;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ddrv4
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-rtl-a.vhd,v 1.1 2004/04/06 10:44:19 wig Exp $
-- $Date: 2004/04/06 10:44:19 $
-- $Log: ddrv4-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:44:19 wig
-- Adding result/padio
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Revision: 1.17 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ddrv4
--
architecture rtl of ddrv4 is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ddrv --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv
alarm_time : in std_ulogic_vector(3 downto 0);
current_time : in std_ulogic_vector(3 downto 0);
display : out std_ulogic_vector(6 downto 0);
key_buffer : in std_ulogic_vector(3 downto 0);
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ddrv
);
end component;
-- ---------
component and_f --
-- No Generated Generics
port (
-- Generated Port for Entity and_f
out_p : out std_ulogic;
y : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity and_f
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sound_alarm : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_display_ls_hr_go <= display_ls_hr; -- __I_O_BUS_PORT
p_mix_display_ls_min_go <= display_ls_min; -- __I_O_BUS_PORT
p_mix_display_ms_hr_go <= display_ms_hr; -- __I_O_BUS_PORT
p_mix_display_ms_min_go <= display_ms_min; -- __I_O_BUS_PORT
p_mix_sound_alarm_go <= sound_alarm; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv
port map (
alarm_time => alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time => current_time_ls_hr, -- Display storage buffer 2 ls_hr
display => display_ls_hr, -- Display storage buffer 2 ls_hr
key_buffer => key_buffer_2, -- Display storage buffer 2 ls_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(2) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ls_hr
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv
port map (
alarm_time => alarm_time_ls_min, -- Display storage buffer 0 ls_min
current_time => current_time_ls_min, -- Display storage buffer 0 ls_min
display => display_ls_min, -- Display storage buffer 0 ls_min
key_buffer => key_buffer_0, -- Display storage buffer 0 ls_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ls_min
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv
port map (
alarm_time => alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time => current_time_ms_hr, -- Display storage buffer 3 ms_hr
display => display_ms_hr, -- Display storage buffer 3 ms_hr
key_buffer => key_buffer_3, -- Display storage buffer 3 ms_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(3) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ms_hr
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv
port map (
alarm_time => alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time => current_time_ms_min, -- Display storage buffer 1 ms_min
display => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer => key_buffer_1, -- Display storage buffer 1 ms_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(1) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for d_ms_min
-- Generated Instance Port Map for u_and_f
u_and_f: and_f
port map (
out_p => sound_alarm,
y => alarm -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDisp
);
-- End of Generated Instance Port Map for u_and_f
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: sounds_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY sounds_mem_tb IS
END ENTITY;
ARCHITECTURE sounds_mem_tb_ARCH OF sounds_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
sounds_mem_synth_inst:ENTITY work.sounds_mem_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: sounds_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY sounds_mem_tb IS
END ENTITY;
ARCHITECTURE sounds_mem_tb_ARCH OF sounds_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
sounds_mem_synth_inst:ENTITY work.sounds_mem_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- NEED RESULT: ARCH00298: Dynamic boolean short circuiting results passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00298
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.1 (6)
-- 7.2.1 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00298)
-- ENT00298_Test_Bench(ARCH00298_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00298 of E00000 is
begin
P00298 :
process
variable vboolean, boolean0, boolean1 : boolean ;
variable bool : boolean := true ;
function do_not_evaluate return boolean is
begin
test_report ( "ARCH00298" ,
"Dynamic boolean short circuiting correct" ,
false ) ;
return false ;
end do_not_evaluate ;
begin
boolean0 := false ;
boolean1 := true ;
vboolean := boolean0 and (do_not_evaluate and do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 and do_not_evaluate) and do_not_evaluate ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean0 and do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 and boolean0) and do_not_evaluate ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean1 and boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 and boolean1) and boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean1 and boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 and boolean1) and boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 or (boolean0 or boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 or boolean0) or boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean0 or (boolean0 or boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 or boolean0) or boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 or (boolean1 or do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 or boolean1) or do_not_evaluate ;
bool := bool and vboolean = true ;
vboolean := boolean1 or (do_not_evaluate or do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 or do_not_evaluate) or do_not_evaluate ;
bool := bool and vboolean = true ;
vboolean := boolean0 or (boolean0 and do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 or boolean0) and do_not_evaluate ;
bool := bool and vboolean = false ;
vboolean := boolean0 or (boolean1 and boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 or boolean1) and boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean0 or (boolean1 and boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 or boolean1) and boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 or (do_not_evaluate and do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 or do_not_evaluate) and boolean0 ;
bool := bool and vboolean = false ;
vboolean := (boolean1 or do_not_evaluate) and boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 and (do_not_evaluate or do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 and do_not_evaluate) or boolean0 ;
bool := bool and vboolean = false ;
vboolean := (boolean0 and do_not_evaluate) or boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 and (boolean0 or boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 and boolean0) or boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean1 and (boolean0 or boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 and boolean0) or boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 and (boolean1 or do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 and boolean1) or do_not_evaluate ;
bool := bool and vboolean = true ;
vboolean := boolean0 nand (do_not_evaluate nand do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := boolean1 nand (boolean0 nand do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean1 nand boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 nand boolean1) nand boolean0 ;
bool := bool and vboolean = true ;
vboolean := boolean1 nand (boolean1 nand boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 nand boolean1) nand boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 nor (boolean0 nor boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 nor boolean0) nor boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean0 nor (boolean0 nor boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 nor boolean0) nor boolean1 ;
bool := bool and vboolean = false ;
vboolean := boolean0 nor (boolean1 nor do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := boolean0 nor (boolean0 nand do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := boolean0 nor (boolean1 nand boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean0 nor boolean1) nand boolean0 ;
bool := bool and vboolean = true ;
vboolean := boolean0 nor (boolean1 nand boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 nor boolean1) nand boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean1 nor (do_not_evaluate nand do_not_evaluate) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 nor do_not_evaluate) nand boolean0 ;
bool := bool and vboolean = true ;
vboolean := (boolean1 nor do_not_evaluate) nand boolean1 ;
bool := bool and vboolean = true ;
vboolean := boolean0 nand (do_not_evaluate nor do_not_evaluate) ;
bool := bool and vboolean = true ;
vboolean := (boolean0 nand do_not_evaluate) nor boolean0 ;
bool := bool and vboolean = false ;
vboolean := (boolean0 nand do_not_evaluate) nor boolean1 ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean0 nor boolean0) ;
bool := bool and vboolean = false ;
vboolean := (boolean1 nand boolean0) nor boolean0 ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean0 nor boolean1) ;
bool := bool and vboolean = true ;
vboolean := (boolean1 nand boolean0) nor boolean1 ;
bool := bool and vboolean = false ;
vboolean := boolean1 nand (boolean1 nor do_not_evaluate) ;
bool := bool and vboolean = true ;
test_report ( "ARCH00298" ,
"Dynamic boolean short circuiting results" ,
bool ) ;
wait ;
end process P00298 ;
end ARCH00298 ;
entity ENT00298_Test_Bench is
end ENT00298_Test_Bench ;
architecture ARCH00298_Test_Bench of ENT00298_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00298 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00298_Test_Bench ;
|
-- Version: 20141019
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPISlave_tb is
end entity;
architecture behavior of SPISlave_tb is
type TestState is (
idle
, select_slave
, wait_for_the_first_clock_tick
, wait_for_eight_spi_clock_ticks
, check_slave_output_from_one_byte_of_zeroes
, check_slave_output_from_one_byte_of_zeroes_2
, prepare_master_data
, send_master_data
, check_final_byte
);
constant IDLE_DURATION : integer := 5000;
constant CHECK_SLAVE_OUTPUT_FROM_ONE_BYTE_OF_ZEROES_2_DURATION : integer := 1700;
component SPISlave is
port(
clock : in std_logic
; resetN : in std_logic
; spi_clock_I : in std_logic
; spi_slave_select_NI : in std_logic
; spi_mosi_I : in std_logic
; spi_miso_O : out std_logic
; data_ready_I : in std_logic
; data_I : in std_logic_vector(7 downto 0)
; data_ack_O : out std_logic
; data_ready_O : out std_logic
; new_data_byte_O : out std_logic
; data_O : out std_logic_vector(7 downto 0)
);
end component;
signal clock : std_logic := '0';
signal resetN : std_logic := '1';
signal internal_spi_clock : std_logic := '0';
signal spi_clock : std_logic := '0';
signal enable_spi_clock : std_logic := '0';
signal test_state : TestState := idle;
signal spi_miso : std_logic;
signal data_ready_from_the_slave : std_logic := '0';
signal data_ready_to_the_slave : std_logic := '0';
signal data_to_the_slave : std_logic_vector(7 downto 0) := (others => '0');
signal data_ack_from_the_slave : std_logic := '0';
signal new_data_byte_from_the_slave : std_logic := '0';
signal data_from_the_slave : std_logic_vector(7 downto 0) := (others => '0');
signal spi_slave_select_NI : std_logic := '1';
signal prev_spi_clock : std_logic := '0';
signal master_data : std_logic_vector(63 downto 0);
signal spi_mosi : std_logic := '0';
begin
-- we don't really care about the speed of the clock, just as long as it clocks...
clock <= not clock after 1 ps;
under_test : SPISlave
port map(
clock => clock
, resetN => resetN
, spi_clock_I => spi_clock
, spi_slave_select_NI => spi_slave_select_NI
, spi_mosi_I => spi_mosi
, spi_miso_O => spi_miso
, data_ready_I => data_ready_to_the_slave
, data_I => data_to_the_slave
, data_ack_O => data_ack_from_the_slave
, data_ready_O => data_ready_from_the_slave
, new_data_byte_O => new_data_byte_from_the_slave
, data_O => data_from_the_slave
);
p_generate_spi_clock : process(clock)
variable counter : integer := 0;
begin
if rising_edge(clock) then
if counter = 50 then
counter := 0;
internal_spi_clock <= not internal_spi_clock;
else
counter := counter + 1;
end if;
end if;
end process;
spi_clock <= enable_spi_clock and internal_spi_clock;
p_test_driver : process(clock)
variable counter : integer := 0;
begin
if rising_edge(clock) then
case test_state is
when idle =>
enable_spi_clock <= '1';
assert spi_miso = 'Z' report "Slave shouldn't drive unless selected" severity failure;
assert data_ack_from_the_slave = '0' report "Slave cannot acknowledge data we did not give it" severity failure;
assert data_ready_from_the_slave = '0' and new_data_byte_from_the_slave = '0' report "Slave cannot produce data when not selected" severity failure;
if counter = IDLE_DURATION then
test_state <= select_slave;
counter := 0;
else
counter := counter + 1;
end if;
when select_slave =>
assert spi_miso = 'Z' report "Slave shouldn't drive unless selected" severity failure;
assert data_ack_from_the_slave = '0' report "Slave cannot acknowledge data we did not give it" severity failure;
assert data_ready_from_the_slave = '0' and new_data_byte_from_the_slave = '0' report "Slave cannot produce data when not selected" severity failure;
spi_slave_select_NI <= '0';
test_state <= wait_for_the_first_clock_tick;
when wait_for_the_first_clock_tick =>
assert spi_miso = 'Z' report "Slave only start driving on the first clock tick rising edge" severity failure;
assert data_ack_from_the_slave = '0' report "Slave cannot acknowledge data we did not give it" severity failure;
assert data_ready_from_the_slave = '0' and new_data_byte_from_the_slave = '0' report "Slave cannot produce data before selection takes effect and at least one byte was received" severity failure;
if prev_spi_clock = '0' and spi_clock = '1' then
counter := 0;
test_state <= wait_for_eight_spi_clock_ticks;
end if;
when wait_for_eight_spi_clock_ticks =>
assert spi_miso = '0' report "Slave should drive low when selected and no data to send" severity failure;
assert data_ack_from_the_slave = '0' report "Slave cannot acknowledge data we did not give it" severity failure;
assert data_ready_from_the_slave = '0' and new_data_byte_from_the_slave = '0' report "Slave cannot produce data yet" severity failure;
test_state <= wait_for_eight_spi_clock_ticks;
if prev_spi_clock = '1' and spi_clock = '0' then
if counter = 7 then
counter := 0;
spi_slave_select_NI <= '1';
test_state <= check_slave_output_from_one_byte_of_zeroes;
else
counter := counter + 1;
spi_slave_select_NI <= '0';
end if;
else
spi_slave_select_NI <= '0';
end if;
when check_slave_output_from_one_byte_of_zeroes =>
assert data_ack_from_the_slave = '0' report "Slave cannot acknowledge data we did not give it" severity failure;
assert data_ready_from_the_slave = '1' and new_data_byte_from_the_slave = '1' report "Slave should now produce a byte" severity failure;
assert data_from_the_slave = "00000000" report "Byte should be all zeroes" severity failure;
test_state <= check_slave_output_from_one_byte_of_zeroes_2;
counter := 0;
when check_slave_output_from_one_byte_of_zeroes_2 =>
assert spi_miso = 'Z' report "Slave shouldn't drive unless selected" severity failure;
assert data_ack_from_the_slave = '0' report "Slave cannot acknowledge data we did not give it" severity failure;
assert data_ready_from_the_slave = '1' and new_data_byte_from_the_slave = '0' report "Slave should have produced a byte but that byte is no longer new" severity failure;
assert data_from_the_slave = "00000000" report "Byte should be all zeroes" severity failure;
if counter = CHECK_SLAVE_OUTPUT_FROM_ONE_BYTE_OF_ZEROES_2_DURATION then
test_state <= prepare_master_data;
else
counter := counter + 1;
end if;
when prepare_master_data =>
master_data <= x"c6847e6300257495";
counter := 63;
spi_slave_select_NI <= '0';
test_state <= send_master_data;
when send_master_data =>
if new_data_byte_from_the_slave = '1' then
if counter >= 55 then
assert data_from_the_slave = x"c6" report "Expected C6" severity failure;
elsif counter >= 47 then
assert data_from_the_slave = x"84" report "Expected C6" severity failure;
elsif counter >= 39 then
assert data_from_the_slave = x"7e" report "Expected C6" severity failure;
elsif counter >= 31 then
assert data_from_the_slave = x"63" report "Expected C6" severity failure;
elsif counter >= 23 then
assert data_from_the_slave = x"00" report "Expected C6" severity failure;
elsif counter >= 15 then
assert data_from_the_slave = x"25" report "Expected C6" severity failure;
elsif counter >= 7 then
assert data_from_the_slave = x"74" report "Expected C6" severity failure;
end if;
end if;
if prev_spi_clock = '0' and spi_clock = '1' then
spi_mosi <= master_data(63);
master_data <= master_data(62 downto 0) & '0';
if counter = 0 then
test_state <= check_final_byte;
else
counter := counter - 1;
end if;
end if;
when check_final_byte =>
if new_data_byte_from_the_slave = '1' then
assert data_from_the_slave = x"95" report "Expected C6" severity failure;
end if;
if prev_spi_clock = '0' and spi_clock = '1' then
spi_slave_select_NI <= '1';
end if;
when others =>
null;
end case;
prev_spi_clock <= spi_clock;
end if;
end process;
end architecture;
|
library nvc;
use nvc.sim_pkg.all;
entity wait24 is
end entity;
architecture test of wait24 is
begin
p1: process is
begin
assert now = 0 ns;
assert current_delta_cycle = 0;
wait for 0 ns;
assert now = 0 ns;
assert current_delta_cycle = 1;
for i in 1 to 5 loop
wait for 0 ns;
end loop;
assert current_delta_cycle = 6;
wait for 1 ps;
assert current_delta_cycle = 0;
wait;
end process;
end architecture;
|
--
-- Copyright (C) 2009-2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
sysClk_in : in std_logic; -- 50MHz system clock
-- USB interface -----------------------------------------------------------------------------
serClk_in : in std_logic; -- serial clock (async to sysClk_in)
serData_in : in std_logic; -- serial data in
serData_out : out std_logic -- serial data out
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- SPI signals
signal spiCS : std_logic_vector(NUM_DEVS-1 downto 0);
signal spiClk : std_logic;
signal spiMOSI : std_logic;
signal spiMISO : std_logic;
-- Component from the Altera library to give application access to the config flash.
component altserial_flash_loader
generic (
enable_quad_spi_support : natural;
enable_shared_access : string;
enhanced_mode : natural;
intended_device_family : string;
lpm_type : string
);
port (
data0out : out std_logic;
noe : in std_logic;
scein : in std_logic;
asmi_access_granted : in std_logic;
asmi_access_request : out std_logic;
dclkin : in std_logic;
sdoin : in std_logic
);
end component;
begin
-- CommFPGA module
comm_fpga_ss : entity work.comm_fpga_ss
port map(
clk_in => sysClk_in,
reset_in => '0',
-- USB interface
serClk_in => serClk_in,
serData_in => serData_in,
serData_out => serData_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => sysClk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk,
spiData_out => spiMOSI,
spiData_in => spiMISO,
spiCS_out => spiCS
);
-- Allow application access to config flash
spi_access : altserial_flash_loader
generic map (
enable_quad_spi_support => 0,
enable_shared_access => "ON",
enhanced_mode => 1,
intended_device_family => "Cyclone II",
lpm_type => "altserial_flash_loader"
)
port map (
asmi_access_granted => '0',
asmi_access_request => open,
noe => '0',
scein => spiCS(0),
dclkin => spiClk,
sdoin => spiMOSI,
data0out => spiMISO
);
end architecture;
|
-- 32-bit register, can be used for many purposes
-- has write enable, synchronous clear, asynchronous reset inputs
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity reg_32_bit is
port (
-- 32-bit input
in_32 : in std_logic_vector(31 downto 0);
-- clock, async reset, sync clear
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
-- write enable
wr_en : in std_logic;
-- 32-bit output
out_32 : out std_logic_vector(31 downto 0)
);
end entity reg_32_bit;
architecture reg_32_bit_arch of reg_32_bit is
-- this circuit does not require any internal signals
begin
wrt : process(rst, clk)
begin
-- on async reset high, register contents set to 0
if rst = '1' then
out_32 <= (others => '0');
-- otherwise on rising clock edge and write enable high, transfer input to output
-- or if clr high, zero output
else
if rising_edge(clk) then
if clr = '1' then
out_32 <= (others => '0');
else
if wr_en = '1' then
out_32 <= in_32;
end if;
end if;
end if;
end if;
end process wrt;
end architecture reg_32_bit_arch; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrintpkg
-- File: ddrintpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Internal components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
package ddrintpkg is
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
component ddr2buf is
generic (
tech : integer := 0;
wabits : integer := 6;
wdbits : integer := 8;
rabits : integer := 6;
rdbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits -1) downto 0);
dataout : out std_logic_vector((rdbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits -1) downto 0);
datain : in std_logic_vector((wdbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
type ddr_request_type is record
startaddr : std_logic_vector(31 downto 0);
endaddr : std_logic_vector(9 downto 0);
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
maskdata : std_ulogic;
maskcb : std_ulogic;
burst : std_ulogic;
end record;
type ddr_response_type is record
done_tog : std_ulogic;
rctr_gray : std_logic_vector(3 downto 0);
readerr : std_ulogic;
end record;
constant ddr_request_none: ddr_request_type :=
((others => '0'), (others => '0'), "000", '0','0','0','0','0');
constant ddr_response_none: ddr_response_type := ('0',"0000",'0');
component ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
component ft_ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := 64;
bufbits : integer := 96;
ddrbits : integer := 16;
hwidthen : integer := 0;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ce : out std_logic;
request : out ddr_request_type;
start_tog : out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen)-2 downto 0);
wbwdata : out std_logic_vector(bufbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig : out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(bufbits-1 downto 0);
hwidth : in std_logic;
synccfg : in std_logic;
request2 : out ddr_request_type;
start_tog2 : out std_logic;
beid : in std_logic_vector(3 downto 0)
);
end component;
constant FTFE_BEID_DDR2 : std_logic_vector(3 downto 0) := "0000";
constant FTFE_BEID_SDR : std_logic_vector(3 downto 0) := "0001";
constant FTFE_BEID_DDR1 : std_logic_vector(3 downto 0) := "0010";
constant FTFE_BEID_SSR : std_logic_vector(3 downto 0) := "0011";
constant FTFE_BEID_LPDDR2: std_logic_vector(3 downto 0) := "0100";
component ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
-- dynamic sync (nosync=2)
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
component ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- Other components re-using sub-components above
-----------------------------------------------------------------------------
component ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Gray-code routines
-----------------------------------------------------------------------------
function lin2gray(l: std_logic_vector) return std_logic_vector;
function gray2lin(g: std_logic_vector) return std_logic_vector;
function nextgray(g: std_logic_vector) return std_logic_vector;
-----------------------------------------------------------------------------
-- Data-mask routines
-----------------------------------------------------------------------------
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector;
function masklast(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer) return std_logic_vector;
end package;
package body ddrintpkg is
function lin2gray(l: std_logic_vector) return std_logic_vector is
variable lx,r: std_logic_vector(l'length-1 downto 0);
begin
lx := l;
r(l'length-1) := lx(l'length-1);
if l'length > 1 then
r(l'length-2 downto 0) := lx(l'length-1 downto 1) xor lx(l'length-2 downto 0);
end if;
return r;
end lin2gray;
function gray2lin(g: std_logic_vector) return std_logic_vector is
variable x: std_logic_vector(15 downto 0);
variable r: std_logic_vector(g'length-1 downto 0);
begin
x := (others => '0');
x(g'length-1 downto 0) := g;
if g'length > 1 then
x(14 downto 0) := x(14 downto 0) xor x(15 downto 1);
end if;
if g'length > 2 then
x(13 downto 0) := x(13 downto 0) xor x(15 downto 2);
end if;
if g'length > 4 then
x(11 downto 0) := x(11 downto 0) xor x(15 downto 4);
end if;
if g'length > 8 then
x(7 downto 0) := x(7 downto 0) xor x(15 downto 8);
end if;
r := x(g'length-1 downto 0);
return r;
end gray2lin;
function nextgray(g: std_logic_vector) return std_logic_vector is
variable gx,r: std_logic_vector(g'length-1 downto 0);
variable gx3,r3: std_logic_vector(2 downto 0) := "000";
variable l,nl: std_logic_vector(g'length-1 downto 0);
begin
gx := g;
if gx'length = 1 then
r(0) := not gx(0);
elsif gx'length = 2 then
r(1) := gx(0);
r(0) := not gx(1);
elsif gx'length = 3 then
-- r(2) := (gx(1) or gx(0)) and (not gx(2) or not gx(0));
-- r(1) := (gx(1) or gx(0)) and (gx(2) or not gx(0));
-- r(0) := gx(2) xor gx(1);
gx3 := gx(2 downto 0);
case gx3 is
when "000" => r3 := "001";
when "001" => r3 := "011";
when "011" => r3 := "010";
when "010" => r3 := "110";
when "110" => r3 := "111";
when "111" => r3 := "101";
when "101" => r3 := "100";
when others => r3 := "000";
end case;
r(2 downto 0) := r3;
else
l := gray2lin(g);
nl := std_logic_vector(unsigned(l)+1);
r := lin2gray(nl);
end if;
return r;
end nextgray;
function maskfirst(addr: std_logic_vector(9 downto 0); ddrbits: integer) return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
r := (others => '0');
a32 := addr(3 downto 2);
a432 := addr(4 downto 2);
case ddrbits is
when 32 =>
if addr(2)='0' then r := "00000000";
else r := "11110000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0000";
when "01" => r := x"F000";
when "10" => r := x"FF00";
when others => r := x"FFF0";
end case;
when 128 =>
case a432 is
when "000" => r := x"00000000";
when "001" => r := x"F0000000";
when "010" => r := x"FF000000";
when "011" => r := x"FFF00000";
when "100" => r := x"FFFF0000";
when "101" => r := x"FFFFF000";
when "110" => r := x"FFFFFF00";
when others => r := x"FFFFFFF0";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end maskfirst;
function masklast(addr: std_logic_vector(9 downto 0);
hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable xaddr: std_logic_vector(9 downto 0);
variable a32: std_logic_vector(3 downto 2);
variable a432: std_logic_vector(4 downto 2);
begin
xaddr := addr;
if hsize(2)='1' then
xaddr(3 downto 2) := "11";
xaddr(3 downto 2) := "11";
end if;
if hsize(2)='1' and hsize(0)='1' then
xaddr(4) := '1';
end if;
if hsize(1 downto 0)="11" then
xaddr(2) := '1';
end if;
a32 := xaddr(3 downto 2);
a432 := xaddr(4 downto 2);
r := (others => '0');
case ddrbits is
when 32 =>
if xaddr(2)='0' then r := "00001111";
else r := "00000000";
end if;
when 64 =>
case a32 is
when "00" => r := x"0FFF";
when "01" => r := x"00FF";
when "10" => r := x"000F";
when others => r := x"0000";
end case;
when 128 =>
case a432 is
when "000" => r := x"0FFFFFFF";
when "001" => r := x"00FFFFFF";
when "010" => r := x"000FFFFF";
when "011" => r := x"0000FFFF";
when "100" => r := x"00000FFF";
when "101" => r := x"000000FF";
when "110" => r := x"0000000F";
when others => r := x"00000000";
end case;
when others =>
--pragma translate_off
assert ddrbits=16 report "Unsupported DDR width" severity failure;
--pragma translate_on
null;
end case;
return r;
end masklast;
function masksub32(addr: std_logic_vector(9 downto 0); hsize: std_logic_vector(2 downto 0); ddrbits: integer)
return std_logic_vector is
variable r: std_logic_vector(ddrbits/4-1 downto 0);
variable r16: std_logic_vector(3 downto 0);
variable a10: std_logic_vector(1 downto 0);
begin
r16 := (others => '0');
if hsize(2 downto 1)="00" then
r16 := addr(1) & addr(1) & (not addr(1)) & (not addr(1));
if hsize(0)='0' then
r16 := r16 or (addr(0) & (not addr(0)) & addr(0) & (not addr(0)));
end if;
end if;
r := (others => '0');
for x in 0 to ddrbits/16-1 loop
r(x*4+3 downto x*4) := r16;
end loop;
return r;
end masksub32;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk_raw : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
leds : out STD_LOGIC_VECTOR (7 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end top;
architecture Behavioral of top is
constant horz : integer := 5;
signal clk_100MHz: std_logic;
signal clk_193MHz: std_logic;
signal clk_250MHz: std_logic;
signal sw_buffer: std_logic_vector(7 downto 0);
signal hscnt: std_logic_vector(11 downto 0);
signal vscnt: std_logic_vector(11 downto 0);
signal data: std_logic_vector(11 downto 0):= (others=>'0');
signal addra: std_logic_vector(10 downto 0);
signal addrb: std_logic_vector(10 downto 0);
signal dina_ch1: std_logic_vector(15 downto 0);
signal dina_ch2: std_logic_vector(15 downto 0);
signal doutb_ch1: std_logic_vector(15 downto 0);
signal doutb_ch2: std_logic_vector(15 downto 0);
alias sine:std_logic_vector(7 downto 0) is doutb_ch1(7 downto 0);
alias cosine:std_logic_vector(7 downto 0) is doutb_ch2(7 downto 0);
signal s_axis_config_tdata: std_logic_vector(7 downto 0);
signal phase: std_logic_vector(31 downto 0);
signal m_axis_data_tdata: std_logic_vector(15 downto 0);
signal m_last: std_logic_vector(7 downto 0);
signal valid: std_logic;
signal write: std_logic;
signal new_sample: std_logic;
signal sine_out: std_logic_vector(7 downto 0);
signal cosine_out: std_logic_vector(7 downto 0);
-- Data master channel alias signals
signal m_axis_data_tdata_cosine : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_sine : std_logic_vector(7 downto 0) := (others => '0');
-- Alias signals for each separate TDM channel (these are 1 cycle delayed relative to the above alias signals)
signal m_axis_data_channel : integer := 0; -- indicates TDM channel number of data master channel outputs
signal m_axis_data_tdata_cosine_c0 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c0 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c1 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c1 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c2 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c2 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c3 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c3 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c4 : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c4 : std_logic_vector(7 downto 0) := (others => '0');
signal fpulse: std_logic;
signal vga_fpulse: std_logic;
signal saved: std_logic;
signal timer : std_logic_vector(5 downto 0);
signal sine_signed : signed (7 downto 0);
signal cosine_signed : signed (7 downto 0);
signal last: signed (7 downto 0);
signal colast: signed (7 downto 0);
signal y: signed (11 downto 0);
component clk_base is
port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
clk_100MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
component clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
COMPONENT bram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- COMPONENT dds
-- PORT (
-- aclk : IN STD_LOGIC;
-- s_axis_phase_tvalid : IN STD_LOGIC;
-- s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- m_axis_data_tvalid : OUT STD_LOGIC;
-- m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-- );
-- END COMPONENT;
COMPONENT dds
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
begin
clk_base1: clk_base port map(clk_raw, clk_250MHz, clk_100MHz, open);
clk_video1: clk_video port map(clk_100MHz, clk_193MHz, open);
vga1: vga generic map(
Hsync=> 208,
Hact=> 1920,
Hfp=>128,
Hbp=>336,
Vsync=>3,
Vact=> 1200,
Vfp=> 1,
Vbp=> 38
) port map( clk_193MHz, hscnt,vscnt,VGA_HSYNC, VGA_VSYNC,vga_fpulse);
bram_disp_ch1: bram
PORT MAP (
clka => clk_250MHz,
wea(0) => '1',
addra => addra,
dina => dina_ch1,
clkb => clk_193MHz,
addrb => addrb,
doutb => doutb_ch1
);
bram_disp_ch2: bram
PORT MAP (
clka => clk_250MHz,
wea(0) => '1',
addra => addra,
dina => dina_ch2,
clkb => clk_193MHz,
addrb => addrb,
doutb => doutb_ch2
);
-- sig_gen: dds
-- PORT MAP (
-- aclk => clk_250MHz,
-- s_axis_phase_tvalid => '1',
-- s_axis_phase_tdata => addra(7 downto 0),
-- m_axis_data_tvalid => valid,
-- m_axis_data_tdata => m_axis_data_tdata
-- );
sig_gen: dds
PORT MAP (
aclk => clk_250MHz,
m_axis_data_tvalid => valid,
m_axis_data_tdata => m_axis_data_tdata
);
--sine_gen: dds
--PORT MAP (
-- aclk => clk_250MHz,
-- s_axis_config_tvalid => '1',
-- s_axis_config_tdata => s_axis_config_tdata,
-- m_axis_data_tvalid => valid,
-- m_axis_data_tdata => m_axis_data_tdata,
-- m_axis_phase_tvalid => open,
-- m_axis_phase_tdata => phase
--);
y <= (600-1)-signed(vscnt);
sine_signed <= signed(sine);
cosine_signed <= signed(cosine);
--s_axis_config_tdata(31 downto 1) <= (others=>'0');
--s_axis_config_tdata(0) <= '1';
--addrb <= (others=>'0');
--dina(15 downto 0) <= (others=>'0');
--dina(7 downto 0) <= m_axis_data_tdata;
--s_axis_config_tdata <= "000000000000000000000000"&sw;
--dina <= y ;
addrb <= hscnt(10 downto 0);
dina_ch1(15 downto 8) <= (others=>'0');
dina_ch2(15 downto 8) <= (others=>'0');
--sine_out <= m_axis_data_tdata_sine_c4;
--std_logic_vector(to_signed(10,11));
process(clk_250MHz) begin
if(clk_250MHz'event and clk_250MHz='1')then
sw_buffer <= sw;
leds <= sw_buffer;
s_axis_config_tdata <= sw_buffer;
if(sw_buffer(6 downto 4) = 0)then
sine_out <= m_axis_data_tdata_sine_c0;
cosine_out <= m_axis_data_tdata_cosine_c0;
elsif(sw_buffer(6 downto 4) = 1)then
sine_out <= m_axis_data_tdata_sine_c1;
cosine_out <= m_axis_data_tdata_cosine_c1;
elsif(sw_buffer(6 downto 4) = 2)then
sine_out <= m_axis_data_tdata_sine_c2;
cosine_out <= m_axis_data_tdata_cosine_c2;
elsif(sw_buffer(6 downto 4) = 3)then
sine_out <= m_axis_data_tdata_sine_c3;
cosine_out <= m_axis_data_tdata_cosine_c3;
else
sine_out <= m_axis_data_tdata_sine_c4;
cosine_out <= m_axis_data_tdata_cosine_c4;
end if;
if valid = '1' then
if m_axis_data_channel = 4 then
m_axis_data_channel <= 0;
else
m_axis_data_channel <= m_axis_data_channel + 1;
end if;
if m_axis_data_channel = 0 then
m_axis_data_tdata_cosine_c0 <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c0 <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 1 then
m_axis_data_tdata_cosine_c1 <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c1 <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 2 then
m_axis_data_tdata_cosine_c2 <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c2 <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 3 then
m_axis_data_tdata_cosine_c3 <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c3 <= m_axis_data_tdata(15 downto 8);
elsif m_axis_data_channel = 4 then
m_axis_data_tdata_cosine_c4 <= m_axis_data_tdata(7 downto 0);
m_axis_data_tdata_sine_c4 <= m_axis_data_tdata(15 downto 8);
end if;
end if;
end if;
end process;
process(clk_250MHz) begin
if(clk_250MHz'event and clk_250MHz='1')then
if(timer = sw_buffer(3 downto 0))then
timer <= (others=>'0');
if(sw_buffer(7) = '1')then
m_last <= dina_ch1(7 downto 0);
dina_ch1(7 downto 0) <= sine_out;
dina_ch2(7 downto 0) <= cosine_out;
if(addra < 1920)then
addra <= addra+1;
end if;
if(addra >= 1920 and signed(dina_ch1(7 downto 0)) >= 0 and signed(m_last) <= 0 )then
addra <= (others=>'0');
end if;
end if;
end if;
timer <= timer + 1;
--if(write = '1')then
-- write <= '0';
-- end if;
end if;
end process;
process(clk_193MHz) begin
if(clk_193MHz'event and clk_193MHz='1')then
if( hscnt < 1920 and vscnt < 1200)then
VGA_DATA <= data;
else
VGA_DATA <= (others=>'0');
end if;
if (vscnt = 600 or hscnt = 0)then
data <= X"07F";
elsif( (hscnt = 128) or (hscnt = 256) or (hscnt = 384) or (hscnt = 512) or (hscnt = 640) or (hscnt = 768) or (hscnt = 896) or (hscnt = 1024) or (hscnt = 1152) or (hscnt = 1280) or (hscnt = 1408) or (hscnt = 1536) or (hscnt = 1664) or (hscnt = 1792) or (hscnt = 1920-1)) then
data <= X"0F0";
elsif((vscnt = 0) or (vscnt = 120) or (vscnt = 120*2) or (vscnt = 120*3) or (vscnt = 120*4) or (vscnt = 120*5) or (vscnt = 120*6) or (vscnt = 120*7) or (vscnt = 120*8) or (vscnt = 120*9) or (vscnt = 1200-1)) then
data <= X"0F0";
elsif( y = sine_signed or (sine_signed > last and y > last and y < sine_signed) or sine_signed = y or (sine_signed < last and y < last and y > sine_signed) )then --or (doutb < last and vscnt < last and vscnt > doutb)
data <= X"0FF";
elsif( y = cosine_signed or (cosine_signed > colast and y > colast and y < cosine_signed) or cosine_signed = y or (cosine_signed < colast and y < colast and y > cosine_signed) )then
data <= X"F70";
else
data <= X"000";
end if;
last <= sine_signed;
colast <= cosine_signed;
end if;
end process;
end Behavioral;
|
--**********************************************************************************************
-- Resynchronizer(1 bit,cp2 clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_cp2;
architecture RTL of Resync1b_cp2 is
signal DIn_Tmp : std_logic;
begin
ResynchronizerDFFs:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock
DIn_Tmp <= DIn; -- Stage 1
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
|
--**********************************************************************************************
-- Resynchronizer(1 bit,cp2 clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_cp2;
architecture RTL of Resync1b_cp2 is
signal DIn_Tmp : std_logic;
begin
ResynchronizerDFFs:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock
DIn_Tmp <= DIn; -- Stage 1
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
|
--**********************************************************************************************
-- Resynchronizer(1 bit,cp2 clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_cp2;
architecture RTL of Resync1b_cp2 is
signal DIn_Tmp : std_logic;
begin
ResynchronizerDFFs:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock
DIn_Tmp <= DIn; -- Stage 1
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
|
--**********************************************************************************************
-- Resynchronizer(1 bit,cp2 clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_cp2;
architecture RTL of Resync1b_cp2 is
signal DIn_Tmp : std_logic;
begin
ResynchronizerDFFs:process(cp2)
begin
if(cp2='1' and cp2'event) then -- Clock
DIn_Tmp <= DIn; -- Stage 1
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
|
--
-- VM2413.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package VM2413 is
constant MAXCH : integer := 9;
constant MAXSLOT : integer := MAXCH * 2;
subtype CH_TYPE is integer range 0 to MAXCH-1;
subtype SLOT_TYPE is integer range 0 to MAXSLOT-1;
subtype STAGE_TYPE is integer range 0 to 3;
subtype REGS_VECTOR_TYPE is std_logic_vector(23 downto 0);
type REGS_TYPE is record
INST : std_logic_vector(3 downto 0);
VOL : std_logic_vector(3 downto 0);
SUS : std_logic;
KEY : std_logic;
BLK : std_logic_vector(2 downto 0);
FNUM : std_logic_vector(8 downto 0);
end record;
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE;
subtype VOICE_ID_TYPE is integer range 0 to 37;
subtype VOICE_VECTOR_TYPE is std_logic_vector(35 downto 0);
type VOICE_TYPE is record
AM, PM, EG, KR : std_logic;
ML : std_logic_vector(3 downto 0);
KL : std_logic_vector(1 downto 0);
TL : std_logic_vector(5 downto 0);
WF : std_logic;
FB : std_logic_vector(2 downto 0);
AR, DR, SL, RR : std_logic_vector(3 downto 0);
end record;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE;
-- Voice Parameter Types
subtype AM_TYPE is std_logic; -- AM switch - '0':off '1':3.70Hz
subtype PM_TYPE is std_logic; -- PM switch - '0':stop '1':6.06Hz
subtype EG_TYPE is std_logic; -- Envelope type - '0':release '1':sustine
subtype KR_TYPE is std_logic; -- Keyscale Rate
subtype ML_TYPE is std_logic_vector(3 downto 0); -- Multiple
subtype WF_TYPE is std_logic; -- WaveForm - '0':sine '1':half-sine
subtype FB_TYPE is std_logic_vector(2 downto 0); -- Feedback
subtype AR_TYPE is std_logic_vector(3 downto 0); -- Attack Rate
subtype DR_TYPE is std_logic_vector(3 downto 0); -- Decay Rate
subtype SL_TYPE is std_logic_vector(3 downto 0); -- Sustine Level
subtype RR_TYPE is std_logic_vector(3 downto 0); -- Release Rate
-- F-Number, Block and Rks(Rate and key-scale) types
subtype BLK_TYPE is std_logic_vector(2 downto 0); -- Block
subtype FNUM_TYPE is std_logic_vector(8 downto 0); -- F-Number
subtype RKS_TYPE is std_logic_vector(3 downto 0); -- Rate-KeyScale
-- 18 bits phase counter
subtype PHASE_TYPE is std_logic_vector (17 downto 0);
-- Phage generator's output
subtype PGOUT_TYPE is std_logic_vector (8 downto 0);
-- Final linear output of opll
subtype LI_TYPE is std_logic_vector (8 downto 0); -- Wave in Linear
-- Total Level and Envelope output
subtype DB_TYPE is std_logic_vector(6 downto 0); -- Wave in dB, Reso: 0.375dB
subtype SIGNED_LI_VECTOR_TYPE is std_logic_vector(LI_TYPE'high + 1 downto 0);
type SIGNED_LI_TYPE is record
sign : std_logic;
value : LI_TYPE;
end record;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE;
subtype SIGNED_DB_VECTOR_TYPE is std_logic_vector(DB_TYPE'high + 1 downto 0);
type SIGNED_DB_TYPE is record
sign : std_logic;
value : DB_TYPE;
end record;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE;
-- Envelope generator states
subtype EGSTATE_TYPE is std_logic_vector(1 downto 0);
constant Attack : EGSTATE_TYPE := "01";
constant Decay : EGSTATE_TYPE := "10";
constant Release : EGSTATE_TYPE := "11";
constant Finish : EGSTATE_TYPE := "00";
-- Envelope generator phase
subtype EGPHASE_TYPE is std_logic_vector(22 downto 0);
-- Envelope data (state and phase)
type EGDATA_TYPE is record
state : EGSTATE_TYPE;
phase : EGPHASE_TYPE;
end record;
subtype EGDATA_VECTOR_TYPE is std_logic_vector(EGSTATE_TYPE'high + EGPHASE_TYPE'high + 1 downto 0);
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE;
component Opll port(
XIN : in std_logic;
XOUT : out std_logic;
XENA : in std_logic;
D : in std_logic_vector(7 downto 0);
A : in std_logic;
CS_n : in std_logic;
WE_n : in std_logic;
IC_n : in std_logic;
MO : out std_logic_vector(9 downto 0);
RO : out std_logic_vector(9 downto 0)
);
end component;
component Controller port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
wr : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
am : out AM_TYPE;
pm : out PM_TYPE;
wf : out WF_TYPE;
ml : out ML_TYPE;
tl : out DB_TYPE;
fb : out FB_TYPE;
ar : out AR_TYPE;
dr : out DR_TYPE;
sl : out SL_TYPE;
rr : out RR_TYPE;
blk : out BLK_TYPE;
fnum : out FNUM_TYPE;
rks : out RKS_TYPE;
key : out std_logic;
rhythm : out std_logic
);
end component;
-- Slot and stage counter
component SlotCounter
generic (
DELAY : integer range 0 to MAXSLOT*4-1
);
port(
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : out SLOT_TYPE;
stage : out STAGE_TYPE
);
end component;
component EnvelopeGenerator
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
am : in AM_TYPE;
tl : in DB_TYPE;
ar : in AR_TYPE;
dr : in DR_TYPE;
sl : in SL_TYPE;
rr : in RR_TYPE;
rks : in RKS_TYPE;
key : in std_logic;
egout : out DB_TYPE
);
end component;
component PhaseGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
pm : in PM_TYPE;
ml : in ML_TYPE;
blk : in BLK_TYPE;
fnum : in FNUM_TYPE;
key : in std_logic;
noise : out std_logic;
pgout : out PGOUT_TYPE
);
end component;
component Operator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
WF : in WF_TYPE;
FB : in FB_TYPE;
noise : in std_logic;
pgout : in PGOUT_TYPE;
egout : in DB_TYPE;
faddr : out CH_TYPE;
fdata : in SIGNED_LI_TYPE;
opout : out SIGNED_DB_TYPE
);
end component;
component OutputGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
opout : in SIGNED_DB_TYPE;
faddr : in CH_TYPE;
fdata : out SIGNED_LI_TYPE;
maddr : in SLOT_TYPE;
mdata : out SIGNED_LI_TYPE
);
end component;
component TemporalMixer port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end component;
end VM2413;
package body VM2413 is
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE is
begin
return regs.INST & regs.VOL & "00" & regs.SUS & regs.KEY & regs.BLK & regs.FNUM;
end CONV_REGS_VECTOR;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE is
begin
return (
INST=>vec(23 downto 20), VOL=>vec(19 downto 16),
SUS=>vec(13), KEY=>vec(12), BLK=>vec(11 downto 9), FNUM=>vec(8 downto 0)
);
end CONV_REGS;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE is
begin
return inst.AM & inst.PM & inst.EG & inst.KR &
inst.ML & inst.KL & inst.TL & inst.WF & inst.FB &
inst.AR & inst.DR & inst.SL & inst.RR;
end CONV_VOICE_VECTOR;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE is
begin
return (
AM=>inst_vec(35), PM=>inst_vec(34), EG=>inst_vec(33), KR=>inst_vec(32),
ML=>inst_vec(31 downto 28), KL=>inst_vec(27 downto 26), TL=>inst_vec(25 downto 20),
WF=>inst_vec(19), FB=>inst_vec(18 downto 16),
AR=>inst_vec(15 downto 12), DR=>inst_vec(11 downto 8), SL=>inst_vec(7 downto 4), RR=>inst_vec(3 downto 0)
);
end CONV_VOICE;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE is
begin
return li.sign & li.value;
end;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE is
begin
return db.sign & db.value;
end;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE is
begin
return data.state & data.phase;
end;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE is
begin
return ( state => vec(vec'high downto EGPHASE_TYPE'high + 1),
phase => vec(EGPHASE_TYPE'range) );
end;
end VM2413;
|
--
-- VM2413.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package VM2413 is
constant MAXCH : integer := 9;
constant MAXSLOT : integer := MAXCH * 2;
subtype CH_TYPE is integer range 0 to MAXCH-1;
subtype SLOT_TYPE is integer range 0 to MAXSLOT-1;
subtype STAGE_TYPE is integer range 0 to 3;
subtype REGS_VECTOR_TYPE is std_logic_vector(23 downto 0);
type REGS_TYPE is record
INST : std_logic_vector(3 downto 0);
VOL : std_logic_vector(3 downto 0);
SUS : std_logic;
KEY : std_logic;
BLK : std_logic_vector(2 downto 0);
FNUM : std_logic_vector(8 downto 0);
end record;
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE;
subtype VOICE_ID_TYPE is integer range 0 to 37;
subtype VOICE_VECTOR_TYPE is std_logic_vector(35 downto 0);
type VOICE_TYPE is record
AM, PM, EG, KR : std_logic;
ML : std_logic_vector(3 downto 0);
KL : std_logic_vector(1 downto 0);
TL : std_logic_vector(5 downto 0);
WF : std_logic;
FB : std_logic_vector(2 downto 0);
AR, DR, SL, RR : std_logic_vector(3 downto 0);
end record;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE;
-- Voice Parameter Types
subtype AM_TYPE is std_logic; -- AM switch - '0':off '1':3.70Hz
subtype PM_TYPE is std_logic; -- PM switch - '0':stop '1':6.06Hz
subtype EG_TYPE is std_logic; -- Envelope type - '0':release '1':sustine
subtype KR_TYPE is std_logic; -- Keyscale Rate
subtype ML_TYPE is std_logic_vector(3 downto 0); -- Multiple
subtype WF_TYPE is std_logic; -- WaveForm - '0':sine '1':half-sine
subtype FB_TYPE is std_logic_vector(2 downto 0); -- Feedback
subtype AR_TYPE is std_logic_vector(3 downto 0); -- Attack Rate
subtype DR_TYPE is std_logic_vector(3 downto 0); -- Decay Rate
subtype SL_TYPE is std_logic_vector(3 downto 0); -- Sustine Level
subtype RR_TYPE is std_logic_vector(3 downto 0); -- Release Rate
-- F-Number, Block and Rks(Rate and key-scale) types
subtype BLK_TYPE is std_logic_vector(2 downto 0); -- Block
subtype FNUM_TYPE is std_logic_vector(8 downto 0); -- F-Number
subtype RKS_TYPE is std_logic_vector(3 downto 0); -- Rate-KeyScale
-- 18 bits phase counter
subtype PHASE_TYPE is std_logic_vector (17 downto 0);
-- Phage generator's output
subtype PGOUT_TYPE is std_logic_vector (8 downto 0);
-- Final linear output of opll
subtype LI_TYPE is std_logic_vector (8 downto 0); -- Wave in Linear
-- Total Level and Envelope output
subtype DB_TYPE is std_logic_vector(6 downto 0); -- Wave in dB, Reso: 0.375dB
subtype SIGNED_LI_VECTOR_TYPE is std_logic_vector(LI_TYPE'high + 1 downto 0);
type SIGNED_LI_TYPE is record
sign : std_logic;
value : LI_TYPE;
end record;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE;
subtype SIGNED_DB_VECTOR_TYPE is std_logic_vector(DB_TYPE'high + 1 downto 0);
type SIGNED_DB_TYPE is record
sign : std_logic;
value : DB_TYPE;
end record;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE;
-- Envelope generator states
subtype EGSTATE_TYPE is std_logic_vector(1 downto 0);
constant Attack : EGSTATE_TYPE := "01";
constant Decay : EGSTATE_TYPE := "10";
constant Release : EGSTATE_TYPE := "11";
constant Finish : EGSTATE_TYPE := "00";
-- Envelope generator phase
subtype EGPHASE_TYPE is std_logic_vector(22 downto 0);
-- Envelope data (state and phase)
type EGDATA_TYPE is record
state : EGSTATE_TYPE;
phase : EGPHASE_TYPE;
end record;
subtype EGDATA_VECTOR_TYPE is std_logic_vector(EGSTATE_TYPE'high + EGPHASE_TYPE'high + 1 downto 0);
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE;
component Opll port(
XIN : in std_logic;
XOUT : out std_logic;
XENA : in std_logic;
D : in std_logic_vector(7 downto 0);
A : in std_logic;
CS_n : in std_logic;
WE_n : in std_logic;
IC_n : in std_logic;
MO : out std_logic_vector(9 downto 0);
RO : out std_logic_vector(9 downto 0)
);
end component;
component Controller port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
wr : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
am : out AM_TYPE;
pm : out PM_TYPE;
wf : out WF_TYPE;
ml : out ML_TYPE;
tl : out DB_TYPE;
fb : out FB_TYPE;
ar : out AR_TYPE;
dr : out DR_TYPE;
sl : out SL_TYPE;
rr : out RR_TYPE;
blk : out BLK_TYPE;
fnum : out FNUM_TYPE;
rks : out RKS_TYPE;
key : out std_logic;
rhythm : out std_logic
);
end component;
-- Slot and stage counter
component SlotCounter
generic (
DELAY : integer range 0 to MAXSLOT*4-1
);
port(
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : out SLOT_TYPE;
stage : out STAGE_TYPE
);
end component;
component EnvelopeGenerator
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
am : in AM_TYPE;
tl : in DB_TYPE;
ar : in AR_TYPE;
dr : in DR_TYPE;
sl : in SL_TYPE;
rr : in RR_TYPE;
rks : in RKS_TYPE;
key : in std_logic;
egout : out DB_TYPE
);
end component;
component PhaseGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
pm : in PM_TYPE;
ml : in ML_TYPE;
blk : in BLK_TYPE;
fnum : in FNUM_TYPE;
key : in std_logic;
noise : out std_logic;
pgout : out PGOUT_TYPE
);
end component;
component Operator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
WF : in WF_TYPE;
FB : in FB_TYPE;
noise : in std_logic;
pgout : in PGOUT_TYPE;
egout : in DB_TYPE;
faddr : out CH_TYPE;
fdata : in SIGNED_LI_TYPE;
opout : out SIGNED_DB_TYPE
);
end component;
component OutputGenerator port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
opout : in SIGNED_DB_TYPE;
faddr : in CH_TYPE;
fdata : out SIGNED_LI_TYPE;
maddr : in SLOT_TYPE;
mdata : out SIGNED_LI_TYPE
);
end component;
component TemporalMixer port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end component;
end VM2413;
package body VM2413 is
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE is
begin
return regs.INST & regs.VOL & "00" & regs.SUS & regs.KEY & regs.BLK & regs.FNUM;
end CONV_REGS_VECTOR;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE is
begin
return (
INST=>vec(23 downto 20), VOL=>vec(19 downto 16),
SUS=>vec(13), KEY=>vec(12), BLK=>vec(11 downto 9), FNUM=>vec(8 downto 0)
);
end CONV_REGS;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE is
begin
return inst.AM & inst.PM & inst.EG & inst.KR &
inst.ML & inst.KL & inst.TL & inst.WF & inst.FB &
inst.AR & inst.DR & inst.SL & inst.RR;
end CONV_VOICE_VECTOR;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE is
begin
return (
AM=>inst_vec(35), PM=>inst_vec(34), EG=>inst_vec(33), KR=>inst_vec(32),
ML=>inst_vec(31 downto 28), KL=>inst_vec(27 downto 26), TL=>inst_vec(25 downto 20),
WF=>inst_vec(19), FB=>inst_vec(18 downto 16),
AR=>inst_vec(15 downto 12), DR=>inst_vec(11 downto 8), SL=>inst_vec(7 downto 4), RR=>inst_vec(3 downto 0)
);
end CONV_VOICE;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE is
begin
return li.sign & li.value;
end;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE is
begin
return db.sign & db.value;
end;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE is
begin
return data.state & data.phase;
end;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE is
begin
return ( state => vec(vec'high downto EGPHASE_TYPE'high + 1),
phase => vec(EGPHASE_TYPE'range) );
end;
end VM2413;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--comment to go here
entity single_port_memfile is
generic(
ADDR_WIDTH : integer := 4;
DATA_WIDTH : integer := 16;
MEM_LENGTH : integer := 128
);
port(
CLK: in std_logic;
WRITE_EN: in std_logic;
ADDR: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
DATA_IN: in std_logic_vector(DATA_WIDTH - 1 downto 0);
DATA_OUT: out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture beh of single_port_memfile is
type memory_type is array(0 to MEM_LENGTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal memory : memory_type := (
0 => x"01F001",
1 => x"000002",
2 => x"02F004",
3 => x"000002",
4 => x"000000",
-- 0 => x"000001",
-- 1 => x"000002",
-- 2 => x"000003",
-- 3 => x"000004",
-- 4 => x"000005",
-- 5 => x"000000",
others => (others => '0')
);
begin
process(CLK)
begin
if rising_edge(CLK) then
if WRITE_EN = '1' then
memory(to_integer(unsigned(ADDR))) <= DATA_IN;
end if;
end if;
end process;
DATA_OUT <= memory(to_integer(unsigned(ADDR)));
end architecture beh; |
-- NEED RESULT: ARCH00655: (Multiple object) declarations equivalent to multiple (object declarations) (globally static) passed
-- NEED RESULT: ARCH00655: (Multiple object) declarations equivalent to multiple (object declarations) (dynamic) passed
-- NEED RESULT: ARCH00655: (Multiple object) declarations equivalent to multiple (object declarations) (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00655
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00655_1)
-- ENT00655(ARCH00655)
-- ENT00655_Test_Bench(ARCH00655_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00655_1 of E00000 is
--
constant r1 : integer := 1 ;
constant r2 : integer := 3 ;
constant c1 : integer := 2 ;
constant c2 : boolean := false ;
constant r3 : integer := 2 ;
constant r4 : integer := 2 ;
constant c3 : string := "a" ;
constant c4 : bit_vector := B"0110" ;
constant cinteger1, cinteger2, cinteger3 : integer range r1 to r2 := c1 ;
constant cbool1, cbool2, cbool3 : boolean := c2 ;
constant cstring1, cstring2, cstring3 : string ( r3 to r4 )
:= c3 ;
constant cbv1, cbv2, cbv3 : bit_vector := c4 ;
--
signal sinteger1, sinteger2, sinteger3 : integer range 1 to 3 ;
signal sbool1, sbool2, sbool3 : boolean ;
signal sstring1, sstring2, sstring3 : string ( cinteger1 to cinteger2 ) ;
signal toggle : boolean := false ;
begin
process
begin
sinteger1 <= c1 ;
sinteger2 <= c1 ;
sinteger3 <= c1 ;
sbool1 <= c2 ;
sbool2 <= c2 ;
sbool3 <= c2 ;
sstring1 <= c3 ;
sstring2 <= c3 ;
sstring3 <= c3 ;
toggle <= true ;
wait ;
end process ;
process (toggle)
variable vinteger1, vinteger2, vinteger3 : integer range 1 to 3
:= 2 ;
variable vbool1, vbool2, vbool3 : boolean
:= false ;
variable vstring1, vstring2, vstring3 : string ( cinteger1 to cinteger2 )
:= "a" ;
begin
if toggle = true then
test_report ( "ARCH00655" ,
"(Multiple object) declarations equivalent to"
& " multiple (object declarations) (locally static)" ,
vinteger1 = cinteger1 and cinteger1 = sinteger1
and sinteger1 = vinteger2 and
vinteger2 = cinteger2 and cinteger2 = sinteger2
and sinteger2 = vinteger3 and
vinteger3 = cinteger3 and cinteger3 = sinteger3
and sinteger3 = vinteger1
and vinteger1 = c1 and
vbool1 = cbool1 and cbool1 = sbool1
and sbool1 = vbool2 and
vbool2 = cbool2 and cbool2 = sbool2
and sbool2 = vbool3 and
vbool3 = cbool3 and cbool3 = sbool3
and sbool3 = vbool1
and vbool1 = c2 and
vstring1 = cstring1 and cstring1 = sstring1
and sstring1 = vstring2 and
vstring2 = cstring2 and cstring2 = sstring2
and sstring2 = vstring3 and
vstring3 = cstring3 and cstring3 = sstring3
and sstring3 = vstring1
and vstring1 = c3 and
cbv1 = cbv2 and cbv2 = cbv3 and cbv3 = c4 ) ;
end if ;
end process ;
end ARCH00655_1 ;
--
entity ENT00655 is
generic ( r1 : integer := 1 ;
r2 : integer := 3 ;
c1 : integer := 2 ;
c2 : boolean := false ;
r3 : integer := 2 ;
r4 : integer := 2 ;
c3 : string := "a" ;
c4 : bit_vector := B"0110" ) ;
end ENT00655 ;
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00655 of ENT00655 is
--
constant cinteger1, cinteger2, cinteger3 : integer range r1 to r2 := c1 ;
constant cbool1, cbool2, cbool3 : boolean := c2 ;
constant cstring1, cstring2, cstring3 : string ( r3 to r4 )
:= c3 ;
constant cbv1, cbv2, cbv3 : bit_vector := c4 ;
--
signal sinteger1, sinteger2, sinteger3 : integer range 1 to 3 ;
signal sbool1, sbool2, sbool3 : boolean ;
signal sstring1, sstring2, sstring3 : string ( cinteger1 to cinteger2 ) ;
signal toggle : boolean := false ;
procedure p1 (
r1 : integer ;
r2 : integer ;
c1 : integer ;
c2 : boolean ;
r3 : integer ;
r4 : integer ;
c3 : string ;
c4 : bit_vector
) is
constant cinteger1, cinteger2, cinteger3 : integer range r1 to r2 := c1 ;
constant cbool1, cbool2, cbool3 : boolean := c2 ;
constant cstring1, cstring2, cstring3 : string ( r3 to r4 )
:= c3 ;
constant cbv1, cbv2, cbv3 : bit_vector := c4 ;
--
variable vinteger1, vinteger2, vinteger3 : integer range 1 to 3
:= 2 ;
variable vbool1, vbool2, vbool3 : boolean
:= false ;
variable vstring1, vstring2, vstring3 : string ( cinteger1 to cinteger2 )
:= "a" ;
begin
test_report ( "ARCH00655" ,
"(Multiple object) declarations equivalent to"
& " multiple (object declarations) (dynamic)" ,
vinteger1 = cinteger1 and cinteger1 = vinteger2 and
vinteger2 = cinteger2 and cinteger2 = vinteger3 and
vinteger3 = cinteger3 and cinteger2 = vinteger1
and vinteger1 = c1 and
vbool1 = cbool1 and cbool1 = vbool2 and
vbool2 = cbool2 and cbool2 = vbool3 and
vbool3 = cbool3 and cbool2 = vbool1
and vbool1 = c2 and
vstring1 = cstring1 and cstring1 = vstring2 and
vstring2 = cstring2 and cstring2 = vstring3 and
vstring3 = cstring3 and cstring2 = vstring1
and vinteger1 = c1 and
cbv1 = cbv2 and cbv2 = cbv3 and cbv3 = c4 ) ;
end p1 ;
begin
process
begin
sinteger1 <= c1 ;
sinteger2 <= c1 ;
sinteger3 <= c1 ;
sbool1 <= c2 ;
sbool2 <= c2 ;
sbool3 <= c2 ;
sstring1 <= c3 ;
sstring2 <= c3 ;
sstring3 <= c3 ;
toggle <= true ;
wait ;
end process ;
process (toggle)
variable vinteger1, vinteger2, vinteger3 : integer range 1 to 3
:= 2 ;
variable vbool1, vbool2, vbool3 : boolean
:= false ;
variable vstring1, vstring2, vstring3 : string ( cinteger1 to cinteger2 )
:= "a" ;
begin
if toggle = true then
test_report ( "ARCH00655" ,
"(Multiple object) declarations equivalent to"
& " multiple (object declarations) (globally static)" ,
vinteger1 = cinteger1 and cinteger1 = vinteger2 and
vinteger2 = cinteger2 and cinteger2 = vinteger3 and
vinteger3 = cinteger3 and cinteger2 = vinteger1
and vinteger1 = c1 and
vbool1 = cbool1 and cbool1 = vbool2 and
vbool2 = cbool2 and cbool2 = vbool3 and
vbool3 = cbool3 and cbool2 = vbool1
and vbool1 = c2 and
vstring1 = cstring1 and cstring1 = vstring2 and
vstring2 = cstring2 and cstring2 = vstring3 and
vstring3 = cstring3 and cstring2 = vstring1
and vinteger1 = c1 and
cbv1 = cbv2 and cbv2 = cbv3 and cbv3 = c4 ) ;
p1 ( 1, 3, 2, false, 2, 2, "a", B"0110" ) ;
end if ;
end process ;
end ARCH00655 ;
--
entity ENT00655_Test_Bench is
end ENT00655_Test_Bench ;
architecture ARCH00655_Test_Bench of ENT00655_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00655_1 ) ;
for CIS2 : UUT use entity WORK.ENT00655 ( ARCH00655 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
end block L1 ;
end ARCH00655_Test_Bench ;
--
|
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: FL and FL^-1 functions, only for 128-bit key en/decryption
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity FL128 is
generic (
fl_ke_offset : INTEGER; -- encryption
fl_ke_shift : INTEGER;
fli_ke_offset : INTEGER;
fli_ke_shift : INTEGER;
fl_kd_offset : INTEGER; -- decryption
fl_kd_shift : INTEGER;
fli_kd_offset : INTEGER;
fli_kd_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 255);
dec : in STD_LOGIC;
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end FL128;
architecture RTL of FL128 is
signal fl_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_in_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_r : STD_LOGIC_VECTOR (0 to 31);
signal tmp_fl_ke : STD_LOGIC_VECTOR (0 to 127); -- encryption
signal tmp_fli_ke : STD_LOGIC_VECTOR (0 to 127);
signal tmp_fl_kd : STD_LOGIC_VECTOR (0 to 127); -- decryption
signal tmp_fli_kd : STD_LOGIC_VECTOR (0 to 127);
signal fl_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_k_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_r : STD_LOGIC_VECTOR (0 to 31);
signal fl_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b2 : STD_LOGIC_VECTOR (0 to 31);
-- registers
signal reg_fl_in : STD_LOGIC_VECTOR (0 to 63);
signal reg_fli_in : STD_LOGIC_VECTOR (0 to 63);
begin
REG : process(reset, clk)
begin
if (reset = '1') then
reg_fl_in <= (others=>'0');
reg_fli_in <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg_fl_in <= fl_in;
reg_fli_in <= fli_in;
end if;
end if;
end process;
--FL function
fl_in_l <= reg_fl_in(0 to 31);
fl_in_r <= reg_fl_in(32 to 63);
tmp_fl_ke <= k(fl_ke_offset+fl_ke_shift to fl_ke_offset+127) &
k(fl_ke_offset to fl_ke_offset+fl_ke_shift-1);
tmp_fl_kd <= k(fl_kd_offset+fl_kd_shift to fl_kd_offset+127) &
k(fl_kd_offset to fl_kd_offset+fl_kd_shift-1);
fl_k_l <= tmp_fl_ke(0 to 31) when dec='0' else tmp_fl_kd(64 to 95);
fl_k_r <= tmp_fl_ke(32 to 63) when dec='0' else tmp_fl_kd(96 to 127);
fl_a1 <= fl_in_l and fl_k_l;
fl_a2 <= (fl_a1(1 to 31) & fl_a1(0)) xor fl_in_r;
fl_b1 <= fl_a2 or fl_k_r;
fl_b2 <= fl_in_l xor fl_b1;
fl_out <= fl_b2 & fl_a2;
--FL^-1 function
fli_in_l <= reg_fli_in(0 to 31);
fli_in_r <= reg_fli_in(32 to 63);
tmp_fli_ke <= k(fli_ke_offset+fli_ke_shift to fli_ke_offset+127) &
k(fli_ke_offset to fli_ke_offset+fli_ke_shift-1);
tmp_fli_kd <= k(fli_kd_offset+fli_kd_shift to fli_kd_offset+127) &
k(fli_kd_offset to fli_kd_offset+fli_kd_shift-1);
fli_k_l <= tmp_fli_ke(64 to 95) when dec='0' else tmp_fli_kd(0 to 31);
fli_k_r <= tmp_fli_ke(96 to 127) when dec='0' else tmp_fli_kd(32 to 63);
fli_a1 <= fli_in_r or fli_k_r;
fli_a2 <= fli_in_l xor fli_a1;
fli_b1 <= fli_a2 and fli_k_l;
fli_b2 <= (fli_b1(1 to 31) & fli_b1(0)) xor fli_in_r;
fli_out <= fli_a2 & fli_b2;
end RTL;
|
library verilog;
use verilog.vl_types.all;
entity \bus\ is
port(
clk : in vl_logic;
reset : in vl_logic;
m0_req_n : in vl_logic;
m0_grant_n : out vl_logic;
m0_addr : in vl_logic_vector(29 downto 0);
m0_as_n : in vl_logic;
m0_rw : in vl_logic;
m0_wr_data : in vl_logic_vector(31 downto 0);
m1_req_n : in vl_logic;
m1_grant_n : out vl_logic;
m1_addr : in vl_logic_vector(29 downto 0);
m1_as_n : in vl_logic;
m1_rw : in vl_logic;
m1_wr_data : in vl_logic_vector(31 downto 0);
m2_req_n : in vl_logic;
m2_grant_n : out vl_logic;
m2_addr : in vl_logic_vector(29 downto 0);
m2_as_n : in vl_logic;
m2_rw : in vl_logic;
m2_wr_data : in vl_logic_vector(31 downto 0);
m3_req_n : in vl_logic;
m3_grant_n : out vl_logic;
m3_addr : in vl_logic_vector(29 downto 0);
m3_as_n : in vl_logic;
m3_rw : in vl_logic;
m3_wr_data : in vl_logic_vector(31 downto 0);
s_addr : out vl_logic_vector(29 downto 0);
s_as_n : out vl_logic;
s_rw : out vl_logic;
s_wr_data : out vl_logic_vector(31 downto 0);
s0_cs_n : out vl_logic;
s0_rd_data : in vl_logic_vector(31 downto 0);
s0_rdy_n : in vl_logic;
s1_cs_n : out vl_logic;
s1_rd_data : in vl_logic_vector(31 downto 0);
s1_rdy_n : in vl_logic;
s2_cs_n : out vl_logic;
s2_rd_data : in vl_logic_vector(31 downto 0);
s2_rdy_n : in vl_logic;
s3_cs_n : out vl_logic;
s3_rd_data : in vl_logic_vector(31 downto 0);
s3_rdy_n : in vl_logic;
s4_cs_n : out vl_logic;
s4_rd_data : in vl_logic_vector(31 downto 0);
s4_rdy_n : in vl_logic;
s5_cs_n : out vl_logic;
s5_rd_data : in vl_logic_vector(31 downto 0);
s5_rdy_n : in vl_logic;
s6_cs_n : out vl_logic;
s6_rd_data : in vl_logic_vector(31 downto 0);
s6_rdy_n : in vl_logic;
s7_cs_n : out vl_logic;
s7_rd_data : in vl_logic_vector(31 downto 0);
s7_rdy_n : in vl_logic;
m_rd_data : out vl_logic_vector(31 downto 0);
m_rdy_n : out vl_logic
);
end \bus\;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:28:54 11/19/2013
-- Design Name:
-- Module Name: CPU_CORE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU_CORE is
Port ( CLK_IN : in STD_LOGIC;
RAM1_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1_EN : out STD_LOGIC;
RAM1_WE : out STD_LOGIC;
RAM1_OE : out STD_LOGIC;
RAM1_Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM2_EN : out STD_LOGIC;
RAM2_WE : out STD_LOGIC;
RAM2_OE : out STD_LOGIC;
RAM2_Data : inout STD_LOGIC_VECTOR (15 downto 0);
com_data_ready : in STD_LOGIC;
com_rdn : out STD_LOGIC;
com_tbre : in STD_LOGIC;
com_tsre : in STD_LOGIC;
com_wrn : out STD_LOGIC;
DISP1 : inout std_logic_vector(6 downto 0) := "0111111";
DISP2 : inout std_logic_vector(6 downto 0) := "0111111";
LED : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000");
end CPU_CORE;
architecture Behavioral of CPU_CORE is
COMPONENT CLK_MODULE
Port ( CLK_IN : in STD_LOGIC;
CLK : inout STD_LOGIC
);
END COMPONENT;
COMPONENT PC_Register
Port ( PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_OR_NOT : in STD_LOGIC;
CLK : in STD_LOGIC
);
END COMPONENT;
COMPONENT MUX_2
Port ( SELEC : in STD_LOGIC;
SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_3
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_4
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_6
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_5 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_6 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (2 downto 0) := "111";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
END COMPONENT;
COMPONENT RAM1_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
DataReady: in std_logic;
WriteData: in std_logic_vector(15 downto 0);
TSRE: in std_logic;
TBRE: in std_logic;
---output
RAM1_Enable: out std_logic;
RAM1_ReadEnable: out std_logic;
RAM1_WriteEnable: out std_logic;
SPort_WriteEnable:out std_logic;
SPort_ReadEnable: out std_logic;
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT RAM2_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0);
---output
RAM2_Enable: out std_logic := '1';
RAM2_ReadEnable: out std_logic := '1';
RAM2_WriteEnable: out std_logic := '1';
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT PC_Adder
Port ( OLD_PC : in STD_LOGIC_VECTOR (15 downto 0);
NEW_PC : out STD_LOGIC_VECTOR (15 downto 0)
);
END COMPONENT;
COMPONENT IF_ID_Register
Port ( NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_PC_OR_NOT : in STD_LOGIC;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
CLK : in STD_LOGIC;
INST_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_IR_OR_NOT : in STD_LOGIC;
WRITE_IR_SRC_SELEC : in STD_LOGIC;
INST_OUT_CODE : out STD_LOGIC_VECTOR(4 downto 0);
INST_OUT_RS : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RT : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RD : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_FUNC : out STD_LOGIC_VECTOR(1 downto 0));
END COMPONENT;
COMPONENT Imm_Extend
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
rd : in STD_LOGIC_VECTOR(2 downto 0);
func : in STD_LOGIC_VECTOR(1 downto 0);
imm : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT adder
port(
pc : in STD_LOGIC_VECTOR(15 downto 0);
imm : in STD_LOGIC_VECTOR(15 downto 0);
res : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Hazard_Detector
Port ( STALL_OR_NOT_FU : in STD_LOGIC;
CUR_INST_CODE : in STD_LOGIC_VECTOR (4 downto 0);
CUR_INST_RS : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RD : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_FUNC : in STD_LOGIC_VECTOR (1 downto 0);
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_DM_VISIT_ADDR : in STD_LOGIC_VECTOR (15 downto 0);
CUR_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
CUR_DM_WRITE_DATA_SRC : in STD_LOGIC_VECTOR(1 downto 0);
JUMP_OR_NOT : in STD_LOGIC;
WRITE_PC_OR_NOT : out STD_LOGIC;
NEW_PC_SRC_SELEC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_IR_OR_NOT : out STD_LOGIC;
WRITE_IR_SRC_SELEC : out STD_LOGIC;
COMMAND_ORIGIN_OR_NOP : out STD_LOGIC;
DM_DATA_RESULT_SELEC : out STD_LOGIC;
IM_ADDR_SELEC : out STD_LOGIC;
IM_DATA_SELEC : out STD_LOGIC;
IM_READ_WRITE_SELEC : out STD_LOGIC_VECTOR(1 downto 0)
);
END COMPONENT;
COMPONENT Controller
Port ( INST_CODE : in STD_LOGIC_VECTOR(4 downto 0);
INST_RS : in STD_LOGIC_VECTOR(2 downto 0);
INST_RT : in STD_LOGIC_VECTOR(2 downto 0);
INST_RD : in STD_LOGIC_VECTOR(2 downto 0);
INST_FUNC : in STD_LOGIC_VECTOR(1 downto 0);
ALU_OP : out STD_LOGIC_VECTOR (3 downto 0);
ALU_A_SRC : out STD_LOGIC_VECTOR (2 downto 0);
ALU_B_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_REGS_DEST : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_DM_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_RA_OR_NOT : out STD_LOGIC;
WRITE_IH_OR_NOT : out STD_LOGIC;
WRITE_T_OR_NOT : out STD_LOGIC;
WRITE_SP_OR_NOT : out STD_LOGIC;
WRITE_T_SRC : out STD_LOGIC;
DATA_MEM_READ_WRITE : out STD_LOGIC_VECTOR(1 downto 0);
REGS_WRITE_OR_NOT : out STD_LOGIC;
REGS_WRITE_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT Common_Register
port(
clk : in STD_LOGIC;
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
write_flag : in STD_LOGIC;
write_reg : in STD_LOGIC_VECTOR(2 downto 0);
write_data : in STD_LOGIC_VECTOR(15 downto 0);
a : out STD_LOGIC_VECTOR(15 downto 0);
b : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Comparator
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
write_t : in STD_LOGIC;
t : in STD_LOGIC_VECTOR(15 downto 0);
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(15 downto 0);
jump : out STD_LOGIC
);
END COMPONENT;
COMPONENT ID_EXE_Register
port(
clk : in STD_LOGIC;
--cmd cmd
command_origin_or_nop : in STD_LOGIC;
--common input
in_pc : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_a : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_b : in STD_LOGIC_VECTOR(15 downto 0);
in_imm : in STD_LOGIC_VECTOR(15 downto 0);
in_rs : in STD_LOGIC_VECTOR(2 downto 0);
in_rt : in STD_LOGIC_VECTOR(2 downto 0);
in_rd : in STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
in_alu : in STD_LOGIC_VECTOR(3 downto 0);
in_a_src : in STD_LOGIC_VECTOR(2 downto 0);
in_b_src : in STD_LOGIC_VECTOR(1 downto 0);
in_reg_result : in STD_LOGIC_VECTOR(1 downto 0);
in_mem_src : in STD_LOGIC_VECTOR(1 downto 0);
in_flag_RA : in STD_LOGIC;
in_flag_IH : in STD_LOGIC;
in_flag_T : in STD_LOGIC;
in_flag_SP : in STD_LOGIC;
in_T_src : in STD_LOGIC;
--mem cmd
in_mem_cmd : in STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
in_flag_reg : in STD_LOGIC;
in_reg_src : in STD_LOGIC_VECTOR(1 downto 0);
--common output
out_pc : out STD_LOGIC_VECTOR(15 downto 0);
out_imm : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_a : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_b : out STD_LOGIC_VECTOR(15 downto 0);
--memory data
out_mem_data : out STD_LOGIC_VECTOR(15 downto 0);
--result register
out_res_reg : out STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
out_alu : out STD_LOGIC_VECTOR(3 downto 0);
out_a_src : out STD_LOGIC_VECTOR(2 downto 0);
out_b_src : out STD_LOGIC_VECTOR(1 downto 0);
out_flag_RA : out STD_LOGIC;
out_flag_IH : out STD_LOGIC;
out_flag_T : out STD_LOGIC;
out_flag_SP : out STD_LOGIC;
out_T_src : out STD_LOGIC;
--mem cmd
out_mem_cmd : out STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
out_flag_reg : out STD_LOGIC;
out_reg_src : out STD_LOGIC_VECTOR(1 downto 0);
cur_rs_num : out STD_LOGIC_VECTOR(2 downto 0);
cur_rt_num : out STD_LOGIC_VECTOR(2 downto 0)
);
END COMPONENT;
COMPONENT alu
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(15 downto 0);
op : in STD_LOGIC_VECTOR(3 downto 0);
zf : out STD_LOGIC;
sf : out STD_LOGIC;
c : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Special_Register
port(
clk : in STD_LOGIC;
T_cmd_write : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
RA_cmd_write : in STD_LOGIC;
RA_src : in STD_LOGIC_VECTOR(15 downto 0);
IH_cmd_write : in STD_LOGIC;
IH_src : in STD_LOGIC_VECTOR(15 downto 0);
SP_cmd_write : in STD_LOGIC;
SP_src : in STD_LOGIC_VECTOR(15 downto 0);
T_value : out STD_LOGIC_VECTOR(15 downto 0);
RA_value : out STD_LOGIC_VECTOR(15 downto 0);
IH_value : out STD_LOGIC_VECTOR(15 downto 0);
SP_value : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Forward_Unit
Port ( -- current instruction info, if use reg as alu src, conflict may exist
CUR_RS_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_RT_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_A_SRC_SELECT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_B_SRC_SELECT : in STD_LOGIC_VECTOR (1 downto 0);
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
-- last last instruction info, if write regs, conflict may exist
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
STALL_OR_NOT : out STD_LOGIC;
ALU_A_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0);
ALU_B_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT EXE_MEM_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_IN : in STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_OUT : out STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT MEM_WB_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
--controller, all to id/exe reg
signal alu_op_controller : std_logic_vector(3 downto 0) := ALU_NULL;
signal alu_a_src_select_controller : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_controller : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal write_regs_dest_select_controller : std_logic_vector(1 downto 0) := WRITE_REGS_DEST_RS;
signal write_dm_data_src_select_controller : std_logic_vector(1 downto 0) := WRITE_DM_DATA_SRC_Z;
signal write_ra_or_not_select_controller : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_controller : std_logic := WRITE_IH_NO;
signal write_t_or_not_select_controller : std_logic := WRITE_T_NO;
signal write_sp_or_not_select_controller : std_logic := WRITE_SP_NO;
signal write_t_src_select_controller : std_logic := T_SRC_IS_SF;
signal data_mem_read_write_select_controller : std_logic_vector(1 downto 0) := MEM_NONE;
signal regs_read_write_select_controller : std_logic := WRITE_REGS_NO;
signal regs_write_data_src_select_controller : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- hazard detector
-- to PC reg
signal write_pc_or_not_hazard_detector : std_logic := WRITE_PC_YES;
-- to PC mux
signal new_pc_src_select_hazard_detector : std_logic_vector(1 downto 0) := NEW_PC_SRC_SELEC_PC_ADD_ONE;
-- to if/id reg
signal write_ir_or_not_hazard_detector : std_logic := WRITE_IR_YES;
signal write_ir_src_select_hazard_detector : std_logic := WRITE_IR_SRC_SELEC_ORIGIN;
-- to id/exe reg
signal command_origin_or_nop_hazard_detector : std_logic := COMMAND_ORIGIN;
-- to mem/wb reg
signal dm_visit_data_result_select_hazard_detector : std_logic := DM_DATA_RESULT_DM;
-- to im
signal im_visit_data_select_hazard_detector : std_logic :=IM_DATA_Z;
signal im_visit_addr_select_hazard_detector : std_logic := IM_ADDR_PC;
signal im_read_write_select_hazard_detector : std_logic_vector(1 downto 0) := MEM_READ;
-- forward unit
-- to hazard detector
signal stall_or_not_forward_unit : std_logic := STALL_NO;
-- to alu a src mux 2
signal alu_a_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_A_SRC_SELECT_FINAL_ORIGIN;
-- to alu b src mux 2
signal alu_b_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_B_SRC_SELECT_FINAL_ORIGIN;
-- comparator
-- to hazard detector
signal jump_or_not_comparator : std_logic := JUMP_FALSE;
-- if
-- PC to IM, PC Adder
signal pc_value_pc_reg_to_im : std_logic_vector(15 downto 0) := ZERO;
-- PC Adder to if/id reg, PC mux
signal pc_value_pc_adder_to_if_id_reg : std_logic_vector(15 downto 0) := ZERO;
-- IM to if/id reg
signal inst_im_to_if_id_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- PC mux to PC
signal pc_value_pc_mux_to_pc : std_logic_vector(15 downto 0) := ZERO;
-- id
-- if/id reg to controller, imm extender, id/exe reg(rs, rt, rd),
--comparator(code), hazard detector, common regs(rs, st)
signal inst_code_if_id_reg_to_controller : std_logic_vector(4 downto 0) := NOP_INST(15 downto 11);
signal inst_rs_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(10 downto 8);
signal inst_rt_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(7 downto 5);
signal inst_rd_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(4 downto 2);
signal inst_func_if_id_reg_to_controller : std_logic_vector(1 downto 0) := NOP_INST(1 downto 0);
-- if/id reg to id/exe reg, PC IMM Adder, to special regs(RA)
signal pc_value_if_id_reg_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- imm extender to id/exe reg, PC IMM Adder
signal imm_imm_extend_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- PC IMM Adder to PC mux
signal pc_value_pc_imm_adder_to_pc_mux : std_logic_vector(15 downto 0) := ZERO;
-- common regs to id/exe reg, comparator(A), PC mux(A)
signal a_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- if/id reg to im
--signal inst_if_id_reg_to_im : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- if/id reg to forward unit
signal cur_rs_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
signal cur_rt_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
-- exe
-- id/exe reg to alu src mux 1
signal alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1 : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal a_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal imm_id_exe_reg_to_alu_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- id/exe reg to exe/mem reg
signal pc_value_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
signal write_dm_data_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
signal regs_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_id_exe_reg_to_exe_mem_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal data_mem_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := MEM_NONE;
-- id/exe reg to alu
signal alu_op_id_exe_reg_to_alu : std_logic_vector(3 downto 0) := ALU_NULL;
-- id/exe to special regs, to comparator(write t or not)
signal write_t_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_T_NO;
signal write_t_src_select_id_exe_reg_to_special_regs : std_logic := T_SRC_IS_SF;
signal write_ra_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_IH_NO;
signal write_sp_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_SP_NO;
-- constant to alu src mux 1
signal all_zeros : std_logic_vector(15 downto 0) := ZERO;
-- special regs to alu src mux 1(SP)
signal sp_reg_special_regs_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- special regs to exe/mem reg(IH)
signal ih_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- special regs to comparator(T)
signal t_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu src mux 1 to alu src mux 2
signal alu_a_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
-- alu mux 2 to alu
signal alu_a_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
-- alu to exe/mem reg
signal alu_result_alu_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu to special regs(T)
signal alu_sf_alu_to_special_regs : std_logic := '0';
signal alu_zf_alu_to_special_regs : std_logic := '0';
-- mem in exe/mem reg
-- to RAM_Visitor
signal data_mem_read_write_select_exe_mem_reg_to_dm : std_logic_vector(1 downto 0) := MEM_NONE;
-- as data memory address, to mem/wb reg
signal alu_result_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := ZERO;
-- as data memory data, to mem/wb reg
signal write_dm_data_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- to mem/wb reg
signal regs_read_write_select_exe_mem_reg_to_mem_wb_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_exe_mem_reg_to_mem_wb_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal ih_reg_exe_mem_reg_to_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
signal pc_value_exe_mem_reg_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
-- lw/sw to IM
signal im_visit_addr_im_mux_to_im : std_logic_vector(15 downto 0);
signal im_visit_data_im_mux_to_im : std_logic_vector(15 downto 0);
-- DM to mem/wb reg
signal read_dm_data_dm_to_mem_wb_reg : std_logic_vector(15 downto 0);
signal dm_visit_data_dm_mux_to_mem_wb_reg : std_logic_vector(15 downto 0);
-- wb in mem/wb reg
-- to common regs write src mux
signal ih_reg_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal alu_result_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
--alse to special regs(IH, SP)
signal dm_data_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
-- also to alu src mux 2
signal pc_value_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- to common regs
signal regs_read_write_select_mem_wb_reg_to_common_regs : std_logic := WRITE_REGS_NO;
signal write_regs_num_mem_wb_reg_to_common_regs : std_logic_vector(2 downto 0) := "ZZZ";
-- common regs write src mux to common regs
signal write_regs_data_src_mux_to_regs : std_logic_vector(15 downto 0) := ZERO;
-- not used
signal ra_reg_special_regs_to_where : std_logic_vector(15 downto 0) := ZERO;
signal watch_info : std_logic_vector(15 downto 0) := ZERO;
signal high_resist_port : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- signal write_pc_force : std_logic := '1';
-- signal write_ir_force : std_logic := '1';
-- signal write_ir_origin_force : std_logic := '0';
-- signal write_pc_add_one_force : std_logic_vector(1 downto 0) := "00";
signal led_ram_visitor_to_cpu_core : std_logic_vector(7 downto 0) := "00000000";
signal useless_pin : std_logic_vector(4 downto 0) := "11111";
signal CLK : std_logic := '1';
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
begin
Unit_CLK_MODULE : CLK_MODULE port map (
CLK_IN => CLK_IN,
CLK => CLK
);
Unit_New_PC_Src_Mux3 : MUX_3 port map (
-- PC + 1
SRC_1 => pc_value_pc_adder_to_if_id_reg,
-- PC + IMM
SRC_2 => pc_value_pc_imm_adder_to_pc_mux,
-- A reg
SRC_3 => a_reg_common_regs_to_id_exe_reg,
SELEC => new_pc_src_select_hazard_detector, --write_pc_add_one_force,--
OUTPUT => pc_value_pc_mux_to_pc
);
Unit_PC_Register : PC_Register port map (
PC_IN => pc_value_pc_mux_to_pc,
PC_OUT => pc_value_pc_reg_to_im,
WRITE_OR_NOT => write_pc_or_not_hazard_detector, --write_pc_force,--
CLK => CLK
);
Unit_PC_Adder : PC_Adder port map (
OLD_PC => pc_value_pc_reg_to_im,
NEW_PC => pc_value_pc_adder_to_if_id_reg
);
Unit_IM_Addr_Mux : MUX_2 port map(
SELEC => im_visit_addr_select_hazard_detector,
SRC_1 => pc_value_pc_reg_to_im,
SRC_2 => alu_result_exe_mem_reg_to_dm,
OUTPUT => im_visit_addr_im_mux_to_im
);
Unit_IM_Data_Mux : MUX_2 port map(
SELEC => im_visit_data_select_hazard_detector,
SRC_1 => high_resist_port,
SRC_2 => write_dm_data_exe_mem_reg_to_dm,
OUTPUT => im_visit_data_im_mux_to_im
);
Unit_RAM1_Visitor : RAM1_Visitor port map (
---input
clk => CLK,
DMemReadWrite => data_mem_read_write_select_exe_mem_reg_to_dm,
EXandMEM_AluRes => alu_result_exe_mem_reg_to_dm,
DataReady => com_data_ready,
WriteData => write_dm_data_exe_mem_reg_to_dm,
TSRE => com_tsre,
TBRE => com_tbre,
---output
RAM1_Enable => RAM1_EN,
RAM1_ReadEnable => RAM1_OE,
RAM1_WriteEnable => RAM1_WE,
SPort_WriteEnable => com_wrn,
SPort_ReadEnable => com_rdn,
DMemData => RAM1_Data,
DMemAddr => RAM1_Addr(15 downto 0)
);
Unit_RAM2_Visitor : RAM2_Visitor port map (
---input
clk => CLK,
DMemReadWrite => im_read_write_select_hazard_detector,
EXandMEM_AluRes => im_visit_addr_im_mux_to_im,
-- DataReady => useless_pin(4),
WriteData => im_visit_data_im_mux_to_im,
-- TSRE => useless_pin(3),
-- TBRE => useless_pin(2),
---output
RAM1_Enable => RAM2_EN,
RAM1_ReadEnable => RAM2_OE,
RAM1_WriteEnable => RAM2_WE,
-- SPort_WriteEnable => useless_pin(1),
-- SPort_ReadEnable => useless_pin(0),
DMemData => RAM2_Data,
DMemAddr => RAM2_Addr(15 downto 0)
);
RAM1_Addr(17 downto 16) <= "00";
RAM2_Addr(17 downto 16) <= "00";
-- LED(15 downto 8) <= led_ram_visitor_to_cpu_core;
Unit_IF_ID_Register : IF_ID_Register port map (
NEW_PC_IN => pc_value_pc_adder_to_if_id_reg,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_OUT => pc_value_if_id_reg_to_id_exe_reg,
CLK => CLK,
INST_IN => inst_im_to_if_id_reg,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector, --write_ir_force,--
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector, --write_ir_origin_force,--
INST_OUT_CODE => inst_code_if_id_reg_to_controller,
INST_OUT_RS => inst_rs_if_id_reg_to_controller,
INST_OUT_RT => inst_rt_if_id_reg_to_controller,
INST_OUT_RD => inst_rd_if_id_reg_to_controller,
INST_OUT_FUNC => inst_func_if_id_reg_to_controller
);
-- detect before id, just after INST could be read rightly
Unit_Hazard_Detector : Hazard_Detector port map (
STALL_OR_NOT_FU => stall_or_not_forward_unit,
CUR_INST_CODE => inst_code_if_id_reg_to_controller,
CUR_INST_RS => inst_rs_if_id_reg_to_controller,
CUR_INST_RT => inst_rt_if_id_reg_to_controller,
CUR_INST_RD => inst_rd_if_id_reg_to_controller,
CUR_INST_FUNC => inst_func_if_id_reg_to_controller,
-- in id/exe reg
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- in exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,
-- in exe/mem reg
LAST_LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_exe_mem_reg_to_dm,
LAST_LAST_DM_VISIT_ADDR => alu_result_exe_mem_reg_to_dm,
CUR_DM_READ_WRITE => data_mem_read_write_select_controller,
CUR_DM_WRITE_DATA_SRC => write_dm_data_src_select_controller,
JUMP_OR_NOT => jump_or_not_comparator,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_SRC_SELEC => new_pc_src_select_hazard_detector,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector,
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector,
COMMAND_ORIGIN_OR_NOP => command_origin_or_nop_hazard_detector,
DM_DATA_RESULT_SELEC => dm_visit_data_result_select_hazard_detector,
IM_ADDR_SELEC => im_visit_addr_select_hazard_detector,
IM_DATA_SELEC => im_visit_data_select_hazard_detector,
IM_READ_WRITE_SELEC => im_read_write_select_hazard_detector
);
Unit_Controller : Controller port map (
INST_CODE => inst_code_if_id_reg_to_controller,
INST_RS => inst_rs_if_id_reg_to_controller,
INST_RT => inst_rt_if_id_reg_to_controller,
INST_RD => inst_rd_if_id_reg_to_controller,
INST_FUNC => inst_func_if_id_reg_to_controller,
ALU_OP => alu_op_controller,
ALU_A_SRC => alu_a_src_select_controller,
ALU_B_SRC => alu_b_src_select_controller,
WRITE_REGS_DEST => write_regs_dest_select_controller,
WRITE_DM_DATA_SRC => write_dm_data_src_select_controller,
WRITE_RA_OR_NOT => write_ra_or_not_select_controller,
WRITE_IH_OR_NOT => write_ih_or_not_select_controller,
WRITE_T_OR_NOT => write_t_or_not_select_controller,
WRITE_SP_OR_NOT => write_sp_or_not_select_controller,
WRITE_T_SRC => write_t_src_select_controller,
DATA_MEM_READ_WRITE => data_mem_read_write_select_controller,
REGS_WRITE_OR_NOT => regs_read_write_select_controller,
REGS_WRITE_DATA_SRC => regs_write_data_src_select_controller
);
Unit_Imm_Extend : Imm_Extend port map (
code => inst_code_if_id_reg_to_controller,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
rd => inst_rd_if_id_reg_to_controller,
func => inst_func_if_id_reg_to_controller,
imm => imm_imm_extend_to_id_exe_reg
);
Unit_adder : adder port map (
pc => pc_value_if_id_reg_to_id_exe_reg,
imm => imm_imm_extend_to_id_exe_reg,
res => pc_value_pc_imm_adder_to_pc_mux
);
Unit_Common_regs_write_src_Mux4 : MUX_4 port map (
-- ALU result
SRC_1 => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
-- DM data
SRC_2 => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
-- IH
SRC_3 => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
-- PC
SRC_4 => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
SELEC => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux,
OUTPUT => write_regs_data_src_mux_to_regs
);
Unit_Common_Register : Common_Register port map (
clk => CLK,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
write_flag => regs_read_write_select_mem_wb_reg_to_common_regs,
write_reg => write_regs_num_mem_wb_reg_to_common_regs,
write_data => write_regs_data_src_mux_to_regs,
a => a_reg_common_regs_to_id_exe_reg,
b => b_reg_common_regs_to_id_exe_reg
);
Unit_Comparator : Comparator port map (
code => inst_code_if_id_reg_to_controller,
write_t => write_t_or_not_select_id_exe_reg_to_special_regs,
t => t_reg_special_regs_to_exe_mem_reg,
-- could not be given as one value
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
a => a_reg_common_regs_to_id_exe_reg,
jump => jump_or_not_comparator
);
Unit_ID_EXE_Register : ID_EXE_Register port map (
clk => CLK,
--cmd cmd
command_origin_or_nop => command_origin_or_nop_hazard_detector,
--common input
in_pc => pc_value_if_id_reg_to_id_exe_reg,
in_reg_a => a_reg_common_regs_to_id_exe_reg,
in_reg_b => b_reg_common_regs_to_id_exe_reg,
in_imm => imm_imm_extend_to_id_exe_reg,
in_rs => inst_rs_if_id_reg_to_controller,
in_rt => inst_rt_if_id_reg_to_controller,
in_rd => inst_rd_if_id_reg_to_controller,
--exe cmd
in_alu => alu_op_controller,
in_a_src => alu_a_src_select_controller,
in_b_src => alu_b_src_select_controller,
in_reg_result => write_regs_dest_select_controller,
in_mem_src => write_dm_data_src_select_controller,
in_flag_RA => write_ra_or_not_select_controller,
in_flag_IH => write_ih_or_not_select_controller,
in_flag_T => write_t_or_not_select_controller,
in_flag_SP => write_sp_or_not_select_controller,
in_T_src => write_t_src_select_controller,
--mem cmd
in_mem_cmd => data_mem_read_write_select_controller,
--wb cmd
in_flag_reg => regs_read_write_select_controller,
in_reg_src => regs_write_data_src_select_controller,
--common output
out_pc => pc_value_id_exe_reg_to_exe_mem_reg,
out_imm => imm_id_exe_reg_to_alu_src_mux_1,
out_reg_a => a_reg_id_exe_reg_to_alu_a_src_mux_1,
out_reg_b => b_reg_id_exe_reg_to_alu_a_src_mux_1,
--memory data
out_mem_data => write_dm_data_id_exe_reg_to_exe_mem_reg,
--result register
out_res_reg => write_regs_num_id_exe_reg_to_exe_mem_reg,
--exe cmd
out_alu => alu_op_id_exe_reg_to_alu,
out_a_src => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
out_b_src => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
out_flag_RA => write_ra_or_not_select_id_exe_reg_to_special_regs,
out_flag_IH => write_ih_or_not_select_id_exe_reg_to_special_regs,
out_flag_T => write_t_or_not_select_id_exe_reg_to_special_regs,
out_flag_SP => write_sp_or_not_select_id_exe_reg_to_special_regs,
out_T_src => write_t_src_select_id_exe_reg_to_special_regs,
--mem cmd
out_mem_cmd => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
--wb cmd
out_flag_reg => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
out_reg_src => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
cur_rs_num => cur_rs_num_if_id_reg_to_forward_unit,
cur_rt_num => cur_rt_num_if_id_reg_to_forward_unit
);
all_zeros <= ZERO;
Unit_ALU_A_Src_Select1_Mux6 : MUX_6 port map (
-- A
SRC_1 => a_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
-- SP
SRC_4 => sp_reg_special_regs_to_alu_a_src_mux_1,
-- PC
SRC_5 => pc_value_id_exe_reg_to_exe_mem_reg,
-- IH
SRC_6 => ih_reg_special_regs_to_exe_mem_reg,
SELEC => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
OUTPUT => alu_a_src_value_mux1_to_mux2
);
Unit_ALU_B_Src_Select1_Mux3 : MUX_3 port map (
-- B
SRC_1 => b_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
SELEC => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
OUTPUT => alu_b_src_value_mux1_to_mux2
);
Unit_ALU_A_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_a_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_a_src_select_final_forward_unit,
OUTPUT => alu_a_src_alu_mux2_to_alu
);
Unit_ALU_B_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_b_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_b_src_select_final_forward_unit,
OUTPUT => alu_b_src_alu_mux2_to_alu
);
Unit_ALU : alu port map (
a => alu_a_src_alu_mux2_to_alu,
b => alu_b_src_alu_mux2_to_alu,
op => alu_op_id_exe_reg_to_alu,
zf => alu_zf_alu_to_special_regs,
sf => alu_sf_alu_to_special_regs,
c => alu_result_alu_to_exe_mem_reg
);
Unit_Special_Register : Special_Register port map (
clk => CLK,
T_cmd_write => write_t_or_not_select_id_exe_reg_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
-- from controller, id/exe reg is too late
RA_cmd_write => write_ra_or_not_select_controller,
RA_src => pc_value_if_id_reg_to_id_exe_reg,
IH_cmd_write => write_ih_or_not_select_id_exe_reg_to_special_regs,
IH_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
SP_cmd_write => write_sp_or_not_select_id_exe_reg_to_special_regs,
SP_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
T_value => t_reg_special_regs_to_exe_mem_reg,
RA_value => ra_reg_special_regs_to_where,
IH_value => ih_reg_special_regs_to_exe_mem_reg,
SP_value => sp_reg_special_regs_to_alu_a_src_mux_1
);
-- judge before update id/exe reg, to stop next inst get in
Unit_Forward_Unit : Forward_Unit port map (
-- current instruction info, if use reg as alu src, conflict may exist
-- get from if/id reg
-- detect early, stop early
CUR_RS_REG_NUM => cur_rs_num_if_id_reg_to_forward_unit,--inst_rs_if_id_reg_to_controller,
CUR_RT_REG_NUM => cur_rt_num_if_id_reg_to_forward_unit,--inst_rt_if_id_reg_to_controller,
-- get it from controller, from id/exe reg is too late
CUR_ALU_A_SRC_SELECT => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,--alu_a_src_select_controller,
CUR_ALU_B_SRC_SELECT => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,--alu_b_src_select_controller,
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
-- from id/exe reg
--
--
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,--regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,--write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_DM_READ_WRITE => data_mem_read_write_select_exe_mem_reg_to_dm,--data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- last last instruction info, if write regs, conflict may exist
-- from exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_mem_wb_reg_to_common_regs, --regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_mem_wb_reg_to_common_regs, --write_regs_num_exe_mem_reg_to_mem_wb_reg,
STALL_OR_NOT => stall_or_not_forward_unit,
ALU_A_SRC_SELECT_FINAL => alu_a_src_select_final_forward_unit,
ALU_B_SRC_SELECT_FINAL => alu_b_src_select_final_forward_unit
);
Unit_EXE_MEM_Register : EXE_MEM_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_id_exe_reg_to_exe_mem_reg,
WRITE_DM_DATA_IN => write_dm_data_id_exe_reg_to_exe_mem_reg,
WRITE_REG_NUM_IN => write_regs_num_id_exe_reg_to_exe_mem_reg,
ALU_RESULT_IN => alu_result_alu_to_exe_mem_reg,
IH_REG_IN => ih_reg_special_regs_to_exe_mem_reg,
DATA_MEM_READ_WRITE_IN => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_READ_WRITE_IN => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
NEW_PC_OUT => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_DM_DATA_OUT => write_dm_data_exe_mem_reg_to_dm,
WRITE_REG_NUM_OUT => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_OUT => alu_result_exe_mem_reg_to_dm,
IH_REG_OUT => ih_reg_exe_mem_reg_to_mem_wb_reg,
DATA_MEM_READ_WRITE_OUT => data_mem_read_write_select_exe_mem_reg_to_dm,
REGS_READ_WRITE_OUT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg
);
Unit_DM_Data_Result_Mux : MUX_2 port map(
SELEC => dm_visit_data_result_select_hazard_detector,
SRC_1 => read_dm_data_dm_to_mem_wb_reg,
SRC_2 => inst_im_to_if_id_reg,
OUTPUT => dm_visit_data_dm_mux_to_mem_wb_reg
);
Unit_MEM_WB_Register : MEM_WB_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_REGS_NUM_IN => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_IN => alu_result_exe_mem_reg_to_dm,
IH_REG_IN => ih_reg_exe_mem_reg_to_mem_wb_reg,
DM_DATA_IN => dm_visit_data_dm_mux_to_mem_wb_reg,
-- cmd
REGS_READ_WRITE_IN => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg,
NEW_PC_OUT => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
WRITE_REGS_NUM_OUT => write_regs_num_mem_wb_reg_to_common_regs,
ALU_RESULT_OUT => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
IH_REG_OUT => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
DM_DATA_OUT => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
REGS_READ_WRITE_OUT => regs_read_write_select_mem_wb_reg_to_common_regs,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux
);
read_dm_data_dm_to_mem_wb_reg <= RAM1_Data;
inst_im_to_if_id_reg <= RAM2_Data;
process (CLK, inst_im_to_if_id_reg, pc_value_pc_reg_to_im, write_pc_or_not_hazard_detector, write_ir_or_not_hazard_detector)
--variable step : integer := 0;
begin
if (CLK'event and CLK = '0') then
-- IF
watch_info <= watch_info + "0000000000000001";
-- LED(15 downto 11) <= inst_code_if_id_reg_to_controller;
-- LED(10 downto 8) <= inst_rs_if_id_reg_to_controller;
-- LED(7 downto 5) <= inst_rt_if_id_reg_to_controller;
-- LED(4 downto 2) <= inst_rd_if_id_reg_to_controller;
-- LED(1 downto 0) <= inst_func_if_id_reg_to_controller;
LED <= pc_value_pc_reg_to_im;
case DISP1 is
when "0111111" =>
DISP1 <= "0000110";
when "0000110" =>
DISP1 <= "1011011";
when "1011011" =>
DISP1 <= "1001111";
when "1001111" =>
DISP1 <= "1100110";
when "1100110" =>
DISP1 <= "1101101";
when "1101101" =>
DISP1 <= "1111101";
when "1111101" =>
DISP1 <= "0000111";
when "0000111" =>
DISP1 <= "1111111";
when "1111111" =>
DISP1 <= "1101111";
when "1101111" =>
DISP1 <= "0111111";
case DISP2 is
when "1101111" =>
DISP2 <= "0111111";
when "0111111" =>
DISP2 <= "0000110";
when "0000110" =>
DISP2 <= "1011011";
when "1011011" =>
DISP2 <= "1001111";
when "1001111" =>
DISP2 <= "1100110";
when "1100110" =>
DISP2 <= "1101101";
when "1101101" =>
DISP2 <= "1111101";
when "1111101" =>
DISP2 <= "0000111";
when "0000111" =>
DISP2 <= "1111111";
when "1111111" =>
DISP2 <= "1101111";
when others =>
DISP2 <= "0111111";
end case;
when others =>
DISP1 <= "0111111";
end case;
elsif (CLK = '1') then
high_resist_port <= HIGH_RESIST;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:28:54 11/19/2013
-- Design Name:
-- Module Name: CPU_CORE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU_CORE is
Port ( CLK_IN : in STD_LOGIC;
RAM1_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1_EN : out STD_LOGIC;
RAM1_WE : out STD_LOGIC;
RAM1_OE : out STD_LOGIC;
RAM1_Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM2_EN : out STD_LOGIC;
RAM2_WE : out STD_LOGIC;
RAM2_OE : out STD_LOGIC;
RAM2_Data : inout STD_LOGIC_VECTOR (15 downto 0);
com_data_ready : in STD_LOGIC;
com_rdn : out STD_LOGIC;
com_tbre : in STD_LOGIC;
com_tsre : in STD_LOGIC;
com_wrn : out STD_LOGIC;
DISP1 : inout std_logic_vector(6 downto 0) := "0111111";
DISP2 : inout std_logic_vector(6 downto 0) := "0111111";
LED : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000");
end CPU_CORE;
architecture Behavioral of CPU_CORE is
COMPONENT CLK_MODULE
Port ( CLK_IN : in STD_LOGIC;
CLK : inout STD_LOGIC
);
END COMPONENT;
COMPONENT PC_Register
Port ( PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_OR_NOT : in STD_LOGIC;
CLK : in STD_LOGIC
);
END COMPONENT;
COMPONENT MUX_2
Port ( SELEC : in STD_LOGIC;
SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_3
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_4
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_6
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_5 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_6 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (2 downto 0) := "111";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
END COMPONENT;
COMPONENT RAM1_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
DataReady: in std_logic;
WriteData: in std_logic_vector(15 downto 0);
TSRE: in std_logic;
TBRE: in std_logic;
---output
RAM1_Enable: out std_logic;
RAM1_ReadEnable: out std_logic;
RAM1_WriteEnable: out std_logic;
SPort_WriteEnable:out std_logic;
SPort_ReadEnable: out std_logic;
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT RAM2_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0);
---output
RAM2_Enable: out std_logic := '1';
RAM2_ReadEnable: out std_logic := '1';
RAM2_WriteEnable: out std_logic := '1';
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT PC_Adder
Port ( OLD_PC : in STD_LOGIC_VECTOR (15 downto 0);
NEW_PC : out STD_LOGIC_VECTOR (15 downto 0)
);
END COMPONENT;
COMPONENT IF_ID_Register
Port ( NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_PC_OR_NOT : in STD_LOGIC;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
CLK : in STD_LOGIC;
INST_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_IR_OR_NOT : in STD_LOGIC;
WRITE_IR_SRC_SELEC : in STD_LOGIC;
INST_OUT_CODE : out STD_LOGIC_VECTOR(4 downto 0);
INST_OUT_RS : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RT : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RD : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_FUNC : out STD_LOGIC_VECTOR(1 downto 0));
END COMPONENT;
COMPONENT Imm_Extend
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
rd : in STD_LOGIC_VECTOR(2 downto 0);
func : in STD_LOGIC_VECTOR(1 downto 0);
imm : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT adder
port(
pc : in STD_LOGIC_VECTOR(15 downto 0);
imm : in STD_LOGIC_VECTOR(15 downto 0);
res : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Hazard_Detector
Port ( STALL_OR_NOT_FU : in STD_LOGIC;
CUR_INST_CODE : in STD_LOGIC_VECTOR (4 downto 0);
CUR_INST_RS : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RD : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_FUNC : in STD_LOGIC_VECTOR (1 downto 0);
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_DM_VISIT_ADDR : in STD_LOGIC_VECTOR (15 downto 0);
CUR_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
CUR_DM_WRITE_DATA_SRC : in STD_LOGIC_VECTOR(1 downto 0);
JUMP_OR_NOT : in STD_LOGIC;
WRITE_PC_OR_NOT : out STD_LOGIC;
NEW_PC_SRC_SELEC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_IR_OR_NOT : out STD_LOGIC;
WRITE_IR_SRC_SELEC : out STD_LOGIC;
COMMAND_ORIGIN_OR_NOP : out STD_LOGIC;
DM_DATA_RESULT_SELEC : out STD_LOGIC;
IM_ADDR_SELEC : out STD_LOGIC;
IM_DATA_SELEC : out STD_LOGIC;
IM_READ_WRITE_SELEC : out STD_LOGIC_VECTOR(1 downto 0)
);
END COMPONENT;
COMPONENT Controller
Port ( INST_CODE : in STD_LOGIC_VECTOR(4 downto 0);
INST_RS : in STD_LOGIC_VECTOR(2 downto 0);
INST_RT : in STD_LOGIC_VECTOR(2 downto 0);
INST_RD : in STD_LOGIC_VECTOR(2 downto 0);
INST_FUNC : in STD_LOGIC_VECTOR(1 downto 0);
ALU_OP : out STD_LOGIC_VECTOR (3 downto 0);
ALU_A_SRC : out STD_LOGIC_VECTOR (2 downto 0);
ALU_B_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_REGS_DEST : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_DM_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_RA_OR_NOT : out STD_LOGIC;
WRITE_IH_OR_NOT : out STD_LOGIC;
WRITE_T_OR_NOT : out STD_LOGIC;
WRITE_SP_OR_NOT : out STD_LOGIC;
WRITE_T_SRC : out STD_LOGIC;
DATA_MEM_READ_WRITE : out STD_LOGIC_VECTOR(1 downto 0);
REGS_WRITE_OR_NOT : out STD_LOGIC;
REGS_WRITE_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT Common_Register
port(
clk : in STD_LOGIC;
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
write_flag : in STD_LOGIC;
write_reg : in STD_LOGIC_VECTOR(2 downto 0);
write_data : in STD_LOGIC_VECTOR(15 downto 0);
a : out STD_LOGIC_VECTOR(15 downto 0);
b : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Comparator
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
write_t : in STD_LOGIC;
t : in STD_LOGIC_VECTOR(15 downto 0);
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(15 downto 0);
jump : out STD_LOGIC
);
END COMPONENT;
COMPONENT ID_EXE_Register
port(
clk : in STD_LOGIC;
--cmd cmd
command_origin_or_nop : in STD_LOGIC;
--common input
in_pc : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_a : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_b : in STD_LOGIC_VECTOR(15 downto 0);
in_imm : in STD_LOGIC_VECTOR(15 downto 0);
in_rs : in STD_LOGIC_VECTOR(2 downto 0);
in_rt : in STD_LOGIC_VECTOR(2 downto 0);
in_rd : in STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
in_alu : in STD_LOGIC_VECTOR(3 downto 0);
in_a_src : in STD_LOGIC_VECTOR(2 downto 0);
in_b_src : in STD_LOGIC_VECTOR(1 downto 0);
in_reg_result : in STD_LOGIC_VECTOR(1 downto 0);
in_mem_src : in STD_LOGIC_VECTOR(1 downto 0);
in_flag_RA : in STD_LOGIC;
in_flag_IH : in STD_LOGIC;
in_flag_T : in STD_LOGIC;
in_flag_SP : in STD_LOGIC;
in_T_src : in STD_LOGIC;
--mem cmd
in_mem_cmd : in STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
in_flag_reg : in STD_LOGIC;
in_reg_src : in STD_LOGIC_VECTOR(1 downto 0);
--common output
out_pc : out STD_LOGIC_VECTOR(15 downto 0);
out_imm : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_a : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_b : out STD_LOGIC_VECTOR(15 downto 0);
--memory data
out_mem_data : out STD_LOGIC_VECTOR(15 downto 0);
--result register
out_res_reg : out STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
out_alu : out STD_LOGIC_VECTOR(3 downto 0);
out_a_src : out STD_LOGIC_VECTOR(2 downto 0);
out_b_src : out STD_LOGIC_VECTOR(1 downto 0);
out_flag_RA : out STD_LOGIC;
out_flag_IH : out STD_LOGIC;
out_flag_T : out STD_LOGIC;
out_flag_SP : out STD_LOGIC;
out_T_src : out STD_LOGIC;
--mem cmd
out_mem_cmd : out STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
out_flag_reg : out STD_LOGIC;
out_reg_src : out STD_LOGIC_VECTOR(1 downto 0);
cur_rs_num : out STD_LOGIC_VECTOR(2 downto 0);
cur_rt_num : out STD_LOGIC_VECTOR(2 downto 0)
);
END COMPONENT;
COMPONENT alu
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(15 downto 0);
op : in STD_LOGIC_VECTOR(3 downto 0);
zf : out STD_LOGIC;
sf : out STD_LOGIC;
c : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Special_Register
port(
clk : in STD_LOGIC;
T_cmd_write : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
RA_cmd_write : in STD_LOGIC;
RA_src : in STD_LOGIC_VECTOR(15 downto 0);
IH_cmd_write : in STD_LOGIC;
IH_src : in STD_LOGIC_VECTOR(15 downto 0);
SP_cmd_write : in STD_LOGIC;
SP_src : in STD_LOGIC_VECTOR(15 downto 0);
T_value : out STD_LOGIC_VECTOR(15 downto 0);
RA_value : out STD_LOGIC_VECTOR(15 downto 0);
IH_value : out STD_LOGIC_VECTOR(15 downto 0);
SP_value : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Forward_Unit
Port ( -- current instruction info, if use reg as alu src, conflict may exist
CUR_RS_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_RT_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_A_SRC_SELECT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_B_SRC_SELECT : in STD_LOGIC_VECTOR (1 downto 0);
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
-- last last instruction info, if write regs, conflict may exist
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
STALL_OR_NOT : out STD_LOGIC;
ALU_A_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0);
ALU_B_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT EXE_MEM_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_IN : in STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_OUT : out STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT MEM_WB_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
--controller, all to id/exe reg
signal alu_op_controller : std_logic_vector(3 downto 0) := ALU_NULL;
signal alu_a_src_select_controller : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_controller : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal write_regs_dest_select_controller : std_logic_vector(1 downto 0) := WRITE_REGS_DEST_RS;
signal write_dm_data_src_select_controller : std_logic_vector(1 downto 0) := WRITE_DM_DATA_SRC_Z;
signal write_ra_or_not_select_controller : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_controller : std_logic := WRITE_IH_NO;
signal write_t_or_not_select_controller : std_logic := WRITE_T_NO;
signal write_sp_or_not_select_controller : std_logic := WRITE_SP_NO;
signal write_t_src_select_controller : std_logic := T_SRC_IS_SF;
signal data_mem_read_write_select_controller : std_logic_vector(1 downto 0) := MEM_NONE;
signal regs_read_write_select_controller : std_logic := WRITE_REGS_NO;
signal regs_write_data_src_select_controller : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- hazard detector
-- to PC reg
signal write_pc_or_not_hazard_detector : std_logic := WRITE_PC_YES;
-- to PC mux
signal new_pc_src_select_hazard_detector : std_logic_vector(1 downto 0) := NEW_PC_SRC_SELEC_PC_ADD_ONE;
-- to if/id reg
signal write_ir_or_not_hazard_detector : std_logic := WRITE_IR_YES;
signal write_ir_src_select_hazard_detector : std_logic := WRITE_IR_SRC_SELEC_ORIGIN;
-- to id/exe reg
signal command_origin_or_nop_hazard_detector : std_logic := COMMAND_ORIGIN;
-- to mem/wb reg
signal dm_visit_data_result_select_hazard_detector : std_logic := DM_DATA_RESULT_DM;
-- to im
signal im_visit_data_select_hazard_detector : std_logic :=IM_DATA_Z;
signal im_visit_addr_select_hazard_detector : std_logic := IM_ADDR_PC;
signal im_read_write_select_hazard_detector : std_logic_vector(1 downto 0) := MEM_READ;
-- forward unit
-- to hazard detector
signal stall_or_not_forward_unit : std_logic := STALL_NO;
-- to alu a src mux 2
signal alu_a_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_A_SRC_SELECT_FINAL_ORIGIN;
-- to alu b src mux 2
signal alu_b_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_B_SRC_SELECT_FINAL_ORIGIN;
-- comparator
-- to hazard detector
signal jump_or_not_comparator : std_logic := JUMP_FALSE;
-- if
-- PC to IM, PC Adder
signal pc_value_pc_reg_to_im : std_logic_vector(15 downto 0) := ZERO;
-- PC Adder to if/id reg, PC mux
signal pc_value_pc_adder_to_if_id_reg : std_logic_vector(15 downto 0) := ZERO;
-- IM to if/id reg
signal inst_im_to_if_id_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- PC mux to PC
signal pc_value_pc_mux_to_pc : std_logic_vector(15 downto 0) := ZERO;
-- id
-- if/id reg to controller, imm extender, id/exe reg(rs, rt, rd),
--comparator(code), hazard detector, common regs(rs, st)
signal inst_code_if_id_reg_to_controller : std_logic_vector(4 downto 0) := NOP_INST(15 downto 11);
signal inst_rs_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(10 downto 8);
signal inst_rt_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(7 downto 5);
signal inst_rd_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(4 downto 2);
signal inst_func_if_id_reg_to_controller : std_logic_vector(1 downto 0) := NOP_INST(1 downto 0);
-- if/id reg to id/exe reg, PC IMM Adder, to special regs(RA)
signal pc_value_if_id_reg_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- imm extender to id/exe reg, PC IMM Adder
signal imm_imm_extend_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- PC IMM Adder to PC mux
signal pc_value_pc_imm_adder_to_pc_mux : std_logic_vector(15 downto 0) := ZERO;
-- common regs to id/exe reg, comparator(A), PC mux(A)
signal a_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- if/id reg to im
--signal inst_if_id_reg_to_im : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- if/id reg to forward unit
signal cur_rs_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
signal cur_rt_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
-- exe
-- id/exe reg to alu src mux 1
signal alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1 : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal a_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal imm_id_exe_reg_to_alu_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- id/exe reg to exe/mem reg
signal pc_value_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
signal write_dm_data_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
signal regs_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_id_exe_reg_to_exe_mem_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal data_mem_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := MEM_NONE;
-- id/exe reg to alu
signal alu_op_id_exe_reg_to_alu : std_logic_vector(3 downto 0) := ALU_NULL;
-- id/exe to special regs, to comparator(write t or not)
signal write_t_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_T_NO;
signal write_t_src_select_id_exe_reg_to_special_regs : std_logic := T_SRC_IS_SF;
signal write_ra_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_IH_NO;
signal write_sp_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_SP_NO;
-- constant to alu src mux 1
signal all_zeros : std_logic_vector(15 downto 0) := ZERO;
-- special regs to alu src mux 1(SP)
signal sp_reg_special_regs_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- special regs to exe/mem reg(IH)
signal ih_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- special regs to comparator(T)
signal t_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu src mux 1 to alu src mux 2
signal alu_a_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
-- alu mux 2 to alu
signal alu_a_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
-- alu to exe/mem reg
signal alu_result_alu_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu to special regs(T)
signal alu_sf_alu_to_special_regs : std_logic := '0';
signal alu_zf_alu_to_special_regs : std_logic := '0';
-- mem in exe/mem reg
-- to RAM_Visitor
signal data_mem_read_write_select_exe_mem_reg_to_dm : std_logic_vector(1 downto 0) := MEM_NONE;
-- as data memory address, to mem/wb reg
signal alu_result_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := ZERO;
-- as data memory data, to mem/wb reg
signal write_dm_data_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- to mem/wb reg
signal regs_read_write_select_exe_mem_reg_to_mem_wb_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_exe_mem_reg_to_mem_wb_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal ih_reg_exe_mem_reg_to_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
signal pc_value_exe_mem_reg_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
-- lw/sw to IM
signal im_visit_addr_im_mux_to_im : std_logic_vector(15 downto 0);
signal im_visit_data_im_mux_to_im : std_logic_vector(15 downto 0);
-- DM to mem/wb reg
signal read_dm_data_dm_to_mem_wb_reg : std_logic_vector(15 downto 0);
signal dm_visit_data_dm_mux_to_mem_wb_reg : std_logic_vector(15 downto 0);
-- wb in mem/wb reg
-- to common regs write src mux
signal ih_reg_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal alu_result_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
--alse to special regs(IH, SP)
signal dm_data_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
-- also to alu src mux 2
signal pc_value_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- to common regs
signal regs_read_write_select_mem_wb_reg_to_common_regs : std_logic := WRITE_REGS_NO;
signal write_regs_num_mem_wb_reg_to_common_regs : std_logic_vector(2 downto 0) := "ZZZ";
-- common regs write src mux to common regs
signal write_regs_data_src_mux_to_regs : std_logic_vector(15 downto 0) := ZERO;
-- not used
signal ra_reg_special_regs_to_where : std_logic_vector(15 downto 0) := ZERO;
signal watch_info : std_logic_vector(15 downto 0) := ZERO;
signal high_resist_port : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- signal write_pc_force : std_logic := '1';
-- signal write_ir_force : std_logic := '1';
-- signal write_ir_origin_force : std_logic := '0';
-- signal write_pc_add_one_force : std_logic_vector(1 downto 0) := "00";
signal led_ram_visitor_to_cpu_core : std_logic_vector(7 downto 0) := "00000000";
signal useless_pin : std_logic_vector(4 downto 0) := "11111";
signal CLK : std_logic := '1';
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
begin
Unit_CLK_MODULE : CLK_MODULE port map (
CLK_IN => CLK_IN,
CLK => CLK
);
Unit_New_PC_Src_Mux3 : MUX_3 port map (
-- PC + 1
SRC_1 => pc_value_pc_adder_to_if_id_reg,
-- PC + IMM
SRC_2 => pc_value_pc_imm_adder_to_pc_mux,
-- A reg
SRC_3 => a_reg_common_regs_to_id_exe_reg,
SELEC => new_pc_src_select_hazard_detector, --write_pc_add_one_force,--
OUTPUT => pc_value_pc_mux_to_pc
);
Unit_PC_Register : PC_Register port map (
PC_IN => pc_value_pc_mux_to_pc,
PC_OUT => pc_value_pc_reg_to_im,
WRITE_OR_NOT => write_pc_or_not_hazard_detector, --write_pc_force,--
CLK => CLK
);
Unit_PC_Adder : PC_Adder port map (
OLD_PC => pc_value_pc_reg_to_im,
NEW_PC => pc_value_pc_adder_to_if_id_reg
);
Unit_IM_Addr_Mux : MUX_2 port map(
SELEC => im_visit_addr_select_hazard_detector,
SRC_1 => pc_value_pc_reg_to_im,
SRC_2 => alu_result_exe_mem_reg_to_dm,
OUTPUT => im_visit_addr_im_mux_to_im
);
Unit_IM_Data_Mux : MUX_2 port map(
SELEC => im_visit_data_select_hazard_detector,
SRC_1 => high_resist_port,
SRC_2 => write_dm_data_exe_mem_reg_to_dm,
OUTPUT => im_visit_data_im_mux_to_im
);
Unit_RAM1_Visitor : RAM1_Visitor port map (
---input
clk => CLK,
DMemReadWrite => data_mem_read_write_select_exe_mem_reg_to_dm,
EXandMEM_AluRes => alu_result_exe_mem_reg_to_dm,
DataReady => com_data_ready,
WriteData => write_dm_data_exe_mem_reg_to_dm,
TSRE => com_tsre,
TBRE => com_tbre,
---output
RAM1_Enable => RAM1_EN,
RAM1_ReadEnable => RAM1_OE,
RAM1_WriteEnable => RAM1_WE,
SPort_WriteEnable => com_wrn,
SPort_ReadEnable => com_rdn,
DMemData => RAM1_Data,
DMemAddr => RAM1_Addr(15 downto 0)
);
Unit_RAM2_Visitor : RAM2_Visitor port map (
---input
clk => CLK,
DMemReadWrite => im_read_write_select_hazard_detector,
EXandMEM_AluRes => im_visit_addr_im_mux_to_im,
-- DataReady => useless_pin(4),
WriteData => im_visit_data_im_mux_to_im,
-- TSRE => useless_pin(3),
-- TBRE => useless_pin(2),
---output
RAM1_Enable => RAM2_EN,
RAM1_ReadEnable => RAM2_OE,
RAM1_WriteEnable => RAM2_WE,
-- SPort_WriteEnable => useless_pin(1),
-- SPort_ReadEnable => useless_pin(0),
DMemData => RAM2_Data,
DMemAddr => RAM2_Addr(15 downto 0)
);
RAM1_Addr(17 downto 16) <= "00";
RAM2_Addr(17 downto 16) <= "00";
-- LED(15 downto 8) <= led_ram_visitor_to_cpu_core;
Unit_IF_ID_Register : IF_ID_Register port map (
NEW_PC_IN => pc_value_pc_adder_to_if_id_reg,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_OUT => pc_value_if_id_reg_to_id_exe_reg,
CLK => CLK,
INST_IN => inst_im_to_if_id_reg,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector, --write_ir_force,--
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector, --write_ir_origin_force,--
INST_OUT_CODE => inst_code_if_id_reg_to_controller,
INST_OUT_RS => inst_rs_if_id_reg_to_controller,
INST_OUT_RT => inst_rt_if_id_reg_to_controller,
INST_OUT_RD => inst_rd_if_id_reg_to_controller,
INST_OUT_FUNC => inst_func_if_id_reg_to_controller
);
-- detect before id, just after INST could be read rightly
Unit_Hazard_Detector : Hazard_Detector port map (
STALL_OR_NOT_FU => stall_or_not_forward_unit,
CUR_INST_CODE => inst_code_if_id_reg_to_controller,
CUR_INST_RS => inst_rs_if_id_reg_to_controller,
CUR_INST_RT => inst_rt_if_id_reg_to_controller,
CUR_INST_RD => inst_rd_if_id_reg_to_controller,
CUR_INST_FUNC => inst_func_if_id_reg_to_controller,
-- in id/exe reg
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- in exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,
-- in exe/mem reg
LAST_LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_exe_mem_reg_to_dm,
LAST_LAST_DM_VISIT_ADDR => alu_result_exe_mem_reg_to_dm,
CUR_DM_READ_WRITE => data_mem_read_write_select_controller,
CUR_DM_WRITE_DATA_SRC => write_dm_data_src_select_controller,
JUMP_OR_NOT => jump_or_not_comparator,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_SRC_SELEC => new_pc_src_select_hazard_detector,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector,
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector,
COMMAND_ORIGIN_OR_NOP => command_origin_or_nop_hazard_detector,
DM_DATA_RESULT_SELEC => dm_visit_data_result_select_hazard_detector,
IM_ADDR_SELEC => im_visit_addr_select_hazard_detector,
IM_DATA_SELEC => im_visit_data_select_hazard_detector,
IM_READ_WRITE_SELEC => im_read_write_select_hazard_detector
);
Unit_Controller : Controller port map (
INST_CODE => inst_code_if_id_reg_to_controller,
INST_RS => inst_rs_if_id_reg_to_controller,
INST_RT => inst_rt_if_id_reg_to_controller,
INST_RD => inst_rd_if_id_reg_to_controller,
INST_FUNC => inst_func_if_id_reg_to_controller,
ALU_OP => alu_op_controller,
ALU_A_SRC => alu_a_src_select_controller,
ALU_B_SRC => alu_b_src_select_controller,
WRITE_REGS_DEST => write_regs_dest_select_controller,
WRITE_DM_DATA_SRC => write_dm_data_src_select_controller,
WRITE_RA_OR_NOT => write_ra_or_not_select_controller,
WRITE_IH_OR_NOT => write_ih_or_not_select_controller,
WRITE_T_OR_NOT => write_t_or_not_select_controller,
WRITE_SP_OR_NOT => write_sp_or_not_select_controller,
WRITE_T_SRC => write_t_src_select_controller,
DATA_MEM_READ_WRITE => data_mem_read_write_select_controller,
REGS_WRITE_OR_NOT => regs_read_write_select_controller,
REGS_WRITE_DATA_SRC => regs_write_data_src_select_controller
);
Unit_Imm_Extend : Imm_Extend port map (
code => inst_code_if_id_reg_to_controller,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
rd => inst_rd_if_id_reg_to_controller,
func => inst_func_if_id_reg_to_controller,
imm => imm_imm_extend_to_id_exe_reg
);
Unit_adder : adder port map (
pc => pc_value_if_id_reg_to_id_exe_reg,
imm => imm_imm_extend_to_id_exe_reg,
res => pc_value_pc_imm_adder_to_pc_mux
);
Unit_Common_regs_write_src_Mux4 : MUX_4 port map (
-- ALU result
SRC_1 => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
-- DM data
SRC_2 => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
-- IH
SRC_3 => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
-- PC
SRC_4 => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
SELEC => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux,
OUTPUT => write_regs_data_src_mux_to_regs
);
Unit_Common_Register : Common_Register port map (
clk => CLK,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
write_flag => regs_read_write_select_mem_wb_reg_to_common_regs,
write_reg => write_regs_num_mem_wb_reg_to_common_regs,
write_data => write_regs_data_src_mux_to_regs,
a => a_reg_common_regs_to_id_exe_reg,
b => b_reg_common_regs_to_id_exe_reg
);
Unit_Comparator : Comparator port map (
code => inst_code_if_id_reg_to_controller,
write_t => write_t_or_not_select_id_exe_reg_to_special_regs,
t => t_reg_special_regs_to_exe_mem_reg,
-- could not be given as one value
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
a => a_reg_common_regs_to_id_exe_reg,
jump => jump_or_not_comparator
);
Unit_ID_EXE_Register : ID_EXE_Register port map (
clk => CLK,
--cmd cmd
command_origin_or_nop => command_origin_or_nop_hazard_detector,
--common input
in_pc => pc_value_if_id_reg_to_id_exe_reg,
in_reg_a => a_reg_common_regs_to_id_exe_reg,
in_reg_b => b_reg_common_regs_to_id_exe_reg,
in_imm => imm_imm_extend_to_id_exe_reg,
in_rs => inst_rs_if_id_reg_to_controller,
in_rt => inst_rt_if_id_reg_to_controller,
in_rd => inst_rd_if_id_reg_to_controller,
--exe cmd
in_alu => alu_op_controller,
in_a_src => alu_a_src_select_controller,
in_b_src => alu_b_src_select_controller,
in_reg_result => write_regs_dest_select_controller,
in_mem_src => write_dm_data_src_select_controller,
in_flag_RA => write_ra_or_not_select_controller,
in_flag_IH => write_ih_or_not_select_controller,
in_flag_T => write_t_or_not_select_controller,
in_flag_SP => write_sp_or_not_select_controller,
in_T_src => write_t_src_select_controller,
--mem cmd
in_mem_cmd => data_mem_read_write_select_controller,
--wb cmd
in_flag_reg => regs_read_write_select_controller,
in_reg_src => regs_write_data_src_select_controller,
--common output
out_pc => pc_value_id_exe_reg_to_exe_mem_reg,
out_imm => imm_id_exe_reg_to_alu_src_mux_1,
out_reg_a => a_reg_id_exe_reg_to_alu_a_src_mux_1,
out_reg_b => b_reg_id_exe_reg_to_alu_a_src_mux_1,
--memory data
out_mem_data => write_dm_data_id_exe_reg_to_exe_mem_reg,
--result register
out_res_reg => write_regs_num_id_exe_reg_to_exe_mem_reg,
--exe cmd
out_alu => alu_op_id_exe_reg_to_alu,
out_a_src => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
out_b_src => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
out_flag_RA => write_ra_or_not_select_id_exe_reg_to_special_regs,
out_flag_IH => write_ih_or_not_select_id_exe_reg_to_special_regs,
out_flag_T => write_t_or_not_select_id_exe_reg_to_special_regs,
out_flag_SP => write_sp_or_not_select_id_exe_reg_to_special_regs,
out_T_src => write_t_src_select_id_exe_reg_to_special_regs,
--mem cmd
out_mem_cmd => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
--wb cmd
out_flag_reg => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
out_reg_src => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
cur_rs_num => cur_rs_num_if_id_reg_to_forward_unit,
cur_rt_num => cur_rt_num_if_id_reg_to_forward_unit
);
all_zeros <= ZERO;
Unit_ALU_A_Src_Select1_Mux6 : MUX_6 port map (
-- A
SRC_1 => a_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
-- SP
SRC_4 => sp_reg_special_regs_to_alu_a_src_mux_1,
-- PC
SRC_5 => pc_value_id_exe_reg_to_exe_mem_reg,
-- IH
SRC_6 => ih_reg_special_regs_to_exe_mem_reg,
SELEC => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
OUTPUT => alu_a_src_value_mux1_to_mux2
);
Unit_ALU_B_Src_Select1_Mux3 : MUX_3 port map (
-- B
SRC_1 => b_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
SELEC => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
OUTPUT => alu_b_src_value_mux1_to_mux2
);
Unit_ALU_A_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_a_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_a_src_select_final_forward_unit,
OUTPUT => alu_a_src_alu_mux2_to_alu
);
Unit_ALU_B_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_b_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_b_src_select_final_forward_unit,
OUTPUT => alu_b_src_alu_mux2_to_alu
);
Unit_ALU : alu port map (
a => alu_a_src_alu_mux2_to_alu,
b => alu_b_src_alu_mux2_to_alu,
op => alu_op_id_exe_reg_to_alu,
zf => alu_zf_alu_to_special_regs,
sf => alu_sf_alu_to_special_regs,
c => alu_result_alu_to_exe_mem_reg
);
Unit_Special_Register : Special_Register port map (
clk => CLK,
T_cmd_write => write_t_or_not_select_id_exe_reg_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
-- from controller, id/exe reg is too late
RA_cmd_write => write_ra_or_not_select_controller,
RA_src => pc_value_if_id_reg_to_id_exe_reg,
IH_cmd_write => write_ih_or_not_select_id_exe_reg_to_special_regs,
IH_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
SP_cmd_write => write_sp_or_not_select_id_exe_reg_to_special_regs,
SP_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
T_value => t_reg_special_regs_to_exe_mem_reg,
RA_value => ra_reg_special_regs_to_where,
IH_value => ih_reg_special_regs_to_exe_mem_reg,
SP_value => sp_reg_special_regs_to_alu_a_src_mux_1
);
-- judge before update id/exe reg, to stop next inst get in
Unit_Forward_Unit : Forward_Unit port map (
-- current instruction info, if use reg as alu src, conflict may exist
-- get from if/id reg
-- detect early, stop early
CUR_RS_REG_NUM => cur_rs_num_if_id_reg_to_forward_unit,--inst_rs_if_id_reg_to_controller,
CUR_RT_REG_NUM => cur_rt_num_if_id_reg_to_forward_unit,--inst_rt_if_id_reg_to_controller,
-- get it from controller, from id/exe reg is too late
CUR_ALU_A_SRC_SELECT => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,--alu_a_src_select_controller,
CUR_ALU_B_SRC_SELECT => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,--alu_b_src_select_controller,
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
-- from id/exe reg
--
--
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,--regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,--write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_DM_READ_WRITE => data_mem_read_write_select_exe_mem_reg_to_dm,--data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- last last instruction info, if write regs, conflict may exist
-- from exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_mem_wb_reg_to_common_regs, --regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_mem_wb_reg_to_common_regs, --write_regs_num_exe_mem_reg_to_mem_wb_reg,
STALL_OR_NOT => stall_or_not_forward_unit,
ALU_A_SRC_SELECT_FINAL => alu_a_src_select_final_forward_unit,
ALU_B_SRC_SELECT_FINAL => alu_b_src_select_final_forward_unit
);
Unit_EXE_MEM_Register : EXE_MEM_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_id_exe_reg_to_exe_mem_reg,
WRITE_DM_DATA_IN => write_dm_data_id_exe_reg_to_exe_mem_reg,
WRITE_REG_NUM_IN => write_regs_num_id_exe_reg_to_exe_mem_reg,
ALU_RESULT_IN => alu_result_alu_to_exe_mem_reg,
IH_REG_IN => ih_reg_special_regs_to_exe_mem_reg,
DATA_MEM_READ_WRITE_IN => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_READ_WRITE_IN => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
NEW_PC_OUT => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_DM_DATA_OUT => write_dm_data_exe_mem_reg_to_dm,
WRITE_REG_NUM_OUT => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_OUT => alu_result_exe_mem_reg_to_dm,
IH_REG_OUT => ih_reg_exe_mem_reg_to_mem_wb_reg,
DATA_MEM_READ_WRITE_OUT => data_mem_read_write_select_exe_mem_reg_to_dm,
REGS_READ_WRITE_OUT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg
);
Unit_DM_Data_Result_Mux : MUX_2 port map(
SELEC => dm_visit_data_result_select_hazard_detector,
SRC_1 => read_dm_data_dm_to_mem_wb_reg,
SRC_2 => inst_im_to_if_id_reg,
OUTPUT => dm_visit_data_dm_mux_to_mem_wb_reg
);
Unit_MEM_WB_Register : MEM_WB_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_REGS_NUM_IN => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_IN => alu_result_exe_mem_reg_to_dm,
IH_REG_IN => ih_reg_exe_mem_reg_to_mem_wb_reg,
DM_DATA_IN => dm_visit_data_dm_mux_to_mem_wb_reg,
-- cmd
REGS_READ_WRITE_IN => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg,
NEW_PC_OUT => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
WRITE_REGS_NUM_OUT => write_regs_num_mem_wb_reg_to_common_regs,
ALU_RESULT_OUT => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
IH_REG_OUT => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
DM_DATA_OUT => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
REGS_READ_WRITE_OUT => regs_read_write_select_mem_wb_reg_to_common_regs,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux
);
read_dm_data_dm_to_mem_wb_reg <= RAM1_Data;
inst_im_to_if_id_reg <= RAM2_Data;
process (CLK, inst_im_to_if_id_reg, pc_value_pc_reg_to_im, write_pc_or_not_hazard_detector, write_ir_or_not_hazard_detector)
--variable step : integer := 0;
begin
if (CLK'event and CLK = '0') then
-- IF
watch_info <= watch_info + "0000000000000001";
-- LED(15 downto 11) <= inst_code_if_id_reg_to_controller;
-- LED(10 downto 8) <= inst_rs_if_id_reg_to_controller;
-- LED(7 downto 5) <= inst_rt_if_id_reg_to_controller;
-- LED(4 downto 2) <= inst_rd_if_id_reg_to_controller;
-- LED(1 downto 0) <= inst_func_if_id_reg_to_controller;
LED <= pc_value_pc_reg_to_im;
case DISP1 is
when "0111111" =>
DISP1 <= "0000110";
when "0000110" =>
DISP1 <= "1011011";
when "1011011" =>
DISP1 <= "1001111";
when "1001111" =>
DISP1 <= "1100110";
when "1100110" =>
DISP1 <= "1101101";
when "1101101" =>
DISP1 <= "1111101";
when "1111101" =>
DISP1 <= "0000111";
when "0000111" =>
DISP1 <= "1111111";
when "1111111" =>
DISP1 <= "1101111";
when "1101111" =>
DISP1 <= "0111111";
case DISP2 is
when "1101111" =>
DISP2 <= "0111111";
when "0111111" =>
DISP2 <= "0000110";
when "0000110" =>
DISP2 <= "1011011";
when "1011011" =>
DISP2 <= "1001111";
when "1001111" =>
DISP2 <= "1100110";
when "1100110" =>
DISP2 <= "1101101";
when "1101101" =>
DISP2 <= "1111101";
when "1111101" =>
DISP2 <= "0000111";
when "0000111" =>
DISP2 <= "1111111";
when "1111111" =>
DISP2 <= "1101111";
when others =>
DISP2 <= "0111111";
end case;
when others =>
DISP1 <= "0111111";
end case;
elsif (CLK = '1') then
high_resist_port <= HIGH_RESIST;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2299.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02299ent IS
END c07s02b06x00p35n01i02299ent;
ARCHITECTURE c07s02b06x00p35n01i02299arch OF c07s02b06x00p35n01i02299ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test simple user-defined physical type * integer expressions.
assert ((1 cm / 10.0) < 1 cm);
assert ((1 mm / 1000.0) < 1 mm);
assert ((1 um / 1000.0) < 1 um);
assert ((1 nm / 10.0) < 1 nm);
wait for 5 ns;
assert NOT( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***PASSED TEST: c07s02b06x00p35n01i02299"
severity NOTE;
assert ( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***FAILED TEST: c07s02b06x00p35n01i02299 - Division of an user-defined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02299arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2299.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02299ent IS
END c07s02b06x00p35n01i02299ent;
ARCHITECTURE c07s02b06x00p35n01i02299arch OF c07s02b06x00p35n01i02299ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test simple user-defined physical type * integer expressions.
assert ((1 cm / 10.0) < 1 cm);
assert ((1 mm / 1000.0) < 1 mm);
assert ((1 um / 1000.0) < 1 um);
assert ((1 nm / 10.0) < 1 nm);
wait for 5 ns;
assert NOT( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***PASSED TEST: c07s02b06x00p35n01i02299"
severity NOTE;
assert ( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***FAILED TEST: c07s02b06x00p35n01i02299 - Division of an user-defined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02299arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2299.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02299ent IS
END c07s02b06x00p35n01i02299ent;
ARCHITECTURE c07s02b06x00p35n01i02299arch OF c07s02b06x00p35n01i02299ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
-- Test simple user-defined physical type * integer expressions.
assert ((1 cm / 10.0) < 1 cm);
assert ((1 mm / 1000.0) < 1 mm);
assert ((1 um / 1000.0) < 1 um);
assert ((1 nm / 10.0) < 1 nm);
wait for 5 ns;
assert NOT( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***PASSED TEST: c07s02b06x00p35n01i02299"
severity NOTE;
assert ( ((1 cm / 10.0) < 1 cm) and
((1 mm / 1000.0) < 1 mm)and
((1 um / 1000.0) < 1 um)and
((1 nm / 10.0) < 1 nm) )
report "***FAILED TEST: c07s02b06x00p35n01i02299 - Division of an user-defined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02299arch;
|
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1<= sig2;
sig2<= sig3;
end process;
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_A is
generic(
NUM_BITS : positive := 163
);
port(
A : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
B : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c0 : in STD_LOGIC;
c1 : in STD_LOGIC;
toA : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_A is
----------------------------------------------------------------------------------------------------
signal R1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal A1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal B1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
A1 <= A when c0 = '1' else
(others => '0');
B1 <= B when c1 = '1' else
(others => '0');
R1 <= A1 xor B1;
toA <= '0'&R1(NUM_BITS downto 1);
end behave; |
-- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sinewave is
port ( clk: in std_logic;
gain: in unsigned(5 downto 0);
phase: in unsigned(7 downto 0);
waveform: in std_logic_vector(1 downto 0); -- 0: Full sine (++--), 1: Half sine (++00), 3: Full sine positive (++++), 4: Quarter sine positive (+0+0)
data_out: out integer range -128 to 127);
end sinewave;
architecture Behavioral of sinewave is
type log_sine_type is array (0 to 64) of integer range 0 to 511;
type log_gain_type is array (0 to 63) of integer range 0 to 511;
type exp_table_type is array (0 to 1023) of integer range -128 to 127;
signal log_sine : log_sine_type := (511,237,193,167,149,134,123,113,105,97,91,85,79,74,70,65,61,58,54,51,48,45,43,40,38,35,33,31,29,27,25,24,22,21,19,18,16,15,14,13,12,11,10,9,8,7,6,6,5,4,4,3,3,2,2,2,1,1,1,0,0,0,0,0,0);
signal log_gain : log_gain_type := (511,265,221,195,176,162,150,141,132,125,118,112,106,101,96,92,88,84,80,77,73,70,67,64,62,59,57,54,52,50,47,45,43,41,39,38,36,34,32,31,29,27,26,24,23,22,20,19,17,16,15,14,12,11,10,9,8,6,5,4,3,2,1,0);
signal exp_table : exp_table_type := (127,125,123,121,119,117,116,114,112,110,109,107,105,104,102,100,99,97,96,94,93,91,90,89,87,86,85,83,82,81,79,78,77,76,75,74,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,55,54,53,52,51,51,50,49,48,47,47,46,45,45,44,43,43,42,41,41,40,39,39,38,38,37,36,36,35,35,34,34,33,33,32,32,31,31,30,30,29,29,28,28,27,27,27,26,26,25,25,25,24,24,23,23,23,22,22,22,21,21,21,20,20,20,19,19,19,19,18,18,18,17,17,17,17,16,16,16,16,15,15,15,15,14,14,14,14,14,13,13,13,13,13,12,12,12,12,12,11,11,11,11,11,11,10,10,10,10,10,10,9,9,9,9,9,9,9,9,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,7,6,6,6,6,6,6,6,6,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
begin
process(clk)
begin
if (rising_edge(clk)) then
if (phase <= 64) then
data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(to_integer(phase)));
elsif (phase > 64 and phase <= 128) then
if (waveform = "00" or waveform = "01" or waveform = "10") then
data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(64 - (to_integer(phase) - 64)));
else
data_out <= 0;
end if;
elsif (phase > 128 and phase <= 192) then
if (waveform = "00") then
data_out <= -exp_table(log_gain(to_integer(gain)) + log_sine(to_integer(phase) - 128));
elsif (waveform = "10" or waveform = "11") then
data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(to_integer(phase) - 128));
else
data_out <= 0;
end if;
else -- phase > 192 and phase < 256
if (waveform = "00") then
data_out <= -exp_table(log_gain(to_integer(gain)) + log_sine(64 - (to_integer(phase) - 192)));
elsif (waveform = "10") then
data_out <= exp_table(log_gain(to_integer(gain)) + log_sine(64 - (to_integer(phase) - 192)));
else
data_out <= 0;
end if;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity fulladdr is
port(a, b, c_in : in std_logic;
sum, c_out : out std_logic);
end entity fulladdr;
architecture arch_fulladdr_v1 of fulladdr is
begin
sum <= a xor b xor c_in;
c_out <= (a and b) or (a and c_in) or (b and c_in);
end architecture arch_fulladdr_v1;
architecture arch_fulladdr_v2 of fulladdr is
component halfaddr is
port(a, b : in std_logic;
sum, c_out : out std_logic);
end component halfaddr;
signal temp1 : std_logic;
signal temp2 : std_logic;
signal temp3 : std_logic;
begin
h1 : halfaddr port map(a, b, temp1, temp2);
h2 : halfaddr port map(temp1, c_in, sum, temp3);
c_out <= temp3 or temp2;
end architecture arch_fulladdr_v2;
|
--
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.cryptopan.all;
entity aes_encrypt_unit is
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic
);
end aes_encrypt_unit;
architecture rtl of aes_encrypt_unit is
component round_unit
generic (
do_mixcolumns : boolean);
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
load_en : in std_logic;
load_data : in std_logic_vector(31 downto 0);
load_clk : in std_logic;
clk : in std_logic;
reset : in std_logic);
end component;
component dual_bram_256x8
port (
addra : IN std_logic_VECTOR(7 downto 0);
addrb : IN std_logic_VECTOR(7 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
douta : OUT std_logic_VECTOR(7 downto 0);
doutb : OUT std_logic_VECTOR(7 downto 0));
end component;
component sbox
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
end component;
signal cipher_key : s_vector;
signal input : s_vector;
type states is (INIT, KEY_EXP_INIT, KEY_EXP, LOADED);
signal state : states;
signal key_exp_counter : std_logic_vector(1 downto 0);
--signal round_onehot_counter : std_logic_vector(9 downto 0);
signal round_shift_counter : std_logic_vector(9 downto 0);
signal rcon : std_logic_vector(7 downto 0);
signal subword : std_logic_vector(31 downto 0);
signal subword_xor_rcon : std_logic_vector(31 downto 0);
signal cur_w : std_logic_vector(31 downto 0);
signal cur_w_rot : std_logic_vector(31 downto 0);
signal w0 : std_logic_vector(31 downto 0);
signal w1 : std_logic_vector(31 downto 0);
signal w2 : std_logic_vector(31 downto 0);
signal load_bit : std_logic;
type s_vector_array is array (0 to 10) of s_vector;
signal round_bytes : s_vector_array;
signal round_en : std_logic_vector(0 to 10);
signal round_load_en : std_logic_vector(0 to 9);
signal sbox_clk : std_logic;
signal slow_clk : std_logic;
signal clk_counter : std_logic_vector(1 downto 0);
signal key_wren_int : std_logic;
signal key_wren_counter : std_logic_vector(2 downto 0);
begin -- rtl
SLOWCLK_LOGIC: process (clk, reset)
begin
if reset = '1' then
clk_counter <= (others => '0');
elsif clk'event and clk = '1' then
clk_counter <= clk_counter + 1;
end if;
end process SLOWCLK_LOGIC;
slow_clk <= clk_counter(1);
sbox_clk <= not slow_clk;
cur_w_rot <= cur_w(23 downto 0) & cur_w(31 downto 24);
subword_xor_rcon <= (rcon xor subword(31 downto 24)) & subword(23 downto 0);
GEN_BRAM: if use_bram=true generate
GEN_SBOX_BRAM: for i in 0 to 1 generate
SBOX_i: dual_bram_256x8
port map (
addra => cur_w_rot((8*i)+7 downto (8*i)),
addrb => cur_w_rot((8*i)+23 downto (8*i)+16),
clka => sbox_clk,
clkb => sbox_clk,
douta => subword((8*i)+7 downto (8*i)),
doutb => subword((8*i)+23 downto (8*i)+16)
);
end generate GEN_SBOX_BRAM;
end generate GEN_BRAM;
GEN_NO_BRAM: if use_bram=false generate
GEN_SBOX_NO_BRAM: for i in 0 to 3 generate
SBOX_i: sbox
port map (
clk => sbox_clk,
reset => reset,
addra => cur_w_rot((8*i)+7 downto (8*i)),
douta => subword((8*i)+7 downto (8*i)) );
end generate GEN_SBOX_NO_BRAM;
end generate GEN_NO_BRAM;
round_en(0) <= data_wren;
data_dv <= round_en(10);
data_out(127 downto 120) <= round_bytes(10)(0);
data_out(119 downto 112) <= round_bytes(10)(4);
data_out(111 downto 104) <= round_bytes(10)(8);
data_out(103 downto 96) <= round_bytes(10)(12);
data_out(95 downto 88) <= round_bytes(10)(1);
data_out(87 downto 80) <= round_bytes(10)(5);
data_out(79 downto 72) <= round_bytes(10)(9);
data_out(71 downto 64) <= round_bytes(10)(13);
data_out(63 downto 56) <= round_bytes(10)(2);
data_out(55 downto 48) <= round_bytes(10)(6);
data_out(47 downto 40) <= round_bytes(10)(10);
data_out(39 downto 32) <= round_bytes(10)(14);
data_out(31 downto 24) <= round_bytes(10)(3);
data_out(23 downto 16) <= round_bytes(10)(7);
data_out(15 downto 8) <= round_bytes(10)(11);
data_out(7 downto 0) <= round_bytes(10)(15);
input(0) <= data_in(127 downto 120);
input(4) <= data_in(119 downto 112);
input(8) <= data_in(111 downto 104);
input(12) <= data_in(103 downto 96);
input(1) <= data_in(95 downto 88);
input(5) <= data_in(87 downto 80);
input(9) <= data_in(79 downto 72);
input(13) <= data_in(71 downto 64);
input(2) <= data_in(63 downto 56);
input(6) <= data_in(55 downto 48);
input(10) <= data_in(47 downto 40);
input(14) <= data_in(39 downto 32);
input(3) <= data_in(31 downto 24);
input(7) <= data_in(23 downto 16);
input(11) <= data_in(15 downto 8);
input(15) <= data_in(7 downto 0);
FIRST_ROUND_INPUT : for i in 0 to 15 generate
round_bytes(0)(i) <= cipher_key(i) xor input(i);
end generate FIRST_ROUND_INPUT;
KEYWREN_LOGIC: process (clk, reset)
begin
if reset = '1' then
key_wren_counter <= (others => '0');
elsif clk'event and clk = '1' then
if key_wren='1' then
key_wren_counter <= "100";
elsif key_wren_counter(2)='1' then
key_wren_counter <= key_wren_counter + 1;
end if;
end if;
end process KEYWREN_LOGIC;
key_wren_int <= key_wren_counter(2);
CLKLOGIC : process (slow_clk, reset)
begin
if reset = '1' then
for i in 0 to 15 loop
cipher_key(i) <= (others => '0');
end loop;
state <= INIT;
ready <= '0';
elsif slow_clk'event and slow_clk = '1' then
if key_wren_int = '1' then
cipher_key(0) <= key_in(127 downto 120);
cipher_key(4) <= key_in(119 downto 112);
cipher_key(8) <= key_in(111 downto 104);
cipher_key(12) <= key_in(103 downto 96);
cipher_key(1) <= key_in(95 downto 88);
cipher_key(5) <= key_in(87 downto 80);
cipher_key(9) <= key_in(79 downto 72);
cipher_key(13) <= key_in(71 downto 64);
cipher_key(2) <= key_in(63 downto 56);
cipher_key(6) <= key_in(55 downto 48);
cipher_key(10) <= key_in(47 downto 40);
cipher_key(14) <= key_in(39 downto 32);
cipher_key(3) <= key_in(31 downto 24);
cipher_key(7) <= key_in(23 downto 16);
cipher_key(11) <= key_in(15 downto 8);
cipher_key(15) <= key_in(7 downto 0);
state <= KEY_EXP_INIT;
end if;
if state = KEY_EXP_INIT then
state <= KEY_EXP;
end if;
if state = KEY_EXP then
if round_shift_counter(9) = '1' and key_exp_counter = "11" then
state <= LOADED;
end if;
end if;
if state = LOADED then
ready <= '1';
else
ready <= '0';
end if;
end if;
end process CLKLOGIC;
with round_shift_counter select
rcon <=
X"02" when "0000000010",
X"04" when "0000000100",
X"08" when "0000001000",
X"10" when "0000010000",
X"20" when "0000100000",
X"40" when "0001000000",
X"80" when "0010000000",
X"1b" when "0100000000",
X"36" when "1000000000",
X"01" when others;
with state select
load_bit <=
'1' when KEY_EXP,
'0' when others;
ROUNTER_CNT_LOGIC : process (slow_clk, reset)
begin
if reset = '1' then
key_exp_counter <= (others => '0');
--round_onehot_counter <= "0000000001";
round_shift_counter <= "0000000001";
w0 <= (others => '0');
w1 <= (others => '0');
w2 <= (others => '0');
cur_w <= (others => '0');
elsif slow_clk'event and slow_clk = '1' then
if key_wren_int = '1' then
w0 <= key_in(127 downto 96);
w1 <= key_in(95 downto 64);
w2 <= key_in(63 downto 32);
cur_w <= key_in(31 downto 0);
elsif state = KEY_EXP then
w0 <= w1;
w1 <= w2;
w2 <= cur_w;
if key_exp_counter = "00" then
cur_w <= subword_xor_rcon xor w0;
else
cur_w <= cur_w xor w0;
end if;
key_exp_counter <= key_exp_counter + 1;
if key_exp_counter = "11" then
round_shift_counter <= round_shift_counter(8 downto 0) & round_shift_counter(9);
end if;
end if;
end if;
end process ROUNTER_CNT_LOGIC;
ROUND_GEN : for i in 0 to 8 generate
ROUND_I : round_unit
generic map (
do_mixcolumns => true )
port map (
bytes_in => round_bytes(i),
bytes_out => round_bytes(i+1),
in_en => round_en(i),
out_en => round_en(i+1),
load_en => round_load_en(i),
load_data => cur_w,
load_clk => slow_clk,
clk => clk,
reset => reset);
end generate ROUND_GEN;
ROUND9 : round_unit
generic map (
do_mixcolumns => false)
port map (
bytes_in => round_bytes(9),
bytes_out => round_bytes(10),
in_en => round_en(9),
out_en => round_en(10),
load_en => round_load_en(9),
load_data => cur_w,
load_clk => slow_clk,
clk => clk,
reset => reset);
LOAD_EN_DELAY : process (slow_clk, reset)
begin
if reset = '1' then
round_load_en <= (others => '0');
elsif slow_clk'event and slow_clk = '1' then
for i in 0 to 9 loop
round_load_en(i) <= round_shift_counter(i) and load_bit;
end loop;
end if;
end process LOAD_EN_DELAY;
end rtl;
|
-- add4.vhd --
-- This component is an adder with a single input
-- output is always = input + 4
-- both carries (input and output) are ignored
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add4 is
generic (
SIZE : integer := 32
);
port (
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end add4;
architecture bhe of add4 is
begin
OUT1 <= IN1+4;
end bhe;
|
-- add4.vhd --
-- This component is an adder with a single input
-- output is always = input + 4
-- both carries (input and output) are ignored
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add4 is
generic (
SIZE : integer := 32
);
port (
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end add4;
architecture bhe of add4 is
begin
OUT1 <= IN1+4;
end bhe;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
attribute mark_debug of mm2s_cmnd_wr_i : signal is "true";
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02400_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of reset name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02400_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02400_good;
architecture Behavioral of CNE_02400_good is
begin
DFF1:DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_511 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_511;
architecture augh of mul_511 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_511 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_511;
architecture augh of mul_511 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: sui
-- File: apbsui.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Simple User Interface
--
-- Single Peripheral containting the following:
-- Input:
-- Switches 0..31
-- Buttons 0..31
-- Output
-- LED 7 Segment, 4 digits non multiplexed, 32 digits in multiplexed mode
-- Single LED 0..31
-- Buzzer
-- Character LCD
--
-- Version 0: All functions are software assisted, IP Core has minimal
-- intelligence providing bit-bang access to all the connected hardware
--
--
--
--
--
--
--
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library openchip;
use openchip.sui.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbsui is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- active level for Segment LED segments
led7act : integer := 1;
-- active level for single LED's
ledact : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
suii : in sui_in_type;
suio : out sui_out_type);
end;
architecture rtl of apbsui is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBSUI, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type suiregs is record
ledreg : std_logic_vector(31 downto 0); -- Output Latch, single LEDs
led7reg : std_logic_vector(31 downto 0); -- Output Latch, 7 Seg LEDs
lcdreg : std_logic_vector(15 downto 0); -- Output Latch LCD
buzreg : std_logic_vector(0 downto 0); -- Buzzer
sw_inreg : std_logic_vector(31 downto 0); -- Switches in
btn_inreg : std_logic_vector(31 downto 0); -- Buttons in
irq : std_ulogic; -- interrupt (internal), not used
end record;
signal r, rin : suiregs;
begin
comb : process(rst, r, apbi, suii )
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : suiregs;
begin
v := r;
v.sw_inreg := suii.switch_in;
v.btn_inreg := suii.button_in;
irq := (others => '0');
--irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- read/write registers
case apbi.paddr(4 downto 2) is
when "100" =>
rdata(31 downto 0) := r.sw_inreg; -- read switches
when "101" =>
rdata(31 downto 0) := r.btn_inreg; -- read buttons
when others =>
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
v.ledreg := apbi.pwdata(31 downto 0);
when "001" =>
v.led7reg := apbi.pwdata(31 downto 0);
when "010" =>
v.lcdreg(15 downto 0) := apbi.pwdata(15 downto 0);
when "011" =>
v.buzreg(0) := apbi.pwdata(0);
when others =>
end case;
end if;
-- reset operation
if rst = '0' then
v.ledreg := (others => '0');
v.led7reg := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
suio.lcd_out <= r.lcdreg(7 downto 0);
suio.lcd_en <= r.lcdreg(11 downto 8);
suio.lcd_rs <= r.lcdreg(12);
suio.lcd_r_wn <= r.lcdreg(13);
suio.lcd_backlight <= r.lcdreg(14);
suio.lcd_oe <= r.lcdreg(15);
suio.buzzer <= r.buzreg(0);
suio.led_out <= r.ledreg;
suio.led_a_out(0) <= r.led7reg(0);
suio.led_b_out(0) <= r.led7reg(1);
suio.led_c_out(0) <= r.led7reg(2);
suio.led_d_out(0) <= r.led7reg(3);
suio.led_e_out(0) <= r.led7reg(4);
suio.led_f_out(0) <= r.led7reg(5);
suio.led_g_out(0) <= r.led7reg(6);
suio.led_dp_out(0) <= r.led7reg(7);
suio.led_a_out(1) <= r.led7reg(8);
suio.led_b_out(1) <= r.led7reg(9);
suio.led_c_out(1) <= r.led7reg(10);
suio.led_d_out(1) <= r.led7reg(11);
suio.led_e_out(1) <= r.led7reg(12);
suio.led_f_out(1) <= r.led7reg(13);
suio.led_g_out(1) <= r.led7reg(14);
suio.led_dp_out(1) <= r.led7reg(15);
suio.led_a_out(2) <= r.led7reg(16);
suio.led_b_out(2) <= r.led7reg(17);
suio.led_c_out(2) <= r.led7reg(18);
suio.led_d_out(2) <= r.led7reg(19);
suio.led_e_out(2) <= r.led7reg(20);
suio.led_f_out(2) <= r.led7reg(21);
suio.led_g_out(2) <= r.led7reg(22);
suio.led_dp_out(2) <= r.led7reg(23);
suio.led_a_out(3) <= r.led7reg(24);
suio.led_b_out(3) <= r.led7reg(25);
suio.led_c_out(3) <= r.led7reg(26);
suio.led_d_out(3) <= r.led7reg(27);
suio.led_e_out(3) <= r.led7reg(28);
suio.led_f_out(3) <= r.led7reg(29);
suio.led_g_out(3) <= r.led7reg(30);
suio.led_dp_out(3) <= r.led7reg(31);
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbsui" & tost(pindex) &
": SUI rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: sui
-- File: apbsui.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Simple User Interface
--
-- Single Peripheral containting the following:
-- Input:
-- Switches 0..31
-- Buttons 0..31
-- Output
-- LED 7 Segment, 4 digits non multiplexed, 32 digits in multiplexed mode
-- Single LED 0..31
-- Buzzer
-- Character LCD
--
-- Version 0: All functions are software assisted, IP Core has minimal
-- intelligence providing bit-bang access to all the connected hardware
--
--
--
--
--
--
--
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library openchip;
use openchip.sui.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbsui is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- active level for Segment LED segments
led7act : integer := 1;
-- active level for single LED's
ledact : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
suii : in sui_in_type;
suio : out sui_out_type);
end;
architecture rtl of apbsui is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBSUI, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type suiregs is record
ledreg : std_logic_vector(31 downto 0); -- Output Latch, single LEDs
led7reg : std_logic_vector(31 downto 0); -- Output Latch, 7 Seg LEDs
lcdreg : std_logic_vector(15 downto 0); -- Output Latch LCD
buzreg : std_logic_vector(0 downto 0); -- Buzzer
sw_inreg : std_logic_vector(31 downto 0); -- Switches in
btn_inreg : std_logic_vector(31 downto 0); -- Buttons in
irq : std_ulogic; -- interrupt (internal), not used
end record;
signal r, rin : suiregs;
begin
comb : process(rst, r, apbi, suii )
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : suiregs;
begin
v := r;
v.sw_inreg := suii.switch_in;
v.btn_inreg := suii.button_in;
irq := (others => '0');
--irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- read/write registers
case apbi.paddr(4 downto 2) is
when "100" =>
rdata(31 downto 0) := r.sw_inreg; -- read switches
when "101" =>
rdata(31 downto 0) := r.btn_inreg; -- read buttons
when others =>
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
v.ledreg := apbi.pwdata(31 downto 0);
when "001" =>
v.led7reg := apbi.pwdata(31 downto 0);
when "010" =>
v.lcdreg(15 downto 0) := apbi.pwdata(15 downto 0);
when "011" =>
v.buzreg(0) := apbi.pwdata(0);
when others =>
end case;
end if;
-- reset operation
if rst = '0' then
v.ledreg := (others => '0');
v.led7reg := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
suio.lcd_out <= r.lcdreg(7 downto 0);
suio.lcd_en <= r.lcdreg(11 downto 8);
suio.lcd_rs <= r.lcdreg(12);
suio.lcd_r_wn <= r.lcdreg(13);
suio.lcd_backlight <= r.lcdreg(14);
suio.lcd_oe <= r.lcdreg(15);
suio.buzzer <= r.buzreg(0);
suio.led_out <= r.ledreg;
suio.led_a_out(0) <= r.led7reg(0);
suio.led_b_out(0) <= r.led7reg(1);
suio.led_c_out(0) <= r.led7reg(2);
suio.led_d_out(0) <= r.led7reg(3);
suio.led_e_out(0) <= r.led7reg(4);
suio.led_f_out(0) <= r.led7reg(5);
suio.led_g_out(0) <= r.led7reg(6);
suio.led_dp_out(0) <= r.led7reg(7);
suio.led_a_out(1) <= r.led7reg(8);
suio.led_b_out(1) <= r.led7reg(9);
suio.led_c_out(1) <= r.led7reg(10);
suio.led_d_out(1) <= r.led7reg(11);
suio.led_e_out(1) <= r.led7reg(12);
suio.led_f_out(1) <= r.led7reg(13);
suio.led_g_out(1) <= r.led7reg(14);
suio.led_dp_out(1) <= r.led7reg(15);
suio.led_a_out(2) <= r.led7reg(16);
suio.led_b_out(2) <= r.led7reg(17);
suio.led_c_out(2) <= r.led7reg(18);
suio.led_d_out(2) <= r.led7reg(19);
suio.led_e_out(2) <= r.led7reg(20);
suio.led_f_out(2) <= r.led7reg(21);
suio.led_g_out(2) <= r.led7reg(22);
suio.led_dp_out(2) <= r.led7reg(23);
suio.led_a_out(3) <= r.led7reg(24);
suio.led_b_out(3) <= r.led7reg(25);
suio.led_c_out(3) <= r.led7reg(26);
suio.led_d_out(3) <= r.led7reg(27);
suio.led_e_out(3) <= r.led7reg(28);
suio.led_f_out(3) <= r.led7reg(29);
suio.led_g_out(3) <= r.led7reg(30);
suio.led_dp_out(3) <= r.led7reg(31);
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbsui" & tost(pindex) &
": SUI rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: sui
-- File: apbsui.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Simple User Interface
--
-- Single Peripheral containting the following:
-- Input:
-- Switches 0..31
-- Buttons 0..31
-- Output
-- LED 7 Segment, 4 digits non multiplexed, 32 digits in multiplexed mode
-- Single LED 0..31
-- Buzzer
-- Character LCD
--
-- Version 0: All functions are software assisted, IP Core has minimal
-- intelligence providing bit-bang access to all the connected hardware
--
--
--
--
--
--
--
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library openchip;
use openchip.sui.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbsui is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- active level for Segment LED segments
led7act : integer := 1;
-- active level for single LED's
ledact : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
suii : in sui_in_type;
suio : out sui_out_type);
end;
architecture rtl of apbsui is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBSUI, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type suiregs is record
ledreg : std_logic_vector(31 downto 0); -- Output Latch, single LEDs
led7reg : std_logic_vector(31 downto 0); -- Output Latch, 7 Seg LEDs
lcdreg : std_logic_vector(15 downto 0); -- Output Latch LCD
buzreg : std_logic_vector(0 downto 0); -- Buzzer
sw_inreg : std_logic_vector(31 downto 0); -- Switches in
btn_inreg : std_logic_vector(31 downto 0); -- Buttons in
irq : std_ulogic; -- interrupt (internal), not used
end record;
signal r, rin : suiregs;
begin
comb : process(rst, r, apbi, suii )
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable v : suiregs;
begin
v := r;
v.sw_inreg := suii.switch_in;
v.btn_inreg := suii.button_in;
irq := (others => '0');
--irq(pirq) := r.irq;
v.irq := '0';
rdata := (others => '0');
-- read/write registers
case apbi.paddr(4 downto 2) is
when "100" =>
rdata(31 downto 0) := r.sw_inreg; -- read switches
when "101" =>
rdata(31 downto 0) := r.btn_inreg; -- read buttons
when others =>
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
v.ledreg := apbi.pwdata(31 downto 0);
when "001" =>
v.led7reg := apbi.pwdata(31 downto 0);
when "010" =>
v.lcdreg(15 downto 0) := apbi.pwdata(15 downto 0);
when "011" =>
v.buzreg(0) := apbi.pwdata(0);
when others =>
end case;
end if;
-- reset operation
if rst = '0' then
v.ledreg := (others => '0');
v.led7reg := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
suio.lcd_out <= r.lcdreg(7 downto 0);
suio.lcd_en <= r.lcdreg(11 downto 8);
suio.lcd_rs <= r.lcdreg(12);
suio.lcd_r_wn <= r.lcdreg(13);
suio.lcd_backlight <= r.lcdreg(14);
suio.lcd_oe <= r.lcdreg(15);
suio.buzzer <= r.buzreg(0);
suio.led_out <= r.ledreg;
suio.led_a_out(0) <= r.led7reg(0);
suio.led_b_out(0) <= r.led7reg(1);
suio.led_c_out(0) <= r.led7reg(2);
suio.led_d_out(0) <= r.led7reg(3);
suio.led_e_out(0) <= r.led7reg(4);
suio.led_f_out(0) <= r.led7reg(5);
suio.led_g_out(0) <= r.led7reg(6);
suio.led_dp_out(0) <= r.led7reg(7);
suio.led_a_out(1) <= r.led7reg(8);
suio.led_b_out(1) <= r.led7reg(9);
suio.led_c_out(1) <= r.led7reg(10);
suio.led_d_out(1) <= r.led7reg(11);
suio.led_e_out(1) <= r.led7reg(12);
suio.led_f_out(1) <= r.led7reg(13);
suio.led_g_out(1) <= r.led7reg(14);
suio.led_dp_out(1) <= r.led7reg(15);
suio.led_a_out(2) <= r.led7reg(16);
suio.led_b_out(2) <= r.led7reg(17);
suio.led_c_out(2) <= r.led7reg(18);
suio.led_d_out(2) <= r.led7reg(19);
suio.led_e_out(2) <= r.led7reg(20);
suio.led_f_out(2) <= r.led7reg(21);
suio.led_g_out(2) <= r.led7reg(22);
suio.led_dp_out(2) <= r.led7reg(23);
suio.led_a_out(3) <= r.led7reg(24);
suio.led_b_out(3) <= r.led7reg(25);
suio.led_c_out(3) <= r.led7reg(26);
suio.led_d_out(3) <= r.led7reg(27);
suio.led_e_out(3) <= r.led7reg(28);
suio.led_f_out(3) <= r.led7reg(29);
suio.led_g_out(3) <= r.led7reg(30);
suio.led_dp_out(3) <= r.led7reg(31);
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbsui" & tost(pindex) &
": SUI rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package desilog is
subtype u8 is unsigned( 7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype u32 is unsigned(31 downto 0);
subtype u64 is unsigned(63 downto 0);
subtype u2 is unsigned( 1 downto 0);
subtype u4 is unsigned( 3 downto 0);
type string_ptr is access string;
function str(a : std_ulogic) return string;
function str(a : unsigned) return string;
function str(a : integer) return string;
function dg_boolToBit(bval : boolean) return std_ulogic;
end package;
package body desilog is
function dg_boolToBit(bval : boolean) return std_ulogic is begin
if bval then
return '1';
else
return '0';
end if;
end function;
function str(a : std_ulogic) return string is
begin
if a = '1' then
return "1";
elsif a = '0' then
return "0";
end if;
return "X";
end function;
function str(a : unsigned) return string is
variable res : string_ptr;
-- pragma translate_off
variable c : character;
variable len,j : integer;
variable dd : unsigned(3 downto 0);
-- pragma translate_on
begin
-- pragma translate_off
len := (a'length+3)/4;
res := new string(1 to len);
for i in 1 to len loop
j := (len - i)*4;
if (j+3 < a'length) then
dd := a(j+3+a'right downto j+a'right);
else
dd := "0000";
dd(a'left-j downto 0) := a(a'left downto j);
end if;
case dd is
when X"0" => c := '0'; when X"1" => c := '1'; when X"2" => c := '2'; when X"3" => c := '3';
when X"4" => c := '4'; when X"5" => c := '5'; when X"6" => c := '6'; when X"7" => c := '7';
when X"8" => c := '8'; when X"9" => c := '9'; when X"A" => c := 'A'; when X"B" => c := 'B';
when X"C" => c := 'C'; when X"D" => c := 'D'; when X"E" => c := 'E'; when X"F" => c := 'F';
when others => c := 'X';
end case;
res.all(i) := c;
end loop;
return res.all;
-- pragma translate_on
return "stupid xilinx ise";
end function;
function str(a : integer) return string is
begin
return str(to_unsigned(a,32));
end function;
end;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package desilog is
subtype u8 is unsigned( 7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype u32 is unsigned(31 downto 0);
subtype u64 is unsigned(63 downto 0);
subtype u2 is unsigned( 1 downto 0);
subtype u4 is unsigned( 3 downto 0);
type string_ptr is access string;
function str(a : std_ulogic) return string;
function str(a : unsigned) return string;
function str(a : integer) return string;
function dg_boolToBit(bval : boolean) return std_ulogic;
end package;
package body desilog is
function dg_boolToBit(bval : boolean) return std_ulogic is begin
if bval then
return '1';
else
return '0';
end if;
end function;
function str(a : std_ulogic) return string is
begin
if a = '1' then
return "1";
elsif a = '0' then
return "0";
end if;
return "X";
end function;
function str(a : unsigned) return string is
variable res : string_ptr;
-- pragma translate_off
variable c : character;
variable len,j : integer;
variable dd : unsigned(3 downto 0);
-- pragma translate_on
begin
-- pragma translate_off
len := (a'length+3)/4;
res := new string(1 to len);
for i in 1 to len loop
j := (len - i)*4;
if (j+3 < a'length) then
dd := a(j+3+a'right downto j+a'right);
else
dd := "0000";
dd(a'left-j downto 0) := a(a'left downto j);
end if;
case dd is
when X"0" => c := '0'; when X"1" => c := '1'; when X"2" => c := '2'; when X"3" => c := '3';
when X"4" => c := '4'; when X"5" => c := '5'; when X"6" => c := '6'; when X"7" => c := '7';
when X"8" => c := '8'; when X"9" => c := '9'; when X"A" => c := 'A'; when X"B" => c := 'B';
when X"C" => c := 'C'; when X"D" => c := 'D'; when X"E" => c := 'E'; when X"F" => c := 'F';
when others => c := 'X';
end case;
res.all(i) := c;
end loop;
return res.all;
-- pragma translate_on
return "stupid xilinx ise";
end function;
function str(a : integer) return string is
begin
return str(to_unsigned(a,32));
end function;
end;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package desilog is
subtype u8 is unsigned( 7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype u32 is unsigned(31 downto 0);
subtype u64 is unsigned(63 downto 0);
subtype u2 is unsigned( 1 downto 0);
subtype u4 is unsigned( 3 downto 0);
type string_ptr is access string;
function str(a : std_ulogic) return string;
function str(a : unsigned) return string;
function str(a : integer) return string;
function dg_boolToBit(bval : boolean) return std_ulogic;
end package;
package body desilog is
function dg_boolToBit(bval : boolean) return std_ulogic is begin
if bval then
return '1';
else
return '0';
end if;
end function;
function str(a : std_ulogic) return string is
begin
if a = '1' then
return "1";
elsif a = '0' then
return "0";
end if;
return "X";
end function;
function str(a : unsigned) return string is
variable res : string_ptr;
-- pragma translate_off
variable c : character;
variable len,j : integer;
variable dd : unsigned(3 downto 0);
-- pragma translate_on
begin
-- pragma translate_off
len := (a'length+3)/4;
res := new string(1 to len);
for i in 1 to len loop
j := (len - i)*4;
if (j+3 < a'length) then
dd := a(j+3+a'right downto j+a'right);
else
dd := "0000";
dd(a'left-j downto 0) := a(a'left downto j);
end if;
case dd is
when X"0" => c := '0'; when X"1" => c := '1'; when X"2" => c := '2'; when X"3" => c := '3';
when X"4" => c := '4'; when X"5" => c := '5'; when X"6" => c := '6'; when X"7" => c := '7';
when X"8" => c := '8'; when X"9" => c := '9'; when X"A" => c := 'A'; when X"B" => c := 'B';
when X"C" => c := 'C'; when X"D" => c := 'D'; when X"E" => c := 'E'; when X"F" => c := 'F';
when others => c := 'X';
end case;
res.all(i) := c;
end loop;
return res.all;
-- pragma translate_on
return "stupid xilinx ise";
end function;
function str(a : integer) return string is
begin
return str(to_unsigned(a,32));
end function;
end;
|
-- cb20_width_adapter_001.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 52;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 61;
IN_PKT_BYTE_CNT_L : integer := 59;
IN_PKT_TRANS_COMPRESSED_READ : integer := 53;
IN_PKT_BURSTWRAP_H : integer := 62;
IN_PKT_BURSTWRAP_L : integer := 62;
IN_PKT_BURST_SIZE_H : integer := 65;
IN_PKT_BURST_SIZE_L : integer := 63;
IN_PKT_RESPONSE_STATUS_H : integer := 87;
IN_PKT_RESPONSE_STATUS_L : integer := 86;
IN_PKT_TRANS_EXCLUSIVE : integer := 58;
IN_PKT_BURST_TYPE_H : integer := 67;
IN_PKT_BURST_TYPE_L : integer := 66;
IN_ST_DATA_W : integer := 88;
OUT_PKT_ADDR_H : integer := 34;
OUT_PKT_ADDR_L : integer := 18;
OUT_PKT_DATA_H : integer := 15;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 17;
OUT_PKT_BYTEEN_L : integer := 16;
OUT_PKT_BYTE_CNT_H : integer := 43;
OUT_PKT_BYTE_CNT_L : integer := 41;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 35;
OUT_PKT_BURST_SIZE_H : integer := 47;
OUT_PKT_BURST_SIZE_L : integer := 45;
OUT_PKT_RESPONSE_STATUS_H : integer := 69;
OUT_PKT_RESPONSE_STATUS_L : integer := 68;
OUT_PKT_TRANS_EXCLUSIVE : integer := 40;
OUT_PKT_BURST_TYPE_H : integer := 49;
OUT_PKT_BURST_TYPE_L : integer := 48;
OUT_ST_DATA_W : integer := 70;
ST_CHANNEL_W : integer := 7;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(6 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(87 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(69 downto 0); -- .data
out_channel : out std_logic_vector(6 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter_001;
architecture rtl of cb20_width_adapter_001 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(6 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_001 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter_001
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:07:44 06/06/2016
-- Design Name:
-- Module Name: SumadorIP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SumadorIP is
Port ( ip_sal : in STD_LOGIC_VECTOR (11 downto 0);
mux_sum_ip_sal : in STD_LOGIC_VECTOR (11 downto 0);
sum_sal : out STD_LOGIC_VECTOR (11 downto 0));
end SumadorIP;
architecture Behavioral of SumadorIP is
begin
sum_sal <= ip_sal + mux_sum_ip_sal;
end Behavioral; |
-- A-B=A+B'+1
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
--define entity for adder-subtractor
ENTITY add_subb IS
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); --std_logic_vector defines array of 8 elements with indexed from 0 to 7; can use bit_vector as well
add_sub: IN STD_LOGIC;
cout: OUT STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END add_subb;
--define architecture for adder-subtractor
ARCHITECTURE structural OF add_subb IS
COMPONENT full_adder --use a single full adder to build a bigger 8-bit adder-subtractor
PORT(a, b, carry_in: IN STD_LOGIC;
carry_out, sum: OUT STD_LOGIC);
END COMPONENT;
SIGNAL carry: STD_LOGIC_VECTOR(size DOWNTO 0); --for connecting carry-out pins internally among adders
SIGNAL b_bar: STD_LOGIC_VECTOR(size-1 DOWNTO 0);
BEGIN
carry(0)<=add_sub;
cout<=add_sub XOR carry(size);
G0: FOR i IN size-1 DOWNTO 0 GENERATE --create the complete circuit
b_bar(i)<=b(i) XOR carry(0);
adder_subtractor_array: full_adder PORT MAP(a=>a(i), b=>b_bar(i), carry_in=>carry(i), carry_out=>carry(i+1), sum=>sum(i));
END GENERATE G0;
END structural; |
package fifo_pkg is
end package;
package fifo_pkg IS
end package;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16848)
`protect data_block
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`protect end_protected
|
-- Single port 256-byte static RAM
entity sram is
port (
we : in std_logic := '1', -- Write enable
oe : in std_logic := '0', -- Output enable
a : in std_logic_vector(7 downto 0), -- Address
din : in std_logic_vector(7 downto 0), -- Data in
dout : out std_logic_vector(7 downto 0), -- Data out
signal address : integer range 0 to 255;
end sram;
architecture behavioral of sram is
begin
process(oe)
if (oe == '1') then
dout <= std_logic_vector(to_unsigned(mem(address),8));
end if
end process
address <= to_integer(unsigned(a));
end behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Wed Nov 10 10:29:04 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../genwidth.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-e.vhd,v 1.2 2004/11/10 09:54:09 wig Exp $
-- $Date: 2004/11/10 09:54:09 $
-- $Log: inst_aa_e-e.vhd,v $
-- Revision 1.2 2004/11/10 09:54:09 wig
-- testcase extended
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.46 2004/08/18 10:45:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa_e
--
entity inst_aa_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_aa_e
width : integer := 8
-- End of Generated Generics for Entity inst_aa_e
);
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_aa_e
y_p_i : out std_ulogic_vector(width - 1 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end inst_aa_e;
--
-- End of Generated Entity inst_aa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- $Id: pdp11_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_bram - syn
-- Description: pdp11: BRAM based ext. memory dummy
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
-- 2008-02-17 117 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
entity pdp11_bram is -- cache
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end pdp11_bram;
architecture syn of pdp11_bram is
type regs_type is record
req_r : slbit; -- read request
req_w : slbit; -- write request
be : slv2; -- byte enables
addr : slv(AWIDTH-1 downto 1); -- address
end record regs_type;
constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
constant regs_init : regs_type := (
'0','0', -- req_r,w
(others=>'0'), -- be
addrzero -- addr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal MEM_ENB : slbit := '0';
signal MEM_WEA : slv2 := "00";
signal MEM_DOA : slv16 := (others=>'0');
begin
MEM_BYT0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(0),
WEB => R_REGS.be(0),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(7 downto 0),
DIB => MEM_DOA(7 downto 0),
DOA => MEM_DOA(7 downto 0),
DOB => open
);
MEM_BYT1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(1),
WEB => R_REGS.be(1),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(15 downto 8),
DIB => MEM_DOA(15 downto 8),
DOA => MEM_DOA(15 downto 8),
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
N_REGS.be <= EM_MREQ.be;
N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
EM_SRES.ack_r <= R_REGS.req_r;
EM_SRES.ack_w <= R_REGS.req_w;
EM_SRES.dout <= MEM_DOA;
end syn;
|
-- $Id: pdp11_bram.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_bram - syn
-- Description: pdp11: BRAM based ext. memory dummy
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
-- 2008-02-17 117 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
entity pdp11_bram is -- cache
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end pdp11_bram;
architecture syn of pdp11_bram is
type regs_type is record
req_r : slbit; -- read request
req_w : slbit; -- write request
be : slv2; -- byte enables
addr : slv(AWIDTH-1 downto 1); -- address
end record regs_type;
constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
constant regs_init : regs_type := (
'0','0', -- req_r,w
(others=>'0'), -- be
addrzero -- addr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal MEM_ENB : slbit := '0';
signal MEM_WEA : slv2 := "00";
signal MEM_DOA : slv16 := (others=>'0');
begin
MEM_BYT0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(0),
WEB => R_REGS.be(0),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(7 downto 0),
DIB => MEM_DOA(7 downto 0),
DOA => MEM_DOA(7 downto 0),
DOB => open
);
MEM_BYT1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(1),
WEB => R_REGS.be(1),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(15 downto 8),
DIB => MEM_DOA(15 downto 8),
DOA => MEM_DOA(15 downto 8),
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
N_REGS.be <= EM_MREQ.be;
N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
EM_SRES.ack_r <= R_REGS.req_r;
EM_SRES.ack_w <= R_REGS.req_w;
EM_SRES.dout <= MEM_DOA;
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbvga
-- File: vga.vhd
-- Author: Marcus Hellqvist
-- Description: VGA controller
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.charrom_package.all;
entity apbvga is
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port( rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end entity apbvga;
architecture rtl of apbvga is
type state_type is (s0,s1,s2);
constant RAM_DEPTH : integer := 12;
constant RAM_DATA_BITS : integer := 8;
constant MAX_FRAME : std_logic_vector((RAM_DEPTH-1) downto 0):= X"B90";
type ram_out_type is record
dataout2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
end record;
type vga_regs is record
video_out : std_logic_vector(23 downto 0);
hsync : std_ulogic;
vsync : std_ulogic;
csync : std_ulogic;
hcnt : std_logic_vector(9 downto 0);
vcnt : std_logic_vector(9 downto 0);
blank : std_ulogic;
linecnt : std_logic_vector(3 downto 0);
h_video_on : std_ulogic;
v_video_on : std_ulogic;
pixel : std_ulogic;
state : state_type;
rombit : std_logic_vector(2 downto 0);
romaddr : std_logic_vector(11 downto 0);
ramaddr2 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain2 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
raddr : std_logic_vector((RAM_DEPTH-1) downto 0);
tmp : std_logic_vector(RAM_DEPTH-1 downto 0);
end record;
type color_reg_type is record
bgcolor : std_logic_vector(23 downto 0);
txtcolor : std_logic_vector(23 downto 0);
end record;
type vmmu_reg_type is record
waddr : std_logic_vector((RAM_DEPTH-1) downto 0);
wstartaddr : std_logic_vector((RAM_DEPTH-1) downto 0);
ramaddr1 : std_logic_vector((RAM_DEPTH -1) downto 0);
ramdatain1 : std_logic_vector((RAM_DATA_BITS -1) downto 0);
ramenable1 : std_ulogic;
ramwrite1 : std_ulogic;
color : color_reg_type;
end record;
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_VGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant hmax : integer:= 799;
constant vmax : integer:= 524;
constant hvideo : integer:= 639;
constant vvideo : integer:= 480;
constant hfporch : integer:= 19;
constant vfporch : integer:= 11;
constant hbporch : integer:= 45;
constant vbporch : integer:= 31;
constant hsyncpulse : integer:= 96;
constant vsyncpulse : integer:= 2;
constant char_height : std_logic_vector(3 downto 0):="1100";
signal p,pin : vmmu_reg_type;
signal ramo : ram_out_type;
signal r,rin : vga_regs;
signal romdata : std_logic_vector(7 downto 0);
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
comb1: process(rst,r,p,romdata,ramo)
variable v : vga_regs;
begin
v:=r;
v.wstartaddr := p.wstartaddr;
-- horizontal counter
if r.hcnt < conv_std_logic_vector(hmax,10) then
v.hcnt := r.hcnt +1;
else
v.hcnt := (others => '0');
end if;
-- vertical counter
if (r.vcnt >= conv_std_logic_vector(vmax,10)) and (r.hcnt >= conv_std_logic_vector(hmax,10)) then
v.vcnt := (others => '0');
elsif r.hcnt = conv_std_logic_vector(hmax,10) then
v.vcnt := r.vcnt +1;
end if;
-- horizontal pixel out
if r.hcnt <= conv_std_logic_vector(hvideo,10) then
v.h_video_on := '1';
else
v.h_video_on := '0';
end if;
-- vertical pixel out
if r.vcnt <= conv_std_logic_vector(vvideo,10) then
v.v_video_on := '1';
else
v.v_video_on := '0';
end if;
-- generate hsync
if (r.hcnt <= conv_std_logic_vector((hvideo+hfporch+hsyncpulse),10)) and
(r.hcnt >= conv_std_logic_vector((hvideo+hfporch),10)) then
v.hsync := '0';
else
v.hsync := '1';
end if;
-- generate vsync
if (r.vcnt <= conv_std_logic_vector((vvideo+vfporch+vsyncpulse),10)) and
(r.vcnt >= conv_std_logic_vector((vvideo+vfporch),10)) then
v.vsync := '0';
else
v.vsync := '1';
end if;
--generate csync & blank
v.csync := not (v.hsync xor v.vsync);
v.blank := v.h_video_on and v.v_video_on;
-- count line of character
if v.hcnt = conv_std_logic_vector(hvideo,10) then
if (r.linecnt = char_height) or (v.vcnt = conv_std_logic_vector(vmax,10)) then
v.linecnt := (others => '0');
else
v.linecnt := r.linecnt +1;
end if;
end if;
if v.blank = '1' then
case r.state is
when s0 => v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
v.state := s1;
when s1 => v.romaddr := v.linecnt & ramo.dataout2;
v.state := s2;
when s2 => if r.rombit = "011" then
v.ramaddr2 := r.raddr;
v.raddr := r.raddr +1;
elsif r.rombit = "010" then
v.state := s1;
end if;
end case;
v.rombit := r.rombit - 1;
v.pixel := romdata(conv_integer(r.rombit));
end if;
-- read from same address char_height times
if v.raddr = (r.tmp + X"050") then
if (v.linecnt < char_height) then
v.raddr := r.tmp;
elsif v.raddr(11 downto 4) = X"FF" then --check for end of allowed memory(80x51)
v.raddr := (others => '0');
v.tmp := (others => '0');
else
v.tmp := r.tmp + X"050";
end if;
end if;
if v.v_video_on = '0' then
v.raddr := r.wstartaddr;
v.tmp := r.wstartaddr;
v.state := s0;
end if;
-- define pixel color
if v.pixel = '1'and v.blank = '1' then
v.video_out := p.color.txtcolor;
else
v.video_out := p.color.bgcolor;
end if;
if rst = '0' then
v.hcnt := conv_std_logic_Vector(hmax,10);
v.vcnt := conv_std_logic_Vector(vmax,10);
v.v_video_on := '0';
v.h_video_on := '0';
v.hsync := '0';
v.vsync := '0';
v.csync := '0';
v.blank := '0';
v.linecnt := (others => '0');
v.state := s0;
v.rombit := "111";
v.pixel := '0';
v.video_out := (others => '0');
v.raddr := (others => '0');
v.tmp := (others => '0');
v.ramaddr2 := (others => '0');
v.ramdatain2 := (others => '0');
end if;
-- update register
rin <= v;
-- drive outputs
vgao.hsync <= r.hsync;
vgao.vsync <= r.vsync;
vgao.comp_sync <= r.csync;
vgao.blank <= r.blank;
vgao.video_out_r <= r.video_out(23 downto 16);
vgao.video_out_g <= r.video_out(15 downto 8);
vgao.video_out_b <= r.video_out(7 downto 0);
vgao.bitdepth <= "11"; -- All data is valid
end process;
comb2: process(rst,r,p,apbi,ramo)
variable v : vmmu_reg_type;
variable rdata : std_logic_vector(31 downto 0);
begin
v := p;
v.ramenable1 := '0'; v.ramwrite1 := '0';
rdata := (others => '0');
case apbi.paddr(3 downto 2) is
when "00" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.waddr := apbi.pwdata(19 downto 8);
v.ramdatain1 := apbi.pwdata(7 downto 0);
v.ramenable1 := '1';
v.ramwrite1 := '1';
v.ramaddr1 := apbi.pwdata(19 downto 8);
end if;
when "01" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.bgcolor := apbi.pwdata(23 downto 0);
end if;
when "10" => if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
v.color.txtcolor := apbi.pwdata(23 downto 0);
end if;
when others => null;
end case;
if (p.waddr - p.wstartaddr) >= MAX_FRAME then
if p.wstartaddr(11 downto 4) = X"FA" then --last position of allowed memory
v.wstartaddr := X"000";
else
v.wstartaddr := p.wstartaddr + X"050";
end if;
end if;
if rst = '0' then
v.waddr := (others => '0');
v.wstartaddr := (others => '0');
v.color.bgcolor := (others => '0');
v.color.txtcolor := (others => '1');
end if;
--update registers
pin <= v;
--drive outputs
apbo.prdata <= rdata;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
end process;
apbo.pconfig <= pconfig;
reg : process(clk)
begin
if clk'event and clk = '1' then
p <= pin;
end if;
end process;
reg2 : process(vgaclk)
begin
if vgaclk'event and vgaclk = '1' then
r <= rin;
end if;
end process;
rom0 : charrom port map(clk=>vgaclk, addr=>r.romaddr, data=>romdata);
ram0 : syncram_2p generic map (tech => memtech, abits => RAM_DEPTH,
dbits => RAM_DATA_BITS, sepclk => 1)
port map (
rclk => vgaclk, raddress => r.ramaddr2, dataout => ramo.dataout2, renable => vcc,
wclk => clk, waddress => p.ramaddr1, datain => p.ramdatain1, write => p.ramwrite1
);
-- ram0 : syncram_dp generic map (tech => memtech, abits => RAM_DEPTH, dbits => RAM_DATA_BITS)
-- port map ( clk1 => clk, address1 => p.ramaddr1, datain1 => p.ramdatain1,
-- dataout1 => open, enable1 => p.ramenable1, write1 => p.ramwrite1,
-- clk2 => vgaclk, address2 => r.ramaddr2, datain2 => r.ramdatain2,
-- dataout2 => ramo.dataout2, enable2 => gnd, write2 => gnd);
-- pragma translate_off
bootmsg : report_version
generic map ("apbvga" & tost(pindex) & ": APB VGA module rev 0");
-- pragma translate_on
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all; -- libreria IEEE con definizione tipi standard logic
use WORK.alu_types.all; -- libreria WORK user-defined
entity NAND1 is
port (
A: in std_logic;
B: in std_logic;
Y: out std_logic
);
end NAND1;
-- Architectures
architecture STRUCTURAL of NAND1 is
begin
Y <= ( A nand B);
end STRUCTURAL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C: IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal C : std_logic:='0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
ALUOP => ALUOP,
C => C,
ALURESULT => ALURESULT
);
-- Stimulus process
stim_proc: process
begin
C<='1';
------------------SUB-------------------------------
ALUOP<="000111";
-- 5 - 28
Oper1<="00000000000000000000000000000101"; -- +5
Oper2<="00000000000000000000000000011100"; -- +28
wait for 20 ns;
-- 32 - 20
Oper1<="00000000000000000000000000100000";-- +32
Oper2<="00000000000000000000000000010100";-- +20
wait for 20 ns;
-- -45 - (+33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000100001";-- +33
wait for 20 ns;
-- -45 - (+63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000111111";-- +63
wait for 20 ns;
-- -45 - (-33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
-- -45 - (-63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-63)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-33)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
----------------SUMA----------------
ALUOP<="000110";-- 75 + 25
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- 75 + (-25)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- 75 + (-100)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-- -75 + 25
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- -75 + 100
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000001100100";-- +100
wait for 20 ns;
-- -75 + (-25)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- -75 + (-100)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-------------------OR--------------------
ALUOP<="000010";
Oper1<="11111111111111111100011110110101";
Oper2<="00000011101010001001010000001100";
wait for 20 ns;
-----------------orn---------------------
ALUOP<="000011";
wait for 20 ns;
-----------------xor-------------------
ALUOP<="000100";
wait for 20 ns;
-----------------xnor-------------------
ALUOP<="000101";
wait for 20 ns;
-----------------and-------------------
ALUOP<="000000";
wait for 20 ns;
-----------------andn-------------------
ALUOP<="000001";
wait for 20 ns;
-----------------SLL------------------
ALUOP<="001000";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRL-------------------
ALUOP<="001001";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRA----------------------
ALUOP<="001010";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------ANDcc---------------------
ALUOP<="001011";
Oper1<="00000111111000000010010000000111";
Oper2<="00000111111111000000000000000011";
wait for 20 ns;
-----------------ANDNcc--------------------
ALUOP<="001100";
Oper1<="00000000111111111000000010100000";
Oper2<="00001111111100000000000000000011";
wait for 20 ns;
-----------------ORcc----------------------
ALUOP<="001101";
Oper1<="00000001111111111100000000000000";
Oper2<="11111000000000111111110000000000";
wait for 20 ns;
-----------------ORNcc---------------------
ALUOP<="001110";
Oper1<="00000011111111100000011111000000";
Oper2<="00000000001111111111111100000000";
wait for 20 ns;
-----------------XORcc---------------------
ALUOP<="001111";
Oper1<="00001000100000000111111111100000";
Oper2<="00000001111110000110000011000000";
wait for 20 ns;
-----------------XNORcc--------------------
ALUOP<="010000";
Oper1<="00000001111111111100000000000111";
Oper2<="11110000001111100000110001000000";
wait for 20 ns;
-----------------ADDcc---------------------
ALUOP<="010001";
Oper1<="00000000000000000000000001101000";
Oper2<="00000000000000000000000000000101";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------ADDX----------------------
ALUOP<="010010";
Oper1<="00000000000000100101010000000000";
Oper2<="00000000000000000000000100000011";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------ADDXcc--------------------
ALUOP<="010011";
Oper1<="00000000000000000000000000101010";
Oper2<="00000000000000000000000000001101";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------SUBcc---------------------
ALUOP<="010100";
Oper1<="00000000000000000000000100000000";
Oper2<="00000000000000000000000000010000";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------SUBX----------------------
ALUOP<="010101";
Oper1<="00000000000000000000000000001111";
Oper2<="00000000000000000000000000001011";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------SUBXcc--------------------
ALUOP<="010110";
Oper1<="00000000000000000000000100011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------SAVE----------------------
ALUOP<="010111";
Oper1<="00000000000000000000000000011011";
Oper2<="00000000000000000000000000001100";
wait for 20 ns;
-----------------RESTORE-------------------
ALUOP<="011000";
Oper1<="00000000000000000000000000010000";
Oper2<="00000000000000000000000000000111";
wait for 20 ns;
---------------Instrucciones no definidas--------------------------
ALUOP<="111111";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000011111111";
wait;
end process;
END;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package logi_communication_pack is
component i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end component;
end logi_communication_pack;
package body logi_communication_pack is
end logi_communication_pack;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package logi_communication_pack is
component i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end component;
end logi_communication_pack;
package body logi_communication_pack is
end logi_communication_pack;
|
package globals is
signal COMMAND_FILE_ENDIAN : bit;
signal COMMAND_FILE_NAME : string(1 to 1024);
signal COMMAND_FILE_NAMELEN : integer;
signal COMMAND_FILE_TARGET : integer;
signal COMMAND_FILE_START : bit;
signal COMMAND_FILE_ACK : bit;
procedure change (signal what : out bit);
end package globals;
package body globals is
procedure change (signal what : out bit) is
begin
what <= '1';
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue420 is
end entity;
use work.globals.all;
architecture test of issue420 is
begin
check: process is
begin
assert COMMAND_FILE_ACK = '0';
assert COMMAND_FILE_NAME = (1 to 1024 => NUL);
change(COMMAND_FILE_ACK);
wait for 1 ns;
assert COMMAND_FILE_ACK = '1';
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:04:42 10/01/2013
-- Design Name:
-- Module Name: uart_top_shell - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_top_shell is
port(
rst_i : in std_logic;
clk_i : in std_logic;
rx_i : in std_logic;
tx_o : out std_logic
);
end uart_top_shell;
architecture Behavioral of uart_top_shell is
component clock_gen is
port (
rst_i : in std_logic;
clk_i : in std_logic;
ClrDiv_i : in std_logic;
TopRx : out std_logic;
TopTx : out std_logic;
Top16 : out std_logic;
Baud : in std_logic_vector(2 downto 0)
);
end component clock_gen;
component uart_receive is
port (
rst_i : in std_logic;
clk_i : in std_logic;
ClrDiv_o : out std_logic;
Top16_i : std_logic;
TopRx_i : std_logic;
Dout_o : out std_logic_vector(7 downto 0);
Recvd : out std_logic;
Rx_i : in std_logic
);
end component uart_receive;
component uart_transmit is
port (
rst_i : in std_logic;
clk_i : in std_logic;
TopTX : in std_logic;
Din_i : in std_logic_vector(7 downto 0);
Tx_o : out std_logic;
TxBusy_o: out std_logic;
LD_i : in std_logic
);
end component uart_transmit;
constant c_baud : std_logic_vector(2 downto 0) := "000";
signal s_toprx : std_logic;
signal s_toptx : std_logic;
signal s_top16 : std_logic;
signal s_dout : std_logic_vector(7 downto 0);
signal s_txbusy : std_logic;
signal s_clr_div : std_logic;
signal s_recvd : std_logic;
begin
i_clock_gen : clock_gen
port map (
rst_i => rst_i,
clk_i => clk_i,
ClrDiv_i => s_clr_div,
TopRx => s_toprx,
TopTx => s_toptx,
Top16 => s_top16,
Baud => c_baud
);
i_uart_rec : uart_receive
port map (
rst_i => rst_i,
clk_i => clk_i,
ClrDiv_o => s_clr_div,
Top16_i => s_top16,
TopRx_i => s_toprx,
Dout_o => s_dout,
Recvd => s_recvd,
Rx_i => rx_i
);
i_uart_tra : uart_transmit
port map (
rst_i => rst_i,
clk_i => clk_i,
TopTX => s_toptx,
Din_i => s_dout,
Tx_o => tx_o,
TxBusy_o => s_txbusy,
LD_i => s_recvd
);
end Behavioral;
|
-- Ram data types
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE ram_types IS
SUBTYPE ram_word IS STD_LOGIC_VECTOR(31 DOWNTO 0);
TYPE ram_data IS ARRAY(NATURAL RANGE<>) OF ram_word;
END ram_types;
-- Multiplexer data types
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE mux_types IS
SUBTYPE mux_input_data IS STD_LOGIC_VECTOR(31 DOWNTO 0);
TYPE mux_input IS ARRAY(NATURAL RANGE<>) OF mux_input_data;
END mux_types; |
-------------------------------------------------------------------------------
-- Copyright 2014 Paulino Ruiz de Clavijo Vázquez <paulino@dte.us.es>
-- This file is part of the Digilentinc-peripherals project.
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- You can get more info at http://www.dte.us.es/id2
--
--*------------------------------- End auto header, don't touch this line --*--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity port_buttons_dig is port (
r : in std_logic;
clk : in std_logic;
enable : in std_logic;
port_out : out std_logic_vector (7 downto 0);
buttons_in : in std_logic_vector (3 downto 0));
end port_buttons_dig;
architecture behavioral of port_buttons_dig is
begin
port_out(7 downto 4) <= "0000";
read_proc: process(clk)
begin
if falling_edge(clk) and enable='1' and r='1' then
port_out(3 downto 0) <= buttons_in;
end if;
end process;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.midi_pkg.all;
entity track_decoder is
generic(
max_read_bytes : integer
);
port(
ctrl : in ctrl_t;
midi_pulses : in midi_pulse_arr;
midi_pulse_acks : out midi_pulse_arr;
playing_en : in std_logic;
chunk_data : in chunk_data_t_arr;
num_chunks : in integer range 0 to max_num_tracks - 1;
-- ram read interface
read_start_addr : out unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0) := (others => '0');
read_num_bytes : out integer range 0 to max_read_bytes;
read_en : out std_logic;
read_busy : in std_logic;
midi_ram_out : in std_logic_vector((max_read_bytes * 8) - 1 downto 0);
midi_nos : out midi_note_arr_t
);
end;
architecture rtl of track_decoder is
constant read_addr_length : integer := integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1;
type internals_t is record
first_event : std_logic;
read_start_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
status : std_logic_vector(7 downto 0);
last_byte_was_status : std_logic;
unknown_midi_event : std_logic;
midi_no : midi_note_t;
volume : unsigned(7 downto 0);
delta_counter : unsigned(27 downto 0);
end record;
type internals_t_arr is array(1 to max_num_tracks - 1) of internals_t;
signal internals : internals_t_arr;
signal current_internal : internals_t;
type state_t is (
wait_en,
init_read_addrs_1,
init_read_addrs_2,
read_variable_length_1,
read_variable_length_2,
read_variable_length_3,
apply_delta_time,
wait_delta_time_and_cede_control,
wait_delta_time_and_cede_control_delay,
increment_current_internal_1,
increment_current_internal_2,
read_status_1,
read_status_2,
read_status_3,
dispatch_event,
dispatch_meta_1,
dispatch_meta_2,
skip_over_meta_event_1,
skip_over_meta_event_2,
read_note_on_1,
read_note_on_2,
read_note_on_3,
read_note_on_4,
done,
error_state
);
signal state : state_t;
signal return_state : state_t;
signal read_num_bytes_int : integer range 0 to max_read_bytes;
signal variable_length : unsigned(27 downto 0);
signal current_track : integer range 1 to max_num_tracks - 1;
signal read_busy_d1 : std_logic;
-----------------------------------------------------------------------------
-- Enumeration of known events
constant meta_event : std_logic_vector(7 downto 0) := x"FF";
constant note_on_event : std_logic_vector(3 downto 0) := x"9";
constant end_of_track : std_logic_vector(7 downto 0) := x"2F";
constant track_name : std_logic_vector(7 downto 0) := x"03";
constant prefix_port : std_logic_vector(7 downto 0) := x"21";
begin
delay_read_busy : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_busy_d1 <= read_busy;
end if;
end process;
fsm : process(ctrl.clk)
procedure increment_current_track is
begin
if current_track = num_chunks then
current_track <= 1;
else
current_track <= current_track + 1;
end if;
end;
impure function ram_read_finished return boolean is
begin
return read_busy = '0' and read_busy_d1 = '1';
end;
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
internals <= (
others => (
first_event => '1',
read_start_addr => (others => '0'),
status => (others => '0'),
last_byte_was_status => '0',
unknown_midi_event => '0',
midi_no => midi_note_t'low,
volume => (others => '0'),
delta_counter => (others => '0')
));
current_internal <= (
first_event => '1',
read_start_addr => (others => '0'),
status => (others => '0'),
last_byte_was_status => '0',
unknown_midi_event => '0',
midi_no => midi_note_t'low,
volume => (others => '0'),
delta_counter => (others => '0')
);
state <= wait_en;
return_state <= error_state;
variable_length <= (others => '0');
read_en <= '0';
current_track <= 1;
for i in 1 to max_num_tracks - 1 loop
midi_pulse_acks(i) <= '0';
end loop;
else
case state is
when wait_en =>
if playing_en = '1' then
state <= init_read_addrs_1;
end if;
when init_read_addrs_1 =>
for i in internals'range loop
internals(i).read_start_addr <= chunk_data(i).base_addr + 8;
end loop;
state <= init_read_addrs_2;
when init_read_addrs_2 =>
current_internal <= internals(current_track);
return_state <= apply_delta_time;
state <= read_variable_length_1;
when read_variable_length_1 =>
variable_length <= (others => '0');
state <= read_variable_length_2;
when read_variable_length_2 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= read_variable_length_3;
when read_variable_length_3 =>
read_en <= '0';
if ram_read_finished then
variable_length <= variable_length(variable_length'left - 7 downto 0) & unsigned(midi_ram_out(6 downto 0));
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
if midi_ram_out(7) = '1' then
state <= read_variable_length_2;
else
state <= return_state;
end if;
end if;
when apply_delta_time =>
current_internal.delta_counter <= variable_length;
state <= wait_delta_time_and_cede_control;
when wait_delta_time_and_cede_control =>
midi_pulse_acks(current_track) <= '0';
if current_internal.delta_counter = 0 then
state <= read_status_1;
elsif midi_pulses(current_track) = '1' then
current_internal.delta_counter <= current_internal.delta_counter - 1;
midi_pulse_acks(current_track) <= '1';
state <= wait_delta_time_and_cede_control_delay;
else
-- Now we are switching midi track, so we must put the current
-- track back in storage and get another one out.
internals(current_track) <= current_internal;
internals(current_track).first_event <= '0';
state <= increment_current_internal_1;
increment_current_track;
end if;
-- This state prevents the delta counters from accidentally double
-- decrementing.
when wait_delta_time_and_cede_control_delay =>
state <= wait_delta_time_and_cede_control;
when increment_current_internal_1 =>
current_internal <= internals(current_track);
state <= increment_current_internal_2;
when increment_current_internal_2 =>
if current_internal.first_event = '1' then
state <= read_variable_length_1;
return_state <= apply_delta_time;
else
state <= wait_delta_time_and_cede_control;
end if;
when read_status_1 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= read_status_2;
when read_status_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
--here we implement the running status
if midi_ram_out(7) = '1' then
current_internal.status <= midi_ram_out(7 downto 0);
current_internal.last_byte_was_status <= '1';
else
current_internal.last_byte_was_status <= '0';
end if;
state <= dispatch_event;
end if;
-- If last_byte_was_status = '1', then the last byte we read from
-- ram was a data byte, If last_byte_was_status = '0', then that
-- data byte was read and the pointer is looking at the next data
-- byte.
--
-- To remove confusion, in this state, we subtract 1 from the ram
-- read pointer to unify that situation and make sure that the read
-- pointer is at the first data byte.
when dispatch_event =>
if current_internal.last_byte_was_status = '0' then
current_internal.read_start_addr <= current_internal.read_start_addr - 1;
end if;
if current_internal.status = meta_event then
state <= dispatch_meta_1;
elsif current_internal.status(7 downto 4) = note_on_event then
state <= read_note_on_1;
else
current_internal.unknown_midi_event <= '1';
state <= error_state;
end if;
when dispatch_meta_1 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= dispatch_meta_2;
when dispatch_meta_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
if midi_ram_out(7 downto 0) = end_of_track then
state <= done;
elsif midi_ram_out(7 downto 0) = track_name or
midi_ram_out(7 downto 0) = prefix_port then
state <= skip_over_meta_event_1;
else
state <= error_state;
end if;
end if;
when skip_over_meta_event_1 =>
state <= read_variable_length_1;
return_state <= skip_over_meta_event_2;
when skip_over_meta_event_2 =>
current_internal.read_start_addr <= current_internal.read_start_addr +
resize(variable_length, read_addr_length);
state <= read_variable_length_1;
return_state <= apply_delta_time;
when read_note_on_1 =>
read_en <= '1';
read_num_bytes_int <= 2;
state <= read_note_on_2;
when read_note_on_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
current_internal.midi_no <= to_integer(unsigned(midi_ram_out(15 downto 8)));
midi_nos(current_track - 1) <= to_integer(unsigned(midi_ram_out(15 downto 8)));
current_internal.volume <= unsigned(midi_ram_out(7 downto 0));
state <= read_variable_length_1;
return_state <= apply_delta_time;
end if;
when done =>
increment_current_track;
null;
when error_state =>
null;
when others =>
null;
end case;
end if;
end if;
end process;
-- mux the read address output
read_start_addr <= current_internal.read_start_addr;
read_num_bytes <= read_num_bytes_int;
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
subtype opcode is bit_vector(5 downto 0);
function extract_opcode ( instr_word : word ) return opcode;
constant op_nop : opcode := "000000";
constant op_breq : opcode := "000001";
constant op_brne : opcode := "000010";
constant op_add : opcode := "000011";
-- . . .
end package cpu_types;
-- not in book
package body cpu_types is
function extract_opcode ( instr_word : word ) return opcode is
begin
return work.cpu_types.op_nop;
end function extract_opcode;
end package body cpu_types;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
subtype opcode is bit_vector(5 downto 0);
function extract_opcode ( instr_word : word ) return opcode;
constant op_nop : opcode := "000000";
constant op_breq : opcode := "000001";
constant op_brne : opcode := "000010";
constant op_add : opcode := "000011";
-- . . .
end package cpu_types;
-- not in book
package body cpu_types is
function extract_opcode ( instr_word : word ) return opcode is
begin
return work.cpu_types.op_nop;
end function extract_opcode;
end package body cpu_types;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package cpu_types is
constant word_size : positive := 16;
constant address_size : positive := 24;
subtype word is bit_vector(word_size - 1 downto 0);
subtype address is bit_vector(address_size - 1 downto 0);
type status_value is ( halted, idle, fetch, mem_read, mem_write,
io_read, io_write, int_ack );
subtype opcode is bit_vector(5 downto 0);
function extract_opcode ( instr_word : word ) return opcode;
constant op_nop : opcode := "000000";
constant op_breq : opcode := "000001";
constant op_brne : opcode := "000010";
constant op_add : opcode := "000011";
-- . . .
end package cpu_types;
-- not in book
package body cpu_types is
function extract_opcode ( instr_word : word ) return opcode is
begin
return work.cpu_types.op_nop;
end function extract_opcode;
end package body cpu_types;
-- end not in book
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_mux.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: A simple AXI-Streaming MUX
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_axi_mux is
port (
mux_select : in std_logic;
-- mux inputs
tdata0 : in std_logic_vector(7 downto 0);
tvalid0 : in std_logic;
tlast0 : in std_logic;
tready0 : out std_logic;
tdata1 : in std_logic_vector(7 downto 0);
tvalid1 : in std_logic;
tlast1 : in std_logic;
tready1 : out std_logic;
-- mux outputs
tdata : out std_logic_vector(7 downto 0);
tvalid : out std_logic;
tlast : out std_logic;
tready : in std_logic
);
end tri_mode_ethernet_mac_0_axi_mux;
architecture rtl of tri_mode_ethernet_mac_0_axi_mux is
begin
main_mux : process(mux_select, tdata0, tvalid0, tlast0, tdata1,
tvalid1, tlast1)
begin
if mux_select = '1' then
tdata <= tdata1;
tvalid <= tvalid1;
tlast <= tlast1;
else
tdata <= tdata0;
tvalid <= tvalid0;
tlast <= tlast0;
end if;
end process;
split : process (mux_select, tready)
begin
if mux_select = '1' then
tready0 <= '1';
else
tready0 <= tready;
end if;
tready1 <= tready;
end process;
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 8;
USER_DATA_WIDTH_2N : integer := 8;
USER_ADDR_SHIFT : integer := 0; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sample_buffer_if is
component sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component sample_buffer_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto 0) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH -1) + USER_address(31 downto 0);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_sample_buffer_if_req_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize <= req_fifo_dout_req_size;
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_sample_buffer_if_plb_master_if: component sample_buffer_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_sample_buffer_if_rsp_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_sample_buffer_if_rd_data_user_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 8;
USER_DATA_WIDTH_2N : integer := 8;
USER_ADDR_SHIFT : integer := 0; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sample_buffer_if is
component sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component sample_buffer_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto 0) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH -1) + USER_address(31 downto 0);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_sample_buffer_if_req_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize <= req_fifo_dout_req_size;
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_sample_buffer_if_plb_master_if: component sample_buffer_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_sample_buffer_if_rsp_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_sample_buffer_if_rd_data_user_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 8;
USER_DATA_WIDTH_2N : integer := 8;
USER_ADDR_SHIFT : integer := 0; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sample_buffer_if is
component sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component sample_buffer_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto 0) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH -1) + USER_address(31 downto 0);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_sample_buffer_if_req_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize <= req_fifo_dout_req_size;
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_sample_buffer_if_plb_master_if: component sample_buffer_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_sample_buffer_if_rsp_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_sample_buffer_if_rd_data_user_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sample_buffer_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3;
USER_DATA_WIDTH : integer := 8;
USER_DATA_WIDTH_2N : integer := 8;
USER_ADDR_SHIFT : integer := 0; -- log2(byte_count_of_data_width)
REMOTE_DESTINATION_ADDRESS : std_logic_vector(0 to 31):= X"00000000"
);
port
(
-- Bus protocol ports, do not add to or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_UABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- signals from user logic
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read return data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n : out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of MPLB_Clk : signal is "Clk";
attribute SIGIS of MPLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sample_buffer_if is
component sample_buffer_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) );
end component;
component sample_buffer_if_plb_master_if is
generic (
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3);
port (
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8 -1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n : out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
end component;
-- type state_type is (IDLE, );
-- signal cs, ns : st_type;
constant PLB_BW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := C_PLB_DWIDTH/8;
constant USER_DATA_BYTE_COUNT : integer := USER_DATA_WIDTH_2N/8;
constant REQ_FIFO_DATA_WIDTH : integer := 1 + 32 + 32 + USER_DATA_WIDTH_2N; -- nRW + addr + size + wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 5;
constant REQ_FIFO_DEPTH : integer := 32;
constant ALIGN_DATA_WIDTH : integer := USER_DATA_WIDTH_2N + PLB_BW;
constant ALIGN_DATA_BE_WIDTH : integer := (USER_DATA_WIDTH_2N + PLB_BW)/8;
signal user_phy_address : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal user_WrData_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N-1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size, req_fifo_dout_req_size_normalize : STD_LOGIC_VECTOR(31 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size, burst_size : STD_LOGIC_VECTOR(31 downto 0);
signal req_size_user : STD_LOGIC_VECTOR(31 downto 0);
signal req_BE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT-1 downto 0);
signal req_WrData : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal req_WrData_BE : STD_LOGIC_VECTOR(ALIGN_DATA_BE_WIDTH -1 downto 0);
signal req_WrData_byte_p : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal req_valid, req_SOP, req_EOP_user, req_EOP : STD_LOGIC;
signal req_burst_write_counter : STD_LOGIC_VECTOR(31 downto 0);
signal req_burst_mode, req_last_burst: STD_LOGIC;
-- interface to PLB_master_if module
signal PLB_master_if_req_full_n : STD_LOGIC;
signal PLB_master_if_req_push : STD_LOGIC;
signal PLB_master_if_dataout : STD_LOGIC_VECTOR(PLB_BW-1 downto 0);
signal PLB_master_if_rsp_nRW : STD_LOGIC;
signal PLB_master_if_rsp_empty_n : STD_LOGIC;
signal PLB_master_if_rsp_pop : STD_LOGIC;
signal USER_size_local: STD_LOGIC_VECTOR(31 downto 0);
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := PLB_ADDR_SHIFT + 32; -- addr + size
constant RSP_FIFO_ADDR_WIDTH : integer := 6;
constant RSP_FIFO_DEPTH : integer := 64;
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH -1 downto 0);
signal rsp_valid, rsp_SOP : STD_LOGIC;
signal rsp_addr : STD_LOGIC_VECTOR(PLB_ADDR_SHIFT-1 downto 0);
signal rsp_size : STD_LOGIC_VECTOR(31 downto 0);
signal rsp_rd_data : STD_LOGIC_VECTOR(ALIGN_DATA_WIDTH -1 downto 0);
signal rsp_rd_data_byte_count : STD_LOGIC_VECTOR(4 downto 0);
-- rd data user FIFO
signal rd_data_user_fifo_empty_n : STD_LOGIC;
signal rd_data_user_fifo_pop : STD_LOGIC;
signal rd_data_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_full_n : STD_LOGIC;
signal rd_data_user_fifo_push : STD_LOGIC;
signal rd_data_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_data_user_fifo_din_2N : STD_LOGIC_VECTOR(USER_DATA_WIDTH_2N -1 downto 0);
signal BE_ALL_ONE : STD_LOGIC_VECTOR(PLB_BYTE_COUNT -1 downto 0);
begin
BE_ALL_ONE <= (others => '1');
M_UABus <= (others => '0');
M_TAttribute <= (others => '0');
-- interface to user logic
user_phy_address(31 downto 0) <= REMOTE_DESTINATION_ADDRESS(0 to C_PLB_AWIDTH -1) + USER_address(31 downto 0);
USER_size_local <= X"00000001" when conv_integer(USER_size(31 downto 1)) = 0 else USER_size;
USER_req_full_n <= req_fifo_full_n;
process(USER_WrData)
variable i: integer;
begin
user_WrData_2N <= (others=> '0');
for i in 0 to USER_WrData'length -1 loop
user_WrData_2N (USER_DATA_WIDTH_2N-1 -i) <= USER_WrData(i);
end loop;
end process;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= user_phy_address;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32) <= USER_size_local;
req_fifo_din(USER_DATA_WIDTH_2N -1 downto 0) <= user_WrData_2N(USER_DATA_WIDTH_2N-1 downto 0);
req_fifo_push <= USER_req_push;
U_sample_buffer_if_req_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-32);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size_normalize <= req_fifo_dout_req_size;
process(req_fifo_empty_n, req_valid)
begin
req_fifo_pop <= '0';
if (req_fifo_empty_n = '1' and req_valid = '0') then -- lunch next request
req_fifo_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
variable offset: integer;
begin
if (MPLB_Rst = '1') then
req_nRW <= '0';
burst_size <= (others => '0');
req_size_user <= (others => '0');
req_address <= (others => '0');
req_WrData <= (others => '0'); -- set possible MSB to ZERO
req_WrData_BE <= (others => '0'); -- set possible MSB to ZERO
req_WrData_byte_p <= (others => '0'); -- set possible MSB to ZERO
req_valid <= '0';
req_EOP <= '0';
req_burst_write_counter <= (others => '0');
req_burst_mode <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
if (req_fifo_pop = '1') then -- lunch next request
req_valid <= '1';
if (req_burst_mode = '0') then
if (req_fifo_dout_req_nRW = '0') then
if (req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT) and
req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0,PLB_ADDR_SHIFT)) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
elsif (('0'&req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) +
('0'&req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) <= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 1;
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT) + 2;
end if;
else
burst_size <= X"00000001"; -- single by default
if (req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT+1) /= CONV_STD_LOGIC_VECTOR(0,31-PLB_ADDR_SHIFT)) then -- may burst
burst_size(31 downto 32-PLB_ADDR_SHIFT) <= (others=>'0'); -- burst_size for write operation
if (req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) = CONV_STD_LOGIC_VECTOR(0, PLB_ADDR_SHIFT)) or
(conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0)) + conv_integer(req_fifo_dout_req_size_normalize(PLB_ADDR_SHIFT-1 downto 0)) >= PLB_BYTE_COUNT) then
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT);
else
burst_size(31-PLB_ADDR_SHIFT downto 0) <= req_fifo_dout_req_size_normalize(31 downto PLB_ADDR_SHIFT)-1;
end if;
end if;
end if;
offset := conv_integer(req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0));
if (req_fifo_dout_req_nRW = '1') then
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
end if;
req_size_user <= req_fifo_dout_req_size; -- for read operation
req_nRW <= req_fifo_dout_req_nRW;
req_EOP <= '1';
req_address <= req_fifo_dout_req_address;
req_burst_write_counter <= req_fifo_dout_req_size;
req_WrData_byte_p <= req_fifo_dout_req_address(PLB_ADDR_SHIFT-1 downto 0) + USER_DATA_BYTE_COUNT;
if (req_fifo_dout_req_nRW = '1' and req_fifo_dout_req_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_mode <= '1';
req_EOP <= '0';
end if;
else -- in a burst write process
req_burst_write_counter <= req_burst_write_counter -1;
offset := conv_integer(req_WrData_byte_p);
req_WrData(USER_DATA_WIDTH_2N +offset*8 -1 downto offset*8) <= req_fifo_dout(USER_DATA_WIDTH_2N -1 downto 0);
req_WrData_BE(USER_DATA_BYTE_COUNT+offset-1 downto offset) <= (others => '1');
req_WrData_byte_p <= req_WrData_byte_p + USER_DATA_BYTE_COUNT;
if (req_last_burst = '1') then
req_burst_mode <= '0';
req_EOP <= '1';
end if;
end if;
elsif (req_valid = '1') then
if (req_nRW = '0' and PLB_master_if_req_push = '1') then
req_valid <= '0';
elsif (req_nRW = '1') then
if (req_EOP = '1' and PLB_master_if_req_push = '1') then -- last burst request
if (req_WrData_BE(ALIGN_DATA_BE_WIDTH-1 downto PLB_BYTE_COUNT) = CONV_STD_LOGIC_VECTOR(0, ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT)) then
req_valid <= '0';
req_EOP <= '0';
req_WrData <= (others=>'0');
req_WrData_BE <= (others => '0');
else
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH -PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
elsif (req_EOP = '0') then
if (req_WrData_BE(PLB_BYTE_COUNT-1) = '0') then
req_valid <= '0';
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' and PLB_master_if_req_push = '1') then
req_WrData(USER_DATA_WIDTH_2N + PLB_BW -1 downto USER_DATA_WIDTH_2N) <= (others => '0');
req_WrData(USER_DATA_WIDTH_2N -1 downto 0) <= req_WrData(USER_DATA_WIDTH_2N +PLB_BW -1 downto PLB_BW);
req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT) <= (others => '0');
req_WrData_BE(ALIGN_DATA_BE_WIDTH-PLB_BYTE_COUNT-1 downto 0) <= req_WrData_BE(ALIGN_DATA_BE_WIDTH -1 downto PLB_BYTE_COUNT);
req_address(31 downto PLB_ADDR_SHIFT) <= req_address(31 downto PLB_ADDR_SHIFT) +1;
req_address(PLB_ADDR_SHIFT-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end if;
end if;
end process;
req_last_burst <= '1' when (req_burst_mode = '1' and req_burst_write_counter(31 downto 0) = X"00000002") else '0';
process(req_nRW, req_WrData_BE, burst_size)
begin
req_size <= (others => '0');
if (req_nRW = '0') then
req_size <= burst_size;
elsif (req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) = BE_ALL_ONE) then
req_size <= burst_size;
else
req_size <= X"00000001";
end if;
end process;
process(req_valid, PLB_master_if_req_full_n, req_nRW, req_WrData_BE)
begin
PLB_master_if_req_push <= '0';
if (req_valid = '1' and PLB_master_if_req_full_n = '1') then
if (req_nRW = '0') then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
elsif (req_WrData_BE(PLB_BYTE_COUNT-1) = '1' or (req_EOP = '1' and req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0, PLB_BYTE_COUNT))) then
PLB_master_if_req_push <= '1'; -- only push when the last byte been push
end if;
end if;
end process;
req_BE <= req_WrData_BE(PLB_BYTE_COUNT-1 downto 0) when req_nRW = '1' else (others => '1');
U_sample_buffer_if_plb_master_if: component sample_buffer_if_plb_master_if
generic map(
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
PLB_ADDR_SHIFT => PLB_ADDR_SHIFT)
port map (
-- Bus protocol ports, do not add to or delete
PLB_Clk => MPLB_Clk,
PLB_Rst => MPLB_Rst,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
-- signals from user logic
BUS_RdData => PLB_master_if_dataout,
BUS_WrData => req_WrData(PLB_BW-1 downto 0),
BUS_address => req_address,
BUS_size => req_size,
BUS_req_nRW => req_nRW,
BUS_req_BE => req_BE,
BUS_req_full_n => PLB_master_if_req_full_n,
BUS_req_push => PLB_master_if_req_push,
BUS_rsp_nRW => PLB_master_if_rsp_nRW,
BUS_rsp_empty_n => PLB_master_if_rsp_empty_n,
BUS_rsp_pop => PLB_master_if_rsp_pop
);
-- below is the response (bus read data) part
U_sample_buffer_if_rsp_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(32+PLB_ADDR_SHIFT-1 downto 32) <= req_address(PLB_ADDR_SHIFT-1 downto 0);
rsp_fifo_din(31 downto 0) <= req_size_user;
rsp_fifo_push <= PLB_master_if_req_push and (not req_nRW);
process (rsp_valid, PLB_master_if_rsp_empty_n, rsp_rd_data_byte_count)
begin
PLB_master_if_rsp_pop <= '0';
-- fetch data to rsp_rd_data until enough bytes
if (rsp_valid = '1' and PLB_master_if_rsp_empty_n = '1' and CONV_INTEGER(rsp_rd_data_byte_count) < USER_DATA_BYTE_COUNT) then
PLB_master_if_rsp_pop <= '1';
end if;
end process;
process (MPLB_Clk, MPLB_Rst)
begin
if (MPLB_Rst = '1') then
rsp_valid <= '0';
rsp_addr <= (others=> '0');
rsp_size <= (others=> '0');
rsp_SOP <= '1';
rsp_rd_data_byte_count <= (others => '0');
rsp_rd_data <= (others=>'0');
rsp_fifo_pop <= '0';
elsif (MPLB_Clk'event and MPLB_Clk = '1') then
rsp_fifo_pop <= '0';
if (rsp_valid = '0' and rsp_fifo_empty_n = '1') then
rsp_valid <= '1';
rsp_addr <= rsp_fifo_dout(32+PLB_ADDR_SHIFT-1 downto 32);
rsp_size <= rsp_fifo_dout(31 downto 0);
rsp_fifo_pop <= '1';
rsp_rd_data_byte_count <= (others=>'0');
rsp_SOP <= '1';
end if;
-- fetch data to rsp_rd_data until enough bytes
if (PLB_master_if_rsp_pop = '1') then
rsp_rd_data(USER_DATA_WIDTH_2N-1 downto 0) <= rsp_rd_data(USER_DATA_WIDTH_2N + PLB_BW -1 downto PLB_BW);
rsp_rd_data(USER_DATA_WIDTH_2N +PLB_BW -1 downto USER_DATA_WIDTH_2N) <= PLB_master_if_dataout;
if (rsp_SOP = '1') then
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT - rsp_addr;
rsp_SOP <= '0';
else
rsp_rd_data_byte_count <= rsp_rd_data_byte_count + PLB_BYTE_COUNT;
end if;
end if;
-- write one unit of data to USER LOGIC
if (rd_data_user_fifo_push = '1') then
rsp_size <= rsp_size -1;
rsp_rd_data_byte_count <= rsp_rd_data_byte_count - USER_DATA_BYTE_COUNT;
rsp_addr <= rsp_addr + USER_DATA_BYTE_COUNT;
if (rsp_size = X"00000001") then
rsp_valid <= '0';
end if;
end if;
end if;
end process;
process(rsp_addr, rsp_rd_data,rsp_valid, rd_data_user_fifo_full_n, rsp_rd_data_byte_count, rd_data_user_fifo_din_2N)
variable i: integer;
begin
case CONV_INTEGER(rsp_addr) is
when 0 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +8 -1 downto 8);
when 1 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +16 -1 downto 16);
when 2 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +24 -1 downto 24);
when 3 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +32 -1 downto 32);
when 4 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +40 -1 downto 40);
when 5 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +48 -1 downto 48);
when 6 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +56 -1 downto 56);
when 7 => rd_data_user_fifo_din_2N <= rsp_rd_data(USER_DATA_WIDTH_2N +64 -1 downto 64);
when others => null;
end case;
for i in 0 to USER_DATA_WIDTH -1 loop
rd_data_user_fifo_din(i) <= rd_data_user_fifo_din_2N(USER_DATA_WIDTH_2N-1-i);
end loop;
rd_data_user_fifo_push <= '0';
if (rsp_valid = '1' and rd_data_user_fifo_full_n = '1' and
CONV_INTEGER(rsp_rd_data_byte_count)>= USER_DATA_BYTE_COUNT) then
rd_data_user_fifo_push <= '1';
end if;
end process;
U_sample_buffer_if_rd_data_user_fifo: component sample_buffer_if_ap_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 5,
DEPTH => 32)
port map(
clk => MPLB_Clk,
reset => MPLB_Rst,
if_empty_n => rd_data_user_fifo_empty_n,
if_read => USER_rsp_pop,
if_dout => rd_data_user_fifo_dout,
if_full_n => rd_data_user_fifo_full_n,
if_write => rd_data_user_fifo_push,
if_din => rd_data_user_fifo_din
);
USER_RdData <= rd_data_user_fifo_dout;
USER_rsp_empty_n <= rd_data_user_fifo_empty_n;
end IMP;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: J.40
-- \ \ Application: netgen
-- / / Filename: image_gen_bram_green.vhd
-- /___/ /\ Timestamp: Thu Nov 06 17:02:39 2008
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_green.ngc D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp\_cg\image_gen_bram_green.vhd
-- Device : 2vp30ff896-7
-- Input file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_green.ngc
-- Output file : D:/MyDocuments/OpenCores/projects/lq057q3dc02/coregen/tmp/_cg/image_gen_bram_green.vhd
-- # of Entities : 1
-- Design Name : image_gen_bram_green
-- Xilinx : C:\Xilinx\ISE_9_2
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synopsys translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity image_gen_bram_green is
port (
clka : in STD_LOGIC := 'X';
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
douta : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end image_gen_bram_green;
architecture STRUCTURE of image_gen_bram_green is
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena13 : STD_LOGIC;
signal BU2_N18 : STD_LOGIC;
signal BU2_N16 : STD_LOGIC;
signal BU2_N14 : STD_LOGIC;
signal BU2_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N13 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_ena12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta25 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta24 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta27 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta26 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta20 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta19 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta22 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta21 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N8 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta16 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta15 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta18 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta17 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta10 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta9 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta12 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta11 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta4 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N3 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta7 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta6 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta0 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_N1 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta2 : STD_LOGIC;
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta1 : STD_LOGIC;
signal BU2_N1 : STD_LOGIC;
signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED : STD_LOGIC;
signal addra_6 : STD_LOGIC_VECTOR ( 16 downto 0 );
signal douta_7 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta13 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta14 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_ram_douta23 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal BU2_doutb : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
addra_6(16) <= addra(16);
addra_6(15) <= addra(15);
addra_6(14) <= addra(14);
addra_6(13) <= addra(13);
addra_6(12) <= addra(12);
addra_6(11) <= addra(11);
addra_6(10) <= addra(10);
addra_6(9) <= addra(9);
addra_6(8) <= addra(8);
addra_6(7) <= addra(7);
addra_6(6) <= addra(6);
addra_6(5) <= addra(5);
addra_6(4) <= addra(4);
addra_6(3) <= addra(3);
addra_6(2) <= addra(2);
addra_6(1) <= addra(1);
addra_6(0) <= addra(0);
douta(5) <= douta_7(5);
douta(4) <= douta_7(4);
douta(3) <= douta_7(3);
douta(2) <= douta_7(2);
douta(1) <= douta_7(1);
douta(0) <= douta_7(0);
VCC_0 : VCC
port map (
P => NLW_VCC_P_UNCONNECTED
);
GND_1 : GND
port map (
G => NLW_GND_G_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"C65BF1825AEA49D64E8911080801FF0B820843E78E97F6220000000000000000",
INIT_02 => X"C1D167FE7F57FCDC9BF27FDFBEC1026015E4E5FC803FEB525D78380C9307DF90",
INIT_03 => X"B00E83831A923B1874199EFDF9FE23D562086C80C85ABC16CBE30F94D64C95F7",
INIT_04 => X"363D04B25C5C03C2F7DE339F6314B370F3909CDA13A39BF1C1E0BC87F3931CF9",
INIT_05 => X"97C059D19FA05EADBB7FDC204E07F6ED64E3D381CE7F1FBFE36E83811850E2A0",
INIT_06 => X"CB7BBEBD46B3DE8F8C82E481723FEFBE300172013FF140764180DBB087001ACF",
INIT_07 => X"348896E26BBA71FEE2053F000D25AE4A7E75B250B14A115517385E4F81A514C1",
INIT_08 => X"CE0E7018EE1CF88A0727713AC79215F98321311CF7D7F8201BE106747205F849",
INIT_09 => X"3D758B6E04B9CD08DC3F6E7AF837B2C61C02C08E3EF79E4EDD7174F077A08D7C",
INIT_0A => X"7ADEDA0182E467E3135971402A35888DDFF5E199FF4BBB7FF91F77E0DFAADE9A",
INIT_0B => X"277A9C07300AD503CF5C469F2853DF7FF51F77E08B4BAC2A652F86063A23E97B",
INIT_0C => X"D993A41F47633D7FF01DC7C02985403C5249DF05833BFA166BFCBA80CF9FAFFE",
INIT_0D => X"FFCD83C073F93CFE0354F3DFFDF3FFB10BFF64FF0A60954CCD77D8E1C7864551",
INIT_0E => X"54316F0B8BA5F9090F02FE03B22236DE81FB5DC062552A43756E021F406C3BFF",
INIT_0F => X"00FF5E7CDF0D2E8EA955EEC7E58F1100B12D83FFED657BFFDAED030033FDFBFE",
INIT_10 => X"0B1ECD033F884A2668AB860E715DFB3FD66D70205E41F1FE6BE92EFCF2A73D0A",
INIT_11 => X"0D5344C4B88EBC33C52DFC00765EF1FE7B0D4B8425103FFE008080FE1908385B",
INIT_12 => X"5414FC00A99137FE7C05D15005FA3F4600801FEE3A511321948D0B1CE31CE914",
INIT_13 => X"7366360C0BE5DF3A41064EEFCB681D8BF1E9593F6188DE43684D23DD008F3A3B",
INIT_14 => X"CABE80FB5BC2BC45E44DB2F1E210D222EB7FC6455764707E4090C14FD9123F7E",
INIT_15 => X"E872099AAC3690E56A686D615EDBF77F7EF7C7E91BDBBE7E7E9153247D2EBB8E",
INIT_16 => X"F8FE6ED94594F8FD4D5D0F657F21BE7E375D469AA07C56F9389F80813DACCC99",
INIT_17 => X"4F621F1F7CFD1F7E1E27D3D6BF5F03F05C1EFF8E0661E6E2F31506731151A4A7",
INIT_18 => X"7C2951EFD33B6DF41E8CFFCF7186FEDE772B0ACD53C216292342BB5AC7D2A67C",
INIT_19 => X"A8C07FCCEB9C7F6709FC8D5D96EBE8710509237B84A225FC50DABFF6DE715D7E",
INIT_1A => X"F42BAFB924BED9AB374A5A2838C728FFE964BEFD3BFF6CFE7BC09CA44092EDBF",
INIT_1B => X"24CB54D13A4E7AFFEA0E80722FFD90FE7FF8B2148081A00D9C001FFB6536473B",
INIT_1C => X"D0CF81D59DFFA2FE722B0B21009DA06DD98007FE2F9D7B7C7033FE1D5A583CE3",
INIT_1D => X"5ABDD6962EE0259FFD4302FCBD2BF15EB02FF269916F3AB0363C7515F6DF15FF",
INIT_1E => X"4950AF67BD1C97594146F115360DFC4407B14FEF350050F7D5C181807DFFE13E",
INIT_1F => X"8B96E6EB38F85B8B904F56DB2DD6A0FFFD8E5F8B3D1AF83A73D7846122078EAD",
INIT_20 => X"DACFE37B0D9009FF7374415C7C5CF73A7FFAC0FC1EC0B436B0B99FCF77E5F04D",
INIT_21 => X"D4DCB64BCFAA4CBC7FFF95232E2F1ED72574BEDE3D1988F738FAA7F915B6F044",
INIT_22 => X"7FFEDA603E4F81F09B1421C13BBD5F8426296BFF505277D8F303B7FBE569D13F",
INIT_23 => X"776CD33F748A1DFD554AEBFFF5DE2C00603477702E23323F0538BCB147C460BC",
INIT_24 => X"1D4DADFF18D99DADE5795D417B5ABEBC2FDE850647EDAEB67F7F26747426DB53",
INIT_25 => X"817B9BF955779FBDD5565A09FFD78B367F7FF7C864F4673AF56720E05828A38B",
INIT_26 => X"BA8C62D3FF1F25F87FFFF6D0E656E6E54115FF51C10DE67473F30BFE8AB54C00",
INIT_27 => X"7FFFC3BF766476BD059403EAED015C87328F8817830D87DBD91A0F2B90959F3D",
INIT_28 => X"B7DD7740D006CB9A42B272F7C05F744FEBED711411482FFAD891DA45FB91183C",
INIT_29 => X"983986C7389FB43CDD8D6C0DDAA317F9EB7F301DEAD85F8A67F091A70591A18F",
INIT_2A => X"812D8AEF32BA1FFB93E7354FDB4528C67FF777FB178F18E788499EA458594593",
INIT_2B => X"02E6065FA638D7C27DB04A3FE2636EB6E6851DDC5DF6A290CAEF0F95F9BB657C",
INIT_2C => X"4FF57EFCD40784167FAB7E15C81A52EC6636C3E7A0549A1FE31BFDF478710FF8",
INIT_2D => X"0FE2C482BD74870F92BE436E16993EBFE3E1F49F5C50EFFFCDF93E1FADFD0A7A",
INIT_2E => X"93BF40C7FB7F527FCCB7BFF8C1900FFC71FF07BFC180BEFA5C7BA49ED925B137",
INIT_2F => X"C1DBFDE63D51CFF513F0C5EFE04AE0325ACFDAE000957DB23FD50CC50236CAD0",
INIT_30 => X"2FF8F69F6718F5866CB2E4EF688B3438BFAF82F0B713E730D4C1563C83EDC0E6",
INIT_31 => X"41E70BC861D1ED3ABFF5DB52EEF6B0457B2569B7439F87FFDFB0FEF4C9BAEFF1",
INIT_32 => X"7FFDEFC4458E886C7FF2A43A4D9DBDC7E41A73555F7ABFFAEDE6A38F3C09FFE2",
INIT_33 => X"53C81752F1033FCBEE9BC6FCE390BFFA2EBD3CA460707FCC6EB57961E1958AB0",
INIT_34 => X"8B8DF75F19263EFFF6DAFCC99B6CFFBA41865147EFDDC73B7FEBF3CFBEBFE8BE",
INIT_35 => X"DFF0EEA5C44BF7E8386CB004F9D5F8A73F2FF6C7A33FE45FFDCF5F58FFFCEFCF",
INIT_36 => X"5DB47F9700DBF97FBE0713B120F97A7399472AF67F7CBF48000821FE15DFBEF8",
INIT_37 => X"1FC003B677623AAB72C97B9E3FDF4FFEFBC989706854FC7C1BB17CF8CB30E3C6",
INIT_38 => X"CC4C7767D7BF736216F3027EC662FC7D0AD9BBF7C335E3EA3A9A7F1162C28BC7",
INIT_39 => X"AA1F85FFC2B1FE7D673D71FFFE4BCFF045E13F9721A75B988FAEFCC78626BAF0",
INIT_3A => X"6FFF3BF7D1528F1A3098AF5A140D07F1AF87FFD29E1FFC0BFB1F6B72031D86E6",
INIT_3B => X"0A93FD2FC537898BF7D8FFA988D5FE22818DA981956DD947DACDB0FFD9517CF8",
INIT_3C => X"679A3FCD8EEEE35E76A2A060A7B8406FFFDF7DFF27977FFE0D7F1FF3D48D0EDE",
INIT_3D => X"F200E4A4C156307FE8C897FFA6E6FFFE37C737C7B4F70E5871938E7494E89680",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"C80EEFFF70317FFC6EA033E7923FF8845C6D5820878FB58ABEC3EFD93C64DA70",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"47B3F9EF5C6FF8F82A7C5DED86F1CBC88CFAE7E07846FAD8FEF3C745511FABBF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"318F4AE23407009620FFABFF963BEBDAF91B20D7CE2A9DFFCBB11FCF93E47FFF",
INIT_01 => X"E01E7FFF20778BA3FD87710F36A387FBEA02EF8FF26FFFF979215DFFD17DF978",
INIT_02 => X"FB6CBE00642ABFFF184B1E0FF648FFFFFB77C3EF16BDE75C0FEB1B82F84C8D96",
INIT_03 => X"51F7BE0FFC81FFFCA3000FED653FE91A3EC76B0B54A08E8E3A0EE7FFB3606B8C",
INIT_04 => X"86617FFE19BFFA407DF1C9BAB19CEF4CCBF9AADFF2EC67CCFFFFBAB70A283FFF",
INIT_05 => X"7D6EE646C7313F806DAE7D5FBA85CFC0F7F261280665FE7FFD7B3FBFF0F7FFFC",
INIT_06 => X"8EF4725FFC255FC4E7E18BE569E7F8FFF53B7EFEEDE9FFFB1074FFE4EA7EED64",
INIT_07 => X"63F434F5FD73FFF1F5DFBFFFE877FFF0D27BFFF688FFC2FA605395C9111D5787",
INIT_08 => X"FCBA7FFFB5AFFFE33205FFF610FFBCAE69A3227C401F37E349938FF1FE4FAF9A",
INIT_09 => X"8187FFF452FFD31C0BC9275A4E31921B8D6B5BF8FF0D751AE3F7AF8821F51FE4",
INIT_0A => X"32D0215D77AAC66F7DD446FCFF061A8673E371ABFD3C1FF5EAF87FFFD777FFF8",
INIT_0B => X"97F94B7FFF1C284773F9B5EE7BF98FFFF8FF3FFC263FFFFB25D7FFF3BBFD28CE",
INIT_0C => X"F7F18EDBA7FE6FFFDDFF3FF5617FFFF8A953FCF65BFE547050761AB0BB7DB45C",
INIT_0D => X"89C931E06D3FFFFA41C3FCE57FFD8AFE64180199C349D7FEAF42803FFFF5360E",
INIT_0E => X"1146F87ABEFF515E310066F7E80D24F4F0E981BFE1FF67347FB72CFD8088C8FF",
INIT_0F => X"660BE5988A5428FDEFBC3A47EEF8A6673FF87384DE0E03FFF7FBF3E253BFFFFE",
INIT_10 => X"3C555C53F7F91CC07FFCFF8845AEE0FFC7F33FFEF9FFFFF03266F6FF98FDD252",
INIT_11 => X"7FFFFEE70D2E8DFF73FFFFE392BFFFEC95DFFFC9F97D98C2671C99C153D089FF",
INIT_12 => X"5FF7FFF1C73FFFECCB1FF1E8FEEC36E67903F97F919C7EFF1EC95E5CEEFCEDC9",
INIT_13 => X"1BBFF3EB3FE8C5BE67FC871379C1E7FFFFA1214D687FCF8C5886FD2AFB284CFE",
INIT_14 => X"6C417FBC824AABFFFFA01C0D943FE2128E7FFCDEF0B07C7EF7C3F1FFD8FFFFFF",
INIT_15 => X"FFFE93B0DFCFDCB9536BEF2E0B144C399FC7F8FF443EFFF127BFFFCC3FFE717E",
INIT_16 => X"0B07C7D2384EDF6D3FC7FF7F3EFFFFC2DF07FF4EFFE5377E566E7FBE337D31F3",
INIT_17 => X"3FCFFFFFF57E7F97FFFFFFC19FE38F7E5849F7DFEE7EFAFFFFFFF87A17FFFEDB",
INIT_18 => X"FFFFFF291FCBDFFE105501F0A6DB983FFFB7EF9A2FFFF92EC24FDF898187F677",
INIT_19 => X"7FAF03F70F8341100F0FBED0DABCFFF4787F3FE34F87BAE37FB730FFEBFE7F93",
INIT_1A => X"6C0FFFFB262FFF97FE2EFF3A177FEFD0F1DF3DBF27FCFFE4FFFFCFE95FD38FFE",
INIT_1B => X"0537EFAE4E1FAEDB33EB6ABE17FEFF10FFFEC619D3DF8F7E7C6685F50F8A418E",
INIT_1C => X"EDF331BF3BFFFFE5FFFC45E3FBD75DFE0591A1F19FFF7AEFE007FFFF57F67FD7",
INIT_1D => X"FFFCEB1552D4F9C44818078EFFECD4A16FFFFFFF3AB2EFF0086FE43356E7CEF3",
INIT_1E => X"17910381FA1BC26F47FFFFFEB9F337875435F9100A7FFF83F84E24FE67FFFFEF",
INIT_1F => X"C3FFFFD9FC6DFFC96878FECB361F7EB7FF1B35F547C7FF6EFFFF78317AEDFFEE",
INIT_20 => X"749DFAAD72355FEFC10F6075B7C7FFF7FFFFFED4F18EFFA641B0DB317019284A",
INIT_21 => X"E10073A1AFCFFFFF3FFFFB29392E9F5E4B434724001CA359D3BFFFDFFF5E6EF3",
INIT_22 => X"1FFFF8C1F9AF9F3A1C95140F4060986B0E3FFAEFFFA7BAFFDBFBE7DABFA03BC5",
INIT_23 => X"4D6589590766E5A18FAEFFF3FFF5E68FFE7EAC167BBEE5B0CF7CD420FFD7FF9F",
INIT_24 => X"342072736FF03013FFF5DE0A38EEF3CFDFE3756CDFC7FF7FFFFFFA8EF3FFFA12",
INIT_25 => X"FC8FB33D740BFFEB8F90E605CFEFBE3FBFBFE6FF7FFE4C6A03D384C78CFD1331",
INIT_26 => X"8873267B3FEFFFFFFF3FFCBFFFFC2B844212D4E3357E492BE643BC5B5FDFCE15",
INIT_27 => X"FFFFD8DB7F62D0DC180EF7019600D8FCAD4016F7FF1FEE387CC7E64ECE29FF0A",
INIT_28 => X"6414AFFFB46EC208721D22A3FE1FFB948C79FEFCB916FF34DDA7C3E53FFFFFFF",
INIT_29 => X"0C870233F67FFCAC47E7FC424379FFBE71CF83FD3FFFFFFFFFFF837F47DB36A6",
INIT_2A => X"E727FDF62DFB5F7CF5D587C05FFFFFFFFFFE3264DB9163CE691E61FBC846F827",
INIT_2B => X"D56FC7F0BFFFE3FFFFFD85D0E7EE9BC051FF7DE03668A268F38C25ABD9F8FE2A",
INIT_2C => X"FFFC7ED7FF7633FA790EA600EC752C41E16171F151FFBFDEAF40CBF746F5CF2E",
INIT_2D => X"65F3DEFA1D19AE1CCF6828714AFF3FC6175B19F89379174ADFBD4FF4C7FFFBFF",
INIT_2E => X"5A6CFE8E1EFDFFE82DBFA5E00FDCB155A0A6A7F03FFFFBFFFFEFA1EBFFDEF7FE",
INIT_2F => X"224BDFEA8A72937B235C5FBB3DFFB3FFFFF1BDBBFFDD5FFE17877FA3D4150762",
INIT_30 => X"8D1CBDDA9DF87BFFFFE61647FFFDF1FE420FE747E7B886535376E91353BFFEFE",
INIT_31 => X"FFD4DE03FBFDDDFE7EC783E17ADA373555ABD5C97893FFFF825818690EF1FEFF",
INIT_32 => X"58C06760B98617AD93A6AB85A517FFFFF0F4909493953F3DD67FDDDEDDFB67FF",
INIT_33 => X"9B58E4D109F1FFFFF81C55E473F4B27CC97A3040DCFEFFFFFFFA9707FDFCE1FC",
INIT_34 => X"FF5996B70C9A7C3D2BD10FC2BEF3A7FF9F66BF7E3FFFFFFC07C0FF8BDC30A60F",
INIT_35 => X"ED1DE835F8F553FF9D3EFEFEBFBF7F8E0B00FFC502D69E4F41F4D38680789FFF",
INIT_36 => X"F8E777FF7F0FFF0E5040E17CC2E804B876E7CDE48096D3FFDBA89C0C5CB3FA64",
INIT_37 => X"6041FA77BDC3863913138036BE934BFFABE6CFF0068662498570254BFCFEEFFF",
INIT_38 => X"3C6E4E18BD9F0F8763D2C8147E278DED63A2B9BBFFB39FFFF11FBFFFFFFFEC7E",
INIT_39 => X"A861670CC49F21FEA4B51305BEE566FFE7BF3FFFFFFFEEFE2BCF72FFBFB73208",
INIT_3A => X"F8BCBA14FE517FFFE67FFFFFFFFFF3FE35E0FF82BBA525B714424734FA811B47",
INIT_3B => X"A23FFFFFFFFFFFFE05FF00FFA9DAFB2B44CF33DC0BDF63872E32686991503DE3",
INIT_3C => X"75730010B5E96ACD8EFD0925784C4D5F4FD00BFC8684E201BA5D56157F6C7FFF",
INIT_3D => X"F04F5FCD311C6149679EBE0AB9847A4CA2B5D859FF477FFE7707FFFFFFFF3FCE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"DFF3B10759DB900A5C17EA55F238FFFF936FFFFFFFFFFF8E31630F038E0377B7",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0BA4645DD6EDFFF5899FFFFFFFFFFFC6757E0F02DCD71F1FFF9255323C764F49"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_1_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"DFFDFFFFFFFFBFE20EF30FEF41A6E9BFFFF4D4F5501A2F50EC2AA6B30AF3AFD1",
INIT_01 => X"3BE787FDAD41FF9FFFFF27FCFDDB6253A15C4F7765371E27BAE33315507BFFDC",
INIT_02 => X"FFFF8BFFFFB3A22E408C9FC46A839FAEB0166AF509EBFF08D7FD3FFFFDFF3FF2",
INIT_03 => X"0FCD80A80A7EC592B9E8362FE7E5FF501FFCFFFFFFFF7FF830678369C78FFF7F",
INIT_04 => X"F5F77A662711F7037FFDFFFF7FFFE7E078E6704653EEFFF1FFFFBFFFFFECFBE8",
INIT_05 => X"FFFFFFFFFFFFEFE64701F91B169FFFFF00C5FF6FFF1CEE4BCCF383649B730437",
INIT_06 => X"001F84CCB7BF8FFFFFFFFE97FFEDBD0807390EE1C8DD0F4AB44C1FE87B3FC242",
INIT_07 => X"FFBFFE77FFF07F5662083CB69744AF4757C9DA15F15FFDFBFFFFFFFFFFFF8806",
INIT_08 => X"E5A3776F2755825ED7F9098F2C07C4DFFFFFFFFFFFFFDC9A50B800B0E84383FE",
INIT_09 => X"64395BF75D2B933FFEFFFFFFFFFCFEEE409882AF0269FFC8FF9FFFFFFF31FED6",
INIT_0A => X"FFFFF33FFFFE7D1840C7F779D38FFFBC460F3FFFFFFFFFE5AF7BE7C05A181388",
INIT_0B => X"00F352F635D326D66A37B1FCFFFFFB427F3FF66C586B688EB977F2A9F8A2E3FF",
INIT_0C => X"0D19CF8778FFFE97CDE4C847744EDD450E205ED0356121FFFFDFFB3FFFFF02A0",
INIT_0D => X"4E209FC349F1904AF6C9B3AFDFAB1FFF7F1FEFFFFFFEA5FA06DBF70B0BD8C2FB",
INIT_0E => X"4428DEDF9DA87FFFFFFFF8FFFFF1984C1AF4F2F2E3A715AF8D94262A3A2BFF39",
INIT_0F => X"BDF1FFFFFEE6D110271DCB965372D099380843CB8BBAFFFF98D43E130ECAA9E5",
INIT_10 => X"629D3763736A602C1B1B6EAA9579DFFF33C5CE81E133209950456D571C4CFFF3",
INIT_11 => X"FCD61E26AA27CFFE82D5C280E65B83892CF8D8B7BF2BFCF3DDD53FFFFFEFAFEA",
INIT_12 => X"CBBD831FB4A9D785E698CC39DDAFF6ADE32FBFFFFE1FF86A037AFA4EAF15E879",
INIT_13 => X"643A4EBFF0FFF1208C753FFF183FE0643D9613248D68453F00836D131FFFFFFC",
INIT_14 => X"5766FFFF403FC94C2608864A963697F81CEB31CF9FFFFFFBB54281C6F670D462",
INIT_15 => X"1A88CE6B8F8BB7CF9F7E82FFFFC1FFF725F2C3F0F34E9BF049B8743F17FFF2FA",
INIT_16 => X"FDB1FFFFFFA2FFFA696B4EA3ACC58C55E82ED9DC8BF53ECEAB83FFFF59C02374",
INIT_17 => X"DF598CD981F37430DEEF9FF907F7E094ED5FFF7F1FF71CB82C90B476E0E63DF9",
INIT_18 => X"813DFDA67FD0755E6A07FFFFFF87DC70283B0F9D00135C39BB9FFFF8FF997CF4",
INIT_19 => X"083FFFFFFE9FAFFC73FF519343DC629655DFFFC0FFFFE0E616B18E78A297BD39",
INIT_1A => X"689E7A77C25CF8431A7BFFFFFFFFE4848D61DE70145A828AE83524D5FFD46BFF",
INIT_1B => X"F2C3037FC13F7A883FACF269BE0EED504908DC76FC9025640BDFFFFFFD45D8BC",
INIT_1C => X"8EA1F20F2F9787452C9E8F8BF37495B73C7FFFFFFC20A1D67FECBC00DA0CB46C",
INIT_1D => X"D9BB9D8FE0C308092DFFFF7CF1BD7EF67FCFC64CFE1C8EA02FF100FFF03F1F57",
INIT_1E => X"A17DFFF1B9D055607F632C00F85C70DEFFFFFFAFFC00FCAA2CB31AE18E3FB71F",
INIT_1F => X"73DE3596D5247EFFF9FFFEB2F1D55757747C9CF973EADDE01CFDB79EC7A43683",
INIT_20 => X"F7FF3D234B114879FDC8503BFF007BFFAECBFDDFFE91BD75E878FFEE817E76F2",
INIT_21 => X"FD7DD14BA3EE5BBBB19F49EB188C81C002FFFF00FFF1FDF87F4596D3ECAE749F",
INIT_22 => X"D64AAFF770C5A2FEF7FFD44A99B12E627EFA765C3B83BF5FC1FF3DE0BE7E507D",
INIT_23 => X"97FE98292A60F87C7CEA1493CF0FBF8FC0FE7521F38EF0FFFF966B436A14FB45",
INIT_24 => X"6DE7EBAF2110C767F87F2D8AB1705DFFFDF47465D90D44CB2E695FFE63D7219A",
INIT_25 => X"F7EEDE8528577FFFEAC14935283B2A7E9164BFEDB7C375AFFFD54654DFFEFBFE",
INIT_26 => X"E7F635CC9C1C55ADFE09FFFB3A53101FFFD2DF841FCF3FFE45592E93DA638A21",
INIT_27 => X"B7E2FFFA9F47F15FF8F930579FEBF0BE64CFE53F54E02960E9F6C6FBFB59BFFF",
INIT_28 => X"D20F70FFCFFFF1BE104C08DD874EAF37F49D1D3181637FFCB3FC231BD30B059C",
INIT_29 => X"11828E894F41ADF54B3C98DDFB91FFC0D0B217552A670CE5B793FAE4E9A7C0FF",
INIT_2A => X"B96D58824BE2FFFB29F9DF4865567A2A0665D54FA31F8DFE9AEA69FFCBFFF0FE",
INIT_2B => X"F0F2958EAD5FDF5AFF4E9239CBFFCFFDACD6C7FFC9FDFEFE5DA67862C9ED25A3",
INIT_2C => X"F8BAB4298EFFFFC36B46DFFFF3FDFFFE0971FE23CE1A54854109A7FB4BFC3F98",
INIT_2D => X"19EBFFFFFFFCFFFE5AE2EF6AA84EB332BDB8946879E0DF8E83C7CC524E17EE1D",
INIT_2E => X"1A9145C7E9AE69DEE1023B1FAEDF1FEF07F7FE91B2AFC3BCBF5B83B82D7FEDCE",
INIT_2F => X"73B0E3504F7F3F8C67EFDE4085FFA752BCEFA2BC4EFFFB3FAC8DFF9FFFFEFFFE",
INIT_30 => X"FFC7CC3FF529B99AF8932BD33BFFFF46A6B0BEFFFFFFFFFE551A805ECB309A24",
INIT_31 => X"1F5E2E3EFFFE9E49DFB4B3FFF1FE3FFE712EC35736F4F492E67BB1C64EFFFE6D",
INIT_32 => X"FD8A9FFFE37FBFFE7E80E469A8718EDDCD3F6516533FFF8BFE85FF3E9E726106",
INIT_33 => X"1F3EF7888CE70E154FC454636E7FFEDBFE57A37536CF57F7029AC4F3FF4203B9",
INIT_34 => X"10435E5BC0FFF547FE6FF374BF27E78A9F3427FFFCCCBD95FCB8F1DFFF3FFE2E",
INIT_35 => X"FFC7D76CA14D7B8D003F8FFF7F36038EF8C67F0F3F3FFE1E7BC09919D3C921E4",
INIT_36 => X"1CFBED381108DFBE2D8C67FF3F87FFFE7E54A383C3E6B674A5034FC226FEFA5F",
INIT_37 => X"64890FFFFFFADFFE37D0C911C437BD83BC9B0FF4AF3F88BFFFE7B3693D0AE830",
INIT_38 => X"45F12880FDA812BF7D80A7FB7F37C9BFCFF721AA0E68D02CDD2BA97FE392BFF5",
INIT_39 => X"84198F77FFAD51FFC7FFB36DEE16920DD9C81654854EDEA9666D0BAEFE3827FE",
INIT_3A => X"C7FEE2C95347787BC38523D7F6A09F2B83DE458FFF070FFE6136F75C7C2585B0",
INIT_3B => X"037F22E7CCFE5E9E5C217FE95FFFCBFE4346AADB1B04CDB8E4E7FF7FFFB13FFF",
INIT_3C => X"FFFC02704FFFAE7E4622AF048AAFF600209EFE7FFFF063E7FF7F3E1A6287A2B3",
INIT_3D => X"50281183DBCE801E278FFF7FCFE1ABA7F0FFE76DE8CF63238ED997DA1F319FD5",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"027FFFFFF7EAAFAFF16CBE6BC30FC023D2C1BAFCC42B4EAD99A5A394EFFFE7D6",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFE1002E9119ECD8547247ECF493703A55FDB09BFFF437A34F70BC34DDC5EE4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_2_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"989BC8BEAA3AC56D387307616FFECF623CDE0110B945D82967FCFFFFCEB5BF8F",
INIT_01 => X"FF4364FB0F7E87D227ED03FF9736DFD98FFFFFFF7ECC5FFFFFF43EB73D2BB4FE",
INIT_02 => X"64E584E10EDF9AD63FE99FFFF8BFFFFDFFF0BEA8DEF0C2C1195A59FA847C1B2B",
INIT_03 => X"FF153FFFBC98FFFCFFFB3EE89D332D222B8774992E706FF9FCBA636AFFFC98B0",
INIT_04 => X"FFFB9ED9FE58A020E8FE95ECDB34F1EAA2892143FFFB2F926F4CFE2AA681E889",
INIT_05 => X"FFF920AC810219790D21C607DDF9993A72D5FB6F0EED0C0C7F18CFFF169593FE",
INIT_06 => X"01F40D4CA9BF2B161FAFDB08D23836C6FF528BFCB0D7E9FF7FE90C1D74F0F379",
INIT_07 => X"61C30682B3EFB63F1EA1ABFCC4EDF0FFFFCA7B0E263C8C7A22E3B3BD96FB2EF6",
INIT_08 => X"97AD4FFE5F53FFFFFDC0FFE530C9F5F525C2223DC6BE52E428D0EDAFC13C2B1E",
INIT_09 => X"FCA73C8D5A82BD0A47777C4210BF21AFFE20AA5FFF0788967280796F5EA86D3F",
INIT_0A => X"84798A8A39ED22C46723DC3FECA58F462FE3000BA4EBAFFF1E981E7DD89BFFFF",
INIT_0B => X"8D29B8F814DA9CFC26B3352401BCEFFF52711FFE23BBFFFFFC1FFCC1AA6F971D",
INIT_0C => X"67188DAB415BDFFC4E593FFBB33FFFFFFEE8FCCB9B72BDF417EE5317FBC3FE85",
INIT_0D => X"8F2E7F3A8DBEFFFF3FE1FDA11E6205BBFBB36B7374FD4AF7F49A61E7D71F7FE2",
INIT_0E => X"3F08FD512F3DD179E537423187973D7A4A067BC081BDDF8A1EE7FD77FEBEEFFA",
INIT_0F => X"5D6AE49511016C7D4E87AA0394BFFFA03DA7B59216566FF666D87F67087EFFFF",
INIT_10 => X"90D41200DFBBF878240CC94A18587CC7531FB91ECDBFFFFF3F0FFDDD0E1BAEFD",
INIT_11 => X"7491607D4E66EABE93DD77577BBDFFFF3E2DFCB5B266D3F83455E08B51FA0177",
INIT_12 => X"784FB287ACFFFFFF3D8DFEAAF2031FBF1CE9DD40D7C70357DB8A087F9EFF7EE8",
INIT_13 => X"BE77F90F25CC291E9459FD1025D1F66223DCA59FF9DFF75A5CED4CDC6576220F",
INIT_14 => X"017FEC91C8E8C915CE38F0C7F02EE7F679DDCDEE8F9299A2DB38201F517FFFFF",
INIT_15 => X"4BA4B0DFF37EE7D62EB8C89EFCA8E1174968AE1B0EE7FFFE74D7660065B4D70F",
INIT_16 => X"3F166BCF3C11CE5BE8CDD20A23E37EFFB95F7B9D89BA67CED15F69DC908F199C",
INIT_17 => X"7D682BC64FE728BFB457EB994FC2B9CE8C13F2C4A9248390F7CE8B7FC45FCEF2",
INIT_18 => X"9CAE9966E22A71FE4E3BBAFD8DB16281721DC5E7C94CAFAE27FDF65F79A430F7",
INIT_19 => X"24D3FBFD8563C7F06A7696F7F5D56CBA723B8F9FE01796FCD32041C497EF3E5F",
INIT_1A => X"8EFEE0377B066F52423F1EE7EC33A970C7586FCD2FFF134CDBEFA2736415F2FF",
INIT_1B => X"3B283F0DA5084DA371E6D2275FFDB14BE4A7E982741C19FE0230BD4BF65DD516",
INIT_1C => X"C1E0341FDDFF7EBFE35325BC671DDFBFD961A26C1011AE73927EFB6E9E7F27FE",
INIT_1D => X"A113C87D4EC9553FB075EC2F163AF6F8DFCC684533FFDBFE2673FFFFCC258FAF",
INIT_1E => X"B979EF88B4BF9FFE69827B43D41FDBFE645AFFFE4A212EB37CDC3BC9B8F4C8FF",
INIT_1F => X"90A761D6E7DFE7FE46F7FFFC05D82C1CBEA819547FE41DFFE5A3D6B0FF0E1F3F",
INIT_20 => X"5C6FF7FBF0305135BFA0E095FF8A8E7FCF67DB705644D1FFA043F3086E5623DF",
INIT_21 => X"7FBCF8F7BF5743FFC8DFF34B5296F07FFB03FC5263363FAFEA5D35A7BE15FFFE",
INIT_22 => X"CB7FE069EA2D36FFDD33FB21CCEB95DF781AEDCDC7C3FC7E539FA7F6E47604CF",
INIT_23 => X"D124FF28702093BB1BC41C9EBB1FFB121A57F7C09D8217C1BD59C53F3F5E7FFF",
INIT_24 => X"48FC52663C6613AA6FFBFFC26E86C9F6FE77A7CAFF46A0E7FCFFDE6C9CD2D77F",
INIT_25 => X"2FB1FFCA49E798DC329E75A5FE3B6AE7F7F6BB0CD6278B7FAD62C4EF306D4783",
INIT_26 => X"4B6A6E6FEE2E87D6F8F5723C9070B4BBFE2A6918F0A89C58DD36A3063FF7FF32",
INIT_27 => X"ECFB055E06735B9FE385C9EAF7E9886470AB0410FE9FFDC6417FFFFBED396F1A",
INIT_28 => X"E263CDDE9730364EFACD5C9B3EFFFECE73FFADDF681ADBFD91236C7FFB2DBEEF",
INIT_29 => X"FCB36ECA478FFFFE7BFFD6F6D2E30BF047F5421FF3F57BFA02F6E0F6F5B34D8F",
INIT_2A => X"7FFFD011D74572A0B11E81B7BA49A5B86CE08BCAEC01723DEC09949E97FC4DE8",
INIT_2B => X"CD2B72FFF461593E25ECB42C88F8E0DF7FF386D18B157EA2B0F43EB507C1FFFE",
INIT_2C => X"07E22E5D98CF549FF428C70E7CC96EC2BF706A255FFFFFFE7FEFB6CE3A04675A",
INIT_2D => X"FFCA31F7390A9F1B1F83B9726FFFFFFE7FD76A4CCCEEB99C977902797F8B7D7C",
INIT_2E => X"6F17A20587FFFFFE1FD53A9C98D3A4570526D579BD684E7ECFD9C6E981A035D7",
INIT_2F => X"38E1E3A2F3C36A061351D2F643294E7A197D80B38916478A7E0B56677EDD0C53",
INIT_30 => X"81A4CFE53D35FF3F676551514E87AFF1909300E4AFFE9D8FBF87ED013BFF9FFE",
INIT_31 => X"94E9C8A4E41D01C6A3014DE5EF5BDCA50FEFF00607FFBFFE4EF9076D7E7843B7",
INIT_32 => X"307C8B2FCFE0F87CB1FFFAD21FFFFFFE4EFE05DD8A42F6772D72F1FBACDD2F79",
INIT_33 => X"9CFFFF494FC7FFFE7FFCF419B7C12BBE5DC903FE2A4A2F7F91FC149C08F982BF",
INIT_34 => X"7FFBFFFE5620AD99692533FD7CD12FF134E0014E6EA7372EF7B9E6F2FFF0497B",
INIT_35 => X"B7C46FCC8B5C3F61DE20430A188B2DCDC2D612AA7FA9DDAB5B7E3FC10FFFFFFC",
INIT_36 => X"B97AA13F31BDD47B958E46EFFF8492C3A170FFEB8BFFEF3E6C36FFFF5F2004A9",
INIT_37 => X"5DF7DBD7FC33B26E94D5FF7F9C7FFF3E61E1FFFFCEBA15EA27A4F2BE5BFF47E8",
INIT_38 => X"96F87FFF8F37FF3E6087FE1FFFF567EBB7412343227C47F3CCF26F6DA24C643E",
INIT_39 => X"7FFFFE8FFFCEDFF2013EDE8EAF0D73FCF7FF75C081617DCFBD6E2947FFFA72C2",
INIT_3A => X"988D7726A780739DA1F97DB1206EC572C243CE5783F70E3608B9FEFFB4A7CF5E",
INIT_3B => X"5DF5BB40CAF03D66512BBE4BBF7BBCDC5FEABFBFCCD019761FFFFE7FFC56F7F3",
INIT_3C => X"E8C08D9DD3FEDA5C8CA0BF8FF4A9C46A2FFFFEFFFE687FF8396FF809CC41F3D8",
INIT_3D => X"F4E39FC3FFED42EA07F8FFFFF8D47FFDEDB0FDE0DEB4FF9FEAAD7743A7DF5F61",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"79FB7FFFD6FA07F77B1BDDEEADD9FF65378A5DC565AD25609182B849E0FE91AE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"B929DFF4D12CFFA25EADEAABAE67F660B9D77D2438EF661D7FC78FF1FF2EAFE0"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_3_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"3FEE7A4EB9EDABDC4FE89C9D42EF0C2AFEA78BFFFFE31A167B9B7F3DB916F3F5",
INIT_01 => X"F7FC15134CF7C80AFE07F3FFFFF444787B4FFCE5E7B787F6DC247FB5CF30FF47",
INIT_02 => X"7E17FFFFF3FA16187B9FBADF657FF3FF3A1BFB2704743E8AFF3D46FEBEE32F56",
INIT_03 => X"73FF828A387FF7EE018DF44E1D7C3F3E1EE6AF7F4EE509FE7FE109BFA6F7CCAD",
INIT_04 => X"9F9AF6A28C8FFBB7E617CFC712A598FC5FE02699A0FFFE832FE3E7EFFFFE8780",
INIT_05 => X"FE1F53E34CF998FC5FE7FEA7C47FCDF4AFC7E7CFFFFD73925BFFFE38C0FFDFE4",
INIT_06 => X"67EFDC230EFFCFDDC7C1FFCFFFFF420C67FFC0A7B1BE6BC4700CDF820C8ABDD5",
INIT_07 => X"FFFDFBFBFFFFDFC87FFFFECE46FEE7CD31D1D873DDB65EDF9857F7B33EB7F8F8",
INIT_08 => X"7F8FFFF92F7EFF8EDDE72871550516FFE96D37A2CC8B3CD039FFD32C90FFE439",
INIT_09 => X"43FF067C56D7665BA159FF42929E08F287FFE6D647FFEC51FFF168F0FFFFFD38",
INIT_0A => X"FE5FFB25CB3500F33FFFFDE231FFF5737FFAF1FAFFFF7FCE7F77FFFE30FEFF97",
INIT_0B => X"B9FFFAEAF7FFF5A33FF978FDFFFFFFE07F2FFFF2CDFEFFE60C7FB277668FE26B",
INIT_0C => X"D72F7BFCFF7FFCB86FFFF66E193DFFCE081FC23CA6B9F9C7BEF4BB81EBFF006F",
INIT_0D => X"47FFE62114FDFF5FC5878ABD392FF5FB9E0E3A8F7640E07481FF79DA2FFFF0DA",
INIT_0E => X"50AEB2ED514FE7EF254C7F47F9C8CF0285FFF8D43F7FF602CCCFFFFFFFFFDFA8",
INIT_0F => X"8A2F7ECFFCB460C1E3FFFCB1C6AFF17E3ADFFFFFFFFFCFF00FFCC4F4FAFFD6BE",
INIT_10 => X"25FFDD08347FB397D2FFBFFFFFFFCFF84FFA77B8C6BFD7FEF61EBCCA500FE8FF",
INIT_11 => X"07FE07FFFFFFFF3C7F0FAEE65F7FD7FEF77DC23E5DEFCAF9827D3E91FA740C7F",
INIT_12 => X"7F9CCB6D7FFFFFFF67726F7E3D47D27812CEBF7EFFE4CF3C51FC5E1FC7FF7BFF",
INIT_13 => X"E6FFF371BD57E5780CAD3E63F09204D9A3FC1E7146EFFFFF31FEAFDFFFFFFF3E",
INIT_14 => X"11BD7F87B79F6B6EDC7D9E56423FFF07B5FCFF6FFFFFFE3E7FE329A07EFFB7F8",
INIT_15 => X"EA7FBFCA57DFFF1BC3FCFE8F9FFFFFBE7BFF3FE4BFFFAFF2227FF96CCCC32F33",
INIT_16 => X"DFF8FD5F1FFFFFBE73FFBC9EBFCFDFFEC8FFBCA7C938B927037F5D119729077A",
INIT_17 => X"63FF2CDF7FE7FFF8BDFCC0FAD011F7B97FDADD33E7BE38E7E43E77DADA3FFEBE",
INIT_18 => X"3554921D947F9BB8CC6BCE6DF3E7C424E27EEBE8389EFFFDFFFCF19FBEFFFFFE",
INIT_19 => X"6561EE71F1F31254D43FE3F1849FFFFC5EF8FD5FCFFFFFFE63F99363FFC7BFC5",
INIT_1A => X"D2FFFFFAC65FFFFF7EF7F32FD7FFFFFE7FF4807AFFFFBFC50916A865F947C5BA",
INIT_1B => X"FEE7F377E7FFFFFE7FF8364FDFFF3FCFEDB80AD30A07C253D9B8FFD5F1FEC70E",
INIT_1C => X"7FFFF9D9BE3F7FD8483E587AA40689641B08FF33F7FC71F3527FF3FD835DFFFF",
INIT_1D => X"577B63FA8C6F3345E1B7FAD7F7F1890CD77EE4FE7A5FFF3FFFE7FA80FBFFFFFE",
INIT_1E => X"0107F893FFEF630E24FFEFFDE9BFFFFFFFE7BF7BFEFFFFFE7F9E6D3C7E7FFFFC",
INIT_1F => X"DFFFF0FD5FB7FFFFCFE70FFD37FFFFFE7CE26134FE7FFFEF5ACD3022997E7D7F",
INIT_20 => X"B7E2BFFFC3FFFFFE782687B7FCFFFFFB79D6D723373EE8E16275F693BFE8ED70",
INIT_21 => X"70E2A42FF8FEFFFD52BC87E6EEFEDBF372ED3804BFF291EEB1EFFBFF1AF7FF7F",
INIT_22 => X"7F8E0862907EF7F13939665AFEF6DD665A91FFFFC8FFFFFFE7E778FF3BFFFFFE",
INIT_23 => X"23D66CC3FEF4E4FEE7AFFFFFC3B7FFFFE7E1FFFFDBFFFFFE6FFAB687FFFFFFFE",
INIT_24 => X"42D3FFFFBC0FFFFFFFE0FBFFF3FFFFFE4FF9F4C7FFFFFFF07FF4C9AB461E6BED",
INIT_25 => X"FFE3733FFFFFFFFE4FFE49C7FFFFFFE0FFAE7C692C96C4EC066ADBEF7FFBE039",
INIT_26 => X"1FFCFBBFFFFFFFE13FF9FDA5D918917FB17A6A5BF1F33D3BB17FFFFFDEEFFFFF",
INIT_27 => X"FFB33A2831D24EAEE7483EA175F7EAF3E19FFFFFDDEFFFFFFFF379BEFFFFFFFE",
INIT_28 => X"9137D53A79FF5D23BB7FFFFFFF97FFFFFFF7F93EFFFFFFFE1F67A60FFFFFFFD7",
INIT_29 => X"CD6FFFFFE1FFFFFF7FFFE2FFFFFFFFFE1FE810BFFFC6FFD87EFFDD456409347A",
INIT_2A => X"00000000000000003FD33F7FFFC67FE2F71E26E1FE4C3C858222D832FCFFD068",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_4_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0FB400FDDB4B6FC0816988FE2AE7FE3841F3BC180DF83AC40000000000000000",
INIT_02 => X"F04BA2003F2FFE19AC018000427C7AD452189680BFFF60E7DEFFF0AFD576E061",
INIT_03 => X"640D0000E6282F341403F74077FF5B4C7CF0AAB09F54C0E607ECF029092B39C3",
INIT_04 => X"55FB0A55283FE84107DF8BA2F825046D370C600B6B249ED4805C70003E7FFEDF",
INIT_05 => X"67C0C96185D7476E37832002B13873645A9E9C0022FFFF7DE16D0000E76D2602",
INIT_06 => X"078340F11A41F0A15DEB9800827EDF7C26038100C00CE44A1BB5EEBA1BAF66C0",
INIT_07 => X"99F0B2028BF1EF7C0C07C000010973EA1FC6286C6A8D9971E700B729E7924A44",
INIT_08 => X"F80D8000E0C47D205AE7C3280B1AFF4603010E790955CB6107010089F589C9C2",
INIT_09 => X"3B8EB1666DD3ADA8C000D6951896DD2B0300C06E0074595E462792008FDAFFFF",
INIT_0A => X"7420AEFE32F7AF77ED497000669140468F588DE00E4FBCFFFF1C8000DA21D272",
INIT_0B => X"BC83800000EA6457639C0FE0CC919CFFEF1C8000D105213E3E1A4AD6B5D5F652",
INIT_0C => X"4BB04BE085A01DFFFE1C00004E0E3FFE136EBCE87800FD2764008E00EAF6B7FA",
INIT_0D => X"E60C00005117FFFE428D1DAB872BFD86040004FF244AE63F21AA20E025C9445B",
INIT_0E => X"6663E5BE8C1FFC8300FD00035FC8DEBFFF03ECC0207A34782461FCE08258BE7F",
INIT_0F => X"000080005AA85B755A480EC7DA5B667070E3FC0009DBBC7FE00C0000738BFCFE",
INIT_10 => X"E734C1036F9279E844E5B9000EC9B97FE88C0000517BF8FE72F1657326BBFD32",
INIT_11 => X"2E8830C0865AF97FFCCC00003285F8FE031D2EA35B13FEFE008000002FBEA477",
INIT_12 => X"FEE40000155AF9FE00EFAA8A3515FF9A00801F100045AE40E81245006418CBE9",
INIT_13 => X"7C0AF43E5B00FF9D40000E10EDD00DEEEE1D8600045427129F7BA8C10331767F",
INIT_14 => X"210000037D436A69F133D00D31CDAF677AF1EE38CFD2797DCE60C000FD96FFFE",
INIT_15 => X"F714A5627981F61ED62F303DC1597E7CE87FC00897A1BFFE7F1BCE058F50F7E7",
INIT_16 => X"3E8C8A31340A727EDD980004349C3FFE7E67DB59CC373BF0210000010A9E821B",
INIT_17 => X"FC7D00006DE77EFE7E7A9040CEE730FCA00000005B9FF9F5EBA57671DFDEF8F0",
INIT_18 => X"7F2CCC80809582FE338000006644FF24E7A8007B9E9DEA0BC3413E3CF6786AFF",
INIT_19 => X"53C0000355E5FF3EF0760EB2017A8DEB67D84686B939EAFFFCB90068D1F88EFE",
INIT_1A => X"3BF7D8B61A4F9CF0DF21CEFB81215DFFD7AF0060B7FC9FFE7F2844A781AADF7F",
INIT_1B => X"6F743D687FD8F9FFD7CF0062CFFEB9FE7BDA1CCB00008C3FC80000042F7540F0",
INIT_1C => X"FC0601C3FF7DDFFE7D70E7FA0003BA11EB0000003EDB093E31E7FC0AFDC71BAF",
INIT_1D => X"37B9106F0062E038CD8000006E90B21AED8FFCBC34B2ACA5F123D352BAB3F5FF",
INIT_1E => X"6A730007C4AA1C3E3FEDFFF8DA1DBF8B65F3A709423781FFD20601843E3E45FE",
INIT_1F => X"0384FFF141DC195A58E502F40165A1FFD66E9FB0FE3816FE7FE20E0895000E62",
INIT_20 => X"4DA252FD57D5DDFFC5FA813FBFB1A5FE7FFCC226B70000808482000FD3A0A221",
INIT_21 => X"8606C8A2BFF8AB7E7FFE341AA1CF03071EC3001E3688EE98D3FB7FF0B4BFA562",
INIT_22 => X"7FFF959D196F00A18AFF1E00ED80474BFF3B97FEA02BB3A31DE4BEFF4A5CC3FF",
INIT_23 => X"8350CC00AD8F187AB89F67FEFABF28BD682235F109A88FFF84E963D13FE73D7E",
INIT_24 => X"2F4B1BFFFFBD1DDEFD8CF7F69AB80F7F37593C57FFCB2A7C7FFFBF4517360340",
INIT_25 => X"9043E1B69C97F77E306166E3FFC7CA7C7FFFB8EA01F8983BE013E0DFD9D570C4",
INIT_26 => X"FAFFEB37FFDD5ABC7FFFF5E92E381906C6C2FFCEF568996B8D9E08BFA88DA559",
INIT_27 => X"7FFFE81633D80658758603E75F339E678FBE254FFE60CCEF28DF86C57EFFE7FD",
INIT_28 => X"1630E87BD4C52F1D806216CFE631D91CF4BDE64AD89097FC215A3BBFF7AA5F7E",
INIT_29 => X"BAB187E3F33C59FFF1DED823B18D6FFB1BB2136FF779569E7FFF611FEFF04128",
INIT_2A => X"F4DE9CF132B14FF80EF0C7DF8663887A7FF80F37E34C5801096FF13C41068DD0",
INIT_2B => X"E1F10FBFA1E62BF87E88F1FFF716BE335109BC1F41B8FEB679B1BDDBF84CFD5F",
INIT_2C => X"7EC18D3FEADE0409709F3EE6C06CD4A966A095487C7652FFD5BC57A13D52CFFD",
INIT_2D => X"075C2A7B8A0A44EDBA083822DF366EFF8FB1B283C5E17FFFDDF7F0FFA915662E",
INIT_2E => X"3BB6020FC825B3FFFA9A0A185FFEDFFBF7F506DF8A54BDAE7E1628BFE62D90F9",
INIT_2F => X"978679E5C7987FFE53FB065F8575BC283E99540E7F629CC51F77DE390C642BC0",
INIT_30 => X"DBFBC8AF9977EFC02A9EC72607F681C3FFC1840CB6B0C3A027C50BEEAA2747FF",
INIT_31 => X"354F6B0853A934FA7FE3E38C455090A7031589FF20CFFFFFFE6FFE7555A1BFFC",
INIT_32 => X"FFF5FDEF7D3F2CA1014EF69CF1A08FFFFE9CFA210ABDBFFFFFFBD79F4FA37FE6",
INIT_33 => X"6C41850DFEDA8FF7C8BC99BB4F6E7FFFDF79C29BECB3FFDC2DFFDF7236D3EE85",
INIT_34 => X"8FA2077E36913FFB1F8C32B0FE86FFE013C1DD7D75F4A727FFF8FF5B30FFA4C7",
INIT_35 => X"D7B8A474BBB3FFB82C727A85EBB4F22FFFFBFA9D46FFDAC2C34CCC5EFFF4DFFF",
INIT_36 => X"32947F88C22FED17FFFBEF09C2FEF4EB61CD8897FFFD5FFCAF6BE51F4250FFFD",
INIT_37 => X"FFFFFDC94AD67A02D94B49013FFE2FD402D65D1F655AFFFFBD7C89EDDA99FFBE",
INIT_38 => X"F24201D26FDFE1116D57D8FF23AF7FFC8FF0B5E5FFB7FFBE41917E717EA28B83",
INIT_39 => X"E1DB13FF827F7DFD125447F3F01BFFFA7103FF9721868DD3BFDFFF09C897FD4B",
INIT_3A => X"E77F0DFFCD5BFFA44B939FAD26B3A8FC5FFFFFDDB357FCF2781055D8D80FCBB7",
INIT_3B => X"151DA3C524F30D80AFE0FFC09D4FFDEEFA5817ED8B836D5FE12785FFAB98FFFC",
INIT_3C => X"7FE0BFEB3893FCA6FDA1D7907AE65197FA7FC3FFB07F7FFE25B71BCFD01BFF58",
INIT_3D => X"FE7373D3CD9E60EFECFDFFFF32AC7FFE8E1F07FF502FFDC01B60EFED132D8315",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"EAE6AFFFF5AAFFFF67A153FFD46FFFB230CAB639F693BE0633F8EFE75D67E673",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"F7BA3BF797BFFAA449DA090400E47407E5FDCFFC331AE703FA0810729817FA7F"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_5_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"4E79EAA625573F0F867E47FFAC88777DFC49D77A2C27FFFFE0052FFFE32DFFFC",
INIT_01 => X"06BF3DFFAF5AB7BDFE93D79CE92FEFFFE12A4FFFED6AFFFC6751C3E7FB3FF4C6",
INIT_02 => X"FF9D6115D671BFFF64951FFFFAC3FFFCDD2F0FFE383FF0587FA2D2AEE04E8F0F",
INIT_03 => X"B202BFFFF8C5FFFFC6215FFF3E7FEFC87FFFC59F70E36D0005C724FFFBAF37D7",
INIT_04 => X"7844BFFFED7FF1183E663087E504AC7FDC1BC53FE2F74FCDFFF5C14D0E357FFF",
INIT_05 => X"7ECC51B88AB8FCFF6012F23FFE23C7E4FFFBE155E45AFFFFFE05BFFFE18FFFFE",
INIT_06 => X"E17E7CBFFE8727FEFFE07D870F7BFFFFFB383FFFFEDFFFFCBC9BFFFCC7FFE8CC",
INIT_07 => X"FFE0C7C0815BFFFFF7D37FFFFEA7FFFF1D07FFFDBDFFF7C07CD4C1A3C5E7B727",
INIT_08 => X"E26EFFFE69EBFFFF6DF5FFFFF1FFEF5C7748D4A1506992B85E0E63FFFED649F8",
INIT_09 => X"6B61FFFC75FF7920776918E60EA2EC65B0094FFFFEC8E7FE7FE48BF37848FFFB",
INIT_0A => X"2ED10147C2E0C60659A379FFFFA3F3FEFFEABA0BBF522FFBEAF0FFFD4237FFFF",
INIT_0B => X"CC06DCFEFFCEA6BFFFF9C94B989FE3FFF1FEFFFA2E7FFFFDC207FFFD4BFEE61C",
INIT_0C => X"7FE5DBFFB7B5B3FFE3FEFFF70D7FFFFD350DFFF36FFC696E5BF06436E4912FBE",
INIT_0D => X"F1FEFFF2E9FFFFFD84B7FFFB5FFE35DE2707FE99A2FF65FFD30C08FFFFFA05BF",
INIT_0E => X"F83FFFF497FFAAFE30006680124257FF7820B22FFFFDE1FDBFFF0B4C111E93FF",
INIT_0F => X"00F06467C0888BFEFC25A0D7F1FE93F23FFFBE5408B8EEFFDFFFFFF3F19FFFFD",
INIT_10 => X"FEB79C97FFFD4B12BFFF7F0E337A38FF5BFFFFE3A03FFFFEB027F9FA5FFE383E",
INIT_11 => X"3FFEFF3415A76DFF57FFFFF4517FFFFF1387F1F63EFF38FE001CF83E9071A3FF",
INIT_12 => X"E7FFFFFFC67FFFFEFDAFFFFB3FFD1ABE0600F80011027FFFFF1AE601FFFF588E",
INIT_13 => X"977FFFDA7FFCFA7E41030010813C6FFFFFC4A4AFFFFFE104FBCFFD426969A27E",
INIT_14 => X"113F803C7C3721FFFFC7BD7B7BFFC8B99A9FFE4DA487F7FDFFFFFFFF91FFFFEF",
INIT_15 => X"FFFFE79ADFFFF8030827FF742966727CAFFFFFFFB7FFFFEC637FFFD2DFE75FFE",
INIT_16 => X"2593FF25ED0FF6365FFFFFFF057CFFFB8FFFFFA0DFF64FFE2811803E0C0639FF",
INIT_17 => X"BFFFFFFFF1FDFFFF1FFFFF615FF13FFE4030001FE004CBFFFFFFBA3D3FFFFE53",
INIT_18 => X"FFFFFF303FFF3FFC47270000E004F5BFFFCF9F1EB3FFFE5BC613FFA9825FF1F3",
INIT_19 => X"577700080001E2EFFFFFFFFB4DFFFF0FFC57FFC9069FF690BFCFFFFFB3FDFFFD",
INIT_1A => X"9FFFFFF266CEFFF16587FFFD0F1FDFA0FFEF1AFF0BFFFFFBFFFFB6B97FF7EFFC",
INIT_1B => X"CAB3FF6C9CBFDFACFFFF23FFABFFFFCFFFFFBE139FCABFFC24F6040E00819C03",
INIT_1C => X"F3F361FEFBFFFFC9FFFFFF5E97D67FFE3F95200E0000E343DFFFFFFFDF7DFFFE",
INIT_1D => X"FFFFFEF0BFBC7FBA154AB800000073A67FFFFFFFD416BFF9AAF3FB226F1BFFF7",
INIT_1E => X"08EDA401001B031AEFFFFFFF7AE4CFF862FEF58F74FEFE51EF8D39FFE7FFFFEB",
INIT_1F => X"57FFFFFFFEFC47F612BFF3D0A4CBFF63D7B294FFD7FFFFF7FFFFF8B4FFAAFF8C",
INIT_20 => X"BCFBF586E85F3FEBEE2750FD9FFFFFEFFFFFFD303F86FFDE5D3814310019DFF7",
INIT_21 => X"FEA3527F5FF7FFFFFFFFFFBCFF8FFF6004D7F0200016432FD27FFFFFFFAE15FF",
INIT_22 => X"FFFFF7C87FDFFE40740C880040092548B84FFC7FFF6059BFD28FF29D8645C7E3",
INIT_23 => X"146C95460009C581D6E6FA57FFD38BFFFF3FFB75266DC3CFFFD8497F7FEFFFFF",
INIT_24 => X"1B220B3B9FFF1C6FF5C7E2D735D9FF81B7E9C5181FFFFFFFFFFFF7697FFFDD86",
INIT_25 => X"FAC3CB09D7BBFF92CB77427FEFFFFFFFFFFFEE81FFFFE4D241EFDEC0E9013A81",
INIT_26 => X"7B4721F34FFFFFFFFFFFE8517FFF9C6401EFB8E038BE964BEFAB7243BFFF8D37",
INIT_27 => X"FFFFD0F5FFF0771C0007F40052F9E5912142F5E3FFFFEDF69DF3F9D77E33FFB6",
INIT_28 => X"18129200107FDE078C03F591FFFFFE808E77FABEEB31FF9FA287CDFD3FFFFFFF",
INIT_29 => X"0083F5947FFFFC07D7E2FFE653A33F8FFFF807F05FFFFFFFFFFFDBE0FFE15DF6",
INIT_2A => X"0BA4FFFFB8273F2BFF4B7FFFFFFFFFFFFFFFEE41E7C15F9E101EC4006626BE18",
INIT_2B => X"F199BFCE7FFFFFFFFFFE44FDFFC81FBE00FF8A0049BF8B38F38160ABBFFFFF57",
INIT_2C => X"FFFE9DDFFFF13FFE00002000E1E4E896E115CE08F3FC7FCE4A569DF93CAF305B",
INIT_2D => X"180CA000F338F075C00CD03B55FCFFC9F6CBD3F77257E78A3A5EBF521FFFE7FF",
INIT_2E => X"BD1056B1AAFEFFF8D3A04AFA55EDB2D9F0CD1F595FFFE7FFFFFAB3FBFFC47FFE",
INIT_2F => X"278ADDE590B146742393CFDE9FFFD7FFFFF2BBFBFFEF3FFE08008020B715E8F0",
INIT_30 => X"9751AECBBFFFAFFFFFF9F7FBFFF8FFFE010000806197EAE4448DF0FC6E3FFFFD",
INIT_31 => X"FFEFC7AFFFF8E3FE3EC00000800C362D02608BAD793FFFFFC59780E4D12C7EC4",
INIT_32 => X"00C00000C07765C8E26DB6A1E54FFFFFF32570D40FACFE7E982CAF9EBFFCB7FF",
INIT_33 => X"66D6828C0054FFFFFAE9394F1CAE7D7F73AF35F2BFFBF7FFFFBD5FFFFFFFFFFE",
INIT_34 => X"FDB8C3CBDBACE73CFF0BF54C7DF92FFFFFD40FFFFFFFFFFE38C00093000B13F0",
INIT_35 => X"B9DD03D53FFFCFFFFE5F9FFF7FFFFFFE1000006903C4AA30583E384A00A53FFF",
INIT_36 => X"FDE56FFFFFFFFFFE0B800091C33D548086EC7A7F8014CFFFE7C160443B772049",
INIT_37 => X"268000A1814E7100E41666C6806967FFCBF627361EF240B817A4FC3FFFF253FF",
INIT_38 => X"048B8407C18027CF9FFF78764F5D5C5EB5B27D20BEFDC7FFF9F77FFFFFFFF3FE",
INIT_39 => X"DF39EFFE8609DCF5B1A3021AFF9C9FFFFE0DFFFFFFFFF1FE0D0F000051C0F24B",
INIT_3A => X"F87270A67F203FFFFB5FFFFFFFFFFFFE7200000077C1B34DF5B9B217030E2D8F",
INIT_3B => X"BB5FFFFFFFFFFFFE060000FF2E205ABE564EFA030FCBDBFFBFCE6727CD4736F0",
INIT_3C => X"310C00102BF678BC708CE9D278BBD32E1FAE040DC69EF55864C80D6FFE037FFF",
INIT_3D => X"FFB342EF13E704A25F804007FFB2AA5A8AEBFCA6FCC0FFFF0AFFFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"37A94100C1AA6A7F1DC2E77BFB1EFFFA5DFFFFFFFFFFFFFE311C0000216AFF1F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"2111C1B6FD88FFEF79FFFFFFFFFFFFFE71000000F0B3E0FFFFFD08FA88117C5D"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_6_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"AFFFFFFFFFFFFFFC00030000F351F6FFFFFF1DF9D72468DFA2B94681FC5CF74B",
INIT_01 => X"44078002BD3FFFFFFFFEE9FFFE86448D0B160FC2B9332CF54107819852CDFFF8",
INIT_02 => X"FFFF07FFFF57BE0E24C81FD7F2CCAB533883C0E1B46FFE973FFFFFFFFFFFFFE2",
INIT_03 => X"0253001312032B7E31EB51CFD187FDEE9FFFFFFFFFFFFFF64F8780060657FFFF",
INIT_04 => X"FB66A20668FFFA9C3FFFFFFFFFFFFFF40706008103FFFFFFFFFFFFFFFFF7EBA0",
INIT_05 => X"FFFFFFFFFFFFFFFE000001835BEFFFFFFFFEFF9FFFFF3D0330F0009A93F07E13",
INIT_06 => X"000000534F4FFFFFFFFFFF0FFFFE7D200001019F5055B85B3413E4635E17FBDF",
INIT_07 => X"FFFFFF8FFFFFFD99830003C92025704217D7559B90CFF583FFFFFFFFFFFFFF2E",
INIT_08 => X"19A00880C02C06FB6440B586558FF697FFFFFFFFFFFFFE5C10870003908FFFFF",
INIT_09 => X"EFC6306FD90F6E1FFFFFFFFFFFFFFD34008701CE1937FFFFFFFFFFFFFFFFFF9C",
INIT_0A => X"FFFFFCFFFFFF840C00C002D417CF7FC5C48FFFFFFFFFFFF82080180018D90F38",
INIT_0B => X"00F024F1C8835810D6888FFFFFFFFFECF0C0080C18B8F9A2F00E5C572C6D1DFF",
INIT_0C => X"09CFF1B83FFFFFD8C018C08073848B6D11615896DDCE43FFFFFFE0FFFFFF012A",
INIT_0D => X"A5D880004674E39669ACE543CFF357FFFFFFF0FFFFFC92F006F75F92727C6D60",
INIT_0E => X"7EE896627F813FFFFFFFFFFFFFFA36A402F32AEC64746036710F7166F9E7FFC7",
INIT_0F => X"E3CBFFFFFFFB179A181C3C7DBAD551E1F807DC397D92FFFFE838011000587802",
INIT_10 => X"1D1CBB4E5EDD60CFF8E06199792C3FFF99D801000122606D43C49F96FCC5FFFF",
INIT_11 => X"FC2603B56D903FFF38C8010007CCE3A55A06537BB8F3FF0184FAFFFFFFFFDE82",
INIT_12 => X"1B00001F47B6BE71F86057FDF03FF8C8786E7FFFFFFFFE420078ABA11377EEFF",
INIT_13 => X"F0122B3F97BFFA7BAC53FFFFFF7FFC5C3C0445D17E6034FF0080C066F7FFFFFF",
INIT_14 => X"89A3FFFFBF7FE89426CF74EAB90F6700E019675FFFFFFFFC2F81000607297E20",
INIT_15 => X"7D6BD3E38187A10060C887FFFFFFFFFB9E7100000389069DB96A927EBBFFF7B5",
INIT_16 => X"03DCFFFFFFDDFFF95FD9804A48E84F9B2E087ABA27F2C32111A7FFFFBFFFF258",
INIT_17 => X"27E9002F00C3CC16EEE928A75FE522A9C147FFFFFFF13A5E31BA71C600E1DD86",
INIT_18 => X"A139405B3FE3353EBA9FFFFFFFCCE6CE4ACA974000109C689087FFFFFFFFFFF2",
INIT_19 => X"3D8FFFFFFFD4D56E35FE08CC001C7E6A9C7FFFFFFFFFFF798BB0000E209BBDAA",
INIT_1A => X"1F8F4D6C019CFDBF95FFFFFFFFFFC767B60C000985EFC19C00884524FFFAE8A1",
INIT_1B => X"CFFCFFFFFFFFE88F2FBC0C060DDC6C00709167E3FFD1E2CE6E7FFFFFFB4CD6AE",
INIT_1C => X"B43D0C000C47F0DA15C3641FFCC6F71CC2FFFFFFE0E3B3A87FC00C8C19CC19DC",
INIT_1D => X"C003F79FFFCB9A9FB4FFFFFF60C70FE67FE83F803DDC2D1FDFFEFFFFFFFE1659",
INIT_1E => X"04FFFFFA52B7E3E67FC110003B9C5A4FFFFFFFDFFFFC445F1B1004E0888E95D3",
INIT_1F => X"7F83688613C3A4BFFFFFFF57FE15F8DEFEE200FF089A42F08000D0FFFFC037F7",
INIT_20 => X"FFFFFF67CF4F56BFFEFD6003721B0F8A6176AFFFFFFC99E95FFFFFC9B6ACFAC0",
INIT_21 => X"FEE4A1335967AAE88F922BF7E7708235BFFFFE728E74FBD27FE4D4A33B91F57F",
INIT_22 => X"490C9FF84DC4223527FFE341725215BC7F5A542F87F2E3BFFFFFFDA1CF6C3BFF",
INIT_23 => X"8FFF48C9FCFE22FE7DD048A0E3807FFFFFFFBAF99C1387FFFD213B3B00885EAE",
INIT_24 => X"71D863909EB9BE9FFFFE897385655BFFFBF9CC19D8D12E6821F3FFF479EDE5F2",
INIT_25 => X"FBFF2D053BF9BEFFFBE2F90A5B8B69710FD7FFF41780D8DFFFE62BCBBF07DCFE",
INIT_26 => X"D5EC20035B2153EE01F17FE8BD120E3FFF6B5B57FFE7FFFE0A1883100CFC225D",
INIT_27 => X"87A9FFC6FD2FD83FFDA84F33FFF7FFFE0F14016223F3DFC6FBEED71931FBFEFF",
INIT_28 => X"E6A58CFFFFFFFFFE7D3906C89FCC7900E762BD182E9CFFFF95FE8A5833540105",
INIT_29 => X"21078718FEB1A1500C3BF39FB608FFFC43FF2EDC615A2CB587A97DC2D8DFEAFF",
INIT_2A => X"87CA01917979FFE286FC44D5C3A8FB64066C33EEF7BFF3FF135923FFF7FFFFFE",
INIT_2B => X"EFE5E75D1823EA090018CC07677F3FFDB436FFFFF7FFFFFE77F6873CFEE181F9",
INIT_2C => X"072CC64645FFFFE9D8E67FFFFFFFFFFE5EEEF50C36821C2B679727E80593FFFA",
INIT_2D => X"63D1FFFFFFFFFFFE6603350E232E5F06DE80F83A8C2F3FF33FFFD99183BFC7C2",
INIT_2E => X"2711E6076F3E0FAE4101C3F5BA78FFDB7FC9EC106E919ED400569555EAFFFE5B",
INIT_2F => X"0380030C93FFFFF7FFF1EB80BB54144C00A720E3C1FFFE90A307BFFFFFFFFFFE",
INIT_30 => X"FF81DFC09BA542C4000DE016C7FFF07DE7AE9FFFFFFFFFFE030802146D309ECF",
INIT_31 => X"009F59FFFFFFC123DE280FFFFFFFFFFE1DEA123D20F37F5C06C38E11B6FFFF23",
INIT_32 => X"3F7503FFFFFFFFFE5FFEBAE220F2066B0C004E8262FFFC13FF97C800D60CE5A3",
INIT_33 => X"0411B16D65072169C00221C002FFFB2DFFFFF7C9F7E7FECB0099BBFFFF807B54",
INIT_34 => X"0DDB5E8643FFF8BFFF9FCA689A3FF23F80003FFFFF353C6FBF3CAFFFFFFFFFDE",
INIT_35 => X"FFFFCC60518FC5DD00C787FF859B28BD7CAD1FFFFFFFFFFE5B9B5BD1108FD6F7",
INIT_36 => X"1C046056AC2B9F407D5E47FFFF7FFFFE5FAA6163000B2C079910FFFB05FFFFFF",
INIT_37 => X"3C70EFFFFF073FFE68C18C51000553838F137FFA9FFFC5FFFFFFC460000A76EC",
INIT_38 => X"503098C0013CBC800F935FFCFFCFA97FFFFFDE21612E06E01C1147EE8AC23E57",
INIT_39 => X"384BFFFFFFC28E7FFFFF4F236EF9640118311862E008FF6DD856B3DFFFC71FFE",
INIT_3A => X"FFFE81C78F36AF8300051057C8297FB4BF7FABFFFFFFFFFE669B129C014BE58F",
INIT_3B => X"007D457FEB827FA1C07977FF3FFFF7FE590E15180283C1878A07FFFFFFCCFDFF",
INIT_3C => X"65C2F7FEEFFFCDFE36697C0303E27600897FFFFFFFFFBFFFFFFEF095A11FE3C3",
INIT_3D => X"676EED800388DB1E6EFFFFFFFFFB6BDFFFFC5730BDDF9EC380C053FDFEB2FEB5",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"51FDFFFFFFE71FDFFFFC450A222FFAC3AC0678FF775BFF07BEE19794EFFFF61A",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFBB99A5A9BD8018280E5FFE1C85F52993B18425FFFE5127F6303C12CEEFEE5"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_7_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"9341307F53987F3800C3909C5FFF81EE479B010F6DCC5F272FFFFFFFFF99CFFF",
INIT_01 => X"00C1F7284FFFDEF875A403E06B9E7FB31FFCFFFFFF97FFFFFFF8CE923C629CEC",
INIT_02 => X"784900E3A3D6F9503FFD7FFFFD7D3FFFFFF1CF059D4356400741C9FC82F601DC",
INIT_03 => X"FFEA9FFFC77FFFFFFFF6DEA57A45B4B71905152AB27FB1E60301FED7DFFF2FE2",
INIT_04 => X"FFED4E0FB7741C3517FD84424724B2890104FFDF3FFC35DA65C700082542E25C",
INIT_05 => X"0BBB682659BD10F60C21523F3FFE4BAA415A040A2173C5EC3FEC1FFFE7F97FFF",
INIT_06 => X"000FC1C61F7F3D06445B040E91EE6DB53FA65FFF48B5F7FFFFFAAF3EA39A6C63",
INIT_07 => X"5BC7000DF1230DDF3F013FFF0087FFFFFFF7DD88E4ECFB8EC7095117FC0AD26F",
INIT_08 => X"B8219FFEBC1DFFFFFFE0BDFFB912950EE52A35443830E63C6012BD9FFFD6BE1A",
INIT_09 => X"FFE2FE09048EE2B00695CC3C00820D2C81F2AF3FF4F6DF7E31EF7931A7378BFF",
INIT_0A => X"44A17275C15E823478CBAEFFFC9524CE3BE700527E67CFFF226C9FFCEBABFFFF",
INIT_0B => X"99429CFFEF37FFFE20F00C59D9E15FFF8B70FFFD50E7FFFFFFABFE40E3530FF6",
INIT_0C => X"2F0859118DF43FFFD01E7FF9C0CFFFFFFF03FE05AA636BB11DFD978403D42DB7",
INIT_0D => X"47E77FE080FFFFFFFEAAFF00B626D9FDFBFDC83B075CA57B491F45F8E6FF9FFC",
INIT_0E => X"FE99FFE8D369FF7DA2D54B0078678CFC6B2A3AFFC3FF3FEC7E87C9EBDC96FFFC",
INIT_0F => X"43766263F4BE06FEBB070FFF33FFFCCA7E26EAFCA36CFFFA554DFFA6831FFFFF",
INIT_10 => X"9CB520FF6FFFFF8A7FAC7EFD6887C1F06B93FE1384BFFFFFFE69FF939E73EA79",
INIT_11 => X"4D1FB7746FF83E530DA787E132FFFFFFFE7FFEEF29468A7D03FF4A7041B515F8",
INIT_12 => X"1CBF27C0287FFFFFFEAFFBCAEAEA7C7F21808FC2AC91FAE2C41A8DFF7FFFFFC0",
INIT_13 => X"7D8FFF568D6D83FE1B2BFA02633A622710DCAA67FE3F7FF2324028DD896F7CD5",
INIT_14 => X"AB1FF1C20ABA7D47A15B30BFFF1F7FFA2F22DA027DF0D16843DA5D1015FFFFFC",
INIT_15 => X"4EFBE7FFFF1FFFE8336BBBACDEC0F001C9EE9000CFFFFFFCBC17F84F706EEBFE",
INIT_16 => X"3A5F533FFDF6C70D886241F17BFFFFFFF59FE58FCB66F1FF5A67F64360ECFC07",
INIT_17 => X"1FF67E0593FFC77FFC07FDCA8581BDFF149FF9C371C328470629AC1FFB3FFDC0",
INIT_18 => X"FBEFE2327230D9FF9743FF7C7384B5E18165FF1FF1DF5C6E296FFB7FFE4CF031",
INIT_19 => X"D69DB8BD1C70F572EE9FDEEFF9C9DE7E0759397FFCCCF0FCD39C3C0457FF837F",
INIT_1A => X"B949D6B0FCFB9FFE3BBFFF1FFA47E6FDACE1AB8C1FFFE07FF85FD97575DC83FE",
INIT_1B => X"03B37FF3DA8ECE20A3EA5ABFDFFEC4B7FF5FCE7F3AFDEFFF329FFECF69BC8E2E",
INIT_1C => X"07FF33B1FFFA717FBD2FCBC994AC0FFF61E8F5C3E3AA8DFB640F12DDBFFEEFFE",
INIT_1D => X"FA6FE001AE598EFFB108F1D859FD8DFCC8F25907A7FF07FE2680FFFFF960CE7D",
INIT_1E => X"841BF119758D8FFFE041F326500FE7FE2485FFFFF6391EC1AF643805FFF6A07F",
INIT_1F => X"EB808046DF33FFFE0613FFFF7B05D77D7F1A18117FF36C7FEEFFFA346185C6FF",
INIT_20 => X"073FFFFDADF8C2FDDFD800D77FCFD4FFEAFFF5B9D1F744FFFC1DFA972103CFFF",
INIT_21 => X"6FC000947F8CAEFFE97FFCC07114817FD81AFA71E185A9DFE82133F818BDFFFE",
INIT_22 => X"CCFFE289EA07A57FD6DCFB66A05E9C3FBBA3E461EF58FFFE3B5FFFFFA2DB0008",
INIT_23 => X"EEF2FE872F5CCDDC6E070AEF7406FC0E7C4FFFF78BE55891ADB039B4FFE054FF",
INIT_24 => X"90FF499F7E23FC661F87FFF27FA74B1CECE89B85FF1835FFAEFFEEC367C0C5FF",
INIT_25 => X"23FFFFF0D9E443239C4DD9ADFF1877FFFBFF1725A2B897FFEA07BCE4C37942BB",
INIT_26 => X"E7B8B8BFFEEC81EFE5FAC9A549BFBF3FED0518F40317AED167B65C6FFF0FFDF6",
INIT_27 => X"BDFD856CA80F52BFF2E265D2B08D4138FF5F9F5C3FFFFECE3EFFFFF6D86825CB",
INIT_28 => X"F7043F79A6570027FD4FB456BFFFFF3E7CFFC1329F22C3030DEC62FFFC91B5FF",
INIT_29 => X"FE368F8D9FFFFFFE7CFFA55484C3807532F39BFFFDE1C0FF9DF9E003C31350BF",
INIT_2A => X"7FFFB56E18CE3CD4781DED4FF7F6C2FE33F818057B872A4FF1A104BB64902277",
INIT_2B => X"0108B62FF0622EFC1BF624A33B23294FE97BAA0C1DE9AD527FF3BD053FFFFFFE",
INIT_2C => X"3FF066712C64772FFD370421C39AE575FFFFFC404FFFFFFE7FFFF165D1B6D574",
INIT_2D => X"BD85C3D1F8C3D5D3BFFF7123CFFFFFFE7FE01ED78F07A8008D0125BFF25156BC",
INIT_2E => X"3F8FC750DFFFFFFE7FE68E84BE1B7D38CF1BD9FF79D10FBEABF338E630CBFBDF",
INIT_2F => X"7FFA5C63760CA644A74D95FFB091FFBC318C3EB6C1E83357DEB0C6F8357DEB2B",
INIT_30 => X"D49841FBA2136FBF442DA557125A6F25FD4713E14690E7EC5FFFE44A97FFFFFE",
INIT_31 => X"8DFD8BC01452F13E5CCDC35747F6A39EBFFFF72DDFFFFFFE7FFEF8EEE51B258D",
INIT_32 => X"E82D6CF27F1C5FE9A5FFFCC05FFFFFFE7FFFF9C19271DC508A0153C7F8D15FB8",
INIT_33 => X"64FFFF90FFFFFFFE7FFFF8FE589A30EDBF304BFFBA401FFEF25E1CBB104D7102",
INIT_34 => X"7FFCFFFFE571583B7D195FFE8041DFF6F87E1C3E700F2039F9D8086B7F00A664",
INIT_35 => X"7C2A77E2E4C14FF2F9773CC081A46A83CF3610E3FF25A66B4AFFFFF6DFFFFFFE",
INIT_36 => X"9E38DDA9A1942B92657EDD7BFEA74CF828FFFFF703FFFFFE7FF8FFFFE263C54A",
INIT_37 => X"BDE743EFFE5056FC79E3FFFF37DFFFFE7E1FFFFFFA0CDBF0300A8CFF68467FE8",
INIT_38 => X"7025FFFFD5BFFFFE7FFFFFFFF8760BF476455C478847FFE536FA195360007B2E",
INIT_39 => X"7FFFFFFFFB60BFFA1FDA32CA392A6FDF03F3170D71179A4830977EBFFD8CE63F",
INIT_3A => X"AD4878B347857FFB67E73258C61D220DBD2A348FFC5819F36155FFFFA024F6FE",
INIT_3B => X"B3FD77FA970DDA01475E8157C03939BBFDCF3FFFF626BAAE7FFFFFFFFC3E3FF8",
INIT_3C => X"97BC0281B0FFABDC7F155FFFF8746ABA1FFFFFFFFEA37FFD6CF93D2C300F7FCB",
INIT_3D => X"FFB21FFFFDAF65207FFFFFFFF906FFFDF36FBCEEBCBD7FD3D7DAA9F987031800",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFCFFFFF32FFFFC51AD3F079EF77FA2EE039CD9174F0200BFBFC2DBA5FD745F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"02B13F45CE2B7F5EEF1CA5E569890000BFDB82BCEFFE7FD97873DFFFFFC664CE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_8_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FF7637B60E054B20FFC9025C9FFFB5C8FD3FC7FFFFDA52D07CFCFFFE00D78FFF",
INIT_01 => X"AFEFD3CAE5EFD3B1FF1BD7FFFFFA0BC07CBFFE19AD6FFFFF5A5EFFE2C02D7F8F",
INIT_02 => X"3F83E7FFFFFC3D6C7FFFFEFFBC7FFFFF4C96FDA400797FF53FE9FF72D607CF20",
INIT_03 => X"7FFFF9C53F3FFBFF2270FB960131BEF5FF3CBF840E03E98047E3FBAAA5EFD6DF",
INIT_04 => X"4E18FD6100699E45F28DAF902C40E0004FFFE1F5A9FFC2281FC7FFFFFFFC3858",
INIT_05 => X"F7EC1FD7EBDBE000CFFF888849FFFF971FE3FFFFFFFE64EA67FFC04E701FE3FF",
INIT_06 => X"0FFFEB1183FFFD5FFFE3E7FFFFFFB0587FFFFF33333FF7FFC199E5A100EDDFCF",
INIT_07 => X"FFE3E7FFFFFFED007FFFFFF0807FFFFF01B7ECC6C1CC1F5FF235FBC79DDC0000",
INIT_08 => X"7FFFFFF8A0FFFFFF8DFFFC87C9473C47F6547BE7B008002027FFCEF157FFFAD5",
INIT_09 => X"CF27CB87CB0738C7E641FBD75E800000FBFFE44BF3FFF5DAFFFEF7FFFFFFFDD6",
INIT_0A => X"99F0BFA7FC0900000BFFF47D23FFFCC2FFFC7EFDFFFFFAAA7F8FFFF9A17FFFEE",
INIT_0B => X"2BFFF3BF6FFFFCD67FFEFFFEFFFF78F67FDFFFF9A83FFF9F0C0F0A8BDBD83A37",
INIT_0C => X"BFFFFFFFFFFFFF987FFFF9F5D4FFFFBF8BAFDB009B96F27FC17A7F37FF03000C",
INIT_0D => X"7FFFF6746DFFFFBE808E2E810267EEEFD00BFF29FD80001DB7FFF97187FFFE36",
INIT_0E => X"867E5AE1214FF97F73503F01F8090CBF8BFFFFB2169FFA77DFFFFFFFFFFFFFDA",
INIT_0F => X"8810BF69F980071B67FFFC9E2E7FFCF7B9FFFFFFFFFFFFFC7FFFEB02697FEFFF",
INIT_10 => X"CBFFFEFCEF0FFB6F9FFFFFFFFFFFFFFA7FFDD5D5AF7FEFFF07FED0C4205FEAFF",
INIT_11 => X"F6FFFFFFFFFFFFFE7FF05CDD5E3FEFFFC4BE0C00210FFEFF59097F0BFE4462FB",
INIT_12 => X"7FE316A79E3FC7FEC77FDD0001EFC3FF1D887E7BFDF46AD24FFFFF6B2C6FFCFF",
INIT_13 => X"417FBD0E814FE2FEDCAAFE27FF11630F71FFFE8D556FFFFFF8FFFFFFFFFFFFFE",
INIT_14 => X"61A8FF2FFE2C05B6A5FE3F6F9D8FFFF8FBFFFF9FFFFFFFFE7FFFA60CBFFFCFFE",
INIT_15 => X"483E3FB4FEBFFFFCFFFFFF1FFFFFFFFE7FFFAE477FFFDFFD46FF90E1C187F8FE",
INIT_16 => X"FFFF7EBFFFFFFFFE7FFFAE2E7FFFFFE283FEF798C56FFEF383F4FEAFFF6107A3",
INIT_17 => X"7FFFA1EDFFDFFFE3B1FFE618CDE7A67C47C9FF3FFFFFCADCA8BFBFF4C9FFFFFD",
INIT_18 => X"D1246B520A37F17DCED3DE27FFE00D36E53FF7D3A45FFFFEFFFFFEBFFFFFFFFE",
INIT_19 => X"2EF3DE7FFFF4131B15FFFFF5285FFFFFFFFFF93FFFFFFFFE7FFDA4BA1FFF7FFC",
INIT_1A => X"7F7FFFF889FFFFFFFFFFF91FEFFFFFFE7FF8687D1FFF7FFC4124E4B04C6FD89E",
INIT_1B => X"FFFFF90FFFFFFFFE7FFFD6C53FFFFFF9DE34E4E91C5F30FF76EFFF47FFF705B0",
INIT_1C => X"7FFF2FBB7FFFFFFCEC8DF7F8FEAFAE24F06BFC93FFFEDD00B6FFFFF8FAFFFFFF",
INIT_1D => X"8A75E8BC6D9F8799E00BFAB3FFF30F18DCFFFBF981FFFFFFFFFFFC7FFFFFFFFE",
INIT_1E => X"0087F6D1FFF1951FE17FF0FEF83FFFFFFFFFFFFCFFFFFFFE7F7F4C83FFFFFFFC",
INIT_1F => X"1B3FFFFF029FFFFFFFFFFFFEFFFFFFFE7F1C437BFFFFFFFF4305315927FE47ED",
INIT_20 => X"CFFFFFFF3FFFFFFE7FC05D7BFFFFFFFEC8F42EAB33FF9193A0D3FD05FFF3A76D",
INIT_21 => X"7FC06173FFFFFFFE3E1C07B4E6FFE1FEB05DFE0BFFF2E472C0DFFFFE9E6FFFFF",
INIT_22 => X"BD246D93CA3FFDFFBA7BA5CDFFFCCD066343FFFF09DFFFFFFFF8FFFFC7FFFFFE",
INIT_23 => X"A4C153F1FFF97DC79F93FFFFF6EFFFFFFFFEFFFFE7FFFFFE5FFB387FFFFFFFF8",
INIT_24 => X"DD3FFFFFC7A7FFFFFFFFFFFFFFFFFFFE7FFDD5FFFFFFFFF87C075224E71FD5C0",
INIT_25 => X"FFFFFFFFFFFFFFFE7FFD77FFFFFFFFFABF555C27F40063C7828CB15CFFFDB451",
INIT_26 => X"7FFD1BCFFFFFFFFE7F404D536A3CE8D03156F4107FFFDD67353FFFFFD827FFFF",
INIT_27 => X"7FF899B5E4103ED97A5E4E297BFF7D7D573FFFFFE627FFFFFFFFFE7FFFFFFFFE",
INIT_28 => X"0262AEC27FFFEEE2825FFFFFF4B7FFFFFFFFFEFFFFFFFFFE7FF97B1FFFFFFFEF",
INIT_29 => X"AF5FFFFFF9BFFFFFFFFFFFFFFFFFFFFE7FF7A69FFFFFFFE7FFFC64011A9B03B0",
INIT_2A => X"00000000000000007FE1AEFFFFFFFFFFF8FD03313FDE7718357FA0CEFFFF937F",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_9_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"00F0006B3DB183C500CF2B001C4FFF1CBC0000000C0019CE0000000000000000",
INIT_02 => X"A0988C00155FFF3F280000000183972E6FFF08BDFFFF082F6000A3C015C20000",
INIT_03 => X"B00C000001C5A3EE53FD0FF88FFFC3C380009D700EE9000600E00004F88D6DDA",
INIT_04 => X"2C02070D95FF13C007DF873E671FF861300000049FB9FBE970E0000014BFFF3D",
INIT_05 => X"07C0C66E0C270C103003000153A135E6A3B5C00019BFFFFE3D6C00000086A5F2",
INIT_06 => X"000300F1216150E56C75200007BF3FFFC4000000000698322786F8A92B9FCEC0",
INIT_07 => X"F6AA5202093DDFFFF4040000011B13E22038C78A645BC6710700F0740438AF20",
INIT_08 => X"F40C0000E02C29D81CE78033F1B3E78003010064031C00E900010001F8ED0A1B",
INIT_09 => X"42FF3F76A4B0FBC8C000C60E098F1FF70000C00E3D9B4A26CB8991000E2C5FFF",
INIT_0A => X"70008E0009543FFF494970000E676001812085000C72DFFFF51C0000D891732E",
INIT_0B => X"8F838000149DC444E75C04000D1FBFFFED1C0000C4629E1C40BD8A3FD0B4F8D2",
INIT_0C => X"3C30070004EB3EFFE01C00005733FFFE6C31D7D6CEAFFC2660008E00D58FAFFC",
INIT_0D => X"F40C000049E7FFFE7C54C9AA874DFC46000004FF03CF3FFF4F4200E0087F0458",
INIT_0E => X"784B265595ABFCB3000000033CC5917E1E820CC0174EF0478A60000001AE7CFF",
INIT_0F => X"00000000298E49F9ACF00EC7CC4530506CE000000B8B3CFFFE0C00000C07FFFE",
INIT_10 => X"C7AEC10369417829E8E3C00005C47FFFFE0C00002DC7FFFE7CF526244E97FF12",
INIT_11 => X"5005B8C08ACEFEFFE20C00000879FFFE7C162364D507FF0E008000004245A467",
INIT_12 => X"FC0400000238FFFE7F092CFC11FBFF4C00801F00082C0782BA1081006AEB0873",
INIT_13 => X"7FF3A74044EB3FE840000E00BDC795E4F731A00003486044F085D4C108297DFF",
INIT_14 => X"600000032E3EA69BFD97200133A5B8DDB10B9201C02A77FFF800C00001067FFE",
INIT_15 => X"FA44B9023ADBA18FC40CF801C03C7AFFC217C0086238FFFE7FE294440FBF2FF5",
INIT_16 => X"BEBD1621048271FFE26800040BD07FFE7F8694980F3207FFA0000001177F01E7",
INIT_17 => X"FC2000007A0AFFFE7F431B600C06CBFF0000000067FFFFFBFDB64C7019C9D163",
INIT_18 => X"7E8E3ED0012D1DFF838000007F85FFF5F81CE97818C1D3EBAE04657006F475FF",
INIT_19 => X"DBC000002EBEFFF6FAF9F7B003D751653B94C270C0556FFFF3780060FBFFFFFE",
INIT_1A => X"FB3FFF7002EBC0BA98B67161408DECFFF324006017FFFFFE7D6DBDE80072CEFF",
INIT_1B => X"D821064F3E9C19FFF24C00603FFF7FFE7D4E70440000877FDC0000009EEE3FFB",
INIT_1C => X"F1FC01C33FFEB6FE7E5719A000003FCFEC000000FE4748FBFA37FE10C1F2C13E",
INIT_1D => X"7F56877800616349F30000003F22C13F744BFF38880D53C098DB8A9BBFDF2BFF",
INIT_1E => X"F6B00007AE86AB42B61BFFD2C2D65311141DA48381565BFFFDFC01827FFC70FE",
INIT_1F => X"7A8BFFE080ABF798103485B9F3D7DBFFFEED1F867FFCE2FE7FF9029AF8000CD8",
INIT_20 => X"E1B43AF02ABE87FFF8D901057FF8C3FE7FFE61873C0002C03F00000F0D2BA45E",
INIT_21 => X"CFFE00117FF1CDFE7FFF84742E0F0147E140001EBB69C440DDFB7FF894FD8CE6",
INIT_22 => X"7FFF28710E8F009F583C00000FBE1B74F138BFFD2027F87691C5F9FECE3693FF",
INIT_23 => X"ECFCC00041E90894329A5FFF80942538A00D7BF018B817FF97F0402EFFF5CAFE",
INIT_24 => X"10ABB7FF908FE6FFE147E3EAF4D20FFFC60863F5FFEBC0FE7FFFBCC914C60341",
INIT_25 => X"66BFD919E64A07FF0342C167FFFB16FE7FFFFE5B30000039AF7FE0C016E82748",
INIT_26 => X"5277647FFFDEA47E7FFFD7A91E0000021A80FFC0F0F6BFF005E2727FB483CE5F",
INIT_27 => X"7FFFF47FF3C0061BFC5803E0FCF8A1880D421B3FC8600D1CF59722BFEBD7AFFE",
INIT_28 => X"3175E078DDB9C9C7014208CFFD7C0EDFF45F0782223A2FFDBA7B106FFF9A70BC",
INIT_29 => X"39A1946FFEBC111FFD3D37C1B2A91FFF1179081FFFE2A35C7FFFFC5FC5F00188",
INIT_2A => X"FF7D4E20F2DC4FFF25FAFCFFFF906AA47FFFFFFFE4CD980160F5F03C4290D143",
INIT_2B => X"93FA0D3FDE01FDA67F7FFFFFFCEB7E334F843C1F43BA1E5878118B9FFEC01B7F",
INIT_2C => X"7FE1AAFFFD04E4008FD7BE07C72FCF276608B07DFE6915BFEDBDC0E2AD7B5FFC",
INIT_2D => X"5F784E038070DC3182540320CFF8C67FDBBA8A227D38FFFD63FA023FD050DD8C",
INIT_2E => X"03B017C26FF0B9FFACAA7F02B5B27FFD3FF90A3FF011BE267F944B7FFFC4C002",
INIT_2F => X"DAD7FC5E2DBCBFFAEFFCF5BFF8F0FFAA0387BB7FFFFB2C003F8B46010583ECB7",
INIT_30 => X"F7FCF2FFFDF1FFC66C79C5905FFB53947FFE3400B2028A4747F40E79F0544FFF",
INIT_31 => X"79DED323E7C1AF7FFFFFEA00C48F77A0E31F0838D928BFFFEB8CF9429948FFFB",
INIT_32 => X"FFFBF360767FB8C2714665DFFECE3FFFF3FCF9FB0AD13FFFFFFCFA7FFE23FFDC",
INIT_33 => X"184584CBFFEA3FFFF93D697DBFC0BFFFDFFEF37FFB34FFFE68BFE577F110DE43",
INIT_34 => X"DBDE263F59607FFFDEB03F7FF803FFC244A78E7C62F3C50FFFF1FA98347FD311",
INIT_35 => X"9F7F24FBD00FFFC268FDF904E2A3FCFFFFF1FE5C007FF6325C4E0C1FFFFB7FFF",
INIT_36 => X"7BA4FE40C1B2F1DFFFFFFD40023FF41AA24A4805FFFF9FFF1F6771BF9BB17FFC",
INIT_37 => X"FFFFFEB080BFFE9BBE4A09057FFF5FE7CBCFE9BFA990FFFDFF0355F3D007FFC4",
INIT_38 => X"E54181C29FFF9FA03ECFE9BF8B607FFEBDF46BFBE123FFFC7D29FED17E917387",
INIT_39 => X"D4A7FE7F88327FFEDE87ABFFE01BFF947142FF6721800D707FFFFFB1012F7CFD",
INIT_3A => X"E063E3FF9C2FFFA878D09FA8C7809ECCBFFFFFCDB2FFFE85F11041C1D7FE7732",
INIT_3B => X"63D0AFE794F04E1FDFFFFFF2807FFE01FB1801E1487C734BED730FFF94957FFF",
INIT_3C => X"8FFD7FF71C9FFE49FC20D0F002DD69AFEE1B5FFFAAB0FFFFBCF71BFFC447FF60",
INIT_3D => X"FB3190F0280F98DFF1BADFFFBB22FFFF7EFFFBFFA4AFFE70220017F3ABEA000C",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"F85F4FFF9125FFFEC6AFC7FF045FFD205A8CBBF1CA003C0157FD3FF90E51FF4D",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"BE6957FFA4FFFE027286041BE7BD7C002FFE4FFE5785FF0FFE3E7070090F0EFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_10_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7F67C42D5D64BC001DFF0FFFF1C5FFE5FEF470745BDF4BFFF682AFFFC7A4FFFE",
INIT_01 => X"053FD3FFB566FFADFFF7700913D01FFFF5C97FFFFC27FFFE9E12AFFF813FFF02",
INIT_02 => X"FFFA600585BF7FFFF7E33FFFF90FFFFED25DDFFF02FFF4C67FDC3047FFB74C00",
INIT_03 => X"FBFE7FFFFE83FFFE1C5D3FFF41FFF45E7FFF9A679B1C8C0002CFA5FFCF33DFED",
INIT_04 => X"B8187FFC05FFE4527FFFFF7FDED24C7FC077F7FFF9F93FEAFFF7200FB983FFFF",
INIT_05 => X"7F14AFFFD90BDCFF6005FBFFFFE48FF9FFF0C0EDB8C5FFFFFBFC7FFFFD07FFFF",
INIT_06 => X"E062FFFFFAAA97F9FFF28CD1D60FFFFFFB38FFFFF20BFFFFD7CBFFFD0AFFF4D0",
INIT_07 => X"FFF075BE5A6FFFFFFF20FFFFE307FFFF48ABFFFE05FFE2DA7C03F78FD8A125A7",
INIT_08 => X"F6F1FFFFA037FFFFE781FFFB4DFFD6247D172961E564A8A240045FFFFC90C7FC",
INIT_09 => X"E44DFFFC4FFFBEBE2C09002CE2CD081BC008B7FFFF4B5FFCFFF2FC6D237BFFFF",
INIT_0A => X"54D1014E754D879A318013FFFFB9AD7FFFF80E90A4711FFFFFFFFFFE2FFFFFFF",
INIT_0B => X"42005BFFFFF3CE3FFFE5C3DA6700B7FFEDFFFFFCEFBFFFFE1695FFF81BFF632A",
INIT_0C => X"FFF123FC07C7BDFFEDFFFFFD90EFFFFEDE23FFFC0FFF073E23F00030E04B21FF",
INIT_0D => X"DBFFFFF020FFFFFE1CEFFFFE1FFF5ABE27000099E0486FFFEC80027FFFF3F29F",
INIT_0E => X"186FFFE57FFFACFE30006680013463FFFFE083DFFFF96C4E7FF8FFF3D714A7FF",
INIT_0F => X"0000640000000BFFFE44216FFFFD40237FFFFD81297615FFABFFFFF0A67FFFFE",
INIT_10 => X"FFC61C37FFFE0D667FFFFD76F8100FFFF7FFFFF49BFFFFFF0C0FFFF41FFFAABE",
INIT_11 => X"7FFFFD661A7464FFFFFFFFF8EABFFFFE3FAFFFE85FFE9ABE001CF800107007FF",
INIT_12 => X"6FFFFFFFD6FFFFFE969FFFC83FFF907E0000F8001101CFFFFFAE8637FFFFBAED",
INIT_13 => X"B0FFFFE0DFFCF1FE0100001001028BFFFFF97014FFFFE0B647FFFFC8463720FF",
INIT_14 => X"2100003C00036FFFFFFF9A00BFFFF4DAC6F7FF4D854A667EEFFFFFFFCAFFFFFC",
INIT_15 => X"FFFFF2262FFFFF2E470BFFC2185F77BE9FFFFFFF987FFFFC5FFFFFA0BFF8AFFE",
INIT_16 => X"615BFFE4CFA7B3583FFFFFFFFDFFFFFEBFFFFFD0BFFFDFFE1000003E00001FFF",
INIT_17 => X"7FFFFFFF54FFFFFBFFFFFFC0BFFC9FFE3000001FE000BDFFFFFFF87897FFFCC3",
INIT_18 => X"FFFFFFF19FF21FFE37070000E002807FFFFFFFD2F2FFFF0C9327FFB58A57E12B",
INIT_19 => X"3707000000005B5FFFFFFFE9DC7FFF87795FFF9500D7FFEB7FFFFFFF4FFFFFF8",
INIT_1A => X"FFFFFFFC3B1FFFCDABAFFFA40067FF19FFFE31FFF7FFFFF1FFFFFF14DFE8FFFC",
INIT_1B => X"DBCFFFDC095FFFCDFFFD31FF1BFFFFEDFFFFFE987FF5DFFA6406040000807117",
INIT_1C => X"FFF903FFB7FFFFEBFFFFFD07BFD43FF604992000000013683FFFFFFFA37BFFEE",
INIT_1D => X"FFFFFD89BFF9FFF23BCCC00000002C2FDFFFFFFFEEEF7FF82AFFFF3C9B27FFDD",
INIT_1E => X"275EC801001B73FC7FFFFFFFFEF4BFFDAC7FF966E45BFFFBF0FD83FE77FFFFF7",
INIT_1F => X"BFFFFFFFFF056FFF603FFB6211B3FFDBE72FCBFFEFFFFFFFFFFFFF113FFFFFEC",
INIT_20 => X"ACBFF8005813FFD3F0636FFE1FFFFFFFFFFFFF0BBFCFFFC016970831001964C4",
INIT_21 => X"FF449CFD2FFFFFFFFFFFFA4DFFDFFFA24830E820001024F049FFFFFFFFD77BFF",
INIT_22 => X"FFFFFC447FFFFF404403900040061188BDDFFF9FFFF05D7FC3BFFA206D1FFFDB",
INIT_23 => X"0463614000063FC1DAB1FC5FFFEC045FF39FF490BAEFFFDBFFC091FD2FFFFFFF",
INIT_24 => X"080BFCF7FFFF6577F7DFF1F82A57FFDBCFC2E9FE4FFFFFFFFFFFF48FFFFFFE44",
INIT_25 => X"FBCFF7558CEBFFD907A2F1F95FFFFFFFFFFFEECCFFFFF8700005E0C0E0011E61",
INIT_26 => X"0706ABFBBFFFFFFFFFFFD177FFFFEDAE000520E0303E0AA3E019ABAFFFFFCD59",
INIT_27 => X"FFFF8BACFFFF574E00020000120003682141B4EDFFFFFF08BD6BFB0BCC13FFDE",
INIT_28 => X"0011A0005029544800000E8DFFFFF9229EBBFDAB038BFFDF7F647BF3FFFFFFFF",
INIT_29 => X"00800E8AFFFFFE972783FF9FA507FFC0FEDDFFEDDFFFFFFFFFFFA2EBFFFC7C2E",
INIT_2A => X"BBD37FFE89FFFFA7FE9EFFE3DFFFFFFFFFFF10E5FFFC0A7E001E020001501E00",
INIT_2B => X"EF1C7FE21FFFFFFFFFFE9ED3FFF5DD7E00FF1C00029919B8F384BEAAE7FFFF0B",
INIT_2C => X"FFFD5EDFFFEFD7FE00002000E0C07418E108B00593FFFFBB68AB3FFD8E7FFF79",
INIT_2D => X"00008000F1E28EEEC0013001F5FFFFE5AA9D0CFBC12FF8F7DAD87F92FFFFFFFF",
INIT_2E => X"000B66803CFFFFF24DBC81F7451F1F6327CEBF6BFFFFFFFFFFFD9997FFE82FFE",
INIT_2F => X"63EF6CF3438E7F78C4DD7F55BFFFEFFFFFFE4B97FFF0FFFE00000020F0D3EEF1",
INIT_30 => X"B75CDF2DBFFFC7FFFFFBE7AFFFFFFFFE0000000062B5A40DB806400086FFFFFE",
INIT_31 => X"FFEB2FC7FFFFFFFE3EC000000110DE36C41840317A7FFFFFE79D55E1C2E67F32",
INIT_32 => X"00C00000000F95F0583F6EE9E4D7FFFFFC01F76C00423CF0618C3EE0BFFFCFFF",
INIT_33 => X"24135138006FFFFFFE44CB04E093FB32FEF07E70BFFC0FFFFFF8BFFFFFFFFFFE",
INIT_34 => X"FE75218F8034F173332DB1BC3FFD9FFFFFF8FFFFFFFFFFFE40C0006300100000",
INIT_35 => X"1F97B536FFFA7FFFFF613FFFFFFFFFFE200000F103D972004012481A00927FFF",
INIT_36 => X"FED8FFFFFFFFFFFE2C000061C3ED208006E387F78010DFFFFFD87F5FE0FEF934",
INIT_37 => X"3300008181C27600F81000068060EFFFF7F792C65010F87961E60723FFF87FFF",
INIT_38 => X"9608D600018053FFFFE38768D03C2FC6CB83152D7FF2FFFFFE9AFFFFFFFFFFFE",
INIT_39 => X"FFD0605FF8048AB2497B3C0D7FE03FFFF14BFFFFFFFFFFFE050F000010080089",
INIT_3A => X"8D1FEB96FFA57FFFE0AFFFFFFFFFFFFE7B0000003109388399F9E208030005FF",
INIT_3B => X"E57FFFFFFFFFFFFE780000FF23C99BD6D84E9A240FC78AFFDFD5601EC15B4D40",
INIT_3C => X"31000010233C87EBFF0F092078859AF18FF80002C6B3962F0A3C3020FF5FFFFF",
INIT_3D => X"FFFC0326F202F78E77F80000FFA08EAE1877B25FFE6BFFFFEC7FFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"5FE50100C1A85971C2535319FEA3FFFCD6FFFFFFFFFFFFFE3100000023C7000F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"BA63279E3D45FFF593FFFFFFFFFFFFFE71000000F32FFFFFFFFFC40C6250CAD3"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_11_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"B7FFFFFFFFFFFFFE00030000F1A7FFFFFFFEAAFACA681020E7E50680000C27B1",
INIT_01 => X"00078000BC8FFFFFFFFF3DFFFF2D800144B00FC1C1B7D71A7E00EF73FFCBFFEA",
INIT_02 => X"FFFFFFFFFFF3F50E16401FC5424EC609B100DE52BD5BFFC8AFFFFFFFFFFFFFFE",
INIT_03 => X"01600001A2FD8C66F068A2BE180BFE52BFFFFFFFFFFFFFFA0007800006DFFFFF",
INIT_04 => X"77E5EB4EED37FC26FFFFFFFFFFFFFFFC00060000E33FFFFFFFFFFFFFFFF84720",
INIT_05 => X"FFFFFFFFFFFFFFF200000101F3DFFFFFFFFFFFFFFFFFC3C300F00001236C87CC",
INIT_06 => X"00000043E35FFFFFFFFFFFFFFFFFFF4000010000602BE5D67802D95FBE5FFE35",
INIT_07 => X"FFFFFFFFFFFFFE4003000000C0FEEDEF7F012934A2FFFC57FFFFFFFFFFFFFFFE",
INIT_08 => X"01A0000000E9BB90D306892F3EBFEE4FFFFFFFFFFFFFFF8610800003B85FFFFF",
INIT_09 => X"938642CFC46FACFFFFFFFFFFFFFFFE100080000C6A0FFFFFFFFFFFFFFFFFFF28",
INIT_0A => X"FFFFFFFFFFFFF9C200C001936C70FFF9381FFFFFFFFFFF85200000001815FC37",
INIT_0B => X"00F002B9A91C3FE13BF87FFFFFFFFFE5A000000C181F28900C868B2FE04CB4FF",
INIT_0C => X"0E28E07FFFFFFFE09800C0007002EEE8DFE18C4FBBDCD7FFFFFFFFFFFFFFB80E",
INIT_0D => X"F400800040718C66FF6E28DDFDFFCFFFFFFFFFFFFFFFDB2E06F0158893500E49",
INIT_0E => X"316D0FD99E73FFFFFFFFFFFFFFFCDD0602F026F27D68BEC4010050E1F81FFFFF",
INIT_0F => X"C007FFFFFFFC13D0001C6BCD40772E01F8003F070489FFFFEA0000100044D803",
INIT_10 => X"001CA0940A7F600FF80060870BE4FFFFD7C00000010F200146421EBEFE77FFFF",
INIT_11 => X"FC0601931B8FFFFF92C0000007F5B3937C0052B9FD17FFFEA30DFFFFFFFFFF8A",
INIT_12 => X"9800001F0785C63E400051BEE19FFF0E3811FFFFFFFFFE520079E46DEA77EEFF",
INIT_13 => X"E062057FD07FFC42CCC3FFFFFFFFF0023C0DFACE6C6004FF0080222E0FFFFFFF",
INIT_14 => X"EF97FFFFFFFFEC3E262D6B12800007000007CD3FFFFFFFFF980000060713B135",
INIT_15 => X"00C5E9D381804100002D59FFFFFFFFFC7070000003BC2598C972ADFF37FFFB31",
INIT_16 => X"003BFFFFFFFFFFFF8FF8000408A8F5B6DE40557C9FFFF9A1FF2FFFFFFFFF80FA",
INIT_17 => X"47F80006005B4EF9EE4142773FF4CBDEDEAFFFFFFFFA71C618DFB9C600E01D80",
INIT_18 => X"819145EEFFE6DBBF1FAFFFFFFFE2FDCE2DA4D7C000101C088AEFFFFFFFFFFFFC",
INIT_19 => X"F55FFFFFFF4DACC6080020C0001C7E14493FFFFFFFFFFFF203B00007217BB82B",
INIT_1A => X"7FD90060001CFCBAB3FFFFFFFFFFF80FEA0000060603BB0D40103DB3FFD61D9E",
INIT_1B => X"3FFFFFFFFFFFB38DD54000000FACA85780005EA7FFD6FD20F93FFFFFFD299A84",
INIT_1C => X"4AE100000FF79BB70402F1F7FFC0145013FFFFFFF5BCC7F67FDA4300180C0223",
INIT_1D => X"C0C2557FFFEC0E1FC1FFFFFFAAFD5FF07FEC00003C1C103FFFFFFFFFFFFF06F6",
INIT_1E => X"13FFFFFC4377FFFC7FE20000381C473FFFFFFFFFFFFE9E97FFA000E08A6DF4A7",
INIT_1F => X"7FC8608610001F7FFFFFFF7FFF17358FFF1100FF079C18FB00C16FFFFFF132E6",
INIT_20 => X"FFFFFE339082417FFF4A80031007FEA3204129FFFFED9BA0D7FFFFE53091FCAA",
INIT_21 => X"FF90C10333E0A0AF4023BFFFFFD8812897FFFF54A007FDA27FA0C88338749EFF",
INIT_22 => X"00D00FFF93F42028EFFFFA9093E8F97E7F52480F80061FFFFFFFFC48AF8D04FF",
INIT_23 => X"7FFF92F45F001CFE7F604080ED1FFFFFFFFFFAA7DF1C7DFFFE3EBB0325795A78",
INIT_24 => X"79056380167F7FFFFFFFF94D866E27FFFD6F7C01EC0830A2A04D3FFAAF43A1CD",
INIT_25 => X"FFFFA6DF73D57FFFF3037900592DC7F5008EFFF727AA273FFFF8B3C57FFF3FFE",
INIT_26 => X"E4FFAE0047460F6C000CFFFA3F26F33FFF8C98CDFFFFFFFE634B031083FFC4C3",
INIT_27 => X"8792FFFEFCBFB03FFECF850FFFFFFFFE299A01690FFD5963F7FFCA377F457FFF",
INIT_28 => X"FB34F9FFFFFFFFFE001A00FC3FFEB9A8F8FD10306566FFFFD3FC56983DBFBEA5",
INIT_29 => X"2A5C806FFFFF213CF280C08F65D7FFFF77F8109C619271A78796FF4AC57FF33F",
INIT_2A => X"C76980002E63FFFEDFF5909C45F7EE52064FFE068C7FFFFFE78777FFFFFFFFFE",
INIT_2B => X"5FF5D99C7657C31A00023E8366FFFFFEC7F62FFFFFFFFFFE6B340065FF39818B",
INIT_2C => X"00422EAE63FFFFF287D93FFFFFFFFFFE5608B9587B721C29C5BA27D5D1A7FFF7",
INIT_2D => X"683F7FFFFFFFFFFE1F107909064E1F18A080003A6BBFFFFB7FEDF810778BE778",
INIT_2E => X"025598FD6A3E0FF981000302BC3FFFF5FFEBE9107A8BE4500006B7C4E7FFFF93",
INIT_2F => X"0380030AB2FFFFEBFFDBEA00F333CD90009814B33FFFFCDF8808FFFFFFFFFFFE",
INIT_30 => X"FFDBF6008A9EE9A000017DEFFFFFFA834F347FFFFFFFFFFE7A8398E7E1309EA6",
INIT_31 => X"001F4FFFFFFFEA187F75BFFFFFFFFFFE5E3880C1C0F07DF406C380758FFFFFD7",
INIT_32 => X"7E1A8FFFFFFFFFFE0872607420F0030B0C0020D917FFFE2FFFD3CE00FBFFF383",
INIT_33 => X"5B2C4DC164071D51C001AEA567FFFEDFFF8FF9C1C7FFEE83009897FFFFFFACCC",
INIT_34 => X"01C181F95DFFFA4FFFFFEE609BCFEC0380021FFFFF2DC3FA7E6ACFFFFFFFFFFE",
INIT_35 => X"FFFFF0601E0BFEC100020FFFF948E7533EDD5FFFFFFFFFFE6FFDDA41100F4D07",
INIT_36 => X"1C02CBCF3EA3BFC8DF03CFFFFFFFFFFE17F1C543000E0A07810DBFFE13FFFADF",
INIT_37 => X"CF150FFFFFFFFFFE36283A91000165838FA7FFFC7FFFE13FFFFFC66017F19AE0",
INIT_38 => X"58838C00012C88800FF6FFFFFFFF867FFFFFD1203CE828E01C002BC8C4727F9F",
INIT_39 => X"007FFFFFFFFF27FFFFFF26A0974658011800B7B73E3EBFF6046527FFFFFFFFFE",
INIT_3A => X"FFFF32804DBF90030004EDAFED1EBF39445D2BFFFFFFFFFE04A4451C01461180",
INIT_3B => X"007CCE6FE2C6BFF0E9A633F0FFFFFFFE5D73CA1803931980A3FFFFFFFFFE28FF",
INIT_3C => X"221AA7E9DFFFF3FE66DEC00003C7C60002EFFFFFFFF849FFFFFE06503D2FE003",
INIT_3D => X"759281800367631E243FFFFFFFF1B7FFFFFF78F0AE1FD00380C027FFCF013FD5",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"8FFFFFFFFFF24FFFFFFD030A96BFD003800093FF8B907FAF801F0FCDBFFFA9FE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFDDF1AD1B7D001800051FF6CDBBFB2810667D12FFF98FE5CAB03C00CB2DEE4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_12_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"97808DFFE1D61FC800C69F4BAFFFF712683301000C361F20BFFFFFFFFFE26FFF",
INIT_01 => X"00C7F80F5FFFE9FA6E3603E00E6F7F885FFFFFFFFF281FFFFFFA4FD2FA1984E0",
INIT_02 => X"1A3400E0CEBAF86ADFFEFFFFFEA0FFFFFFFD4F403A3F56520B019FFF79FA5F10",
INIT_03 => X"BFFC7FFFF8C33FFFFFF59EA0583924060C4523CC65FDD7000005016F3FFFCF2A",
INIT_04 => X"FFF66EC390C640200BBDDB7473790A880003EA7FFFFFC6F25C72000A84F0E6E9",
INIT_05 => X"0738F0D31D7EE0F00C211B7FFFFFEDA24894000B00FBD7C1FFF4BFFFE605FFFF",
INIT_06 => X"00008B3FFFFFD17E4B5B0008503E3F7BFFF67FFFDC80FFFFFFE65E8CD6B96030",
INIT_07 => X"4FA30006B03E43FFFFF7DFFFD893FFFFFFFC9E946A50F8060006F10298040D92",
INIT_08 => X"7FC2BFFF2C33FFFFFFF53E15B272F47CA41643C6003025A9600BCA7FFFEFC1EE",
INIT_09 => X"FFFC7FC8423FC15D86184C00008150D2000377FFF8F03FF655D87968A63D67FF",
INIT_0A => X"840F020001C71DF850250FFFF772183E4D680043BD619FFFF5A67FFF484FFFFF",
INIT_0B => X"E127EFFFF70FFFFE5EC0038319E2FFFFE0DC3FF9005FFFFFFFF2FF6366D4D277",
INIT_0C => X"5E483BBB00C1FFFF67997FF1003FFFFFFFABFFCFF451B7F45C51277803C3627D",
INIT_0D => X"DBE5FFFE803FFFFFFF11FE7A1E2C2673B945D0030755C0FCE1AA5BFFF9FFFFFE",
INIT_0E => X"FFABFE6F98A950FDA3E28400002382FF43935DFFFFFFFFF07E276429388B7FFF",
INIT_0F => X"8152A4000C56B7FF738DFCFFCFFFFFF27CC6FE48E867FFFC8FC8FFCB82FFFFFF",
INIT_10 => X"808347FF9FFFFFF274726907230DFFFA938DFF9F843FFFFFFF5BFE82B59C8DFA",
INIT_11 => X"67A271B495FDC2E6A193F8D133FFFFFFFF8FFF3F85B229FF83FE27004BBC96FF",
INIT_12 => X"80B7C3E029FFFFFFFE0FFC7FD4999FFEC2EBFA40E08F38B92054AFFFFFFFFFF2",
INIT_13 => X"FFF7FCB1AFE503FF2177F58062ED3DC6B06E8DFFFFFFFFFE52868DC15C70BFAE",
INIT_14 => X"F3BFFF8009AE2CE5E0D51A7FFFFFFFFE43EAE1BCDE89EB914377E25014FFFFFF",
INIT_15 => X"4E1712BFFFFFFFF24FCFC13F3FEF097DC9D7700009FFFFFFFE0FFEE303D63FFF",
INIT_16 => X"481F381FFF10C211887FA000BDFFFFFFFDB7FBE248DAA3FF406FFE0000C6E828",
INIT_17 => X"1B5FBE042FFFFFFFFEFFF226BC6467FF057FFE00012600A806189ABFFFFFFE02",
INIT_18 => X"FE7FFA11D985C7FF06E7F8BC0095B62D002654BFFE3FFE12553E183FFE3CF031",
INIT_19 => X"061FFFFD018DBC5F4E44085FFE3E3FFE7B3D70FFFB7CF0FCC23F7C045FFFFC3F",
INIT_1A => X"B0CFF22FFFFCBFFE7C74BFFFF187E0FCA1FFA80C4FFF643FFBDFE88C4A81E3FF",
INIT_1B => X"7C747FFFF7F1302077F6583DBFFFC57FFA7FE5A58D610BFFC247FC4F67E07E74",
INIT_1C => X"6FF23033BFFD9CFFF27FE18615EAE37FA001FE1D031CAFFC90F147947FFF1FFE",
INIT_1D => X"F53FF1EC07B2E57F801DFE7C9D94CFFFE50132936FFFFFFE5900FFFFF541A60C",
INIT_1E => X"DC05FD78B44E87FFF98003A13BFFFFFE5B03FFFFFE3CC6005FFC38027FF98DFF",
INIT_1F => X"FCC00079F4F7FFFE790FFFFFFC04B77E1FFA1817FFFDBEFFF57FFC3656F7637F",
INIT_20 => X"781FFFFE9E4263FC3F20009EFFF8F1FFE67FF9357B78E07FEC07FC48A00FBFFF",
INIT_21 => X"5EA00085FFC0EFFFC6FFF712C150A7FFE003FB98601A1BFFB641301FD877FFFE",
INIT_22 => X"F1FFF959820964FFF801F8F9E20065FF82C3E3C1F5CDFFFE7C3FFFFA4DDC0009",
INIT_23 => X"EC017D9B62C31CBFBC0706BFFAF5FFFE7FBFFFFF8B07200B7DF0018BFF884BFF",
INIT_24 => X"F6FF474FFF57FF1E7FFFFFFF69C6830E9A608387FFC015FFEAFFCF19BA3DA2FF",
INIT_25 => X"5FFFFFFEB24534880FC1C17FFF6851FF8CFFC434176306FFF00EFE1C8143CADC",
INIT_26 => X"5DE4E1CFFFCC93FFF2FF2236FE5746FFF40400E600F99B14F536E0AEFFFFFE0E",
INIT_27 => X"65FE347055F7867FF2E0646110550D78F8C195527FFFFF3E7FFFFFFC00042880",
INIT_28 => X"FA61BA5946115033FE499278BFFFFFFE7FFFFE06D4C464CCA7E0617FFE5D87FF",
INIT_29 => X"FF8293B93FFFFFFE7FFFC6375E45CE5BB2F0193FFF7DE7FF6DFC0003A00FE1FF",
INIT_2A => X"7FFFD920EBBB7CF3001C0EFFFD3CFFFFC5FE5802B807A13FF920D987EEAA5F57",
INIT_2B => X"0108079FFEE00FFECFFAC420382B41BFFDB1D525E11E6C46FFFB4FF0DFFFFFFE",
INIT_2C => X"1BFEF6713B0D163FFC71B0C5EE063DCC7FFFEE8C9FFFFFFE7FFFD8D9B4F1FA70",
INIT_2D => X"FEC013F9FC84E6933FFFE8B07FFFFFFE7FFFEE3AE3CA510081011D7FFE416FFE",
INIT_2E => X"FFFFF66C8FFFFFFE7FF87179D0163C00D303C5FFF9415FFF1FECD0E034489F4F",
INIT_2F => X"7FFC3F1C7A15E1300D4183FFFA013FFC1FE0B0B104999F2FBE80F7C7FEDBC681",
INIT_30 => X"8A801FFFCC12DFF84BC14270815FDE7E7EE6CB4DFFD8C374CFFFF4F7EFFFFFFE",
INIT_31 => X"D85E88E48419302F414C4F96FF7C9FA7E7FFF8AD6FFFFFFE7FFFFF100428ED9D",
INIT_32 => X"102C33F5FFDD0FC24BFFFF84CFFFFFFE7FFFFE3E615B7D8EE80013FF1CD17FF8",
INIT_33 => X"A9FFFFA0FFFFFFFE7FFFFFFFE20D0220D7003FFF9241FFF8583CBC8580533021",
INIT_34 => X"7FFFFFFFF94B79D67F011FFEA0427FFAE4FF1C9CE00550139EE81BD0FFA13FE9",
INIT_35 => X"861C2FFD0040FFF8D6BA3DF8818598A871460B41FFC877FB3BFFFFD81FFFFFFE",
INIT_36 => X"A0707E7DA194F8B6544EC037FFAC13FFB9FFFFFA27FFFFFE7FFFFFFFFCBF8BF6",
INIT_37 => X"0307CDC7FF012FFE3800FFFEB33FFFFE7FFFFFFFFCD067FA47E30F073841FFF0",
INIT_38 => X"E3C3FFFF226FFFFE7FFFFFFFFDA71FF95AB9FCA338407FE9B1F278B520183808",
INIT_39 => X"7FFFFFFFFEAFBFFCB112BE9F390B7FFD55F3725BC100F85CAF8707F7FEB0F27F",
INIT_3A => X"80E43E520782FFE15FF334FEE008C000476200DFFFC7558FE2607FFFE8730FFE",
INIT_3B => X"4FE334F680081800FE9E82C3FFFF90C7BA8A7FFFEC10CDDE7FFFFFFFFEAA7FFE",
INIT_3C => X"7FAC016FD7FD60C3EEB73FFFFAB1642E7FFFFFFFFC33FFFDA524FD8A0004FFC8",
INIT_3D => X"7A5DFFFFFE8E1ACC7FFFFFFFFD1FFFFE8D267FB880B7FFD87FF82DFEE80A1800",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFE43DFFFF1BA2FE8F80F4FFAB7FEC13F4100600009FEC0143E7FE0A20",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"47ADFFC9C023FFA0FFCA03F4A40600007FD801E0F1FF06D6FDE3FFFFFFAB25E4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_13_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"FFFE4C6FFFFFFFFFFFFFFE492AFBAAF03FFFFFFFFFFFFFFFF900036FFFFFFFFD",
INIT_01 => X"FFFFE04005BFEE3D1B90000400CF000007FFFEB400019EACBB8BFFFFF77EC87F",
INIT_02 => X"3FFFFFFFFFFFAAA950F001BFFFFFFFFED41554FAFFFF8740F0000C7EFFFFF816",
INIT_03 => X"17FFFFB243007BFB678FFFFFFD34162FFFFFEABFFEFFFFFFFFFFFFE34150EBF0",
INIT_04 => X"2A55140AFFFE693000003C8EFFFF9447FFFFD603CFFFD7D89590000000FF0000",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFF9E5AFD1303FFFFFFFFFFA00000FF006FFFFFFFFFE",
INIT_06 => X"FFFFB83CE5FFE6A8B550000000C3C0005BFFFFF623C023FA228FFFFFFE93AADF",
INIT_07 => X"3FFFFFFFFFF900000FFF1BFFFFFFFFFE3CE5555EFFF9043C000301C8BFFF30AF",
INIT_08 => X"5BFFFFFFB8001DFE1E9FFFFFFFFA502FFFFFFFFFFFFFFFFFFFFFFFFF496C0490",
INIT_09 => X"F0E55423FFE7B0000000044CEFFE51AFFFFAB4F327FFFE6FBD00000500000000",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFF939BC5E03FFFFFFFFFFF95013F006FFFFFFFFFFD",
INIT_0B => X"FFE2D0F0CFFFFE6FDB0003C0000000005BFFFFFFEA016DBF03DFFFFFFFFE69AF",
INIT_0C => X"3FFFFFFFFFFFFA900F00BFFFFFFFFFFDF039558BFFE1E0000000CADF4BFCB43F",
INIT_0D => X"43FFFFFFF541FCBFC01BFFFFFFFE596FFFFFFFFFFFFFFFFFFFFFFFFFF93AA0FC",
INIT_0E => X"0039566FFF9B403CF003CF75DFFA7FBFFFD740301FFFFE6FF43003F000000000",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFF925BC43FFFFFFFFFFFFFE50006FFFFFFFFFFFD",
INIT_10 => X"FF593031AFFFFA6FBA8000C00000000025FFFFFFFC12FC6FF05BFFFFFFFA031F",
INIT_11 => X"3FFFFFFFFFFFFFF90C1BFFFFFFFFFFFE00E958BFF9DD003FF0030F90BFF45AFF",
INIT_12 => X"CFBFFFFFFF36F01BF1ABFFFFFFE93EDBFFFFFFFFFFFFFFFFFFFFFFFFFFF895B0",
INIT_13 => X"40E5B2FFE190003FF00F0FAAFFFE47FFFF303001AFFFE96FFC60C00000000000",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFA3A683FFFFFFFFFFFFFF90C6FFFFFFFFFFFFF",
INIT_15 => X"FEF3FF02FFFFE16FFE180003000000000A7FFFFFFF99FFCB02FFFFFFFFE93F16",
INIT_16 => X"3FFFFFFFFFFFFFF9016FFFFFFFFFFFFF90EACBFFD60C000FF00FC0BFFFE1BBFF",
INIT_17 => X"053FFFFFFFCDBFC6F2FFFFFFFFE90056FFFFFFFFFFFFFFFFFFFFFFFFFFFF9394",
INIT_18 => X"90FADBFFB10F0000C00FD5FFFFC91FFFFEF3FF033FFFDC6FFF81000F000000F0",
INIT_19 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A83FFFFFFFFFFFFFE905AFFFFFFFFFFFFF",
INIT_1A => X"FDA0C0033FFFC82FFFEF0000000003F0C42FFFFFFFEAAF15B2FFFFFFFFE555AB",
INIT_1B => X"3FFFFFFFFFEBFFE906AFFFFFFFFFFFFF903FDBFFBDFCC003000F16FFFFA6BFFF",
INIT_1C => X"DE7FFFFFFFF06C55B1FFFFFFFFE6AAFFAFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0C",
INIT_1D => X"903C1BFF580CFC0300031AFFFF467FFFF8633009BFFFD46FFFF640C300F00FFC",
INIT_1E => X"FABFFFFFFFFFFFFFFFFFFFFFFFFFFF943FFFFFFFFFAAFFE506BFFFFFFFFFFFFF",
INIT_1F => X"F6900013BFFF702FFFFB9000000003C063BFFFFFFFFBAC55B2FFABFFFFEAAAFF",
INIT_20 => X"3FFFFFFFFE9AFE941BFFFFFFFFFFFFFF903C6FFF1800F00000002EFFFFF47FFF",
INIT_21 => X"777FFFFFFFFD2855B2FE5BFFFFFAFFFFFEABFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_22 => X"4031BFFF6D000000000333FFFD56BFFFDA00003DFFFFE02FFFF91030001503C0",
INIT_23 => X"FFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFE5BFE405FFFFFFFFFFFFFFF",
INIT_24 => X"C0F0C057FFFF8C2FFFFD6030002A5401B62FFFFFFFFEF850B2FE07FFFFFFFFFF",
INIT_25 => X"3FFFFFFFFEABFA406FFFFFFFFFFFFFFF4031FFFFB1030000000333FFFB1BFFFF",
INIT_26 => X"C12FFFFFFFFF5C54A1FE07FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_27 => X"4006FFFF81030000C0032EFFEDDCFFFF6CF0CCBBFFFF4D6FFFFE18000070EA41",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFBFFFA55BFFFFFFFFFFFFFFF",
INIT_29 => X"B403CCCFFFFE0D6FFFFFBDF000753BD7C1CBFFFFFFFFF5556CBE1BFFFFFFFFFF",
INIT_2A => X"3FFFFFFFFBFFEA95FFFFFFFFFFFFFFFE4007FFFF71000154F003D5FFD7A0FFF8",
INIT_2B => X"F16DFFFFFFFFE25A5B6A1BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_2C => X"001BFFFF2D316AA4F0030CBFD7F5FFF5900FFC0FFFFECDBFFFFFC75700614C3B",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFFBFFFA56FFFFFFFFFFFFFFFA",
INIT_2E => X"803FF11FFFFDCDFFFFFFE238002D403FC132BFFFFFFFFB5A5B291BFFFFFFFFFF",
INIT_2F => X"3FFFFFFFFBFEAA5AFFFFFFFFFFFFFFF90F1FFFFEDE47FFF4F0030CFFE94AFFF9",
INIT_30 => X"F12DBFFFFFFFFDEBA6C51FFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFC",
INIT_31 => X"031FFFE98E703EF9000C10FFE261FFF54000F2EBFFFC8E3FFFFFFF63AA5C503F",
INIT_32 => X"FFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFC3FFFFFFEBFEAA56BFFFFFFFFFFFFFFE9",
INIT_33 => X"4C00F33FFFFF7DFFFFFFFFB4FEAB54000577BFFFFFFFFE7EFAB01FFFFFFFFFFF",
INIT_34 => X"3FFFFFFFFFAA956FFFFFFFFFFFFFFFE9401AA5433A89FAFE40006AFFD2616FEB",
INIT_35 => X"4699FFFFFFFFFF9EBE6F1FFFFFFFFFFFFFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFC",
INIT_36 => X"4000FAFE3AD9FFC3E40182FFDEB10BBC3F00F3AFFFF931AFFFFFFFB4039A155B",
INIT_37 => X"FFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFC3FFFFFFFFE965AAFFFFFFFFFFFFFFFF9",
INIT_38 => X"FF00321FFFF4006FFFFFFF89025A1AAC96EEFFFFFFFFFFE2BE6B1FFFFFFFFFFF",
INIT_39 => X"3FFFFFFFFA556ABFFFFFFFFFFFFFFFFE413901BE4E280015340737FF9FB15B34",
INIT_3A => X"D5A2FFFFFFFFFFF7C3AACBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",
INIT_3B => X"052E98C3E078155549122FFE4FF1AEA3FC00075FFFFA001FFFFFFFD8C35B6FAC",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC3FFFFFFFEA5ABFFFFFFFFFFFFFFFFFFE",
INIT_3D => X"0000C92FFFD104CFFFFFFF866FECB0EB21B6FFFFFFFFFFF9FFAAB2FFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"3FFFFFFFEAAAFFFFFFFFFFFFFFFFFFF90A7D091944B85AA40964BFFF7FF6EAA3",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"3986FFFFFFFFFFFE3FE66DFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_14_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram : RAMB16_S4_S4
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"443444443358DFFFFFFFEB7555656AEFFFFFFFFFFFFFEC8545688789BBCDCBBB",
INIT_01 => X"CDFFEDA74469DEFFEDA9AA999AABBB988865679CEFFFFFFFDCBBBCEFFFFEB743",
INIT_02 => X"8FFFFFFFFFFFFFFFFEEDDDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_04 => X"BBBBCDEEEEFFFFFFFFFFFFFFFFFFFFFFDCBBBA9AA9ADFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"443344444347CEFFFFFFDA66667659DFFFFFFFFFFFFFFD975568989ABBCDDCBC",
INIT_06 => X"DEFFFEB9778ADEFFFEBABA999AABCBA98877779CEFFFFFFFECBBBCEFFFFEA644",
INIT_07 => X"8FFFFFFFFFFFFFFFFEDDDDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_09 => X"BBCCCDDEEEFFFFFFFFFFFFFFFFFFFFFFFEDCBBA999BDFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"443334444446BEDDEFFFC877778757CFFFFFFFFFFFFFFECA87898788AABDEDCC",
INIT_0B => X"DEFFFFECA9ACCDFFFECBAAA99ABBCCA99A97789CEFFFFFFFECBBBBEFFFFDA754",
INIT_0C => X"8FFFFFFFFFFFFFEEEEDCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_0E => X"ABCCCCDEEFFFFFFFFFFFFFFFFFFFFFFFFEDCCBAA99ADFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"443444554457BCBACDFEB878888767BEFFFFFFFFFFFFFFECCA99878889BDEDCB",
INIT_10 => X"EEFFFFFECBCDDDFFFEDBBBAAABBCCCBAAA98878ADEFFFFFFECCCCCEFFFFC8776",
INIT_11 => X"8FFFFFFFFFFFFFFEDDDCDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_13 => X"AACCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFEDCBBBAAADFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"44444567557BDDB99CEDA889A99866AEFFFFFFFFFFFFFFFEEDBA98999ACDEEDB",
INIT_15 => X"EFFFFFFFEDEEDDFFFEDBBBBBBBBCCCBAAA99989ABCDEFFFFECCDDDEFFFFC9996",
INIT_16 => X"8FFFFFFFFFFFFFFEDCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_18 => X"BBBCDCDDFFFFFFFFFFFFFFFFFFFFFFFFFFFDCCCCBAADFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"44334688659DFECAACEDA89BBAA9879DFFFFFFFFFFFFFFFFFEDBAABABCDEEEDC",
INIT_1A => X"FFFFFFFFFEFFEEFFFEDCCCCBBBCCDDCBBAABBBAAAAABCDEEDCCDDEFFFEECCDB6",
INIT_1B => X"8FFFFFFFFFFFFFFDCCCCDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_1D => X"CBCDEDDDEFFFFFFFFFFFFFFFFFFFFFFFFFFEDCCCBAADFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"4333479A87BEEEEDDEFDA9ACBBAB978BFFFFFFFFFFFFFFFFFEDCBCDCCDEEEEED",
INIT_1F => X"FFFFFFFFFFFFFFFFFFDCDEDCBCCDEEEDCBBDEDCA9888ABCDDCCDDDDDCBBCDEB6",
INIT_20 => X"8FFFFFFFFFFFFFECCCCDEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_22 => X"DDDEFFEEEEFFFFFFFFFFFFFFFFFFFFFFFFFEEDDCAAACFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"444469BB99CFFFFFEFECAABCBBBBA76AFFFFFFFFFFFFFFFFFEDCBCDDCDEFFFEE",
INIT_24 => X"FFFFFFFFFFFFFFFFFEDDEEEDCCDEFFFEDCDEFFDB876679ABCCDEEDB9778BED96",
INIT_25 => X"8FFFFFFFFFFFFEDCCDDEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8",
INIT_27 => X"EEEFFFFEEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFECAAACEFFFFFFFFFFFFFFFFFFF",
INIT_28 => X"44458BDC9ADFFFFFFFDBABCCBBBBA76AEFFFFFFFFFFFFFFFFFECCDDDDDEFFFFF",
INIT_29 => X"FFFFFFFFFFFFFFFFFFEEFFEEDDDEFFFEDDEFFFEB7555679BCCDEEC96457ADB75",
INIT_2A => X"8FFFFFFFFFFFFEDCDEEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2B => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2C => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2D => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2E => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_2F => X"8888888888888888888888888888888888888888888888888888888888888888",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(3) => BU2_doutb(0),
DIA(2) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(3) => BU2_doutb(0),
DIB(2) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(3) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
DOA(2) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
DOB(3) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_3_UNCONNECTED,
DOB(2) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_2_UNCONNECTED,
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_15_ram_r_v2_init_ram_dp4x4_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"00F00035BD17F3F60026AA0005DFFFFD080000000C000A620000000000000000",
INIT_02 => X"C04A50000C3FFFFDC000000000000CA27FFFFF537FFFA01F80006840108C0000",
INIT_03 => X"280C00000003DCA26FFE00105FFFB3C0000084B001CF000600E000119D1B83F3",
INIT_04 => X"43FC001653FF83C007DF803E6FEC006130000000622B1FEEA05220000D7FFFFE",
INIT_05 => X"07C0C060039AC80030030000122BD0F7D1F5E000057FFFFFD96C0000000227AE",
INIT_06 => X"000300F1326BF376E1FAC000037FFFFFE00000000002002E4078F8B2197FAAC0",
INIT_07 => X"62CC12020A7E3FFFE004000001070C3E4000FFF362C7EC710700F06E05F4AB08",
INIT_08 => X"E00C0000E01C19DC60E7FFC30089F2000301006E050B9C0500010001C2E7E9AC",
INIT_09 => X"7CFFC0863475F308C000C60007CC6FF10000C00E02F5A8B638B190000C703FFF",
INIT_0A => X"70008E0015ED4FF8494970000093C03F894082000DC3BFFFE11C0000D876CC1C",
INIT_0B => X"0F8380001204844FED9C03000CB23FFFF11C0000C3687FFE7F3FF2068871FD92",
INIT_0C => X"0230000004413FFFFC1C000042A7FFFE7FBFE7C6A465FE8660008E00D9128FFD",
INIT_0D => X"F40C0000447FFFFE7F9BEE6D32DBFEA6000004FF1787EFFE0F0200E016848450",
INIT_0E => X"7F8CC838C667FEE30000000302EC4FFFDEA20CC00B05B0487460000000AB3FFF",
INIT_0F => X"000000002E5FE7FEB1C00EC7C003B04508E0000008B3FFFFF00C000004CFFFFE",
INIT_10 => X"CD70C1036280781AF0E0000003C37CFFF00C0000050FFFFE7F06C818DE8FFE82",
INIT_11 => X"E003C0C086C67AFFF00C0000072BFFFE7FE7CC18330FFF8E0080000005E97387",
INIT_12 => X"EC040000000DFFFE7FF1CF000CF7FFB000801F007CF6EFFE765901006708083C",
INIT_13 => X"7FFCC78042E7FFD240000E00FE3AF21DFFBCC00000D440046003F8C10799FDFF",
INIT_14 => X"600000037FFCDE07FB9460013110082A7D07FA01C0A2FBFFE400C000010CFFFE",
INIT_15 => X"FECC11023B75F03D381B4001C0BFF2FFE5E7C00801C57FFE7FFCE7840D801FFA",
INIT_16 => X"C16AA1C1043DF0FFE6E0000405E2FFFE7FF8E7180D842FFC200000016FFFFFFF",
INIT_17 => X"E5D800006DF1FFFE7F83E3800D4C2FFE400000000FFFFFFFFC97687018F9D0C2",
INIT_18 => X"7F3000E000890FFF638000000FFBFFFBFDE0F27819FED23C312EBCA0064FFCFF",
INIT_19 => X"B3C000007F3DFFF9FC6F053003FBD0BFD0B13E5F00B1F4FFE9C00060DFFFFFFE",
INIT_1A => X"FCAFFDB0006851E5706FC04680DEE1FFE9E400605FFFFFFE7E4E75300002C1FF",
INIT_1B => X"1014F879BEFFC3FFE8BC00615FFFFFFE7E6C0368000086FFF80000001F42FFFC",
INIT_1C => X"EA8C01C17FFF79FE7F9A0C3400003ABFFA0000001F6037FCFC5FFFA0C02C5159",
INIT_1D => X"7FE50D7400606047F80000001E3C40FCF96FFF9080B2502A200DFC153EFB13FF",
INIT_1E => X"FDB00007FE82AF3C7A8DFFF4C23C5384A409D87F007C67FFEA8C0183FFFFFFFE",
INIT_1F => X"DE04FFF500FE50824011F878007D07FFEB9C1F83FFFFF1FE7FFD41B300000D47",
INIT_20 => X"5192FDFEF13A03FFEDB00101FFFFFCFE7FFFC058380001407E40000F0E2447C0",
INIT_21 => X"EDA9000AFFFFE8FE7FFF642FD40F00C75E00001E07BF073FEC78FFFDD4BCC3F5",
INIT_22 => X"7FFF902EF40F008085BC000013E453873CB9FFFE8005B7F8C1D37FF031BA0FFF",
INIT_23 => X"A37CC0000FDB97581A1A7FFF608415893014FFFE070D17FFD3408015FFFBC2FE",
INIT_24 => X"090B2FFF808426FF092BFFF70FA307FFB0874023FFF7F2FE7FFFE81EE0060340",
INIT_25 => X"0C57E62007C30FFFB2537FCFFFE782FE7FFFD41B280000389C7FE0C017E3BFD0",
INIT_26 => X"702A602FFFFB00FE7FFFE246C6000001C300FFC0F0F727E0020229FFE8800400",
INIT_27 => X"7FFFFA2FCBC00618246003E0FFFD27900C8205FFE460059FF20FC3C20CCA9FFF",
INIT_28 => X"5759E078DE7E98C80082019FF27C087FFDFE05007CFE2FFEE33E0C5FFFCF027E",
INIT_29 => X"38418837F93C06BFFB3E05000C970FFDC0FDFCBFFFD7247E7FFFFE3FE1F00188",
INIT_2A => X"FABE34C08DBE3FFDE3FCF8BFFF20714E7FFFFFFFF2CC18017FA9F03C414F71F4",
INIT_2B => X"F7FC087FFFC01C067FFFFFFFFAF1BE335FD63C1F4069B37478619503FD80083F",
INIT_2C => X"7F0191FFFE1544001F1A3E07C25A72B5667096CFFFC0ED7FF6FE3AC14C3C5FFE",
INIT_2D => X"7F828E0385CA8E3382381F853F6103FFECFC7EC014701FFE7BFC057FFE10FE52",
INIT_2E => X"039405EE6799B7FFCFF2FFFF6FEEFFFE4BFEF57FFD907F7A7FC7D1FFFFF4A001",
INIT_2F => X"E3A6FC397FF8BFFC97FFFF7FFC71FFE67C6A01DFFFFC6C027FFD960103EF58C2",
INIT_30 => X"2FFFFA7FFD717FF86FBD84503FFC400DFFFFD000B1AC464F87D604F037A13FFF",
INIT_31 => X"017F23182FFE1396FFFFF800C1BF1202430E0A7FE635FFFFF38DFD3BA870BFFD",
INIT_32 => X"FFFFF86070FFCAD1A14464FFFF0BFFFFFBFDFCFDC0D0FFFD5FFFFAFFF920FFF8",
INIT_33 => X"10460467FFF0FFFFF03CF0FEF2B1FFFD7FFFFAFFF630FFF8106FA9701BEF112F",
INIT_34 => X"EE01C6FF9BE17FFD7F7FC6FFE407FFE4386FEA7C6A0FF91FFFFFFE1830FFC988",
INIT_35 => X"7E0025FFF801FFE4100BFF04E66FFF1FFFFFFC9C03FFED2A28498C35FFFDBFFF",
INIT_36 => X"03B1FD80C069FECFFFFFFEC0007FFDF2344A880EFFFEBFFFD29FB17FE7117FFE",
INIT_37 => X"FFFFFF60013FFE1DD4498901FFFF5FF8163FB97FCAD07FFEDE0073FFE00FFFE0",
INIT_38 => X"F24001C0BFFF6FC0D23FB87FD720FFFF1EF357FFC123FFD801C5FFD17E8AFEAF",
INIT_39 => X"EA7FB1FFD7B0FFFF8CF357FFF007FFC871807FE72182B427FFFFFFF100DFFF0F",
INIT_3A => X"AD9757FFEC1FFFE007113FE0078034D47FFFFFF9B26FFE3FF81041C08FFF1031",
INIT_3B => X"00103FE024F03008BFFFFFF0800FFE87FC1801E167FEE947FAFFAFFFDE12FFFF",
INIT_3C => X"5FFEFFF800A7FF13FB2010F054BEE99FF8E72FFFFA33FFFFF11FAFFF840FFFD0",
INIT_3D => X"FEB0D0F059BF483FF787AFFFE522FFFFB32FB7FFA43FFF203C003FF373E80003",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"F3C0BFFFC020FFFF6B7F8FFFE4FFFE801CF09FFA7A003C00DFFE1FFC805BFF4F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"EBE78FFF04BFFC407CFB0FFD73197C000BFF5FFFD009FFE1FC41507046BFB9FF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_16_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7F9A87DE39A23C0009FF9FFF6306FFE5FF87507038BF87FFFB80FFFFEA23FFFF",
INIT_01 => X"017F8FFFEB837FD5FF03500608BFFFFFF9085FFFF6A7FFFFDB171FFFC0FFFA80",
INIT_02 => X"FFF4400D0C80FFFFF800FFFFFD81FFFFFB1A3FFFC07FFD427FFF5CFFDFFA8C00",
INIT_03 => X"FC01FFFFFD0FFFFF371AFFFE03FFF2447FFFEEFF77FE4C00019FDBFFE4C1BFD1",
INIT_04 => X"0F1BFFFE80FFF24A7FFFFFFF34CFCC7FC027F8FFF6005FF1FFFDC0043880FFFF",
INIT_05 => X"7FE31FFF2318DCFF601BFCFFF9181FFFFFF900073FC3FFFFFC03FFFFFD0FFFFF",
INIT_06 => X"E06BFFFFFCDC5FFFFFF90C6DE007FFFFFCC7FFFFF90BFFFF1899FFFE05FFF2C8",
INIT_07 => X"FFFA84A3E787FFFFF8FFFFFFF61BFFFF90B9FFFC05FFF0CC7EE0D770449C0427",
INIT_08 => X"F9FFFFFFCA07FFFFB773FFFF43FFEC167BE01F1EEB2385DC40023FFFFFAF2BFF",
INIT_09 => X"B723FFFB4FFFD46A4A09001FB85E417D0008AFFFFFD789FFFFFBF2D2C787FFFF",
INIT_0A => X"58D101403ADC09FCA18027FFFFEFC6FFFFF30C4EBC70FFFFF1FFFFFFB43FFFFF",
INIT_0B => X"94004DFFFFEBF37FFFF632FD00006FFFF3FFFFFF544FFFFFA64BFFF807FFB4A6",
INIT_0C => X"FFF90EF887F86BFFF3FFFFF9FA7FFFFF5D1FFFFE1FFFA85E43F00030E2C02FFF",
INIT_0D => X"E7FFFFFBEA1FFFFF5E1FFFF027FFB13E27000099E1326FFFF50004FFFFF9F93F",
INIT_0E => X"5A9FFFF40FFFE2BE3000668000F863FFFDA081BFFFFC689FFFFFF0F8A71895FF",
INIT_0F => X"00006400000017FFFFC4209FFFFE844CFFFFFE7B7F0409FFC7FFFFFB8CFFFFFF",
INIT_10 => X"FF581C5FFFFFAE2EFFFFFE166F4601FF8FFFFFF8643FFFFF421FFFE05FFFE97E",
INIT_11 => X"FFFFFE0E8F5D65FF8FFFFFFFE5FFFFFF4F9FFFE85FFF267E001CF80010704FFF",
INIT_12 => X"9FFFFFFFF07FFFFFF07FFFF01FFEF1FE0000F80011009FFFFFCC061BFFFFD31B",
INIT_13 => X"8FFFFFC03FFE2FFE01000010010137FFFFFEB809FFFFF5CD3FFFFE3AEF5AA7FF",
INIT_14 => X"4100003C00018BFFFFFFD4057FFFFAE6410FFFBF5D9CC0FF1FFFFFFFCF7FFFFE",
INIT_15 => X"FFFFFFC15FFFFD313FE7FF8D21EFDD7F7FFFFFFFFCFFFFFE3FFFFFF07FFD5FFE",
INIT_16 => X"1E37FFB0064FDF3FFFFFFFFF9EFFFFFC7FFFFF807FFA7FFE2000003E00029BFF",
INIT_17 => X"FFFFFFFFD1FFFFFCFFFFFFE07FFA3FFE2000001FE0027BFFFFFFFC505FFFFF9C",
INIT_18 => X"FFFFFFD07FF8BFFE27070000E0018BFFFFFFFFF519FFFFAFB3EFFFE9841FFE1C",
INIT_19 => X"270700000000303FFFFFFFF266FFFFD7D64FFFC9009FFF1CFFFFFFFFC5FFFFFF",
INIT_1A => X"FFFFFFFF91BFFFE9F7DFFFE8003FFFFFFFFFFFFF4BFFFFFFFFFFFF103FF45FFE",
INIT_1B => X"CFFFFFA80627FFF3FFFE1FFF4FFFFFF3FFFFFF54FFE8BFFE340604000080020F",
INIT_1C => X"FFFDDFFFA7FFFFF7FFFFFF8CBFFAFFFE5461200000000067FFFFFFFFD4D7FFF4",
INIT_1D => X"FFFFFC0ABFDBFFF050CF0000000014203FFFFFFFF415FFFD21FFFF840A07FFE3",
INIT_1E => X"48C0F001001B2CFFDFFFFFFFFC4E7FFEA2FFFE44115FFFE7FFF65FFFFFFFFFFF",
INIT_1F => X"AFFFFFFFFFABDFFFC17FFC5C711FFFE7F8CB9FFE4FFFFFFFFFFFFF023FC7FFF0",
INIT_20 => X"EC3FFFF03883FFE7FFB4FFFE2FFFFFFFFFFFF82FFFFFFFF818701031001927C7",
INIT_21 => X"FFA86FFF3FFFFFFFFFFFFA047FFFFF90700FF0200010180017FFFFFFFFECD7FF",
INIT_22 => X"FFFFFE3DFFFFFF400400600040000E08943FFFFFFFFAB4FFF3DFFDF01C8FFFE7",
INIT_23 => X"0460014000001101C96FFF4FFFFEBD3FEBAFF838299FFFE7FFB06EFF3FFFFFFF",
INIT_24 => X"07E6FDE7FFFFAB2FFDDFFBEFAF4BFFE7FF907EFD1FFFFFFFFFFFF419FFFFFD84",
INIT_25 => X"FED7FB628B1FFFE7FFA22FFC1FFFFFFFFFFFF2FAFFFFF574000300C0E0010941",
INIT_26 => X"FFE027FE5FFFFFFFFFFFF8AAFFFFD9980003C0E0303E0633E0076113FFFFE6CB",
INIT_27 => X"FFFFC1E1FFFFC77A0001F800120000F0214076EFFFFFF5FA7F6FFC7805F7FFE1",
INIT_28 => X"001064001010D8300000008FFFFFFD3E3FB3FF27C687FFE0FF0387FA5FFFFFFF",
INIT_29 => X"0080008DFFFFFFD8AF45FFFFC27FFFFFFFDBFFF67FFFFFFFFFFF9065FFFEDCDE",
INIT_2A => X"6FA2FFFF4A7FFFDFFFD9FFF47FFFFFFFFFFFE3EFFFFC86BE001E240000C69400",
INIT_2B => X"FED8FFF5BFFFFFFFFFFFA0FBFFFB34FE00FF0000016F9238F383C0A17FFFFFAC",
INIT_2C => X"FFFE67FBFFF5DFFE00002000E2E8FCE0E104200397FFFFD39DD17FFF8C7FFF87",
INIT_2D => X"00008000F22C8508C004200017FFFFF6C470BFFF417FFF01E41BFFE5BFFFFFFF",
INIT_2E => X"00078680C7FFFFFC93085FFE449BFF80C18DFF8CBFFFFFFFFFFC73D7FFF01FFE",
INIT_2F => X"B4AC23F1C15A3F80019C7F98FFFFFFFFFFF92FD7FFFFFFFE00000020F205E5FA",
INIT_30 => X"711C1FB0FFFFFFFFFFF63FC7FFFFFFFE0000000061599DF600028000037FFFFF",
INIT_31 => X"FFFBCFFFFFFFFFFE3EC0000000E0463838057FC179BFFFFFF24E33FDC1C2BFFB",
INIT_32 => X"00C000000000BE003C1DA131E48FFFFFFAEE0DE00001FFFAD64C4F41FFFFFFFF",
INIT_33 => X"18318FD0002BFFFFFC83EAE0008E7CF928403F31FFFFFFFFFFD0AFFFFFFFFFFE",
INIT_34 => X"FFA32D64906DF8F817B1BEBD7FFE7FFFFFA05FFFFFFFFFFE00C0000300080400",
INIT_35 => X"0419BEB57FFC3FFFFFC07FFFFFFFFFFE4000000103CB4200400E7812008AFFFF",
INIT_36 => X"FF82FFFFFFFFFFFE30000001C3E7B88006E0000780127FFFFFEF5228D051F0FB",
INIT_37 => X"4400008181C47C000010000680607FFFFFFC2146404E300483E73EA17FFC3FFF",
INIT_38 => X"98082600018027FFFFFF00DF600357C0706CDF22FFFBBFFFFD09FFFFFFFFFFFE",
INIT_39 => X"FFE3603F0003A3708E17ED02FFF77FFFFA27FFFFFFFFFFFE760F00001001F908",
INIT_3A => X"0E0A1E8BFFCBFFFFF45FFFFFFFFFFFFE7C00000030FFC2FF61060200030017FF",
INIT_3B => X"C83FFFFFFFFFFFFE000000FF21031B0E20B01A180FC003FFFFF66000C1486E3F",
INIT_3C => X"3100001021CB00E7FFF188E47883E4FFFFC00000C698400F0C06FA1DFF92FFFF",
INIT_3D => X"FFFE00EC0C01FA8E8FC00000FF8786F16C02843DFF75FFFFB2FFFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"CFD90100C18F278054213B3BFCC5FFFF6DFFFFFFFFFFFFFE3100000021F7FFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"0800E7BDF987FFF9F7FFFFFFFFFFFFFE71000000F1B7FFFFFFFE00F41C9031DF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_17_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"6FFFFFFFFFFFFFFE00030000F00FFFFFFFFFBBFC3CB000004FD90680002B7800",
INIT_01 => X"00078000BCBFFFFFFFFFBBFFFFD800012BC80FC001605801B0001F3F3B83FFF3",
INIT_02 => X"FFFFFFFFFFE4CE0E0D901FC482615C07FE003E3BD98FFFEF9FFFFFFFFFFFFFFC",
INIT_03 => X"00800000C25042037E687E746D17FF9E7FFFFFFFFFFFFFFE00078000063FFFFF",
INIT_04 => X"FE6476CB3E1FFF3DFFFFFFFFFFFFFFFA00060000031FFFFFFFFFFFFFFFFF7D20",
INIT_05 => X"FFFFFFFFFFFFFFF800000100E3DFFFFFFFFFFFFFFFFFFD8300F00000C3309650",
INIT_06 => X"000000410B5FFFFFFFFFFFFFFFFFFEC0000100008032C86AFA81E4C2FECFFCF3",
INIT_07 => X"FFFFFFFFFFFFFF2003000000003578603A83448E3EBFF9CFFFFFFFFFFFFFFFF4",
INIT_08 => X"01A00000003C1A0D7A82C49FE2FFF63FFFFFFFFFFFFFFFE810800001745FFFFF",
INIT_09 => X"F50289DFDCE7CDFFFFFFFFFFFFFFFFA20080000D287FFFFFFFFFFFFFFFFFFF90",
INIT_0A => X"FFFFFFFFFFFFFE8400C00010DA0FFFFEFFFFFFFFFFFFFFD620000000183066CC",
INIT_0B => X"00F00136642FFFFAFC17FFFFFFFFFFF6C000000C18063E54F9020F1F5F6B33FF",
INIT_0C => X"F0185FFFFFFFFFFF3000C00070011C70EA650C3FED74CFFFFFFFFFFFFFFFC218",
INIT_0D => X"D00080004073C0074A6B2C3EDEB73FFFFFFFFFFFFFFF1CE206F013014E4F4F72",
INIT_0E => X"FA6A0A3DBF48FFFFFFFFFFFFFFFF1CF202F0299724607FF80100CFE007FFFFFF",
INIT_0F => X"FFFFFFFFFFFFEFF4001C10A239770001F80000FF0387FFFFF800001000425801",
INIT_10 => X"001C1738377F600FF8006080F8E3FFFFE1C00000011E800544400A7BBF73FFFF",
INIT_11 => X"FC060070F87FFFFFD8C0000007D3E3898000467D7E0FFFFF3FFBFFFFFFFFFF22",
INIT_12 => X"CC00001F079336108000447FFE7FFFF0B80BFFFFFFFFFCE20078DFF9A877EEFF",
INIT_13 => X"400214FFEFFFFF830C37FFFFFFFFFA803C03BCF8286004FF00801EE1FFFFFFFF",
INIT_14 => X"F08FFFFFFFFFFA02261BF432800007000000DCFFFFFFFFFFF000000607084897",
INIT_15 => X"002BE4E381800100001B3FFFFFFFFFFF807000000384E0A0A90294FFCFFFFC31",
INIT_16 => X"0057FFFFFFFFFFFDAFF8000008984FE6AE306CFF7FFFFD9E00DFFFFFFFFFD438",
INIT_17 => X"87F800000034C99F4E3101F8FFFBF3BF3F1FFFFFFFFC5FC07FB7F1C600E01D80",
INIT_18 => X"C1613BF1FFF61F7FFC9FFFFFFFF4FC306F9F47C000101C08865FFFFFFFFFFFFA",
INIT_19 => X"F93FFFFFFF9663C87FFF00C0001C7E0FC4FFFFFFFFFFFFF903B0000020F4BFB4",
INIT_1A => X"7FE6C060001CFC6B8FFFFFFFFFFFFFF51C00000005037C9180607BCFFFF6047F",
INIT_1B => X"FFFFFFFFFFFFC38ED40000000D7790DA0060592FFFE8141FF0FFFFFFFE4E4976",
INIT_1C => X"DEC100000D4363BA0462180FFFF803CFE1FFFFFFF93FAFFA7FE58000180C015F",
INIT_1D => X"C062E4FFFFE8064003FFFFFFCCFC3FFA7FF300003C1C027FFFFFFFFFFFFFA630",
INIT_1E => X"0FFFFFFF63F2FFF67FF60000381C43FFFFFFFFFFFFFFA24FFDE000E08957295A",
INIT_1F => X"7FE46086100000FFFFFFFF8FFFE94CBFFF8000FF00C1AA2200602DFFFFE031A6",
INIT_20 => X"FFFFFEA7E0FC42FFFFD7000303404A63A0E14BFFFFD9989FCFFFFFF6308BFF72",
INIT_21 => X"FF4E01031EA0D59080A047FFFFB0809F8FFFFF989FF3FE7C7FE8C083380C0DFF",
INIT_22 => X"80E37FFFE0A421601FFFFCE04C07FEFE7FC2400F8051FFFFFFFFFF93300CFDFF",
INIT_23 => X"FFFFE3033FFFFFFE7EC04080E4BFFFFFFFFFFE2BE01D03FFFF523B030AB9B4F0",
INIT_24 => X"7C82638005FFFFFFFFFFF3847862FFFFFE637C01DFB9EF3320827FFCCF8023BF",
INIT_25 => X"FFFFC8E303CCFFFFFCFF79004799DFA600037FFDC799427FFFFF3C3CFFFFFFFE",
INIT_26 => X"FBFC200040D03FB80006FFF83F515E7FFFF0E7C3FFFFFFFE7641031057FFFF3F",
INIT_27 => X"878DFFE2FCDFDF7FFF0FFCFFFFFFFFFE45B501675FFE6621FFFF6E20FF3CFFFF",
INIT_28 => X"FC3BFBFFFFFFFFFE28BE00D47FEFC665FFFEA3201CFDFFFFEFFE731801507F31",
INIT_29 => X"71AC8037FFCE2109FC7D806F13EBFFFF8FFFB21C2E6DFEDD8783FF9AC3BFFC7F",
INIT_2A => X"052D0000E797FFFCBFFBEC1C19AFF3A0064BFF3686FFFFFFFBFF6FFFFFFFFFFE",
INIT_2B => X"3FFBE31C2FCFECC80029FF4095FFFFFF07F61FFFFFFFFFFE45D00033FF918182",
INIT_2C => X"0021E0A597FFFFFCFFC0FFFFFFFFFFFE05A0813AFCA21C23867C27C3CE6FFFFB",
INIT_2D => X"9800FFFFFFFFFFFE18A0010A748E1F08C0800019679FFFF5FFF3ED102F87D734",
INIT_2E => X"6C920003FC3E0FA20100032FD5FFFFEAFFF7FA102687D7D8003973771FFFFFE3",
INIT_2F => X"0380032719FFFFD5FFE7F800A80FE9E000800937FFFFFF1F67F07FFFFFFFFFFE",
INIT_30 => X"FFE7EC00AF7FF2C000016FFFFFFFFCFFDFC7BFFFFFFFFFFE7C070107F1309E2C",
INIT_31 => X"001F53FFFFFFF3F83FB9DFFFFFFFFFFE6018031600F07C5006C3803215FFFFAB",
INIT_32 => X"FFA31FFFFFFFFFFE78D347A820F001E30C001FA685FFFF57FFEFE400DFFFFAC3",
INIT_33 => X"481E585164070361C0009F8095FFFC4FFFFFD5C1DBFFF4030098A7FFFFFFCFC3",
INIT_34 => X"01C1BFFD4BFFFE9FFFFFDA60879FF5038001AFFFFFA20007FFB37FFFFFFFFFFE",
INIT_35 => X"FFFFC8600367EAC100015FFFFE781FE0FF16EFFFFFFFFFFE27FFFB61100F3E07",
INIT_36 => X"1C01D83FC0D87FEE3E140FFFFFFFFFFE4FFFFB83000E8C0781027FFC0FFFF77F",
INIT_37 => X"DEE637FFFFFFFFFE6F0BC1110003E9838F91FFFFFFFFFF7FFFFFC8600497CCE0",
INIT_38 => X"36043D00012640800FA1FFFFFFFFDBFFFFFFBE20148790E01C0018270089FFC6",
INIT_39 => X"00D7FFFFFFFF90FFFFFFFF2050AF20011800701FC0BA7F992E8607FFFFFFFFFE",
INIT_3A => X"FFFF08009EEF60030004A1EFF1457FA0D19E0FFFFFFFFFFE11E38A1C0155C980",
INIT_3B => X"007C9F9FF3837F60263FE7FFFFFFFFFE485BFC1803A7B1809CAFFFFFFFFF81FF",
INIT_3C => X"1FE66FF03FFFFFFE6F340000038F26005C5FFFFFFFFD93FFFFFFCB90DE1F9003",
INIT_3D => X"726A8180037FC31EB87FFFFFFFF807FFFFFE0DB0503FD00380C0AFFFEF427F45",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFF00FFFFFFF688A7B9FD00380004FFFD8A1BFE780027FEB9FFFDFFE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFCD79A3D8FD001800037FFBB6C3FCA8103FF9F1FFFFFFE1C3303C00C2C9EE4"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_18_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"900079FFB7E47EE000C360781FFFF8FE702301000CAA9F20DFFFFFFFFFD47FFF",
INIT_01 => X"00C2FFE7BFFFF006083803E00EA67F877FFFFFFFFF90FFFFFFFEFE921C07F4E0",
INIT_02 => X"6C0600E00E38F839BFFFFFFFFF803FFFFFFBFE001C00C64C07809AFFB7FCFCE0",
INIT_03 => X"7FFFFFFFFD817FFFFFFDAFA05C0184140484A2F050FEC400000300DFFFFFF026",
INIT_04 => X"FFF33F03EBC7800A073C32878C010C880000193FFFFFF8F669C40009C444E1B4",
INIT_05 => X"0038B2041EFF00F00C2136FFFFFFF1A66D5800094003CCB3FFF87FFFF301FFFF",
INIT_06 => X"000058FFFFFFE1026DD3000A903E14FFFFFD3FFFF889FFFFFFFD5FC0947D6036",
INIT_07 => X"6D8B0002303ED7FFFFFCBFFFB083FFFFFFE13FCF3C3AF87F00003CFB6000000C",
INIT_08 => X"FFF43FFF0C17FFFFFFFA7FCD6C38F41B24088038003013DC600BA7FFFFFF0006",
INIT_09 => X"FFC0FFE6AC7400FB06020C000080CBF9001BEFFFFF0F000E66107962263C5FFF",
INIT_0A => X"0412C20001C29BFA60061FFFF80FFFFE71B0004E3C603FFFF836BFFE0837FFFF",
INIT_0B => X"D1071FFFF8FFFFFE7FA0000F19E1BFFFF4627FFC800FFFFFFFF7FF728C27E1BD",
INIT_0C => X"7F2807CC01C27FFF8C1AFFF8007FFFFFFFD1FF1EEF9FC27E9C35470003CAD5F9",
INIT_0D => X"6BE1FFF0801FFFFFFFAFFFC70E7240FA38C2D0030747C9FF5191BFFFFFFFFFFE",
INIT_0E => X"FF4BFFCB0874D7F8210058000007F7FFD3893FFFFFFFFFFE7F8723A40084FFFF",
INIT_0F => X"8261800003DF60FFE3835FFFFFFFFFFC7E465E7D5469FFFF57C1FFFF82FFFFFF",
INIT_10 => X"608F2FFFFFFFFFFC79412F05560FFFFCA38FFFCB85FFFFFFFF47FF5ACC5D81FD",
INIT_11 => X"763EF889BB0FFDFBC183FF41307FFFFFFFDFFF063C478BFE4312FC00476E50FF",
INIT_12 => X"009BEF4028FFFFFFFF47FFC41D2E43FFC377F640E23CBB7D40309BFFFFFFFFFE",
INIT_13 => X"FE8FFE4D4C4B5FFF02FFFB00615CBDB330209BFFFFFFFFFE6502237E3E823F75",
INIT_14 => X"017FFC00083C4CB1E03109FFFFFFFFFE741950DF3F2FF86A4327AF9013FFFFFF",
INIT_15 => X"4E0F0E7FFFFFFFFE742750DFFFB004E9C96FE00001FFFFFFFEBFFD9E0059A3FF",
INIT_16 => X"73CFAEBFFE50C1E1889F000023FFFFFFFE3FFF1EC85D23FFA1DFFD80008FB070",
INIT_17 => X"187FFE0407FFFFFFFC0FF91E7C47CFFFE4B7FD800107B4700607867FFFFFFFFE",
INIT_18 => X"FF7FF70FC8C7EFFFE657FDBC0087C3790018CC7FFFFFFFFE791FEEFFFDBCF031",
INIT_19 => X"E64BFDBD0306792B8E38B83FFFFFFFFE7CFEFFFFFF7CF0FCC97E3C041FFFFFFF",
INIT_1A => X"E030B39FFFFF7FFE7FF87FFFF807E0FC8BFC280C9FFF98FFFC3FFB03A807CDFF",
INIT_1B => X"7FF8FFFFFE0000203FF9583C3FFF7BFFFAFFFFC3E96742FFE22DFE0F6242BFF8",
INIT_1C => X"7FF030317FFEA0FFF83FF59200EE45FFA015FE0D01B03FFFC8003BB3FFFFFFFE",
INIT_1D => X"F4FFFA0C12FE41FFC009FE0C1CD08FFFE600FC4F1FFFFFFE7FFFFFFFFD7E760C",
INIT_1E => X"EC09FF70346ABFFFF3000360F7FFFFFE7FFFFFFFFA3E16009FE03803FFFAC6FF",
INIT_1F => X"FC0000C00C0FFFFE7FFFFFFFFFF9277DBFC21810FFF231FFF97FFBC8A2FAC3FF",
INIT_20 => X"7FFFFFFF7F7C83FE7F900097FFE4FFFFF1FFFACF5A7DC0FFFC09FD34202B07FF",
INIT_21 => X"3F800087FFF8E1FFEAFFFCEA599280FFC00DFE46600C5FFFC28130BFE7F3FFFE",
INIT_22 => X"C0FFF4E0114403FFF80FFE58E18707FFD303E09E063BFFFE7FFFFFFCDE60000A",
INIT_23 => X"F00FFA3F6183867FD80701DFFCF3FFFE7FFFFFFAA54700075FB0019FFFC041FF",
INIT_24 => X"ECFF409FFF8FFFFE7FFFFFF9B9464CFF1E6083BFFFB00BFFF9FFE6E6CD4B67FF",
INIT_25 => X"7FFFFFF928C4B87218C1C12FFFE84FFFEBFFCAC42A5787FFFC017BBF008100BF",
INIT_26 => X"5FE0E07FFFCC83FFA5FF913AA5FF81FFF405FD8FC0007A89FC360041FFFFFFFE",
INIT_27 => X"C7FF6482A31F82FFFCE799F71039FD29FD80990EFFFFFFFE7FFFFFFAD6C20064",
INIT_28 => X"FA60C393E6355E19FF0F643EFFFFFFFE7FFFFFFB318390182DE0609FFFDD9BFF",
INIT_29 => X"FFC594703FFFFFFE7FFFF8086042FC607AF0183FFE3DC7FF83FE4001C0E7E27F",
INIT_2A => X"7FFFE11F5706FAF0001C0DBFFFBCC7FF4FFD9801381BC17FFE23E135969C3845",
INIT_2B => X"0108047FFC6037FF0BFE0420382B803FFD316157D5001D4BFFFCE7F8FFFFFFFE",
INIT_2C => X"87F90671380396DFFFB0E197F601CE46FFFFF908FFFFFFFE7FFFE03EDCF04670",
INIT_2D => X"FE80228FFC022E967FFFF0C49FFFFFFE7FFFF1FCF032B800810101FFFF410FFE",
INIT_2E => X"5FFFF9771FFFFFFE7FFFFFFE1FDA7200CD03C8FFFE415FFC1FF5E0E033311F5F",
INIT_2F => X"7FFFFFFF83C77CF8134183FFFA011FFD17F7E0B003491F7FFF400779FE9ADFC7",
INIT_30 => X"AE8003FFFC12FFFC77FEE07300111E03FFC6638EFFDABFE39FFFFB7B7FFFFFFE",
INIT_31 => X"963F68E00427D03F3E2C1FE4FF9D3FE84FFFFF29FFFFFFFE7FFFFFFFF9E7DB69",
INIT_32 => X"40AC17FAFFFC9FE437FFFF071FFFFFFE7FFFFFFFFDB7B114BE000FFFA8D0BFFC",
INIT_33 => X"0BFFFFC0DFFFFFFE7FFFFFFFFCFB9BCA91001FFF62417FFA75BF9C860058D00D",
INIT_34 => X"7FFFFFFFFE7833E6010127FF8040FFFC3E3D5C616013101E09080FC1FFA04FFA",
INIT_35 => X"78002FFE4043FFF03FFEBC9B0193988E53C60FDFFF903FF191FFFFE03FFFFFFE",
INIT_36 => X"25F97DA2218398985AEECBEFFF0827FDD3FFFFFC1FFFFFFE7FFFFFFFFF3F17F9",
INIT_37 => X"1807C42FFF7A15FFB3FFFFFF30FFFFFE7FFFFFFFFF1F2FFEF81C7FFAB843FFFC",
INIT_38 => X"4800FFFFBF1FFFFE7FFFFFFFFE38BFFCE1FE9EE63843FFF145FC7A50A008981C",
INIT_39 => X"7FFFFFFFFC30FFFDA31D3DFC3908FFED2FFD73E2810FD8405C07021FFFE50BFF",
INIT_3A => X"A80A7D8C0783FFE90FFD30EF40060000FE220237FF3A617FB87CFFFFCFEFFFFE",
INIT_3B => X"9FF130E920061800FF1E8137FFFD22BFD8F6FFFFF7F0FBFE7FFFFFFFFF30FFFD",
INIT_3C => X"FFAC007BEFFEB17FF0CCFFFFFCCE62267FFFFFFFFF3EFFFF14CA7FEC0000FFF0",
INIT_3D => X"FC8BFFFFFF307E1A7FFFFFFFFE1DFFFE0CCBFE1480B0FFD1BFE426E630041800",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFF83BFFFE984CFF0380F0FFD0FFE805EF180000007FFC0059C3FF515F",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"804EFF99C024FFA2FFF007C2680000001FE000FDDBFFA98FFE97FFFFFFCC5BE2"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_19_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"FF0FFFEE7E0FB7E7FFE04BFFFC3FFFFE0FFFFFFFF3FFFBDC0000000000000000",
INIT_02 => X"FFC41FFFFCFFFFFE0FFFFFFFFFFFFF9C7FFFFFE0FFFFCFFFFFFFE77FECFFFFFF",
INIT_03 => X"CFF3FFFFFFFFFF9C7FFFFFE03FFFDC3FFFFF7CCFFB79FFF9FF1FFFF1BE07BBE3",
INIT_04 => X"7FFFFFE7CFFFDC3FF8207FC19BBAFF9ECFFFFFFFDC27A5F03FCC3FFFFCFFFFFF",
INIT_05 => X"F83F3F9FFBD8CFFFCFFCFFFFCC27ADF81F89FFFFFCFFFFFFEE93FFFFFFFE279C",
INIT_06 => X"FFFCFF0EEC67AEF80C03FFFFFEFFFFFFF7FFFFFFFFFE001C7FFF0743F8FFCD3F",
INIT_07 => X"010FEDFDF6FFFFFFF7FBFFFFFEFF001C7FFF00039E3FF78EF8FF0F9FFFDC930F",
INIT_08 => X"F7F3FFFF1FFC063E7F180003FF87FBFFFCFEFF9FFCEFBFF6FFFEFFFE2CE3B770",
INIT_09 => X"7F0000063BF3FDF73FFF39FFFFB7DFFAFFFF3FF1ECF3B786073E6FFFF2FFFFFF",
INIT_0A => X"8FFF71FFF1D9DFFDB6B68FFFECF07FFF867F7FFFF33C7FFFF6E3FFFF27F03FFE",
INIT_0B => X"F07C7FFFFCFCFBBFE1E3FFFFF38C7FFFF6E3FFFF3F67FFFE7FC002066FF3FEED",
INIT_0C => X"03CFFFFFFBDD7FFFF7E3FFFFBE2FFFFE7FC007C677E3FF399FFF71FF360C9FFE",
INIT_0D => X"FFF3FFFFBC6FFFFE7FE00FEF7BC7FF39FFFFFB00F0001FFF70FDFF1FF0FCFBA8",
INIT_0E => X"7FF00FFFB81FFF3CFFFFFFFCFE0C3FFF61BDF33FF87CCFB8079FFFFFFF937FFF",
INIT_0F => X"FFFFFFFFEEEFDFFF3F1FF1383B7FCFB10F1FFFFFF7837FFFFBF3FFFFFCDFFFFE",
INIT_10 => X"37DF3EFC98FF87FBFF1FFFFFFFC0FFFFFBF3FFFFFDDFFFFE7FF80FFFC17FFFDD",
INIT_11 => X"FFFFFF3F7EC1FDFFFBF3FFFFFFE7FFFE7FF80FFFF0FFFFD1FF7FFFFFD8F1EFF8",
INIT_12 => X"F7FBFFFFFFFBFFFE7FFE0FFFFC0FFFDFFF7FE0FFDFF8E001FAF9FEFF9FF7F7FF",
INIT_13 => X"7FFF07FFBE1FFFE3BFFFF1FF5FFCF003FB5AFFFFFFDC7FC7FFFFFF3EFF86F8FF",
INIT_14 => X"9FFFFFFCDFFF01FFFD93BFFECF63D7E3FEFFFDFE3F9DFAFFF7FF3FFFFEFDFFFE",
INIT_15 => X"FCC3DEFDC6E3DF81FFF87FFE3F80FBFFF7F83FF7FFFCFFFE7FFF07FBF37FFFFD",
INIT_16 => X"FFE73FFEFB80F9FFF60FFFFBFC01FFFE7FFF07E7F3781FFEDFFFFFFEDFFFFFFF",
INIT_17 => X"F4EFFFFF9BFFFFFE7FFC03FFF337E7FF7FFFFFFFDFFFFFFFFE888F8FE5EBFFBC",
INIT_18 => X"7FC000FFFF8EFBFFBC7FFFFFDFFFFFFFFE1F0387E5EDFD703F1F3C3FF9C0F5FF",
INIT_19 => X"DC3FFFFFDFC3FFFFFF9FF9CFFEEEFF771F8E019FFF8EF5FFF0EFFF9F37FFFFFE",
INIT_1A => X"FFDFFECFFEFEFF771FE03F80FFBFF3FFF0CBFF9FCFFFFFFE7F8FF23FFFFD3BFF",
INIT_1B => X"1FF3FF86C1BFE7FFF1D3FF9F3FFFFFFE7F8FF78FFFFF7DFFEFFFFFFFBF81FFFF",
INIT_1C => X"F1D3FE3FFFFFFFFE7FE3FBC7FFFFC67FF3FFFFFFBF80FFFFFF8FFF3F3F76FFEF",
INIT_1D => X"7FF9FC87FF9F9F3FFDFFFFFFBFC03FFFFE67FFDF7FFAFECE3FFBFFEEC1BCD7FF",
INIT_1E => X"FECFFFF85F7C90FFFCFBFFE73DB8FEDC3BFBFFFDFF3877FFF1D3FE7EFFFFF9FE",
INIT_1F => X"3CFDFFF9FF5CFDD99FF3FFFDFF39F7FFF1D3E07EFFFFF9FE7FFE7F83FFFFF33F",
INIT_20 => X"9E71FFFBFF7CF7FFF3DFFEFCFFFFF5FE7FFF7FC03FFFFF3FFF7FFFF0DFDED83F",
INIT_21 => X"F3CFFFF9FFFFFDFE7FFFBBE007F0FFC73F7FFFE1EFC6D800DE86FFFEEB6E6DB3",
INIT_22 => X"7FFFDFE007F0FF7FBEC3FFFFF7C34C07EEC77FFF3FEE5DB71E30FFFBFF7CF7FF",
INIT_23 => X"9D833FFFFBE80F9FF4E53FFFBF73DFC63FF3FFFBFF71FFFFEF80FFF3FFFFEFFE",
INIT_24 => X"F9F49FFFDF7C3D000EE7FFFBFF83EFFFCF007FEFFFFFDFFE7FFFCFC007F9FCBF",
INIT_25 => X"F7CFFFC007C3EFFFCC4C7FDFFFFFDFFE7FFFE7C4CFFFFFC781801F3FEDF02F9F",
INIT_26 => X"8C1C601FFFE7BDFE7FFFFBDFE9FFFFFFC3FF003F0DF82FBFFFFDE7FFCF7FFC3F",
INIT_27 => X"7FFFFC1FEC3FF9E7E47FFC1F02FE2FDFF3FDFCFFF79FFDBFFBBFFCFEF0C36FFF",
INIT_28 => X"C89E1F8722FF07EFFFFDFFBFFB83F83FF9BFF9FEFF03FFFF1CFC003FFFE87EFE",
INIT_29 => X"C7FE7FEFFDC3F07FFD7FF9FF7F7ADFFE3FFE007FFF9FE73E7FFFFFFFF60FFE77",
INIT_2A => X"FC7FF8FF807BDFFE1FFF007FFFBFDDDE7FFFFFFFFB33E7FEDFCE0FC3BF3F8EE7",
INIT_2B => X"0FFFF0FFFF7FBEEE7FFFFFFFFCFFC1CCFFE7C3E0BFE7CCE787FE71F7FEFFF8FF",
INIT_2C => X"7FFE7FFFFFE47BFFBFE3C1F83E798C4699FF7F7BFF7FFCFFF87FFCFF0CFBFFFF",
INIT_2D => X"3FFCF1FC7C7900327DFFF7C3FFBF01FFF07FFCFEE4FBBFFF87FFF8FFFF6FBF76",
INIT_2E => X"FC77F3F19FDF4FFFF07DFDFEF775BFFF87FFF8FFFEEF7FB87FE7C0FFFFFB3FFF",
INIT_2F => X"FC79FE00F76FFFFF0FFFF8FFFE8F7FCE7FF3FF3FFFFFB3FEFFFE19FEFFE078F3",
INIT_30 => X"1FFFFDFFFF8FFFEE107EFBCFFFFF9FFCFFFFE7FF4F9F7E7FF837FDFFCFC7FFFF",
INIT_31 => X"013FBCF81FFFDFF1FFFFF3FF3C7FAE3E7CFFF6FFFFC77FFFFC73FEFC70EFFFFE",
INIT_32 => X"FFFFFD9F8DFFD61F3EBC9BBFFFF37FFFFC03FFFE31FF7FFE3FFFFDFFFDDEFFEE",
INIT_33 => X"1FBCFBDFFFFC7FFFFFC3FFFF01DF7FFE3FFFFDFFFBCDFFEE001FCE8FF7FFE01F",
INIT_34 => X"F1FFF9FFE7BFFFFE3FFFF9FFF7FDFFF6001FF38399FFFEFFFFFFFCE7CDFFEF6F",
INIT_35 => X"3FFFDBFFEFFBFFF60007FDFB1E1FFFFFFFFFFFE3FEFFF7720FB4F3F3FFFE7FFF",
INIT_36 => X"03B3FEFF3FE7FF3FFFFFFF7FFEFFF9BDC7B6F7FDFFFF7FFFE1FFCEFFFFAFFFFF",
INIT_37 => X"FFFFFFBFFF7FFCBFE7B7F6FCFFFFBFFFE1FFC6FFF76EFFFF3FFF8FFFEFFBFFF6",
INIT_38 => X"FBBFFE3E7FFF9FFFE1FFC7FFE05EFFFFFF0F8FFFEED7FFEE01FCFF6E8179FC9F",
INIT_39 => X"F1FFCFFFE0CEFFFFFF0F8FFFDFF7FFEE71FEFFB8DE7E79EFFFFFFFDEFFBFFEDF",
INIT_3A => X"DE0F8FFFD3F7FFCE7FEF7FCFF87F8733FFFFFFEE4DDFFFEFFDEFBE3FBFFF8FCF",
INIT_3B => X"7FEF9FF73B0FFFF87FFFFFFB7FDFFFEFFDE7FE1EDFFF66BFF1FFDFFFE0EEFFFF",
INIT_3C => X"3FFFFFFDFF6FFF77FDDFEF0FCF7F667FF1FF9FFFC4CEFFFFCE0FC7FFDBDFFF9E",
INIT_3D => X"FCCFEF0FC67F87FFF87F1FFFC1DFFFFFCC1FCFFFFB9FFFBE3FFFEFFBDC17FFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FC3F1FFFE1DDFFFF9C1FFFFFBBBFFF3E60FF77FCEDFFC3FFCFFFFFFEFFB7FFFB",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"1C1FFFFFBBFFFF7E7F03FBFEFBFE83FFE7FFBFFF6FFBFFBBFF7F6F8FC07FC7FF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_20_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"7FFCFDFFFE1BC3FFFBFFFFFFBFFDFFBFFF076F8FF87FFFFFFC7F1FFFF3DDFFFF",
INIT_01 => X"FCFFFFFFCFFEFFDFFFFB6FFFF87FFFFFFEF7BFFFF8DDFFFF3CEFFFFF7F7FFCFE",
INIT_02 => X"FFF87FFDFC7FFFFFFFFFFFFFFEFBFFFF3CE7FFFF7EFFF9BE7FFF9DFF3FFCF3FF",
INIT_03 => X"FFFFFFFFFEFBFFFFF8E7FFFF7EFFFBBC7FFFF1FF8FFF73FFFFBFFFFFF7FF7FE3",
INIT_04 => X"F0E7FFFFFDFFFBB87FFFFFFFB33F73803FEFFFFFFBFF3FFFFFF9FFFC387FFFFF",
INIT_05 => X"7FFFFFFFB80763009FF7FFFFFDFFBFFFFFFDFFFCC03FFFFFFFFFFFFFFFFBFFFF",
INIT_06 => X"1F99FFFFFFFFCFFFFFFDF3FCFFFFFFFFFFFFFFFFFDFFFFFFE067FFFEFDFFFB3A",
INIT_07 => X"FFFCFBBEFFFFFFFFFFFFFFFFFBF7FFFFE047FFFEFFFFFB3A7F00C8FF9C83BBD8",
INIT_08 => X"FFFFFFFFF3EFFFFFC70FFFFDBBFFF7F27DFFFF000F1F3CFFBFFEFFFFFF3FE7FF",
INIT_09 => X"C71FFFFDBBFFE7E673F6FFFF8E3F7B81FFF79FFFFF9FFBFFFFFCFE1EFFFFFFFF",
INIT_0A => X"1F2EFEBFFE3EFBFF3E7FEFFFFFCFFDFFFFFC0DEE438FFFFFFFFFFFFFC7EFFFFF",
INIT_0B => X"E7FFBBFFFFF3FEFFFFF801EF00001FFFFFFFFFFF87DFFFFFC63FFFFDF7FFC79E",
INIT_0C => X"FFFEF1EF87FFE7FFFFFFFFFE03DFFFFF9CFFFFFBF7FFCF3E7C0FFFCF1E3DDBFF",
INIT_0D => X"FFFFFFFC13BFFFFF9DFFFFFBEFFFDF7E58FFFF661F039BFFF9FFFDFFFFFDFF7F",
INIT_0E => X"99FFFFFFDFFFCE7E4FFF997FFFFF97FFFEDF7F7FFFFE6FBFFFFFFFEF871F73FF",
INIT_0F => X"7FFF9BFFFFFFF7FFFF7BDFBFFFFF07DFFFFFFFEF0F07FBFFFFFFFFFC77BFFFFF",
INIT_10 => X"FF9FE3CFFFFFCFE1FFFFFFE60F3BFBFFFFFFFFFFF77FFFFF81FFFFF7FFFFC8FE",
INIT_11 => X"FFFFFFF66F399FFFFFFFFFFFF77FFFFF807FFFFFFFFFC1FE7FE307FFEF8FDFFF",
INIT_12 => X"FFFFFFFFE6FFFFFF0FFFFFEFBFFF0FFE7FFF07FFEEFFBFFFFFF0F9F7FFFFE3F8",
INIT_13 => X"7FFFFFEFBFFF1FFE7EFFFFEFFEFF7FFFFFFF3FFBFFFFF9FCFFFFFFF20F3CDDFF",
INIT_14 => X"7EFFFFC3FFFF77FFFFFFE7FCFFFFFCFE3FFFFFF71DBF7DFFFFFFFFFFEEFFFFFF",
INIT_15 => X"FFFFFBFF3FFFFE3F001FFFF739DF9CFFFFFFFFFFDDFFFFFFFFFFFFDFBFFE3FFE",
INIT_16 => X"000FFFC7FFDFE0FFFFFFFFFFDDFFFFFFFFFFFFDFBFFC3FFE3FFFFFC1FFFE67FF",
INIT_17 => X"FFFFFFFF93FFFFFFFFFFFFBFBFFC7FFE3FFFFFE01FFE07FFFFFFFF9FCFFFFF1F",
INIT_18 => X"FFFFFFAFBFFC7FFE38F8FFFF1FFF87FFFFFFFFE7F7FFFFCF8C1FFFCE7FCFFFFF",
INIT_19 => X"38F8FFFFFFFFF7FFFFFFFFFC7DFFFFE7CFBFFFEEFF4FFFFFFFFFFFFF83FFFFFF",
INIT_1A => X"FFFFFFFFDF7FFFF1EFFFFFCFFFEFFFFFFFFFFFFF87FFFFFFFFFFFFAFBFF83FFE",
INIT_1B => X"C7FFFFCFFFEFFFFFFFFFFFFF87FFFFFFFFFFFF6FBFF07FFC3BF9FBFFFF7FF7FF",
INIT_1C => X"FFFE3FFF2FFFFFFFFFFFFEFFFFE1FFFA1BFEDFFFFFFFF79FFFFFFFFFE7CFFFF8",
INIT_1D => X"FFFFFEFBFFE7FFFA1FCFFFFFFFFFF3DFFFFFFFFFF8F3FFFE27FFFFC7FBEFFFFF",
INIT_1E => X"0FC0FFFEFFE4E0003FFFFFFFFF7DFFFF21FFFF87F1B7FFFFFFF83FFF6FFFFFFF",
INIT_1F => X"9FFFFFFFFFCF3FFF80FFFF9FF1F7FFFFFFF3BFFF5FFFFFFFFFFFFDF37FFFFFF6",
INIT_20 => X"CC7FFFDFF8F7FFFFFFC7DFFF1FFFFFFFFFFFFDE37FFFFFEE1FF01FCEFFE6E7C7",
INIT_21 => X"FFCFDFFE1FFFFFFFFFFFFFD8FFFFFFDE7FFFFFDFFFEFFFFFCFFFFFFFFFF7CFFF",
INIT_22 => X"FFFFFBD8FFFFFFFE7BFFFFFFBFFFFFF773FFFFFFFFFCF3FFE3BFFFDFFCFBFFFF",
INIT_23 => X"7B9FFEBFFFFFF1FE381FFFBFFFFF3CFFF39FFFDFD8FBFFFFFFDFDFFE1FFFFFFF",
INIT_24 => X"FFE1FEEFFFFFCF1FF9CFFC0FD847FFFFFFDFDFFE3FFFFFFFFFFFFFB0FFFFFEFA",
INIT_25 => X"FCCFFC80F807FFFFFFFE1FFE3FFFFFFFFFFFF5B1FFFFF98C7FFFFF3F1FFEF87E",
INIT_26 => X"FFBDDFFC3FFFFFFFFFFFEF71FFFFEE7A7FFFFF1FCFC1FE3C1FFF1DF7FFFFF7C7",
INIT_27 => X"FFFFEF73FFFF98C67FFFFFFFEDFFFFFFDEBFF71BFFFFF9F9FE67FF877C0FFFFF",
INIT_28 => X"7FEFE7FFEFFFDFFFFFFFFF7BFFFFFE3E7F37FFDF7E7FFFFFFFBDFFFC3FFFFFFF",
INIT_29 => X"FF7FFF7BFFFFFF1F9F83FFFF7EFFFFFFFF65FFF83FFFFFFFFFFFDEF3FFFF63BE",
INIT_2A => X"E7C1FFFF76FFFFFFFF65FFF83FFFFFFFFFFFBEF3FFFEFE7E7FE1E7FFFFC667FF",
INIT_2B => X"FF65FFF87FFFFFFFFFFF3DE7FFFDF3FE7F00FFFFFF0F63C70C7FFF58FFFFFFCF",
INIT_2C => X"FFFF7DE7FFF9CFFE7FFFDFFF1E0FFCFF1EFC3FFF6FFFFFE3FBE0FFFEF2FFFFFF",
INIT_2D => X"7FFF7FFF0ECF7C0F3FFC3FFF13FFFFF8FDE07FFDBFFFFFFFFF66FFF87FFFFFFF",
INIT_2E => X"FFFFF97FFDFFFFFF1F703FFBBB67FFFFFEF37FF07FFFFFFFFFFEF7EFFFFFFFFE",
INIT_2F => X"C7901FFA3F19FFFFFEE33FE07FFFFFFFFFFDE7EFFFFFFFFE7FFFFFDF0EE61C03",
INIT_30 => X"0E63BFC07FFFFFFFFFFBEFFFFFFFFFFE7FFFFFFF9F1E7C07FFFEFFFFFEFFFFFF",
INIT_31 => X"FFF3DFFFFFFFFFFE413FFFFFFFFFC63FFFFC7FFE877FFFFFFBC00FF63FFE7FFC",
INIT_32 => X"7F3FFFFFFFFF87FFFFFC203E1BBFFFFFFCE003F7FFFF7FFCCF73DF807FFFFFFF",
INIT_33 => X"FFF0001FFFE7FFFFFF0009F7FF7EFFFDE77FEFB07FFFFFFFFFE09FFFFFFFFFFE",
INIT_34 => X"FFC0CCF79FE3FFFDF03E6F3CFFFFFFFFFFC03FFFFFFFFFFE7F3FFFFCFFF807FF",
INIT_35 => X"FC1E6F34FFFFFFFFFF80FFFFFFFFFFFE7FFFFFFEFC387DFFBFFE781DFF79FFFF",
INIT_36 => X"FF01FFFFFFFFFFFE3FFFFFFE3C1C3F7FF91FFFF87FEE3FFFFFF09EF01FCFFFFD",
INIT_37 => X"07FFFF7E7E3D87FFFFEFFFF97F9FDFFFFFF83F399FC1FFFEFFE7EF20FFFFFFFF",
INIT_38 => X"9FF7F9FFFE7FEFFFFFFDFFC07FFF383F7FE0CE21FFFC7FFFFE07FFFFFFFFFFFE",
INIT_39 => X"FFFD9FFFFFFF9C0F0FF01E01FFF8FFFFFC1FFFFFFFFFFFFE07F0FFFFEFFBFDF7",
INIT_3A => X"0FF9FC81FFF0FFFFF83FFFFFFFFFFFFE7FFFFFFFCFFBFCFF01FFFDFFFCFFF3FF",
INIT_3B => X"F0FFFFFFFFFFFFFE7FFFFF00DF07E401FF00E5FFF03FF9FFFFE79FFF3EB86000",
INIT_3C => X"4EFFFFEFDF07FF1FFFFEF7E7877FFDFFFFEFFFFF3977700F0FFDFC03FFE1FFFF",
INIT_3D => X"FFFF7E17FFFFFE71FFEFFFFF006F3EFF0FFE7803FF83FFFFC1FFFFFFFFFFFFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"3FEEFEFF3E67BFFF27FF0307FF03FFFF83FFFFFFFFFFFFFE4EFFFFFFDF0FFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"73FFE783FE03FFFE0FFFFFFFFFFFFFFE0EFFFFFF0F4FFFFFFFFF7DF800EFFFDF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_21_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"1FFFFFFFFFFFFFFE7FFCFFFF0F7FFFFFFFFF39FFFF3FFFFFDFEEF97FFFE7BFFF",
INIT_01 => X"7FF87FFF43FFFFFFFFFFC7FFFFEFFFFEE7EFF03FFEEF9FFF7BFFFF00FC07FFFC",
INIT_02 => X"FFFFFFFFFFF8FFF1FC1FE03BFDDF9FFF7BFFFE03BE07FFF07FFFFFFFFFFFFFFE",
INIT_03 => X"FFFFFFFFFDCF83FEFB97FE07DE0FFFE1FFFFFFFFFFFFFFFC7FF87FFFF9BFFFFF",
INIT_04 => X"FB9BFE33E00FFFC3FFFFFFFFFFFFFFFC7FF9FFFFFCBFFFFFFFFFFFFFFFFF81DF",
INIT_05 => X"FFFFFFFFFFFFFFFC7FFFFEFFFC7FFFFFFFFFFFFFFFFFFEFCFF0FFFFFFCEF0BDD",
INIT_06 => X"7FFFFFBF0CFFFFFFFFFFFFFFFFFFFF7FFFFEFFFFFFECDDCFFCFFFC3CFE3FFF0F",
INIT_07 => X"FFFFFFFFFFFFFFBFFCFFFFFFFFE9DDD6FCFF7C7F3E7FFE3FFFFFFFFFFFFFFFF8",
INIT_08 => X"FE5FFFFFFFE1BFB73CFEFC7FBE7FF9FFFFFFFFFFFFFFFFF06F7FFFFF07FFFFFF",
INIT_09 => X"B9FEF83F9C1FF3FFFFFFFFFFFFFFFFC07F7FFFF313DFFFFFFFFFFFFFFFFFFFDF",
INIT_0A => X"FFFFFFFFFFFFFF027F3FFFEFC3DFFFFFFFFFFFFFFFFFFFE7DFFFFFFFE7F1DBB7",
INIT_0B => X"7F0FFFCFE1E0FFFC000FFFFFFFFFFFF8FFFFFFF3E7FFE3A7B1FEF8FF8067CFFF",
INIT_0C => X"FFF83FFFFFFFFFFFDFFF3FFF8FFFFFFFB39DFBFF1E733FFFFFFFFFFFFFFFFC06",
INIT_0D => X"E7FF7FFFBF8FFFF93397DBFF3F30FFFFFFFFFFFFFFFFE01C790FEFF9C3BF3083",
INIT_0E => X"0397F9FE7F87FFFFFFFFFFFFFFFFE3FA7D0FD8F0199FFFFFFEFFC01FFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFE67FE3F71FFD88FFFE07FFFFFF007FFFFFF3FFFFEFFFBE67FF",
INIT_10 => X"7FE38FFFFB809FF007FF9F7FF81FFFFFFA3FFFFFFEFE3FFD47BFF9FC7F8FFFFF",
INIT_11 => X"03F9FFF007FFFFFFE33FFFFFF8303C79FFFFB1FEFFFFFFFFC007FFFFFFFFFFCC",
INIT_12 => X"EFFFFFE0F870D9F0FFFFB3FFFFFFFFFF3807FFFFFFFFFF7C7F87BFF193881100",
INIT_13 => X"7FFDF3FFFFFFFFFC0C0FFFFFFFFFFCFE43FF7FEFEF9FFB00FF7FFE1FFFFFFFFF",
INIT_14 => X"007FFFFFFFFFF3FE59F8F8DD7FFFF8FFFFFFC3FFFFFFFFFFDFFFFFF9F8F8EF88",
INIT_15 => X"7FE7F7FC7E7FFEFFFFF8FFFFFFFFFFFFDF8FFFFFFC7C77FF36FD73FFFFFFFFCE",
INIT_16 => X"FFCFFFFFFFFFFFFE3007FFFFF778377931FFA3FFFFFFFE7FFFFFFFFFFFFFE7F8",
INIT_17 => X"F807FFFFFFF0306071FEDFFFFFFFFC7FFFFFFFFFFFFF9FC07F8FDE39FF1FE27F",
INIT_18 => X"FEFEDFFFFFF9E0FFFF7FFFFFFFF8FC00107F983FFFEFE3F77E3FFFFFFFFFFFFC",
INIT_19 => X"FEFFFFFFFFE7E0307FFFBF3FFFE381FFC3FFFFFFFFFFFFFDFC4FFFFFDFF04040",
INIT_1A => X"7FFF7F9FFFE303E47FFFFFFFFFFFFFF9FFFFFFFFFB030061FFFFDFFFFFE603FF",
INIT_1B => X"FFFFFFFFFFFFFC70C9FFFFFFF3078023FFFFFFDFFFEFF3FFFFFFFFFFFF8FC7F8",
INIT_1C => X"3CFEFFFFF33B0383FBFDBFFFFFEFF03FFFFFFFFFFE3F9FFC7FFEFFFFE7F3FF3F",
INIT_1D => X"3FFDBBFFFFFFFE3FFFFFFFFFF0FCFFFC7FFDFFFFC3E3FEFFFFFFFFFFFFFFC60F",
INIT_1E => X"FFFFFFFF83F1FFF87FFBFFFFC7E3BEFFFFFFFFFFFFFF3E3FFE3FFF1F7738C1C3",
INIT_1F => X"7FF79F79EFFFFDFFFFFFFFFFFFFE7C7FFFDFFF00FFBFC4E3FFFF73FFFFF7CF99",
INIT_20 => X"FFFFFF2FFF0041FFFF9FFFFCF33F84E3DFFFF7FFFFEE67803FFFFFF83087FFFC",
INIT_21 => X"FF80FEFCF39F0E80FFBEFFFFFFDF7F807FFFFFE0800FFFFE7FCF3F7CC7FC03FF",
INIT_22 => X"FFFEFFFFFF3BDF1FFFFFFF003FFFFFFE7F9DBFF07FCFFFFFFFFFFEF7C00C03FF",
INIT_23 => X"FFFFFC00FFFFFFFE7F7FBF7F1C7FFFFFFFFFFCD8001CFFFFFF8CC4FCE3860F00",
INIT_24 => X"7EFF9C7FF3FFFFFFFFFFFDFC0061FFFFFF9D83FE3F861FC3DFFEFFFF0FFFDF7F",
INIT_25 => X"FFFFF0FF03C3FFFFFFFD86FFBF863FC7FFFEFFF9F8787EFFFFFFC003FFFFFFFE",
INIT_26 => X"FFFEDFFFBFCFFFCFFFFDFFF3C0CF9EFFFFFF003FFFFFFFFE7BB9FCEFCFFFFFFF",
INIT_27 => X"787BFFF503BFE0FFFFF003FFFFFFFFFE7671FE9F3FFF801FFFFF8E3FFF03FFFF",
INIT_28 => X"FFC007FFFFFFFFFE4F83FF33FFF0FFE3FFFF3F3FFC03FFFFFFFF73E7FECFFFC6",
INIT_29 => X"3F777FEFFFEFDEFBFFFEFFF0F007FFFFFFFFCCE3EFDFFF067877FFED3F7FFFFF",
INIT_2A => X"F911FFFFE00FFFFF7FFFFEE3C19FFC1BF9A7FFB97DFFFFFFFC009FFFFFFFFFFE",
INIT_2B => X"FFFFFDE3E03FF033FFE7FF7FF3FFFFFFF809FFFFFFFFFFFE7CE7FFEFFFDE7E79",
INIT_2C => X"FFE01FDC0FFFFFFF003FFFFFFFFFFFFE73CF7EF9FF3DE3D807FFD83FC01FFFFC",
INIT_2D => X"07FFFFFFFFFFFFFE773FFEF6F8F1E0F8FF7FFFF8607FFFF8FFFFF1EFE07FE707",
INIT_2E => X"60EFFFFF0FC1F063FEFFFCE0F3FFFFF1FFFFF3EFE17FE7DFFFFFF073FFFFFFFC",
INIT_2F => X"FC7FFCE0F7FFFFE3FFFFF3FF67FFF1FFFF7FFBCFFFFFFFE01FFFFFFFFFFFFFFE",
INIT_30 => X"FFFFF7FF67FFFCFFFFFE9BFFFFFFFF003FF87FFFFFFFFFFE7FFFFF07FECF6197",
INIT_31 => X"FFE0B7FFFFFFFC07FFC1BFFFFFFFFFFE7FF8FEE7FF0F8327F93C7FF0F3FFFFC7",
INIT_32 => X"FFC3BFFFFFFFFFFE78CC7DCFDF0FFF0CF3FFFF80F3FFFF8FFFFFF7FF37FFFCFC",
INIT_33 => X"47FF9B9E9BF8FF7E3FFF807EF3FFFF5FFFFFE63E37FFF8FCFF676FFFFFFFF03F",
INIT_34 => X"FE3F7FFE47FFFCBFFFFFED9F77FFF9FC7FFF9FFFFFDFFFFFFFC3DFFFFFFFFFFE",
INIT_35 => X"FFFFEF9FF79FF33EFFFF3FFFFF87FFFFFFE7DFFFFFFFFFFE1FFFE47EEFF0FFF8",
INIT_36 => X"E3FFC7FFFF07FFF1FFE7DFFFFFFFFFFE3FFFFDFCFFF18FF87EFEFFFFFFFFFB3F",
INIT_37 => X"3F07EFFFFFFFFFFE1FF7FDEEFFFF0E7C7070FFFFFFFFF7FFFFFFEF9FF30FEF1F",
INIT_38 => X"0F03C1FFFEDDEF7FF06FFFFFFFFFEEFFFFFFDFDFF31FDF1FE3FFF81FFF07FFE6",
INIT_39 => X"FFCFFFFFFFFFDDFFFFFFBFDFCF1FBFFEE7FFF00FFF39FFDF1F07EFFFFFFFFFFE",
INIT_3A => X"FFFFB8FFBF1FBFFCFFFB9E1FFE7CFFFFCE1FE7FFFFFFFFFE0EE003E3FEB3EE7F",
INIT_3B => X"FF83BFFFFCFEFFBFE03FEFFFFFFFFFFE4643FFE7FC6FDE7F7F9FFFFFFFFF3BFF",
INIT_3C => X"FFFE1FFFFFFFFFFE6007FFFFFC5FB9FFC03FFFFFFFFEF7FFFFFF78EFBFFFDFFC",
INIT_3D => X"700D7E7FFCDF7CE19FFFFFFFFFFDEFFFFFFF7ACFBFFFFFFC7F3F9FFFF07EFF9A",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"BFFFFFFFFFFBDFFFFFFE66F5BC7FFFFC7FFFC7FFE73F7FC87FFEFFF07FFFFFFE",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFECEE5BE7FFFFE7FFFF3FFC78F7FED7EFEFFE0FFFFFFFE1C3CFC3FF39FE11B"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_22_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_3B => X"BFFACDF03FFFE7FFBFA17F0FFFFE3E7FE701FFFFF80F07FE7FFFFFFFFFC1FFFE",
WRITE_MODE_B => "WRITE_FIRST",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3A => X"900EFEFFF87EFFFEDFFACDF07FFFFFFFBF5DFE0FFFFC7CFFC783FFFFF01FFFFE",
INIT_3E => X"7FFFFFFFFFC7FFFF180DFFF47F0DFFDEFFFFF3F71FFFFFFFBFD3FF27FFFF9F3F",
SIM_COLLISION_CHECK => "NONE",
INIT_3C => X"BFF3FF07FFFF3F3FFF03FFFFFF0061DE7FFFFFFFFFC1FFFE040EFEEFFFFDFFEF",
INIT_3D => X"FF07FFFFFFC07E067FFFFFFFFFE3FFFF0C0EFF077F4DFFFF7FF7DDF63FFFE7FF",
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"6FFFFBFFCFF83F0FFF3EFF87FFFFFFFE003CFEFFF39CE0DFBFFFFFFFFFE7DFFF",
INIT_01 => X"FF3E001FFFFFFFFE703FFC1FF19B807F3FFFFFFFFFDFBFFFFFFCDFEDBFFFDB1F",
INIT_02 => X"7007FF1FF18307F87FFFFFFFFF3F7FFFFFFDDF7FBFFF99BFFFFF99FFCFFF3EFF",
INIT_03 => X"FFFFFFFFFEFFFFFFFFF99FDFFFFE3BF7FCFB41FF8FFF39FFFFFF003FFFFFFFDE",
INIT_04 => X"FFFB1F7C5C38FFE3FFC361F800FE0F77FFFFF8FFFFFFFF0E71C7FFF7FBC71F83",
INIT_05 => X"FFC781F81FFFFF0FF3DEF1FFFFFFFE5E71DFFFF77FFC3C7FFFFFFFFFFBFCFFFF",
INIT_06 => X"FFFFC7FFFFFFFEFE71DCFFF6EFC1F3FFFFF8FFFFEF7BFFFFFFF73F7F48019FEB",
INIT_07 => X"718CFFFECFC1CFFFFFF87FFFDF77FFFFFFF77F7FE00307DBFFFFFC03FFFFFFFF",
INIT_08 => X"FFF87FFFB3FFFFFFFFEEFF7DE0030BBDDBF8FFFFFFCFF0019FFB9FFFFFFFFFFE",
INIT_09 => X"FFEDFF60E007FFBDF9F773FFFF7FC7FDFFF41FFFFFFFFFFE781F8698D9C33FFF",
INIT_0A => X"FBF77DFFFE3E67FC7FEFFFFFFFFFFFFE7E3FFFB8C39F7FFFFFC67FFF77EFFFFF",
INIT_0B => X"1EEFFFFFFFFFFFFE7F3FFFF9E61F7FFFF87EFFFEFFDFFFFFFFDDFFECE007FF79",
INIT_0C => X"7FB7FFF9FE3EFFFFF7E6FFFDFFDFFFFFFFDBFF80E01FFEF8E3F278FFFC39E3FE",
INIT_0D => X"8C1CFFFB7FBFFFFFFFFBFF8001BE7DFCC7C0DFFCF8B3EBFF9E77FFFFFFFFFFFE",
INIT_0E => X"FFBFFF8807BC6DFEDF002FFFFFEFDDFF9C78FFFFFFFFFFFE7F38E021FF7DFFFF",
INIT_0F => X"FE8077FFFFCFBDFFBC7F3FFFFFFFFFFE7F79C181C79BFFFF983BFFF47DBFFFFF",
INIT_10 => X"BF7F1FFFFFFFFFFE7E7F10F93BFBFFFF3C7BFFEC7B7FFFFFFFF7FF99039C3BFE",
INIT_11 => X"783E007E7DFBFFFCFE77FF9ECEFFFFFFFF77FFBDC3863FFF7EE1F7FFBF1F6DFF",
INIT_12 => X"FF77F07FD5FFFFFFFF6FFF7DE3CE77FF7EFFFBBF1E7EC6FE7FF087FFFFFFFFFE",
INIT_13 => X"FFEFFF7CF38F77FFBEFFFDFF9F3EC37BCFE087FFFFFFFFFE7801CF3FFF01C0F9",
INIT_14 => X"BFFFFEFFF79F73861FF107FFFFFFFFFE78079FBFFFCFF8F3BCEFCFEFEDFFFFFF",
INIT_15 => X"B1FF01FFFFFFFFFE781F9FBFFF3FFC0E36DFBFFFFBFFFFFFFFEFFEFEFF9FD7FF",
INIT_16 => X"7C3FCE7FFF6F3FFE77BFBFFFD7FFFFFFFEEFFDFE379FD7FFBF3FFEFFFF5F3FFF",
INIT_17 => X"E73F41FBEFFFFFFFFEDFFDFE0387FBFFBB8FFEFFFEEFC7FFF9FF81FFFFFFFFFE",
INIT_18 => X"FDDFFBFFC707FBFFB9CFFEC3FF73FB0EFFFFC3FFFFFFFFFE7EFFF1FFFEC30FCE",
INIT_19 => X"B9C7FEC2FFFDFEF3F1FF87FFFFFFFFFE7FFFFFFFFD830F0338FF43FBCFFFFFFF",
INIT_1A => X"3FFF8C7FFFFFFFFE7FFFFFFFFDF81F0367FED7F3BFFFFFFFFDBFF3FFE707FBFF",
INIT_1B => X"7FFFFFFFFBFFFFDFEFFDA7C37FFF80FFFFBFF7FFE66779FFBDE3FF709E7E7FFF",
INIT_1C => X"DFFBCFCFFFFF3DFFFB7FF99E0EEE7CFFFFF3FF72FF5F9FFFEFFF038FFFFFFFFE",
INIT_1D => X"FF7FFC0C0CFE7CFFDFFBFF73E3A75FFFF7FFFFC0FFFFFFFE7FFFFFFFF97FF9F3",
INIT_1E => X"D3FBFE7FCBD36FFFFDFFFCE00FFFFFFE7FFFFFFFFDC019FFBFF7C7FEFFFCFDFF",
INIT_1F => X"FEFFFFC003FFFFFE7FFFFFFFFFFE38837FEDE7EDFFFBCBFFF7FFFC00ECFE7EFF",
INIT_20 => X"7FFFFFFFFF80FC02FFDFFF6DFFF70BFFF6FFFC01B47C7DFFD3FBFE07DFE5EFFF",
INIT_21 => X"FF3FFF73FFEF1BFFFFFFF804B6113DFFEFFBFC3B9FFB77FFFCFECF80000FFFFE",
INIT_22 => X"EDFFF806F783BDFFEFFBFC3D1FFDB3FFE3FC1FBFF807FFFE7FFFFFFF3F7FFFF6",
INIT_23 => X"F7FBFC7D9FFEDDFFEFF8FFBFFF0FFFFE7FFFFFFC9E78FFFF3ECFFE77FFEFBBFF",
INIT_24 => X"F700BFBFFFFFFFFE7FFFFFFDE679CFFFBC9F7C6FFFDFFBFFD5FFF600FB87BDFF",
INIT_25 => X"7FFFFFFDE77B8003BD3E3EFFFFB7BBFFD5FFEE04398FDDFFF7FBFC7EFFFFEE7F",
INIT_26 => X"FA1F1FDFFF7377FFFFFFDF3E3C0FDDFFFFFFFE7F7FFF6DBFF9C9FFDFFFFFFFFE",
INIT_27 => X"BFFFBBFE3F0FDFFFFB1DFE0FAFFEB6E7FEFF9EC1FFFFFFFE7FFFFFFCCF7E1FF7",
INIT_28 => X"FF9DFC17B9F6FBF7FF8F07FE7FFFFFFE7FFFFFFC0EFE0FEF961F9FBFFF6277FF",
INIT_29 => X"FFF867FF7FFFFFFE7FFFFFFF80BE007FFD0FE77FFF422FFFBBFF7FFFFFEFBEFF",
INIT_2A => X"7FFFFEFF9FFE030FFFE3F37FFEC32FFFFBFEE7FFC7F7BFFFFDDEFE33D97FDDB3",
INIT_2B => X"FEF7FAFFFE9FEFFF7FFCFBDFC7DFBF7FFFCFFE73E6FFDFB9FFFFF7FFBFFFFFFE",
INIT_2C => X"F7FDF98EC7FBA9BFFECF7EF3FBFFDEBDFFFFF00FBFFFFFFE7FFFFFFF1CF03B8F",
INIT_2D => X"FFFF7CFBFEFE1FEEFFFFFF07BFFFFFFE7FFFFFFF00027DFF7EFEFCFFFDBEDFFF",
INIT_2E => X"3FFFFF87BFFFFFFE7FFFFFFFE022FBFF3EFC3BFFFDBEFFFEF7F9FF1FCFFBA0FF",
INIT_2F => X"7FFFFFFFFC38F7FFF2BE77FFFFFEBFFFFFF83F4FFFCBA0DFFF7FB87BFFE63F7F",
INIT_30 => X"637FF7FFF7EDBFFDAFFFBF8FFFCFA1DFFF79DC0DFF667FBFBFFFFF83DFFFFFFE",
INIT_31 => X"4FFFB71CFBEFAFE0FFB3C005FFA37FCFDFFFFFD1DFFFFFFE7FFFFFFFFE1FEF0E",
INIT_32 => X"3FF3F001FFA3BFF7EFFFFFF83FFFFFFE7FFFFFFFFE0FDCE763FFF7FFCF2F7FFD",
INIT_33 => X"E7FFFFFF3FFFFFFE7FFFFFFFFF07D9F34AFFF7FFBDBFFFFFCE7F237CFFB7AFE1",
INIT_34 => X"7FFFFFFFFF87B7FBDAFEEFFF3FBEFFFB807E63FA9FF0AFF3B0D7F83FFFFFDFF3",
INIT_35 => X"DBFFFFFF7FBEFFFB9F7CC39EFE702763FB19F83FFFDFEFFDF7FFFFFFFFFFFFFE",
INIT_36 => X"BCFD8346DE702773FBF1381FFFCFEFFEF7FFFFFFFFFFFFFE7FFFFFFFFFC00FFD",
INIT_37 => X"BDF83C1FFF83F3FF37FFFFFFCFFFFFFE7FFFFFFFFFE01FFCDBFFDFFCC7BEFFF7",
INIT_38 => X"87FFFFFFC0FFFFFE7FFFFFFFFFC07FFEDBFFBF1BC7BEFFF6F3FB86EEDFF827FF",
INIT_39 => X"7FFFFFFFFFC07FFE9B1F7EFFC6F6FFFAEFFA8EFCFEFFE7BFBEF8FE0FFF19F9FF",
INIT_3F => X"000DFFEE3FDDFFFFFFEFEFFBEFFFFFFFBFEFFF83E7FFCFBFFF0FFFFFFFF07FE0"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_23_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram : RAMB16_S2_S2
generic map(
WRITE_MODE_B => "WRITE_FIRST",
WRITE_MODE_A => "WRITE_FIRST",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE556FFFAAAAAAAA55BFFFFEAAFFF94",
SRVAL_A => X"0",
INIT_3D => X"555516FFFFF9557FFFFFFFF95556AFAAEAAFFFFFFFFFFFFFAAAAAFFFFFFFFFFF",
INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3B => X"FFE556BEAAAAAAAAA55AFFFFFAAFFF94015555BFFFF955BFFFFFFFFA6955AAAB",
INIT_3A => X"AAAFFFFFFFFFFFFEBEAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_39 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAA5AAAAAA9555AFFFFAAFFFD5",
INIT_38 => X"005545BFFFFE55BFFFFFFFFAA955AAABAAABFFFFFFFFFFFEAAAAFFFFFFFFFFFF",
INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_36 => X"FFFFAAAA956A556955556FFFFAAFFFE5405505BFFFFE45BFFFFFFFEAA955AAAA",
INIT_35 => X"AAABFFFFFFFFFFFAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_34 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE956A555555555BFFFEAFFFF9",
INIT_33 => X"515505FFFFFE41BFFFFFFFEA5555AAAAAA9AFFFFFFFFFFEAAAAFFFFFFFFFFFFF",
INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_31 => X"FEFFFFFFA55A955555515BFFFEAFFFFE555505BFFFFF51FFFFFFFFE95556AA95",
INIT_30 => X"5A96FFFFFFFFFFAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_2F => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAFFFFFFA5555555055457FFFAABFFFE",
INIT_2E => X"554005BFFFFF51BFFFFFFE955556AA956A9AFFFFFFFFFEAAAAFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2C => X"FFFFFFFFE5455555055457FFF95BFFFE555001BFFFFF51BFFFFFF954555AA695",
INIT_2B => X"5AABFFFFFFFFFEAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_2A => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE955555505541BFFF95BFFFF",
INIT_29 => X"9554117FFFFF91BFFFFFE505555A95556ABFFFFFFFFFEAAAABFFFFFFFFFFFFFF",
INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_27 => X"FFFFFFFFF954555515545BFFFA57FFFFE505116FFFFF91BFFFFFE555555A5555",
INIT_26 => X"6AFFFFFFFFFFE6AAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_25 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFE954555555545FFFFE96FFFF",
INIT_24 => X"F905156FFFFF91BFFFFF9545555555555AFFFFFFFFFF96AAAFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_22 => X"FFEFFFFFE555555555545FFFFF96FFFFF955555BFFFF95BFFFFF954555555415",
INIT_21 => X"5AFFFFFFFFFF96AAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_20 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFE555055555555BFFFF96FFFF",
INIT_1F => X"FE55555AFFFFD5BFFFFE5555555554155AFFFFFFFFFE56AAAFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFEBFFFFE551015455545BFFFFE5FFFFFF944556FFFFE5BFFFFE551455055001",
INIT_1C => X"16FFFFFFFFFE56AAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA",
INIT_1B => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEABFFFE501155455505BFFFFE5BFFF",
INIT_1A => X"FF951555FFFFF5BFFFF955555555540516FFFFFFFFF955AAAFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFAABFFFE950555515501BFFFFF5BFFFFF940055FFFFF5BFFFF9555055555505",
INIT_17 => X"56FFFFFFFFF5556AAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAA",
INIT_16 => X"BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAABFFFF951555005501BFFFFF96FFF",
INIT_15 => X"FF940055BFFFF9BFFFE555545555555556FFFFFFFFE5556AFFFFFFFFFFFFEAFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAABFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFF",
INIT_13 => X"FFAAAFFFFE555540055056FFFFF96FFFFFD54555BFFFF9BFFF95155555555555",
INIT_12 => X"16FFFFFFFFD55AAAAFFFFFFFFFFFEABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAE",
INIT_11 => X"BFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFAAABFFFFA55540055456FFFFFE5BFF",
INIT_10 => X"FFE54545BFFFF9BFFE555515555555555BFFFFFFFF9556AAAFFFFFFFFFFFFEFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAABEBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFEAAAFFFFF95541055416EABFFE46FFFFF95545BFFFF9BFFE45540555555555",
INIT_0D => X"6FFFFFFFFE5556AABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAFAA",
INIT_0C => X"BFFFFFFFFFFFFFFFFAFFFFFFFFFFFFFFAFEAAABFFFFE5555555516A5BFFF46FF",
INIT_0B => X"FFFE55057FFFF9BFF9555415555555556FFFFFFFF95556AAFEBFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFEAABFAABFFFFFFFFFFFFFFFEAFFFFFFFFFFFFFF",
INIT_09 => X"AFAAAAAFFFFE9555555556A6BFFF95BFFFFF95046FFFF9BFE555555555555555",
INIT_08 => X"6FFFFFFFE55556AAFABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAABFFAA",
INIT_07 => X"BFFFFFFFFFFFFFFFFAAAFFFFFFFFFFFFEBAAAAABFFFFE5415554556BFFFFD56F",
INIT_06 => X"FFFFE5411BFFF9BF95555555551415556FFFFFFE94155AAAFEBFFFFFFFFEAABF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFAAAAAA9ABFFFFFFFFFFFFFFFFAAFFFFFFFFFFFFF",
INIT_04 => X"EAAAAAABFFFFE5455555416BFFFFE56FFFFFF95416FFF9BA5555555555005555",
INIT_03 => X"6FFFFFE954555AAAFEBFFFFFFFEAAAFFFFFFFFFFFFFFFFFFFFFFFFFEAAAA555A",
INIT_02 => X"BFFFFFFFFFFFFFFFFFAFFFFFFFFFFFFFAAAAAA5BFFFFF9550555515BFFFFE55B",
INIT_01 => X"FFFFFE5556FFFAE555555555551055556FFFFF9555556AABFEBFFFFFFE956BFF",
INIT_00 => X"FFFFFBFFFFFFFFFFFFFFFFFA9555555ABFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFF",
SRVAL_B => X"0",
INIT_3F => X"EABFFFFFFFFFFFFFEAAAABFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(1) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(1) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(1) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
DOB(1) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_1_UNCONNECTED,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_24_ram_r_v2_init_ram_dp2x2_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_A => X"0",
INIT_3C => X"FFFFFFFE001FFF8FFE0000003FFF9FFFFFFFFFFFFF01FFFFFFFFFFFFE03FFFE1",
INIT_32 => X"FFFFFE0003FFE1E0C003007FFFFCFFFFFFFFFFFFFFE0FFFFFFFFFFFFFE01FFF1",
INIT_2E => X"00080FFFFFE0FFFFFFFFFE01F8F87FFFFFFFFFFFFF00FFC7FFF83FFFFFFFC000",
INIT_38 => X"FC000001FFFFFFFFFFFFFFFFFF81FFFFFFFFFFFFF00FFFF1FE03FF800007FF7F",
INIT_0F => X"0000000011F03FFFC0E000000780000EF0000000007CFFFFFC000000033FFFFF",
INIT_13 => X"FFFFF80001FFFFFC000000003FFF0FFFFCE700000023803800000000007FFFFF",
INIT_35 => X"FFFFFFFFF007FFF9FFFFFE0001FFFFFFFFFFFF0001FFF8FDF003000FFFFFFFFF",
INIT_10 => X"F8E000000700000400000000003FFFFFFC000000023FFFFFFFFFF0003FFFFFE0",
INIT_1C => X"FFE00000FFFFFFFFFFFC07F8000001FFFC0000007FFFFFFFFFFFFFC000F9E0F0",
INIT_37 => X"FFFFFFC000FFFF7FF8000003FFFFFFFFFFFFFFFFFF81FFFFFFFFFFFFF007FFF9",
INIT_27 => X"FFFFFFFFF00000001B80000001FFDFE0000003FFF800027FFC7FFF01FF3C1FFF",
INIT_28 => X"3FE0000001FFFFF00000007FFC0007FFFE7FFE01FFFC1FFFFFFFFFFFFFF781FF",
INIT_1F => X"FF03FFFE003FE3E7E00FFFFE00FE0FFFFFE00001FFFFFFFFFFFF807C000000FF",
INIT_20 => X"E00FFFFC00FF0FFFFFE00003FFFFFBFFFFFF803FC00000FFFF8000003FFF3FFF",
INIT_B => X"0",
INIT_0D => X"F8000000039FFFFFFFFFF010FC3FFFC0000000000FFFFFFF800000000F030007",
INIT_1E => X"FF0000003FFF7FFFFF07FFF8007FE1E3C007FFFE00FF8FFFFFE00001FFFFFFFF",
INIT_1B => X"E00FFFFF007FFFFFFFE00000FFFFFFFFFFF00FF0000003FFF00000007FFFFFFF",
INIT_23 => X"7E00000007F7FFE00F00FFFFC00FE3FFC00FFFFC00FE0FFFFFFF000FFFFFF1FF",
INIT_30 => X"FFFFFFFFFE00FFF1FFFF003FFFFFE003FFFFF800007F8180000803FFFFF8FFFF",
INIT_2B => X"FFFFFFFFFF807F1FFFFFFFFFFF0000003FF80000001FFFF800000E0FFF0007FF",
INIT_1D => X"FFFE03F8000000FFFE0000007FFFFFFFFF9FFFE0007DE1F1C007FFFF007FEFFF",
INIT_0A => X"000000000E3E3FFE000000001F0F80007F80000000FFFFFFF8000000000FFFFF",
INIT_29 => X"0000001FFE000FFFFEFFFE00FFFC3FFFFFFFFFFFFFE018FFFFFFFFFFF8000000",
INIT_26 => X"FFFF9FFFFFFFC3FFFFFFFC3FF00000003C00000003FFDFC000001FFFF00003FF",
INIT_04 => X"FFFFFFF83FFFE0000000000007C70000000000003FDFC3FFC03FC00003FFFFFF",
INIT_14 => X"000000003FFFFFFFFE6FC00000FFE01C00000000007FFDFFF80000000003FFFF",
INIT_3A => X"FFFFFFFFE00FFFF18000FFF00000780FFFFFFFF0003FFF1FFE0000007FFFFFFF",
INIT_2F => X"FFFFFFFFF8F07FFFFFFFFFFFFF00FFF1FFFC00FFFFFFC001FFFFE000001F870C",
INIT_0C => X"FC000000003EFFFFF800000001DFFFFFFFFFF839F81FFFC0000000000FFF7FFF",
INIT_06 => X"000000001F9FC1FFF3FC000001FFFFFFF80000000001FFFFFFFFFFFC07FFF000",
INIT_2A => X"FFFFFF007FFC3FFFFFFFFFFFFFC03E3FFFFFFFFFFC0000003FF0000000FFFFF8",
INIT_03 => X"F00000000000007FFFFFFFFFFFFFE00000000300078600000000000E7FFFC7FC",
INIT_39 => X"FFFFFFFFFF01FFFFFFFFFFFFE00FFFF18E01FFC00001FE1FFFFFFFE0007FFF3F",
INIT_31 => X"FEFFC007FFFFE00FFFFFFC0003FFC1C1800001FFFFF8FFFFFFFFFFFFFFF07FFF",
INIT_09 => X"FFFFFFF9C00FFE000000000000783FFC000000001F0FC079FFC0000001FFFFFF",
WRITE_MODE_A => "WRITE_FIRST",
INIT_33 => X"E003003FFFFFFFFFFFFFFFFFFFE0FFFFFFFFFFFFFC03FFF1FFFFF0000FFFFFFF",
INIT_25 => X"F83FFFFFF83C1FFFFFBF803FFFFFE1FFFFFFF83FF00000007E00000003FFDFE0",
INIT_36 => X"FC4FFF00001FFFFFFFFFFF8001FFFE7FF8010003FFFFFFFFFFFFFFFFFFC0FFFF",
INIT_07 => X"FFF0000001FFFFFFF80000000000FFFFFFFFFFFC01FFF8000000000003E37CF0",
INIT_12 => X"F80000000007FFFFFFFFF00003FFFFE0000000003FFF1FFFFDE6000000000000",
SIM_COLLISION_CHECK => "NONE",
INIT_18 => X"FFFFFF00007007FFC00000003FFFFFFFFFFFFC0003F3E0FFC0FFC3C0003FFBFF",
INIT_11 => X"00000000013FFFFFFC000000001FFFFFFFFFF0000FFFFFE0000000003FFE1FFF",
INIT_0B => X"000000000F0300001E000000007FFFFFF8000000009FFFFFFFFFFDF9F00FFF00",
SRVAL_A => X"0",
INIT_3B => X"80007FF8C0000007FFFFFFFC003FFF1FFE0000003FFF9FFFFFFFFFFFFF01FFFF",
INIT_1A => X"FFFFFF0001F1E0F8E01FFFFF007FFFFFFFF000003FFFFFFFFFF00FC0000007FF",
INIT_16 => X"001FC000007FFFFFF9F0000003FFFFFFFFFFF80000FFFFFF000000003FFFFFFF",
INIT_05 => X"0000000007E73000000000003FDFC3FFE07E000003FFFFFFF00000000001D87F",
INIT_15 => X"FF3FE00001FFE07E00078000007FFDFFF80000000003FFFFFFFFF80000FFFFFE",
INIT_19 => X"E00000003FFFFFFFFFFFFE0001F1E0F8E07FFFE0007FFBFFFFF000000FFFFFFF",
INIT_0E => X"FFFFF0007FFFFFC00000000001F3FFFF8040000007830007F8000000007CFFFF",
INIT_3E => X"FFFFFFFFFE03FFFFFFFFFFFFC07FFFC1FF000FFFF00000003FFFFFFF000FFF87",
INIT_24 => X"06007FFFE003C3FFF01FFFFC007C1FFFFFFF801FFFFFE1FFFFFFF03FF8000000",
INIT_22 => X"FFFFE01FF80000007F0000000FFFBFF81F00FFFFC01FE3CFE00FFFFC00FF0FFF",
INIT_08 => X"F80000000003FFFFFFFFFFFC007FFC000000000003F07FF8000000001F1FC0FF",
INIT_02 => X"003FE00003FFFFFFF00000000000007FFFFFFFFFFFFFF00000001F8003000000",
INIT_3D => X"FF0000003FFFFFFFFFFFFFFFFE01FFFFFFFFFFFFC07FFFC1C0001FFCE0000000",
INIT_01 => X"0000001FFFFFCFF8001FF40003FFFFFFF00000000000043FFFFFFFFFFFFFFFFF",
INIT_34 => X"FFFFFFFFFFC0FFFFFFFFFFFFF803FFF9FFFFFC0007FFFFFFFFFFFF0003FFF0F0",
INIT_2D => X"FFFF00000387FFCC00000FFFFFC0FFFFFFFFFF01FBFC7FFFFFFFFFFFFF807F8F",
INIT_2C => X"FFFFFFFFFFFB80007FFC00000187FFF800000F87FF8003FFFFFFFF00F3FC3FFF",
INIT_17 => X"FBF0000007FFFFFFFFFFFC0000F81FFF800000003FFFFFFFFF7FF00003F7E07F",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
WRITE_MODE_B => "WRITE_FIRST",
INIT_21 => X"FFF00007FFFFF3FFFFFFC01FF8000038FF8000001FFF3FFF3F01FFFF001FF3CF",
SRVAL_B => X"0",
INIT_3F => X"FFFFFFFFC07FFF81FFFC07FFFC0000001FFFFFFF8007FFC7FF8080003FFFFFFF"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena,
ENB => BU2_N1,
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_25_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_03 => X"FFFFFFFFFF07FFFFFFFFFFFF81FFFC03FFFFFFFFFFFF8000007FFFFFF800FFFF",
INIT_04 => X"FFFFFFFF03FFFC07FFFFFFFFCFFF8000001FFFFFFC00FFFFFFFE0003C7FFFFFF",
INIT_B => X"0",
INIT_A => X"0",
SIM_COLLISION_CHECK => "NONE",
INIT_3E => X"FFF00000001FC000F800FCFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000FFFFFF",
INIT_01 => X"03FFFFFFF001FFE3FFFC800007FFFFFFFFFFFFFFFF03FFFFFFFFFFFF80FFFF01",
INIT_3D => X"FFFF81F8000001FFFFF00000001FC100F001FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"8000000000FFFFFFFFFF0018000003FFFFF00000000F8FF0F003FFFFFFFFFFFF",
INIT_3B => X"FFFFFFFFFFFFFFFF8000000000FFFFFFFFFF0000000007FFFFF8000000079FFF",
INIT_3A => X"F007FF7FFFFFFFFFFFFFFFFFFFFFFFFF800000000007FF00FE00000000000FFF",
INIT_39 => X"FFFE000000007FFFF00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000007FE00",
INIT_38 => X"6000000000001FFFFFFE003F8000FFFF801F3FDFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_37 => X"F80000000003F8000000000000003FFFFFFFC0FFE03FFFFF00181FDFFFFFFFFF",
INIT_36 => X"FFFFFFFFFFFFFFFFC00000000003C000000000000001FFFFFFFFE1FFE03FFFFE",
INIT_35 => X"03E01FCBFFFFFFFFFFFFFFFFFFFFFFFF8000000000078000000187E00007FFFF",
INIT_34 => X"FFFFF3F8601FFFFE0FC01FC3FFFFFFFFFFFFFFFFFFFFFFFF800000000007F800",
INIT_33 => X"000FFFE0001FFFFFFFFFF7F80001FFFE1F801FCFFFFFFFFFFFFF7FFFFFFFFFFF",
INIT_32 => X"80000000000078000003DFC0007FFFFFFF1FFFF80000FFFF3F803FFFFFFFFFFF",
INIT_31 => X"FFFC3FFFFFFFFFFF80000000000039C00003800000FFFFFFFC3FFFF80001FFFF",
INIT_30 => X"FF807FFFFFFFFFFFFFFC1FFFFFFFFFFF8000000000E003F80001000001FFFFFF",
INIT_2F => X"F87FFFFC00E7FFFFFF00FFFFFFFFFFFFFFFE1FFFFFFFFFFF8000000001F803FC",
INIT_2E => X"0000000003FFFFFFE0FFFFFC00FFFFFFFF00FFFFFFFFFFFFFFFF0FFFFFFFFFFF",
INIT_2D => X"8000000001F003F00003C000EFFFFFFF03FFFFFE00FFFFFFFF81FFFFFFFFFFFF",
INIT_2C => X"FFFF83FFFFFE3FFF8000000001F003000003C000FFFFFFFC07FFFFFF01FFFFFF",
INIT_2B => X"FF83FFFFFFFFFFFFFFFFC3FFFFFE0FFF8000000000F0FC0000000007FFFFFFF0",
INIT_2A => X"1FFFFFFF81FFFFFFFF83FFFFFFFFFFFFFFFFC1FFFFFF01FF800018000039F800",
INIT_29 => X"00000007FFFFFFE07FFFFFFF81FFFFFFFF83FFFFFFFFFFFFFFFFE1FFFFFF807F",
INIT_28 => X"800018000000200000000007FFFFFFC1FFCFFFFF81FFFFFFFFC3FFFFFFFFFFFF",
INIT_27 => X"FFFFF0FFFFFFE03F800000000000000000000807FFFFFE07FF9FFFFF83FFFFFF",
INIT_26 => X"FFC3FFFFFFFFFFFFFFFFF0FFFFFFF00780000000000001C00000FE0FFFFFF83F",
INIT_25 => X"FF3FFFFF07FFFFFFFFC1FFFFFFFFFFFFFFFFF87FFFFFFE038000000000000780",
INIT_24 => X"001FFF1FFFFFF0FFFE3FFFF007BFFFFFFFE03FFFFFFFFFFFFFFFF87FFFFFFF01",
INIT_23 => X"8000000000000E0007FFFFFFFFFFC3FFFC7FFFE00707FFFFFFE03FFFFFFFFFFF",
INIT_22 => X"FFFFFC3FFFFFFF8180000000000000000FFFFFFFFFFF0FFFFC7FFFE00307FFFF",
INIT_21 => X"FFF03FFFFFFFFFFFFFFFFC3FFFFFFFE180000000000000003FFFFFFFFFF83FFF",
INIT_20 => X"F3FFFFE0070FFFFFFFF83FFFFFFFFFFFFFFFFE1CFFFFFFF1E00FE00000001838",
INIT_1F => X"7FFFFFFFFFF0FFFFFFFFFFE00E0FFFFFFFFC7FFFBFFFFFFFFFFFFE0CFFFFFFF9",
INIT_1E => X"F03F000000001FFFFFFFFFFFFF83FFFFDFFFFFF80E0FFFFFFFFFFFFF9FFFFFFF",
INIT_1D => X"FFFFFF047FFFFFFDE030000000000FFFFFFFFFFFFF0FFFFFDFFFFFF8041FFFFF",
INIT_1C => X"FFFFFFFFDFFFFFFFFFFFFF007FFFFFFDE000000000000FFFFFFFFFFFF83FFFFF",
INIT_1B => X"3FFFFFF0001FFFFFFFFFFFFFFFFFFFFFFFFFFF807FFFFFFFC000000000000FFF",
INIT_1A => X"FFFFFFFFE0FFFFFE1FFFFFF0001FFFFFFFFFFFFFFFFFFFFFFFFFFFC07FFFFFFF",
INIT_19 => X"C000000000000FFFFFFFFFFF83FFFFF83FFFFFF0003FFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFC07FFFFFFFC000000000007FFFFFFFFFF80FFFFFF07FFFFFF0003FFFFF",
INIT_17 => X"FFFFFFFFEFFFFFFFFFFFFFC07FFFFFFFC00000000001FFFFFFFFFFE03FFFFFE0",
INIT_16 => X"FFFFFFF8003FFFFFFFFFFFFFE3FFFFFFFFFFFFE07FFFFFFFC00000000001FFFF",
INIT_15 => X"FFFFFC00FFFFFFC0FFFFFFF8C63FE3FFFFFFFFFFE3FFFFFFFFFFFFE07FFFFFFF",
INIT_14 => X"800000000000FFFFFFFFF803FFFFFF01FFFFFFF8E27F83FFFFFFFFFFF1FFFFFF",
INIT_13 => X"FFFFFFF07FFFFFFF800000000000FFFFFFFFC007FFFFFE03FFFFFFFDF0FF03FF",
INIT_12 => X"FFFFFFFFF9FFFFFFFFFFFFF07FFFFFFF8000000000007FFFFFFF000FFFFFFC07",
INIT_11 => X"FFFFFFF9F0FE03FFFFFFFFFFF8FFFFFFFFFFFFF03FFFFFFF8000000000003FFF",
INIT_10 => X"FFE0003FFFFFF01FFFFFFFF9F0FC07FFFFFFFFFFF8FFFFFFFFFFFFF83FFFF7FF",
INIT_0F => X"8000000000000FFFFF80007FFFFFF83FFFFFFFF0F0F807FFFFFFFFFFF87FFFFF",
INIT_0E => X"E7FFFFF83FFFF1FF8000000000000FFFFF0000FFFFFF907FFFFFFFF078E00FFF",
INIT_0D => X"FFFFFFFFFC7FFFFFE3FFFFFC1FFFE0FF8000000000FC07FFFE0003FFFFFE00FF",
INIT_0C => X"FFFFFFF078001FFFFFFFFFFFFC3FFFFFE3FFFFFC0FFFF0FF8000000001FE07FF",
INIT_0B => X"F80007FFFFFC01FFFFFFFFF0FFFFFFFFFFFFFFFFF83FFFFFF9FFFFFE0FFFF87F",
INIT_0A => X"E000000001FF07FFC0001FFFFFF003FFFFFFF3F1FFFFFFFFFFFFFFFFF81FFFFF",
INIT_09 => X"F8FFFFFE07FFF81FFC00000071FF87FE00007FFFFFE007FFFFFF01E1FFFFFFFF",
INIT_08 => X"FFFFFFFFFC1FFFFFF8FFFFFE07FFF80FFE0000FFF0FFC3000001FFFFFFC01FFF",
INIT_07 => X"FFFF0041FFFFFFFFFFFFFFFFFC0FFFFFFFFFFFFF03FFFC07FFFF3FFFE37FC000",
INIT_06 => X"0007FFFFFF003FFFFFFE0003FFFFFFFFFFFFFFFFFE07FFFFFFFFFFFF03FFFC07",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SRVAL_B => X"0",
INIT_02 => X"FFFF800203FFFFFFFFFFFFFFFF07FFFFFFFFFFFF81FFFE01FFFFE3FFFFFF0000",
SRVAL_A => X"0",
INIT_05 => X"FFFFFFFFC7FF8000000FFFFFFE007FFFFFFE0003FFFFFFFFFFFFFFFFFE07FFFF",
INIT_00 => X"FFFF03FFFFFC000007FFFFFFC003FFC3FFF8800007FFFFFFFFFFFFFFFC03FFFF",
INIT_3F => X"FC00187FFFFFFFFFFFFFFFFFFFFFFFFF8000000000FFFFFFFFFF83FFFF000020"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_26_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
INIT_21 => X"FFFF00000C7FFF7F0041FFFFFFE0007FFFFFFFFF7FFFFFFFFFF000000003FFFF",
INIT_06 => X"80000000F03FFFFFFFFFFFFFFFFFFF8000000000001F3E31FF0003FF01FFFFFF",
INIT_0E => X"FC0007FFFFFFFFFFFFFFFFFFFFFFFFFD8000070FFE00000000003FFFFFFFFFFF",
SRVAL_A => X"0",
INIT_1A => X"FFFF80000000001FFFFFFFFFFFFFFFFE0000000000FCFFFE00003FFFFFF9FFFF",
INIT_1F => X"FFF80000000003FFFFFFFFFFFFFF83FFFFE00000007FFF1C0000FFFFFFF8007F",
INIT_12 => X"F0000000000FE00F00000FFFFFFFFFFFC7FFFFFFFFFFFF8180007FFE7C000000",
INIT_2C => X"001FFF03FFFFFFFFFFFFFFFFFFFFFFFF8FF00007FFC00007F80000003FFFFFFF",
INIT_38 => X"FFFFFE000003F000001FFFFFFFFFF1FFFFFFE0000FFFE000000007FFFFFFFFF9",
INIT_04 => X"FC0001FC1FFFFFFFFFFFFFFFFFFFFFFF80000000007FFFFFFFFFFFFFFFFFFE00",
INIT_07 => X"FFFFFFFFFFFFFFC000000000001E3E39FF0083FFC1FFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FF00000000FCFC7C00007FFFFFF00FFFFFFFFFFFFFC07FFFFFFF0000000000FF",
INIT_37 => X"FFF81FFFFFFFFFFFFFFFFE000000F000000FFFFFFFFFF8FFFFFFF0000FFFF000",
INIT_22 => X"0001FFFFFFC000FFFFFFFFFFFFFFFFFFFFE00000003FFFFFFFFFFF0FFFF3FFFF",
INIT_30 => X"FFFFF8001FFFFF00000007FFFFFFFFFFFFFFFFFFFFFFFFFF800000F800000078",
INIT_2A => X"FEFE00001FFFFFFFFFFFFF003E7FFFFC001FFFC003FFFFFFFFFFFFFFFFFFFFFF",
INIT_2D => X"FFFFFFFFFFFFFFFF8FC00001FF000007000000079FFFFFFFFFFFFE001FFFF8F8",
INIT_0C => X"0007FFFFFFFFFFFFE0000000000000007C0207FFFF8FFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"7E0107FFE3FFFFFFFFFFFFFFFFFFFFFF80000000FC3FFFFFFFFFFFFFFFFFFFE0",
INIT_2B => X"FFFFFE001FFFFFFC001FFF800FFFFFFFFFFFFFFFFFFFFFFF83F8001FFFE00007",
INIT_32 => X"FFFC7FFFFFFFFFFF873F83F0000000F00000007F0FFFFFFFFFFFF8000FFFFF00",
INIT_24 => X"FF0000000FFFFFFFFFFFFE03FF9FFFFFFFFE0000007FFFFC0001FFFFF00000FF",
INIT_16 => X"003FFFFFFFFFFFFFC00000000007F8FFC0001FFFFFFFFFFFFFFFFFFFFFFFF807",
INIT_13 => X"80000FFFFFFFFFFFF3FFFFFFFFFFFF018000FFF010000000000001FFFFFFFFFF",
INIT_0D => X"F800000000000000FC0007FFFFCFFFFFFFFFFFFFFFFFFFFF800000063C00FFFC",
INIT_2F => X"0000001F0FFFFFFFFFFFFC001FFFFE00000007FFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_2E => X"9F000000F000001C0000001F0FFFFFFFFFFFFC001FFFF82000000F8FFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFF3E00000000F87FFC00003FFFFFF00FFFFFFFFFFFFFF03FFF",
INIT_35 => X"FFFFF0000FFFFC000000FFFFFFFFFFFFFFF83FFFFFFFFFFFFFFFFF8000000000",
INIT_34 => X"0000FFFFBFFFFF7FFFFFF0000FFFFE0000007FFFFFFFFFFFFFFC3FFFFFFFFFFF",
SRVAL_B => X"0",
INIT_18 => X"00003FFFFFFFFFFFFFFFFFFFFFFF03FFFFFFE0000000000001FFFFFFFFFFFFFF",
INIT_10 => X"80007FFFFC0000000000000007FFFFFFFC0000000001C002B80007FFFFFFFFFF",
INIT_20 => X"FFFFFFDFFFFFBFFFFFE000000CFFFF1C0000FFFFFFF0007FFFFFFFFFCF7FFFFF",
INIT_39 => X"003FFFFFFFFFE3FFFFFFC0003FFFC00000000FFFFFC7FFE0FFF81FFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFF000003E00000003FE000FC0001FC7FFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFF81FFFFFFFC000000000003FFFFFFFFFFFFFFE00000000000FFFFF",
INIT_11 => X"0000000FFFFFFFFFFC000000000FC00600000FFFFFFFFFFFFFFFFFFFFFFFFFF1",
INIT_1D => X"00007FFFFFF001FFFFFFFFFFFF03FFFFFFFE0000000001FFFFFFFFFFFFFFF9FF",
INIT_23 => X"FFFFFFFFFFFFFFFFFF80000003FFFFFFFFFFFF07FFE3FFFFFFFF00001C7FFFFF",
INIT_01 => X"80000000007FFFFFFFFFFFFFFFF000001FF00000001FE000FC0000FFFFFFFFFF",
INIT_17 => X"00000000000FFFFF80003FFFFFFFFFFFFFFFFFFFFFFFE03F807FE00000000000",
INIT_0F => X"FFFFFFFFFFFFFFF980000FFFFE00000000000000FFFFFFFFFC00000000018000",
INIT_08 => X"00000000001E7C78FF0103FFC1FFFFFFFFFFFFFFFFFFFFFF80000000F83FFFFF",
INIT_36 => X"00003FFFFFFFFFFFFFF83FFFFFFFFFFFFFFFFE00000070000001FFFFFFFFFCFF",
INIT_26 => X"FFFF0000003FFFF00003FFFC003FE1FFFFFFFFFFFFFFFFFFFC0600003FFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFC018007FFE00000000000003FFFFFFFFFFFE00000000007F07F",
INIT_33 => X"BFFFE7E00000008000007FFF0FFFFFBFFFFFF8000FFFFF0000001FFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFF80000000003FFFFFFFFFFFFFFFFFFF0000000000001FFC23",
INIT_28 => X"FFFFFFFFFFFFFFFFF07C000FFFFF001FFFFFC0C003FFFFFFFFFF8C00003FFFF8",
INIT_29 => X"C0F8001FFFF00007FFFF00000FFFFFFFFFFFFF00103FFFF8000FFFF000FFFFFF",
INIT_31 => X"00000FFFFFFFFFFFFFFE7FFFFFFFFFFF800701F8000000F80000000F0FFFFFFF",
INIT_03 => X"00000000003FFC01FC0001F83FFFFFFFFFFFFFFFFFFFFFFF80000000007FFFFF",
INIT_0B => X"800000001E1FFFFFFFFFFFFFFFFFFFFF0000000000001C787E0107FFFF9FFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFF800000003C3FFFFFFFFFFFFFFFFFFFF800000000000E3C78",
INIT_27 => X"0007FFF8007FFFFFFFFFFFFFFFFFFFFFF80E0000FFFFFFFFFFFFF1C000FFFFFF",
INIT_00 => X"FFFFFFFFFFFFFFFF8000000000FFFFFFFFFFC7FFFFC000003FF00000001FC000",
INIT_1E => X"FFFFFFFFFC0FFFFFFFFC0000000001FFFFFFFFFFFFFFC1FFFFC0000000FFFE3C",
INIT_25 => X"FFFFFF00FC3FFFFFFFFE0000007FFFF80001FFFE000781FFFFFFFFFFFFFFFFFF",
INIT_15 => X"801FF800000000000007FFFFFFFFFFFFE00000000003F87FC0000FFFFFFFFFFF",
INIT_3A => X"FFFFC7007FFFC00000007FFFFF83FFC03FE01FFFFFFFFFFFFF1FFC00000FF000",
INIT_3B => X"00007FFFFF01FFC01FC01FFFFFFFFFFFBFBC0000001FE000007FFFFFFFFFC7FF",
INIT_3C => X"0001FFFFFFFFFFFF9FF80000003FC0003FFFFFFFFFFF0FFFFFFF87007FFFE000",
INIT_3D => X"8FF00000003F80007FFFFFFFFFFE1FFFFFFF87007FFFE00000007FFFFF81FFE0",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"7FFFFFFFFFFC3FFFFFFF9F007FFFE00000003FFFFFC0FFF00001FFFFFFFFFFFF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFFF3F007FFFE00000000FFFFFF0FFF00001FFFFFFFFFFFFE3C00000007F0000"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_27_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram : RAMB16_S1_S1
generic map(
SRVAL_A => X"0",
SRVAL_B => X"0",
INIT_00 => X"000007FFFFFFFFF00001FFFFFFFFFFFFFFC00000007F00007FFFFFFFFFF83FFF",
INIT_01 => X"0001FFFFFFFFFFFFFFC00000007C0000FFFFFFFFFFE07FFFFFFF3F007FFFE000",
INIT_02 => X"FFF80000007C0007FFFFFFFFFFC0FFFFFFFE3F807FFFE000000067FFFFFFFF00",
INIT_03 => X"FFFFFFFFFF00FFFFFFFE7F003FFFC0080300FFFFFFFFFE000000FFFFFFFFFFFF",
INIT_04 => X"FFFCFF803FFF001C0000FFFFFFFFF000000007FFFFFFFFFFFE3800000038007F",
INIT_05 => X"00007FFFE000000000000FFFFFFFFFFFFE200000800003FFFFFFFFFFFC03FFFF",
INIT_06 => X"00003FFFFFFFFFFFFE20000100000FFFFFFFFFFFF007FFFFFFF8FF803FFE001C",
INIT_07 => X"FE70000100003FFFFFFFFFFFE00FFFFFFFF8FF801FFC003C000003FC00000000",
INIT_08 => X"FFFFFFFFC00FFFFFFFF1FF821FFC007E0007000000000FFE00047FFFFFFFFFFF",
INIT_09 => X"FFF3FF9F1FF8007E000F800000003FFE000FFFFFFFFFFFFFFFE000070000FFFF",
INIT_0A => X"000F80000001FFFF801FFFFFFFFFFFFFFFC000070000FFFFFFF9FFFF801FFFFF",
INIT_0B => X"E01FFFFFFFFFFFFFFFC000060000FFFFFF81FFFF003FFFFFFFE3FF9F1FF800FE",
INIT_0C => X"FFC000060001FFFFF801FFFE003FFFFFFFE7FFFF1FE001FF000F80000007FFFF",
INIT_0D => X"F003FFFC007FFFFFFFC7FFFFFFC183FF003F2000000FF7FFE00FFFFFFFFFFFFF",
INIT_0E => X"FFC7FFF7FFC383FF00FFF000001FE3FFE007FFFFFFFFFFFFFFC01FDE0003FFFF",
INIT_0F => X"01FFF800003FC3FFC000FFFFFFFFFFFFFF803FFE3807FFFFE007FFF8007FFFFF",
INIT_10 => X"C000FFFFFFFFFFFFFF80FFFEFC07FFFFC007FFF000FFFFFFFF8FFFE7FFE3C7FF",
INIT_11 => X"FFC1FFFFFE07FFFF000FFFE001FFFFFFFF8FFFC3FFF9C7FF81FFF80000FF83FF",
INIT_12 => X"000FFF8003FFFFFFFF9FFF83FFF18FFF81FFFC0001FF01FF800F7FFFFFFFFFFF",
INIT_13 => X"FF1FFF83FFF08FFFC1FFFE0000FF00FC001F7FFFFFFFFFFFFFFFF0FFFFFFFFFE",
INIT_14 => X"C0FFFF00007F8078000EFFFFFFFFFFFFFFFFE07FFFF007FC001FF00003FFFFFF",
INIT_15 => X"0000FFFFFFFFFFFFFFFFE07FFFC003F0003FC00007FFFFFFFF1FFF01FFE00FFF",
INIT_16 => X"FFFFF1FFFF800000007FC0000FFFFFFFFF1FFE01FFE00FFFC0FFFF00003FC000",
INIT_17 => X"00FF80001FFFFFFFFF3FFE01FFF807FFC07FFF00001FF80000007FFFFFFFFFFF",
INIT_18 => X"FE3FFC003FF807FFC03FFF00000FFCF000003FFFFFFFFFFFFFFFFFFFFF000000",
INIT_19 => X"C03FFF000003FFFC00007FFFFFFFFFFFFFFFFFFFFE00000007FF80003FFFFFFF",
INIT_1A => X"C0007FFFFFFFFFFFFFFFFFFFFE0000001FFF00007FFFFFFFFE7FFC001FF807FF",
INIT_1B => X"FFFFFFFFFC0000001FFE0000FFFFFFFFFC7FF8001F9887FFC01FFF800181FFFF",
INIT_1C => X"3FFC0000FFFFC3FFFCFFFE61FF1183FFC00FFF8000E07FFFF000FC7FFFFFFFFF",
INIT_1D => X"F8FFFFF3FF0183FFE007FF8000783FFFF800003FFFFFFFFFFFFFFFFFFE800000",
INIT_1E => X"E007FF80003C1FFFFE00001FFFFFFFFFFFFFFFFFFFFFE0007FF80001FFFF03FF",
INIT_1F => X"FF00003FFFFFFFFFFFFFFFFFFFFFC000FFF00003FFFC07FFF8FFFFFF1F0181FF",
INIT_20 => X"FFFFFFFFFFFF0001FFE00003FFF807FFF9FFFFFE0F8383FFE007FFF8001E1FFF",
INIT_21 => X"FFC0000FFFF007FFF1FFFFFF0FEFC3FFF007FFFC00078FFFFF00007FFFFFFFFF",
INIT_22 => X"F3FFFFFF0FFFC3FFF007FFFE0003CFFFFC00007FFFFFFFFFFFFFFFFFFF800001",
INIT_23 => X"F807FFFE0001E3FFF000007FFFFFFFFFFFFFFFFF7F800000FF00000FFFF007FF",
INIT_24 => X"F800007FFFFFFFFFFFFFFFFE1F8030007F00001FFFE007FFE3FFF9FF07FFC3FF",
INIT_25 => X"FFFFFFFE1F807FFC7E00001FFFC007FFE3FFF1FBC7FFE3FFF807FFFF0000F1FF",
INIT_26 => X"3C00003FFF800FFFC3FFE0C1C3FFE3FFF803FFFF8000F07FFE00003FFFFFFFFF",
INIT_27 => X"C3FFC001C0FFE1FFFC03FFFFC000781FFF00603FFFFFFFFFFFFFFFFF3F81FFF8",
INIT_28 => X"FC03FFEFC0083C0FFFF0F801FFFFFFFFFFFFFFFFFF01FFF07800007FFF800FFF",
INIT_29 => X"FFFFF800FFFFFFFFFFFFFFFFFF01FF80000000FFFF801FFFC7FF8000001FC1FF",
INIT_2A => X"FFFFFFFFE001FC00000000FFFF001FFF87FF0000000FC0FFFE01FFCFE0003E0F",
INIT_2B => X"000001FFFF001FFF87FF00000007C0FFFE00FF8FF8003E07FFFFF8007FFFFFFF",
INIT_2C => X"0FFE00000007C07FFF00FF0FFC003F03FFFFFFF07FFFFFFFFFFFFFFFE30FFC00",
INIT_2D => X"FF00FF07FF01FF01FFFFFFF87FFFFFFFFFFFFFFFFFFDFE00000003FFFE003FFF",
INIT_2E => X"FFFFFFF87FFFFFFFFFFFFFFFFFFDFC00000007FFFE003FFF0FFE00000007C03F",
INIT_2F => X"FFFFFFFFFFFFF8000C000FFFFC007FFE0FFFC0000037C03FFF807F87FF01FF80",
INIT_30 => X"1C000FFFF8007FFE1FFFC000003FC03FFF803FF3FF81FFC07FFFFFFC3FFFFFFF",
INIT_31 => X"3FFFC003001FC01FFFC03FFBFFC0FFF03FFFFFFE3FFFFFFFFFFFFFFFFFFFF0F0",
INIT_32 => X"FFC00FFFFFC07FF81FFFFFFFFFFFFFFFFFFFFFFFFFFFE3F81C000FFFF000FFFE",
INIT_33 => X"1FFFFFFFFFFFFFFFFFFFFFFFFFFFE7FC3C000FFFC000FFFC3FFFC003000FC01E",
INIT_34 => X"FFFFFFFFFFFFCFFC3C001FFFC001FFFC7FFF8007000FC00C7FE007FFFFC03FFC",
INIT_35 => X"3C001FFF8001FFFC60FF0067000FC01C3CE007FFFFE01FFE0FFFFFFFFFFFFFFF",
INIT_36 => X"43FE00FF000FC00C3C0007FFFFF01FFF0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE",
INIT_37 => X"7E0003FFFFFC0FFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C003FFF0001FFF8",
INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C007FFC0001FFF80FFC01FF0007C000",
INIT_39 => X"FFFFFFFFFFFFFFFF7CE0FF000001FFF01FFC01FF000000007F0001FFFFFE07FF",
INIT_3A => X"7FF1FF000001FFF03FFC03FF800000007F8001FFFFFF83FFFFFFFFFFFFFFFFFF",
INIT_3B => X"7FFC03FFC00000007FC000FFFFFFC1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_3C => X"7FC000FFFFFFC0FFFFFFFFFFFFFF9FFFFFFFFFFFFFFFFFFFFBF1FF100003FFF0",
INIT_3D => X"FFFFFFFFFFFF81FFFFFFFFFFFFFFFFFFF3F1FFF80003FFE0FFF803F9C0000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_3E => X"FFFFFFFFFFFFFFFFE7F3FFF80003FFE1FFF00FF8E00000007FE000FFFFFFE0FF",
SIM_COLLISION_CHECK => "NONE",
INIT_A => X"0",
INIT_B => X"0",
WRITE_MODE_A => "WRITE_FIRST",
INIT_3F => X"FFF3FFF00003FFC1FFF01FFC100000007FF0007FFFFFF07FFFFFFFFFFFFF801F"
)
port map (
CLKA => clka,
CLKB => BU2_doutb(0),
ENA => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12,
ENB => BU2_doutb(0),
SSRA => BU2_doutb(0),
SSRB => BU2_doutb(0),
WEA => BU2_doutb(0),
WEB => BU2_doutb(0),
ADDRA(13) => addra_6(13),
ADDRA(12) => addra_6(12),
ADDRA(11) => addra_6(11),
ADDRA(10) => addra_6(10),
ADDRA(9) => addra_6(9),
ADDRA(8) => addra_6(8),
ADDRA(7) => addra_6(7),
ADDRA(6) => addra_6(6),
ADDRA(5) => addra_6(5),
ADDRA(4) => addra_6(4),
ADDRA(3) => addra_6(3),
ADDRA(2) => addra_6(2),
ADDRA(1) => addra_6(1),
ADDRA(0) => addra_6(0),
ADDRB(13) => BU2_doutb(0),
ADDRB(12) => BU2_doutb(0),
ADDRB(11) => BU2_doutb(0),
ADDRB(10) => BU2_doutb(0),
ADDRB(9) => BU2_doutb(0),
ADDRB(8) => BU2_doutb(0),
ADDRB(7) => BU2_doutb(0),
ADDRB(6) => BU2_doutb(0),
ADDRB(5) => BU2_doutb(0),
ADDRB(4) => BU2_doutb(0),
ADDRB(3) => BU2_doutb(0),
ADDRB(2) => BU2_doutb(0),
ADDRB(1) => BU2_doutb(0),
ADDRB(0) => BU2_doutb(0),
DIA(0) => BU2_doutb(0),
DIB(0) => BU2_doutb(0),
DOA(0) => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
DOB(0) => NLW_BU2_U0_blk_mem_generator_valid_cstr_ramloop_28_ram_r_v2_init_ram_dp1x1_ram_DOB_0_UNCONNECTED
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena131 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addra_6(13),
I1 => addra_6(14),
I2 => addra_6(16),
I3 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena13
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N18,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52,
O => douta_7(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_2_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(0),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N18
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N16,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53,
O => douta_7(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_3_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(1),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta13(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N16
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N14,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54,
O => douta_7(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_4_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(2),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(0),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N14
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5 : LUT4
generic map(
INIT => X"222F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I1 => BU2_N12,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55,
O => douta_7(5)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_5_SW0 : LUT4
generic map(
INIT => X"AF27"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta14(3),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta23(1),
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0),
O => BU2_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_1 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta3,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_11 : LUT4
generic map(
INIT => X"888F"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N13,
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51,
I3 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
O => douta_7(1)
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq00001 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(12),
I1 => addra_6(13),
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3,
O => BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq0000
);
BU2_U0_blk_mem_generator_valid_cstr_bindec_a_bindec_inst_a_enout_18_cmp_eq000011 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(14),
I1 => addra_6(16),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4_221 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
I1 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4),
I2 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
O => BU2_U0_blk_mem_generator_valid_cstr_N13
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena1 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena01 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(14),
I2 => addra_6(15),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena0
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena11 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena1_2
);
BU2_U0_blk_mem_generator_valid_cstr_ram_ena121 : LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra_6(16),
I1 => addra_6(15),
I2 => addra_6(14),
O => BU2_U0_blk_mem_generator_valid_cstr_ram_ena12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_4 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(16),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(4)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_3 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(15),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_2 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(14),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_1 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(13),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(1)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe_0 : FDE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => BU2_N1,
D => addra_6(12),
Q => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(0)
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_4 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N12,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N11,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f55
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_75 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta24,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta25,
O => BU2_U0_blk_mem_generator_valid_cstr_N12
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_65 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta26,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta27,
O => BU2_U0_blk_mem_generator_valid_cstr_N11
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_3 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N10,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N9,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f54
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_74 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta19,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta20,
O => BU2_U0_blk_mem_generator_valid_cstr_N10
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_64 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta21,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta22,
O => BU2_U0_blk_mem_generator_valid_cstr_N9
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_2 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N8,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N7,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f53
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_73 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta15,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta16,
O => BU2_U0_blk_mem_generator_valid_cstr_N8
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_63 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta17,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta18,
O => BU2_U0_blk_mem_generator_valid_cstr_N7
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_1 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N6,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N5,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f52
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_72 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta9,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta10,
O => BU2_U0_blk_mem_generator_valid_cstr_N6
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_62 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta11,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta12,
O => BU2_U0_blk_mem_generator_valid_cstr_N5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_0 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N4,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N3,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f51
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_71 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta4,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta5,
O => BU2_U0_blk_mem_generator_valid_cstr_N4
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_61 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta6,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta7,
O => BU2_U0_blk_mem_generator_valid_cstr_N3
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5 : MUXF5
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_N2,
I1 => BU2_U0_blk_mem_generator_valid_cstr_N1,
S => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(3),
O => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_5_f5_5
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_7 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta0,
O => BU2_U0_blk_mem_generator_valid_cstr_N2
);
BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_Mmux_dout_mux_6 : LUT3
generic map(
INIT => X"1B"
)
port map (
I0 => BU2_U0_blk_mem_generator_valid_cstr_has_mux_a_A_sel_pipe(2),
I1 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta1,
I2 => BU2_U0_blk_mem_generator_valid_cstr_ram_douta2,
O => BU2_U0_blk_mem_generator_valid_cstr_N1
);
BU2_XST_VCC : VCC
port map (
P => BU2_N1
);
BU2_XST_GND : GND
port map (
G => BU2_doutb(0)
);
end STRUCTURE;
-- synopsys translate_on
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2410.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02410ent IS
END c07s03b02x00p09n01i02410ent;
ARCHITECTURE c07s03b02x00p09n01i02410arch OF c07s03b02x00p09n01i02410ent IS
type array_three is array (1 to 6) of integer;
constant x : array_three := (1, 2, 3, 4, 5, 6);
constant y : array_three := (1 => 1, 2 => 2, 2 => 3,others => 0);
-- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p09n01i02410 - An element of the value defined by an aggregate can be represented only once in an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02410arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2410.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02410ent IS
END c07s03b02x00p09n01i02410ent;
ARCHITECTURE c07s03b02x00p09n01i02410arch OF c07s03b02x00p09n01i02410ent IS
type array_three is array (1 to 6) of integer;
constant x : array_three := (1, 2, 3, 4, 5, 6);
constant y : array_three := (1 => 1, 2 => 2, 2 => 3,others => 0);
-- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p09n01i02410 - An element of the value defined by an aggregate can be represented only once in an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02410arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2410.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02410ent IS
END c07s03b02x00p09n01i02410ent;
ARCHITECTURE c07s03b02x00p09n01i02410arch OF c07s03b02x00p09n01i02410ent IS
type array_three is array (1 to 6) of integer;
constant x : array_three := (1, 2, 3, 4, 5, 6);
constant y : array_three := (1 => 1, 2 => 2, 2 => 3,others => 0);
-- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x00p09n01i02410 - An element of the value defined by an aggregate can be represented only once in an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02410arch;
|
constant bitdataLength : integer := 1282;
constant bitdataCfg : std_logic_vector(bitdataLength-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000101011010100000000000000100000100000000000000001100000011000000000000011000000000000000000000000000000000010001000100000000000000000000000000000000000000000000011000000000000000000000000000100100000000000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110110100000000000000000000000000000000000000110101011101001010100010000000000000000000000000000110001100000000000000000000000000000000000000000100011001000110001100011000110001100011000110001101101010000100010000000000010010100000000110100100000000000000000000000000000011011000010001111001110000000000000000000000000000000001000000000000000000000000000000011000100110100000000000000000000001000000010000000000000000000000010100000000000000000000000000000000110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001011000000000011100000000000000000000000000000001101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl
-- Design : system_vga_pll_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0_vga_pll is
port (
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_pll_0_0_vga_pll : entity is "vga_pll";
end system_vga_pll_0_0_vga_pll;
architecture STRUCTURE of system_vga_pll_0_0_vga_pll is
signal \^clk_12_5\ : STD_LOGIC;
signal clk_12_5_s_i_1_n_0 : STD_LOGIC;
signal \^clk_25\ : STD_LOGIC;
signal clk_25_s_i_1_n_0 : STD_LOGIC;
signal \^clk_50\ : STD_LOGIC;
signal \^clk_6_25\ : STD_LOGIC;
signal clk_6_25_s_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
begin
clk_12_5 <= \^clk_12_5\;
clk_25 <= \^clk_25\;
clk_50 <= \^clk_50\;
clk_6_25 <= \^clk_6_25\;
clk_12_5_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_12_5\,
O => clk_12_5_s_i_1_n_0
);
clk_12_5_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_25\,
CE => '1',
D => clk_12_5_s_i_1_n_0,
Q => \^clk_12_5\,
R => '0'
);
clk_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_25\,
O => clk_25_s_i_1_n_0
);
clk_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_50\,
CE => '1',
D => clk_25_s_i_1_n_0,
Q => \^clk_25\,
R => '0'
);
clk_50_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_50\,
O => p_0_in
);
clk_50_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => p_0_in,
Q => \^clk_50\,
R => '0'
);
clk_6_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_6_25\,
O => clk_6_25_s_i_1_n_0
);
clk_6_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_6_25\,
CE => '1',
D => clk_6_25_s_i_1_n_0,
Q => \^clk_6_25\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4";
end system_vga_pll_0_0;
architecture STRUCTURE of system_vga_pll_0_0 is
begin
U0: entity work.system_vga_pll_0_0_vga_pll
port map (
clk_100 => clk_100,
clk_12_5 => clk_12_5,
clk_25 => clk_25,
clk_50 => clk_50,
clk_6_25 => clk_6_25
);
end STRUCTURE;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity AOI is
port (
a, b, c, d : in std_logic;
f : out std_logic
);
end AOI;
architecture v1 of AOI is
begin
f <= not ((a and b) or (c and d));
end v1;
architecture v2 of AOI is
signal ab, cd, o : std_logic;
begin
ab <= a and b after 2ns;
cd <= c and d after 2ns;
o <= ab or cd after 2ns;
f <= not o after 1ns;
end v2;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux2 is
port(
sel, a, b: in STD_LOGIC;
f: out std_logic);
end mux2;
architecture m1 of mux2 is
component INV
port(a: in std_logic; f : out std_logic);
end component;
component AOI
port (
a, b, c, d : in std_logic;
f : out std_logic
);
end component;
signal selB : std_logic;
begin
g1: INV port map (sel, selB);
g2: AOI port map (sel, a, selB, b, f);
end m1;
library IEEE;
use IEEE.std_logic_1164.all;
entity D_FF is
port(D, clk: in bit; Q: out bit);
end entity D_FF;
architecture F of D_FF is
begin
process (clk) begin
if clk = '1' and clk'Event
then Q<=D;
end if;
end process;
end architecture F;
|
package body foo is end;
package body foo is end package body;
package body foo is end package body foo;
package body TriState is
function BitVal (Value: Tri) return Bit is
constant Bits : Bit_Vector := "0100";
begin
return Bits(Tri'Pos(Value));
end;
function TriVal (Value: Bit) return Tri is
begin
return Tri'Val(Bit'Pos(Value));
end;
function Resolve (Sources: TriVector) return Tri is
variable V: Tri := 'Z';
begin
for i in Sources'Range loop
if Sources(i) /= 'Z' then
if V = 'Z' then
V := Sources(i);
else
return 'E';
end if;
end if;
end loop;
return V;
end;
end package body TriState;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 17:17:23 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/fir_lp_54kHz/fir_lp_54kHz_stub.vhdl
-- Design : fir_lp_54kHz
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fir_lp_54kHz is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 95 downto 0 )
);
end fir_lp_54kHz;
architecture stub of fir_lp_54kHz is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[95:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_1,Vivado 2014.1";
begin
end;
|
-- NEED RESULT: ENT00025: Associated composite in ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00025
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00025(ARCH00025)
-- ENT00025_Test_Bench(ARCH00025_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00025 is
port (
i_bit_vector_1, i_bit_vector_2 : in bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : in string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : in t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : in st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : in t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : in st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : in t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : in st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : in t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : in st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : in t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : in st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : in t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : in st_arr3
:= c_st_arr3_1
) ;
begin
end ENT00025 ;
--
architecture ARCH00025 of ENT00025 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00025" ,
"Associated composite in ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00025 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00025_Test_Bench is
end ENT00025_Test_Bench ;
--
architecture ARCH00025_Test_Bench of ENT00025_Test_Bench is
begin
L1:
block
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
component UUT
port (
i_bit_vector_1, i_bit_vector_2 : in bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : in string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : in t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : in st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : in t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : in st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : in t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : in st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : in t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : in st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : in t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : in st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : in t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : in st_arr3
:= c_st_arr3_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00025 ( ARCH00025 ) ;
--
begin
CIS1 : UUT
port map (
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
end block L1 ;
end ARCH00025_Test_Bench ;
|
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity tracking_camera_system_nios2_qsys_0_test_bench is
port (
-- inputs:
signal A_bstatus_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_cmp_result : IN STD_LOGIC;
signal A_ctrl_exception : IN STD_LOGIC;
signal A_ctrl_ld_non_bypass : IN STD_LOGIC;
signal A_dst_regnum : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal A_en : IN STD_LOGIC;
signal A_estatus_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_ienable_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_ipending_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_iw : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_mem_byte_en : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal A_op_hbreak : IN STD_LOGIC;
signal A_op_intr : IN STD_LOGIC;
signal A_pcb : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal A_st_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_status_reg : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_valid : IN STD_LOGIC;
signal A_wr_data_unfiltered : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal A_wr_dst_reg : IN STD_LOGIC;
signal E_add_br_to_taken_history_unfiltered : IN STD_LOGIC;
signal E_logic_result : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_valid : IN STD_LOGIC;
signal M_bht_ptr_unfiltered : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal M_bht_wr_data_unfiltered : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal M_bht_wr_en_unfiltered : IN STD_LOGIC;
signal M_mem_baddr : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal M_target_pcb : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal M_valid : IN STD_LOGIC;
signal W_dst_regnum : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal W_iw : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_iw_op : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal W_iw_opx : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
signal W_pcb : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal W_valid : IN STD_LOGIC;
signal W_vinst : IN STD_LOGIC_VECTOR (55 DOWNTO 0);
signal W_wr_dst_reg : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal d_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal d_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal d_read : IN STD_LOGIC;
signal d_write : IN STD_LOGIC;
signal i_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0);
signal i_read : IN STD_LOGIC;
signal i_readdatavalid : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal A_wr_data_filtered : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal E_add_br_to_taken_history_filtered : OUT STD_LOGIC;
signal E_src1_eq_src2 : OUT STD_LOGIC;
signal M_bht_ptr_filtered : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal M_bht_wr_data_filtered : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal M_bht_wr_en_filtered : OUT STD_LOGIC;
signal test_has_ended : OUT STD_LOGIC
);
end entity tracking_camera_system_nios2_qsys_0_test_bench;
architecture europa of tracking_camera_system_nios2_qsys_0_test_bench is
signal A_mem_baddr : STD_LOGIC_VECTOR (24 DOWNTO 0);
signal A_target_pcb : STD_LOGIC_VECTOR (24 DOWNTO 0);
signal A_wr_data_unfiltered_0_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_10_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_11_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_12_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_13_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_14_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_15_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_16_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_17_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_18_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_19_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_1_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_20_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_21_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_22_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_23_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_24_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_25_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_26_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_27_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_28_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_29_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_2_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_30_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_31_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_3_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_4_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_5_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_6_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_7_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_8_is_x : STD_LOGIC;
signal A_wr_data_unfiltered_9_is_x : STD_LOGIC;
signal W_op_add : STD_LOGIC;
signal W_op_addi : STD_LOGIC;
signal W_op_and : STD_LOGIC;
signal W_op_andhi : STD_LOGIC;
signal W_op_andi : STD_LOGIC;
signal W_op_beq : STD_LOGIC;
signal W_op_bge : STD_LOGIC;
signal W_op_bgeu : STD_LOGIC;
signal W_op_blt : STD_LOGIC;
signal W_op_bltu : STD_LOGIC;
signal W_op_bne : STD_LOGIC;
signal W_op_br : STD_LOGIC;
signal W_op_break : STD_LOGIC;
signal W_op_bret : STD_LOGIC;
signal W_op_call : STD_LOGIC;
signal W_op_callr : STD_LOGIC;
signal W_op_cmpeq : STD_LOGIC;
signal W_op_cmpeqi : STD_LOGIC;
signal W_op_cmpge : STD_LOGIC;
signal W_op_cmpgei : STD_LOGIC;
signal W_op_cmpgeu : STD_LOGIC;
signal W_op_cmpgeui : STD_LOGIC;
signal W_op_cmplt : STD_LOGIC;
signal W_op_cmplti : STD_LOGIC;
signal W_op_cmpltu : STD_LOGIC;
signal W_op_cmpltui : STD_LOGIC;
signal W_op_cmpne : STD_LOGIC;
signal W_op_cmpnei : STD_LOGIC;
signal W_op_crst : STD_LOGIC;
signal W_op_custom : STD_LOGIC;
signal W_op_div : STD_LOGIC;
signal W_op_divu : STD_LOGIC;
signal W_op_eret : STD_LOGIC;
signal W_op_flushd : STD_LOGIC;
signal W_op_flushda : STD_LOGIC;
signal W_op_flushi : STD_LOGIC;
signal W_op_flushp : STD_LOGIC;
signal W_op_hbreak : STD_LOGIC;
signal W_op_initd : STD_LOGIC;
signal W_op_initda : STD_LOGIC;
signal W_op_initi : STD_LOGIC;
signal W_op_intr : STD_LOGIC;
signal W_op_jmp : STD_LOGIC;
signal W_op_jmpi : STD_LOGIC;
signal W_op_ldb : STD_LOGIC;
signal W_op_ldbio : STD_LOGIC;
signal W_op_ldbu : STD_LOGIC;
signal W_op_ldbuio : STD_LOGIC;
signal W_op_ldh : STD_LOGIC;
signal W_op_ldhio : STD_LOGIC;
signal W_op_ldhu : STD_LOGIC;
signal W_op_ldhuio : STD_LOGIC;
signal W_op_ldl : STD_LOGIC;
signal W_op_ldw : STD_LOGIC;
signal W_op_ldwio : STD_LOGIC;
signal W_op_mul : STD_LOGIC;
signal W_op_muli : STD_LOGIC;
signal W_op_mulxss : STD_LOGIC;
signal W_op_mulxsu : STD_LOGIC;
signal W_op_mulxuu : STD_LOGIC;
signal W_op_nextpc : STD_LOGIC;
signal W_op_nor : STD_LOGIC;
signal W_op_opx : STD_LOGIC;
signal W_op_or : STD_LOGIC;
signal W_op_orhi : STD_LOGIC;
signal W_op_ori : STD_LOGIC;
signal W_op_rdctl : STD_LOGIC;
signal W_op_rdprs : STD_LOGIC;
signal W_op_ret : STD_LOGIC;
signal W_op_rol : STD_LOGIC;
signal W_op_roli : STD_LOGIC;
signal W_op_ror : STD_LOGIC;
signal W_op_rsv02 : STD_LOGIC;
signal W_op_rsv09 : STD_LOGIC;
signal W_op_rsv10 : STD_LOGIC;
signal W_op_rsv17 : STD_LOGIC;
signal W_op_rsv18 : STD_LOGIC;
signal W_op_rsv25 : STD_LOGIC;
signal W_op_rsv26 : STD_LOGIC;
signal W_op_rsv33 : STD_LOGIC;
signal W_op_rsv34 : STD_LOGIC;
signal W_op_rsv41 : STD_LOGIC;
signal W_op_rsv42 : STD_LOGIC;
signal W_op_rsv49 : STD_LOGIC;
signal W_op_rsv57 : STD_LOGIC;
signal W_op_rsv61 : STD_LOGIC;
signal W_op_rsv62 : STD_LOGIC;
signal W_op_rsv63 : STD_LOGIC;
signal W_op_rsvx00 : STD_LOGIC;
signal W_op_rsvx10 : STD_LOGIC;
signal W_op_rsvx15 : STD_LOGIC;
signal W_op_rsvx17 : STD_LOGIC;
signal W_op_rsvx21 : STD_LOGIC;
signal W_op_rsvx25 : STD_LOGIC;
signal W_op_rsvx33 : STD_LOGIC;
signal W_op_rsvx34 : STD_LOGIC;
signal W_op_rsvx35 : STD_LOGIC;
signal W_op_rsvx42 : STD_LOGIC;
signal W_op_rsvx43 : STD_LOGIC;
signal W_op_rsvx44 : STD_LOGIC;
signal W_op_rsvx47 : STD_LOGIC;
signal W_op_rsvx50 : STD_LOGIC;
signal W_op_rsvx51 : STD_LOGIC;
signal W_op_rsvx55 : STD_LOGIC;
signal W_op_rsvx56 : STD_LOGIC;
signal W_op_rsvx60 : STD_LOGIC;
signal W_op_rsvx63 : STD_LOGIC;
signal W_op_sll : STD_LOGIC;
signal W_op_slli : STD_LOGIC;
signal W_op_sra : STD_LOGIC;
signal W_op_srai : STD_LOGIC;
signal W_op_srl : STD_LOGIC;
signal W_op_srli : STD_LOGIC;
signal W_op_stb : STD_LOGIC;
signal W_op_stbio : STD_LOGIC;
signal W_op_stc : STD_LOGIC;
signal W_op_sth : STD_LOGIC;
signal W_op_sthio : STD_LOGIC;
signal W_op_stw : STD_LOGIC;
signal W_op_stwio : STD_LOGIC;
signal W_op_sub : STD_LOGIC;
signal W_op_sync : STD_LOGIC;
signal W_op_trap : STD_LOGIC;
signal W_op_wrctl : STD_LOGIC;
signal W_op_wrprs : STD_LOGIC;
signal W_op_xor : STD_LOGIC;
signal W_op_xorhi : STD_LOGIC;
signal W_op_xori : STD_LOGIC;
signal internal_A_wr_data_filtered : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal internal_test_has_ended : STD_LOGIC;
file trace_handle : TEXT ;
begin
W_op_call <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000000")));
W_op_jmpi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000001")));
W_op_ldbu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000011")));
W_op_addi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000100")));
W_op_stb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000101")));
W_op_br <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000110")));
W_op_ldb <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000111")));
W_op_cmpgei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001000")));
W_op_ldhu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001011")));
W_op_andi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001100")));
W_op_sth <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001101")));
W_op_bge <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001110")));
W_op_ldh <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001111")));
W_op_cmplti <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010000")));
W_op_initda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010011")));
W_op_ori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010100")));
W_op_stw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010101")));
W_op_blt <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010110")));
W_op_ldw <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010111")));
W_op_cmpnei <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011000")));
W_op_flushda <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011011")));
W_op_xori <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011100")));
W_op_stc <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011101")));
W_op_bne <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011110")));
W_op_ldl <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011111")));
W_op_cmpeqi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100000")));
W_op_ldbuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100011")));
W_op_muli <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100100")));
W_op_stbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100101")));
W_op_beq <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100110")));
W_op_ldbio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100111")));
W_op_cmpgeui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101000")));
W_op_ldhuio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101011")));
W_op_andhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101100")));
W_op_sthio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101101")));
W_op_bgeu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101110")));
W_op_ldhio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101111")));
W_op_cmpltui <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110000")));
W_op_initd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110011")));
W_op_orhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110100")));
W_op_stwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110101")));
W_op_bltu <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110110")));
W_op_ldwio <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110111")));
W_op_rdprs <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111000")));
W_op_flushd <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111011")));
W_op_xorhi <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111100")));
W_op_rsv02 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000000010")));
W_op_rsv09 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001001")));
W_op_rsv10 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000001010")));
W_op_rsv17 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010001")));
W_op_rsv18 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000010010")));
W_op_rsv25 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011001")));
W_op_rsv26 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000011010")));
W_op_rsv33 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100001")));
W_op_rsv34 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000100010")));
W_op_rsv41 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101001")));
W_op_rsv42 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000101010")));
W_op_rsv49 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110001")));
W_op_rsv57 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111001")));
W_op_rsv61 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111101")));
W_op_rsv62 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111110")));
W_op_rsv63 <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111111")));
W_op_eret <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000001"))));
W_op_roli <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000010"))));
W_op_rol <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000011"))));
W_op_flushp <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000100"))));
W_op_ret <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000101"))));
W_op_nor <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000110"))));
W_op_mulxuu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000111"))));
W_op_cmpge <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001000"))));
W_op_bret <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001001"))));
W_op_ror <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001011"))));
W_op_flushi <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001100"))));
W_op_jmp <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001101"))));
W_op_and <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001110"))));
W_op_cmplt <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010000"))));
W_op_slli <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010010"))));
W_op_sll <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010011"))));
W_op_wrprs <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010100"))));
W_op_or <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010110"))));
W_op_mulxsu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010111"))));
W_op_cmpne <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011000"))));
W_op_srli <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011010"))));
W_op_srl <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011011"))));
W_op_nextpc <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011100"))));
W_op_callr <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011101"))));
W_op_xor <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011110"))));
W_op_mulxss <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011111"))));
W_op_cmpeq <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100000"))));
W_op_divu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100100"))));
W_op_div <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100101"))));
W_op_rdctl <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100110"))));
W_op_mul <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100111"))));
W_op_cmpgeu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101000"))));
W_op_initi <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101001"))));
W_op_trap <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101101"))));
W_op_wrctl <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101110"))));
W_op_cmpltu <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110000"))));
W_op_add <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110001"))));
W_op_break <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110100"))));
W_op_hbreak <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110101"))));
W_op_sync <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110110"))));
W_op_sub <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111001"))));
W_op_srai <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111010"))));
W_op_sra <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111011"))));
W_op_intr <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111101"))));
W_op_crst <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111110"))));
W_op_rsvx00 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000000000"))));
W_op_rsvx10 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001010"))));
W_op_rsvx15 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000001111"))));
W_op_rsvx17 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010001"))));
W_op_rsvx21 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000010101"))));
W_op_rsvx25 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000011001"))));
W_op_rsvx33 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100001"))));
W_op_rsvx34 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100010"))));
W_op_rsvx35 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000100011"))));
W_op_rsvx42 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101010"))));
W_op_rsvx43 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101011"))));
W_op_rsvx44 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101100"))));
W_op_rsvx47 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000101111"))));
W_op_rsvx50 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110010"))));
W_op_rsvx51 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110011"))));
W_op_rsvx55 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000110111"))));
W_op_rsvx56 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111000"))));
W_op_rsvx60 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111100"))));
W_op_rsvx63 <= W_op_opx AND to_std_logic((((std_logic_vector'("00000000000000000000000000") & (W_iw_opx)) = std_logic_vector'("00000000000000000000000000111111"))));
W_op_opx <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000111010")));
W_op_custom <= to_std_logic(((std_logic_vector'("00000000000000000000000000") & (W_iw_op)) = std_logic_vector'("00000000000000000000000000110010")));
process (clk, reset_n)
begin
if reset_n = '0' then
A_target_pcb <= std_logic_vector'("0000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(A_en) = '1' then
A_target_pcb <= M_target_pcb;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
A_mem_baddr <= std_logic_vector'("0000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(A_en) = '1' then
A_mem_baddr <= M_mem_baddr;
end if;
end if;
end process;
E_src1_eq_src2 <= to_std_logic((E_logic_result = std_logic_vector'("00000000000000000000000000000000")));
--Propagating 'X' data bits
E_add_br_to_taken_history_filtered <= E_add_br_to_taken_history_unfiltered;
--Propagating 'X' data bits
M_bht_wr_en_filtered <= M_bht_wr_en_unfiltered;
--Propagating 'X' data bits
M_bht_wr_data_filtered <= M_bht_wr_data_unfiltered;
--Propagating 'X' data bits
M_bht_ptr_filtered <= M_bht_ptr_unfiltered;
internal_test_has_ended <= std_logic'('0');
--vhdl renameroo for output signals
A_wr_data_filtered <= internal_A_wr_data_filtered;
--vhdl renameroo for output signals
test_has_ended <= internal_test_has_ended;
--synthesis translate_off
--Clearing 'X' data bits
A_wr_data_unfiltered_0_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(0))), '1','0');
internal_A_wr_data_filtered(0) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_0_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(0));
A_wr_data_unfiltered_1_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(1))), '1','0');
internal_A_wr_data_filtered(1) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_1_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(1));
A_wr_data_unfiltered_2_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(2))), '1','0');
internal_A_wr_data_filtered(2) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_2_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(2));
A_wr_data_unfiltered_3_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(3))), '1','0');
internal_A_wr_data_filtered(3) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_3_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(3));
A_wr_data_unfiltered_4_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(4))), '1','0');
internal_A_wr_data_filtered(4) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_4_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(4));
A_wr_data_unfiltered_5_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(5))), '1','0');
internal_A_wr_data_filtered(5) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_5_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(5));
A_wr_data_unfiltered_6_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(6))), '1','0');
internal_A_wr_data_filtered(6) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_6_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(6));
A_wr_data_unfiltered_7_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(7))), '1','0');
internal_A_wr_data_filtered(7) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_7_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(7));
A_wr_data_unfiltered_8_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(8))), '1','0');
internal_A_wr_data_filtered(8) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_8_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(8));
A_wr_data_unfiltered_9_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(9))), '1','0');
internal_A_wr_data_filtered(9) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_9_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(9));
A_wr_data_unfiltered_10_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(10))), '1','0');
internal_A_wr_data_filtered(10) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_10_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(10));
A_wr_data_unfiltered_11_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(11))), '1','0');
internal_A_wr_data_filtered(11) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_11_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(11));
A_wr_data_unfiltered_12_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(12))), '1','0');
internal_A_wr_data_filtered(12) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_12_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(12));
A_wr_data_unfiltered_13_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(13))), '1','0');
internal_A_wr_data_filtered(13) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_13_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(13));
A_wr_data_unfiltered_14_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(14))), '1','0');
internal_A_wr_data_filtered(14) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_14_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(14));
A_wr_data_unfiltered_15_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(15))), '1','0');
internal_A_wr_data_filtered(15) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_15_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(15));
A_wr_data_unfiltered_16_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(16))), '1','0');
internal_A_wr_data_filtered(16) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_16_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(16));
A_wr_data_unfiltered_17_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(17))), '1','0');
internal_A_wr_data_filtered(17) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_17_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(17));
A_wr_data_unfiltered_18_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(18))), '1','0');
internal_A_wr_data_filtered(18) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_18_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(18));
A_wr_data_unfiltered_19_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(19))), '1','0');
internal_A_wr_data_filtered(19) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_19_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(19));
A_wr_data_unfiltered_20_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(20))), '1','0');
internal_A_wr_data_filtered(20) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_20_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(20));
A_wr_data_unfiltered_21_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(21))), '1','0');
internal_A_wr_data_filtered(21) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_21_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(21));
A_wr_data_unfiltered_22_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(22))), '1','0');
internal_A_wr_data_filtered(22) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_22_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(22));
A_wr_data_unfiltered_23_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(23))), '1','0');
internal_A_wr_data_filtered(23) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_23_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(23));
A_wr_data_unfiltered_24_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(24))), '1','0');
internal_A_wr_data_filtered(24) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_24_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(24));
A_wr_data_unfiltered_25_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(25))), '1','0');
internal_A_wr_data_filtered(25) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_25_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(25));
A_wr_data_unfiltered_26_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(26))), '1','0');
internal_A_wr_data_filtered(26) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_26_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(26));
A_wr_data_unfiltered_27_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(27))), '1','0');
internal_A_wr_data_filtered(27) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_27_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(27));
A_wr_data_unfiltered_28_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(28))), '1','0');
internal_A_wr_data_filtered(28) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_28_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(28));
A_wr_data_unfiltered_29_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(29))), '1','0');
internal_A_wr_data_filtered(29) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_29_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(29));
A_wr_data_unfiltered_30_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(30))), '1','0');
internal_A_wr_data_filtered(30) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_30_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(30));
A_wr_data_unfiltered_31_is_x <= A_WE_StdLogic(is_x(std_ulogic(A_wr_data_unfiltered(31))), '1','0');
internal_A_wr_data_filtered(31) <= A_WE_StdLogic((std_logic'(((A_wr_data_unfiltered_31_is_x AND (A_ctrl_ld_non_bypass)))) = '1'), std_logic'('0'), A_wr_data_unfiltered(31));
process (clk)
VARIABLE write_line : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(W_wr_dst_reg)) then
write(write_line, now);
write(write_line, string'(": "));
write(write_line, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_wr_dst_reg is 'x'"));
write(output, write_line.all & CR);
deallocate (write_line);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line1 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(W_wr_dst_reg) = '1' then
if is_x(W_dst_regnum) then
write(write_line1, now);
write(write_line1, string'(": "));
write(write_line1, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_dst_regnum is 'x'"));
write(output, write_line1.all & CR);
deallocate (write_line1);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line2 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(W_valid)) then
write(write_line2, now);
write(write_line2, string'(": "));
write(write_line2, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_valid is 'x'"));
write(output, write_line2.all & CR);
deallocate (write_line2);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line3 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(W_valid) = '1' then
if is_x(W_pcb) then
write(write_line3, now);
write(write_line3, string'(": "));
write(write_line3, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_pcb is 'x'"));
write(output, write_line3.all & CR);
deallocate (write_line3);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line4 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(W_valid) = '1' then
if is_x(W_iw) then
write(write_line4, now);
write(write_line4, string'(": "));
write(write_line4, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/W_iw is 'x'"));
write(output, write_line4.all & CR);
deallocate (write_line4);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line5 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(A_en)) then
write(write_line5, now);
write(write_line5, string'(": "));
write(write_line5, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_en is 'x'"));
write(output, write_line5.all & CR);
deallocate (write_line5);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line6 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(E_valid)) then
write(write_line6, now);
write(write_line6, string'(": "));
write(write_line6, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/E_valid is 'x'"));
write(output, write_line6.all & CR);
deallocate (write_line6);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line7 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(M_valid)) then
write(write_line7, now);
write(write_line7, string'(": "));
write(write_line7, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/M_valid is 'x'"));
write(output, write_line7.all & CR);
deallocate (write_line7);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line8 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(A_valid)) then
write(write_line8, now);
write(write_line8, string'(": "));
write(write_line8, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_valid is 'x'"));
write(output, write_line8.all & CR);
deallocate (write_line8);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line9 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(((A_valid AND A_en) AND A_wr_dst_reg)) = '1' then
if is_x(A_wr_data_unfiltered) then
write(write_line9, now);
write(write_line9, string'(": "));
write(write_line9, string'("WARNING: tracking_camera_system_nios2_qsys_0_test_bench/A_wr_data_unfiltered is 'x'"));
write(output, write_line9.all & CR);
deallocate (write_line9);
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line10 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(A_status_reg) then
write(write_line10, now);
write(write_line10, string'(": "));
write(write_line10, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_status_reg is 'x'"));
write(output, write_line10.all & CR);
deallocate (write_line10);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line11 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(A_estatus_reg) then
write(write_line11, now);
write(write_line11, string'(": "));
write(write_line11, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_estatus_reg is 'x'"));
write(output, write_line11.all & CR);
deallocate (write_line11);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line12 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(A_bstatus_reg) then
write(write_line12, now);
write(write_line12, string'(": "));
write(write_line12, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/A_bstatus_reg is 'x'"));
write(output, write_line12.all & CR);
deallocate (write_line12);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line13 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(i_read)) then
write(write_line13, now);
write(write_line13, string'(": "));
write(write_line13, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_read is 'x'"));
write(output, write_line13.all & CR);
deallocate (write_line13);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line14 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(i_read) = '1' then
if is_x(i_address) then
write(write_line14, now);
write(write_line14, string'(": "));
write(write_line14, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_address is 'x'"));
write(output, write_line14.all & CR);
deallocate (write_line14);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line15 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(i_readdatavalid)) then
write(write_line15, now);
write(write_line15, string'(": "));
write(write_line15, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/i_readdatavalid is 'x'"));
write(output, write_line15.all & CR);
deallocate (write_line15);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line16 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(d_write)) then
write(write_line16, now);
write(write_line16, string'(": "));
write(write_line16, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_write is 'x'"));
write(output, write_line16.all & CR);
deallocate (write_line16);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line17 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'(d_write) = '1' then
if is_x(d_byteenable) then
write(write_line17, now);
write(write_line17, string'(": "));
write(write_line17, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_byteenable is 'x'"));
write(output, write_line17.all & CR);
deallocate (write_line17);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk, reset_n)
VARIABLE write_line18 : line;
begin
if reset_n = '0' then
elsif clk'event and clk = '1' then
if std_logic'((d_write OR d_read)) = '1' then
if is_x(d_address) then
write(write_line18, now);
write(write_line18, string'(": "));
write(write_line18, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_address is 'x'"));
write(output, write_line18.all & CR);
deallocate (write_line18);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process (clk)
VARIABLE write_line19 : line;
begin
if clk'event and clk = '1' then
if std_logic'(reset_n) = '1' then
if is_x(std_ulogic(d_read)) then
write(write_line19, now);
write(write_line19, string'(": "));
write(write_line19, string'("ERROR: tracking_camera_system_nios2_qsys_0_test_bench/d_read is 'x'"));
write(output, write_line19.all & CR);
deallocate (write_line19);
assert false report "VHDL STOP" severity failure;
end if;
end if;
end if;
end process;
process is
variable status : file_open_status; -- status for fopen
VARIABLE write_line20 : line;
VARIABLE write_line21 : line;
begin -- process
file_open(status, trace_handle, "tracking_camera_system_nios2_qsys_0.tr", WRITE_MODE);
write(write_line20, string'("version 3"));
write(trace_handle, write_line20.all & LF);
deallocate (write_line20);
write(write_line21, string'("numThreads 1"));
write(trace_handle, write_line21.all & LF);
deallocate (write_line21);
wait; -- wait forever
end process;
process (clk)
VARIABLE write_line22 : line;
begin
if clk'event and clk = '1' then
if std_logic'((((NOT reset_n OR ((A_valid AND A_en)))) AND NOT internal_test_has_ended)) = '1' then
write(write_line22, now);
write(write_line22, string'(": "));
write(write_line22, to_hex_string(NOT reset_n, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_pcb, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_op_intr, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_op_hbreak, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_iw, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(NOT ((A_op_intr OR A_op_hbreak)), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_wr_dst_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_dst_regnum, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(internal_A_wr_data_filtered, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_mem_baddr, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_st_data, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_mem_byte_en, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_cmp_result, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_target_pcb, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_status_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_estatus_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_bstatus_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_ienable_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_ipending_reg, pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(A_WE_StdLogicVector((std_logic'(A_ctrl_exception) = '1'), std_logic_vector'("00000000000000000000000000000001"), std_logic_vector'("00000000000000000000000000000000")), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(","));
write(write_line22, to_hex_string(std_logic_vector'("00000000000000000000000000000000"), pad_none));
write(write_line22, string'(""));
write(trace_handle, write_line22.all & LF);
deallocate (write_line22);
end if;
end if;
end process;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--
-- internal_A_wr_data_filtered <= A_wr_data_unfiltered;
--synthesis read_comments_as_HDL off
end europa;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2967.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n01i02967ent IS
END c02s03b01x00p02n01i02967ent;
ARCHITECTURE c02s03b01x00p02n01i02967arch OF c02s03b01x00p02n01i02967ent IS
function "not" (I1:Bit) return bit is
begin
if (I1 = '1') then
return '1';
else
return '0';
end if;
end;
BEGIN
TESTING: PROCESS
variable k : bit;
BEGIN
k := not('1');
assert NOT(k='1')
report "***PASSED TEST: c02s03b01x00p02n01i02967"
severity NOTE;
assert (k='1')
report "***FAILED TEST: c02s03b01x00p02n01i02967 - The subprogram specification of a unary operator must have only a single parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n01i02967arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2967.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n01i02967ent IS
END c02s03b01x00p02n01i02967ent;
ARCHITECTURE c02s03b01x00p02n01i02967arch OF c02s03b01x00p02n01i02967ent IS
function "not" (I1:Bit) return bit is
begin
if (I1 = '1') then
return '1';
else
return '0';
end if;
end;
BEGIN
TESTING: PROCESS
variable k : bit;
BEGIN
k := not('1');
assert NOT(k='1')
report "***PASSED TEST: c02s03b01x00p02n01i02967"
severity NOTE;
assert (k='1')
report "***FAILED TEST: c02s03b01x00p02n01i02967 - The subprogram specification of a unary operator must have only a single parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n01i02967arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2967.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n01i02967ent IS
END c02s03b01x00p02n01i02967ent;
ARCHITECTURE c02s03b01x00p02n01i02967arch OF c02s03b01x00p02n01i02967ent IS
function "not" (I1:Bit) return bit is
begin
if (I1 = '1') then
return '1';
else
return '0';
end if;
end;
BEGIN
TESTING: PROCESS
variable k : bit;
BEGIN
k := not('1');
assert NOT(k='1')
report "***PASSED TEST: c02s03b01x00p02n01i02967"
severity NOTE;
assert (k='1')
report "***FAILED TEST: c02s03b01x00p02n01i02967 - The subprogram specification of a unary operator must have only a single parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n01i02967arch;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Local package
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library bitvis_vip_axi;
use bitvis_vip_axi.vvc_cmd_pkg.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library work;
use work.axi_bfm_pkg.all;
package local_pkg is
function result_to_string(
constant value : in t_vvc_result
) return string;
end package local_pkg;
package body local_pkg is
function result_to_string(
constant value : in t_vvc_result
) return string is
variable v_line : line;
variable v_return_string : string(1 to 1000);
variable v_string_length : integer;
begin
-- Limiting output to the first four elements in the result queue
write(v_line, LF & "RID: " & to_string(value.rid, HEX, SKIP_LEADING_0, INCL_RADIX));
for i in 0 to minimum(value.len, 3) loop
write(v_line, LF &
"RDATA(" & to_string(i) & "): " & to_string(value.rdata(i), HEX, SKIP_LEADING_0, INCL_RADIX) &
", RRESP(" & to_string(i) & "): " & t_xresp'image(value.rresp(i)) &
", RUSER(" & to_string(i) & "): " & to_string(value.ruser(i), HEX, SKIP_LEADING_0, INCL_RADIX));
end loop;
write(v_line, LF);
if value.len > 3 then
write(v_line, LF & "Truncated remaining result..");
end if;
v_string_length := v_line.all'length;
v_return_string(1 to v_string_length) := v_line.all;
deallocate(v_line);
return v_return_string(1 to v_string_length);
end function;
end package body local_pkg;
------------------------------------------------------------------------------------------
-- axi_sb_pkg
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library bitvis_vip_axi;
use bitvis_vip_axi.vvc_cmd_pkg.all;
library work;
use work.local_pkg.all;
library bitvis_vip_scoreboard;
package axi_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map (t_element => t_vvc_result,
element_match => "=",
to_string_element => result_to_string);
|
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DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
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axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
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|
`protect begin_protected
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HtvhoBS/yl8ATg==
`protect end_protected
|
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