content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cAZfbJbxwjkIXnt0bJyva9of1AojvzxdZR74a+t/8iGNd99Lj7acNp4k9krlNKfNvFBYNMGBR5tx
DRVRf6gVgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Un4ycyHGzVNVexSDCBWvq0p4lhja4DvKHfWBGF0Uu7w/Pks4PoRbk8cXtnFAB1Pioau/nQOrvQdZ
nEDffbN5jVT7tGq5V+79v6LGK/Be39hSdHcq15TKxgIzZccr/E18qXDe4E9zOhSfr+WAVg49Vt4G
axAn73BUJxcBfGDDWws=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RRg0g6rLOCYucCBR3QsFXhbrDQmC2wa7jjh7DvoW5DorScLf2iefnQOkTrPsh8GhtB/X0vhLR//8
JlNiJRrBNjYJe5M4e/Tb8T86dMUDotVCu++Ke1WyZhuT4uVrtalHGWj9hYx/RHJxMAx9wurekcFA
O4s2R95BI+ETLlAoDcdIMuvVpKxtYkWRKNjnv8ZTe2bYFw6zT59BC7UGG92bdcRcAQ8ATLeFS6hF
5k73fXgHFygOW3UK72PTsALcYXCVHg1OKmwTYdiQuDrDf2gaKM0yx8BfzSoMO2UknUQWT2RvT+3n
y9LAMlZ9SvcVzpJJn8BzSWAXa5Q3ZMGrpNtNnA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
vpdJpFPqAja3WYud20cYuVlO1bstNxAtRtBuZbtNXc405vKpxGXS14Xh4xlHOkiiOUchFi0AQxXS
JUNO5p0L4mnlrQ557uG8BtOElMvYlE0sHwTZDZi6b4tomlUFqWRU54jHtgSW3/Nw1+Xj8iIYdjmo
DitJ7YGxGqLkSXbWnVE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NYsTDLIE7fMQgciRSzfZiuy1nC0Cj9jDYeyjGWOu/diRn0bszRWzknE3BsHO8bvnC8V5OqLk5HKB
MrKH3SZWJsAsn/RoEm6+rG7L9dd5EEA/vmw8MM+yCkc/PRxk2zhAU25TpHNcKkhWioHxEnBOQ3nv
erFqmPjsPm+V47a1M7eN3nme2Oh2RyIbVIxbVdoiRJ4L47sTW7cMXBu4ZCDhMbXXRzJD5EEN1GY2
1LFBJkM1xAC/RkA35INmTdzsxidjaTKsylikAiZN9HEif13bTwdpULWCUy+DKz634TgFZeRUBmoK
aCqtBHNq5oRwACA2h+29Oc4MDikc4GsXlXeC3w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
m6YsX2wZKJsid7xAZQSxSLgPlxQelCBemgfjpir5DqIwvllxTFFW54S1M/vEkxHmpGNOtv5GYRIX
BjTVRJ/tU++PJDqygjzKT3E6HWB5gu2xZ3cBYfSVQwWbEquVCGpqKyL9/JywljOZTWk34Rb6SdAZ
GD2nllx1WFPrIDkpOeLidHAwtIc2QB9Dclq4F9HnDeqmWQC26zURh373TRpGIWTH+3E37xewWE4T
zinr2Cwbq4pyl5pKx66yXdHDV8u2oQidy/ICcRHyqJeuhNYMa1Znu9WBzs7zltFvfrNPI8g7fpWK
p+lFPworCFdMZEvEls2jK6xTYpokVng64HfIpSwgtLZE3QDYAmaaEOYY1OI9kZxiYPZGJx94Ltp7
O5CNMVUAg/HVCy3dOJMlakKHMKgoAt9wd1eWY0AnMaisSldmLZvukuqNmNoaljLCoSnkbMNsiATq
+y1QUP8/rfOf3WkxtC+hYBot9fluLREtDkoS14iiEAbTdxOI4E6Esr/+MiFAmJCZkn7s8e/tVvpj
qpwOCQl7BPAhSFt0fkByckB3Udh0J7oHM4S38KuHVR8cB45w7klNoo3Fbnhdv2AGBZeuKX6d8Dt2
SVdMLD2wLMfvOqIYTgRNZtbu+B6CXH+fB3hnih/t2ZKkhDr7iZpKhwtNLmX3vwkZJfIc38ZE7syF
CNveFu4UlVgwQ33GsJke7jDpbyNrp1d5Osr1i9YIFBPjgOFWn/u3GFA2wyWlmJ1f/jF0FUEHU69Z
yjsbRiqVNhPScrCHMzwbeHoKhHsMfmGhqN1BHrbWtICztyrQgpul8csXFEM6bCQCWRl25wCYlY9U
BI1amU4Y5h7QzND9YyWE4lQcmgefpv+e8q5h2/uEqAAyqgoDxM3eHkQokgWhkj+b0rqDRhKqliLy
VsbT+hQ/090BuMlbBRwsprzw6OX5pXdsjRlYHVXPsNwq/Fx1BT5GUGDDLcIzxBPRtk3HRVu+fhX3
kVLSYj77GuPcQuqpDZ5eEgXXM5xzCG4WwCIQ45ZWKb4EMWIXsnKpC+Y5tOtyYMqM+3wSxwhYL4q1
Fn4HGvrCDDlsQLAJnMvXr+LG7oHFIhLRDdy5dyBj9WddKCsRwVpxcJY649CY582qOyc1hO6lziSR
vc498Aw5y/cMKflbPfCjiRWJCqWeQT6n6yL+7pz7LrMPbdfq6gphdoN/TRusVMGCeGUDv9hJsw/b
DPfw+b0Fb1xFR440/jPy2Opc6PJydfLDk0PMq/RSfmt3BCxPCmoS2B2kwhbDOnDIFDfBEGjP3GVu
m1LgENWMhDKjw4eLkX9emRfxdUTfpFiNoapPrJ5XL1WDCHrOy8shK/T4aJ2s4SZ6WHRj6k45o5jy
58vqlPr+xjt/tXOLQDv7F+nNZDdK2Trl3ql0ibSXDF7j99pqaHYCmraGep03KDs7sFlBZ3AwXQLy
GxseX+MX5ahUOiHi+q803X7Ue/QyODVKjV+jFpXWAurZqHnrA7x+keHrS0yjNMiJiEUDA+41V2x+
5uPZFfiga7/n4g8hIgL1IBB6ZQ2juBqgOieXu7j2zbHLsfZCzOnrkwpCDNQAbX+bMq5ezWGgxyNG
cyBt7v3U0ojc/KcBMRQt8MT3GV/FPsQ1cqijMd3nmpJYRObCtn8Avu3+toZJHXgYXX6Ji7t+SKZs
MYIwcErSDku5Fz9IqJege4sVDsVHza0QJonaF5CkNSWcrU+5JlK39sSGZz5nwE6feBef8wAky/Yv
hqYDpUXBtz0ym0gjfv74Bav8OC0QFlUd/j8AQh0jwqVIPeNxdw7bBVDBmNH/tmdHj9PcwYPlnLX6
Vna+LYuKY71dsZB3+XFNCQLvDBZPfyRANpZF9DIyOVcL2zlfMrTdExFMGmhIsTb76jomkq3Q/MmF
V3U2KS4HNG4Ytc8LNEGs0vfpYxAHYM3q0w6mNT0nxPPSXlu8gFFYbfGuj+JuiVD32cPSQkAZf74P
6T0suBjptiRY4qnpPWp6uBl9pg5iMsEM0CBClgahCEJRPHCalhdz2yorqea3z6fVdraouaJTDe21
2wIdX1ZtntjkNqxBl0PDgSzjsWGDy4cPdRj7sI1+Lx7n/XA2mLEZ92qh5FHMNGnlLpz9pYV72bk9
yRhDKR6uC4L63OrFxbPWWBf0CxGDNpWQSzjYhX/cqAGGzWqB075b8CHMRN0mNVQjlLQEtFrMPbKW
ckY8fNarba4DQFou+iPZDsWpMQYtM0enUk/RvRbfoGxbNuX1qsnspTCb/8k6ttOAZ6VgnXJNa9+q
39iugMX3dMs8ADK1yzlJMyK3t7pLQF6NvQ5buwTdRhszbbjjSJLJxio46eOvxVpt2zc1oLAFHg1A
M9ithdlo4JKb4BpNNp2uck8EKKbfbUZhdWJPAhMqXFv2qbTYDlxA4B4+XSiiB5BnKkfg+cOmWVfO
F/TL0IggE81lfhkzwVk6mskbBQ4vFw/kNprpT0LYjp+DuzPJfkfAzw23aaVogqtoD/4VaWbnivp8
wdfLaEuClw1ZKKuSmWXhZPhJd9T8jq0Gic2vgSAeRYeobrAsYMAdSkRT55/tXEVHlSNmW5nFf16R
lycRdQNypkh7xO5zLtpWV0dWZIewzvnQczdaKbEtyVqtLU1XN73BVObIG3D/sASgVR0LqgE+hN3o
DKDITa1WDnWqa8hJ6cH9yS+t2YLVNBm3lyCNdzi6+lQ9wnu1c4IhQQ4M+iO0hHcteMcV+DfSxN9b
AElOoudQxa9EMlUP+ibkgEcwVQDY3bj/jUl6qwOJVP/qhrJkqhncZV7bavRrrduRGcNnz20uU95w
2mYTTRwAVrlH950MONSlL0JtUYxw1kl2Im+RMU15nIGTBDKm+ZCG6eip250Y5V5h7B+4dOKtF8or
HLCtbOQS86S0ort5xvdzp+hRizE6jC6MtAREarOCKq/fr9INA9h8qka3WaryqNZD2U0kb7EaIgjC
AQEEtIjzPcp25fn5qv4hZaB7kbZSNYVhMNXTKgsm5So6opjzEg3vKCkSZDsq0wzPvtxg6rywFKre
Bwo2sziOoQrQMNBdEwvX2PwBoDQz0LbUMJxxOiiGSaWr+0GPfizbkopa0cdL6qySWIOnVtov5Sfq
emyIE3/DBOKck85tJyL8nWIVb4OHcz6uX+HkH0c8cRDgC9z4YKIMMPZZYQlqL/lg9olVAcH2TqGQ
075E3IqQfrqnBovVZpruSxuGVWllRFKkmm2cRofliZO0LAhu8vEyzINLsNt+98gnxILUA1SdaRaV
gCRIlBKmMCYWs7ZDzi3yBBABmNd14c8CO+SMkAwrlWONECn8ZqWxoqhs11COw/60y/pypYTYshoN
Dm4vLxuK2z1k6CE75oHbnhtyUI1PMGZynWTLQk7QaSJgSYyEPhITddvEHq4RbLZ+rpxi+aFsdCkB
rnFFFWONvkApAUIsxDWaUqhhCGR87q9pbVW4Ri9OOlaCxpDms7z4LlDIiEVQXEbn9G1n/UB+8vNW
EgM4iUbtYNU0ztS7zLeQ7cYv3X4hq1lINB3PQd7UDgqR6xONQEwvP3ERiSyPnl+czs5ZLocCdqzU
PhjNCBk04hNADOVBKWKvpJHtBfb7CZPCNgSRMy/++Joi+lQwfIz0EK2VCQXhs1xxa361SS57k6Uc
Q4OjTyBl/jdj1dWhsAbQzh8O1hUMku0CNpOmxglufIaVQCPq3zeJxBIQzjmya4GkdgtLYrJhMrF5
3OFCAvQPR7TGxKl7qhrH6ByuVkcnrQEFatBEMuRVjmIOvFO9AXaH5ijvg/AQ1EB14LGX8Lc0ZZdN
hZ4FMryi1o9T/dleBdlzvGB/cmBhSakLE9n9UiCeCsOJU/vgn/qGGuxzYaPWWV9F5jA6rKBt+x1w
ZfPYgw5R9fTxHmQDnF01CW0SdJQjZTaLVdmTotKiM/LBHLP8FuUSdESw151I090/7u3qbt9DP/Lr
KxlCdExvSg6nNnr6ulaKnV35ckWxcotDxUr6Er9Zg6yut2AJAClmwG+ewFlLffbTJQVoHS3fmsb0
9zy6ULBN4Ua6bH48f5+XQWvvF9WgX6KTvLcwWJPrepjnE4m71lINGlMfyryAV5Y43K8WkuYNEBZT
hIlhuukoLMIQhYt4ZgW2t0RO1YeL7MpYqrOgAFDvnkD1HR0YM2V7/m0GQGvfwDQS1kBKK6EPZjSX
B/S5WHtODjsoBKB8aUcTP9CebCcJtVYH8Bpzi4gSgE/bQYFEI/Z0vniUzalUfKzkal42tE3XqAzS
6Afn+ihh2dkO89QXdWPi9mjCT3ezUdcI5XswFopgI8c+BRfCxt2c4HTNhGQSL+PguzWBw01RqMKC
YRlALr3QycC/lRP5Lfv9Ww2fcNb5EPMc6qEkOU/dq09jbtODSOVd3JJxEMv1g94a21mCXCNRNjMK
Q3d/BZxD86IWXyIMqZal3ZUt6QzeHmAxrlPEpAqYdRKgBarkj9+B5CEtVdCiD68b35hvASqvcR9w
/MgNLNch+CJCoLeuzbJHZMK1TexXI8X/4o4Pc2k33BQEmgUsSBkkscTmIlaVTolra1HgK6GniTnX
Hoebnvbe7fu5feaW4f0PVlCoXBHgwyIb8CoT81P8TouBdTaqVDHK9Lfdjs/beY4jWaS7rYlA7Sjt
wg9mJ+5NRiTqPH0cQpM4IwIMdxpS567NLgdBRLc4V50XJjp3oAFLwFB9TTzQUTInw12uNIGnpl6f
Ey5+lmQRr6univkGLjiehoEAIQzA6LhaBA8JdtODuwGn94FQJlSpB4tAPJMT+I+FJ+nz1uQy+Yl0
T/QeD+Hvctmn4ialcdX2YwpnMw6fA3q+j00zrt+woZsnMkGoE2wyKfyL/gcKY4NYHzJzSY5Xup/W
cFsqQENafc3N5G32hs3eN9ZmNDc/2lMjr8oyNHMPqLoJ3XSNQwgBc0YhUEUZiUpSex9Av8bS9uP/
OhWvzsLBqBcn52L2jW9ZKtXxXXy7wOG1FO3eQVuKyEfZhyULIXTBfptw2FZ17Pr51nv2gLmYJ3JC
tsOSAvTIfXI2pGjD1NPvnCss0KIyOGzTQbgucEkBkGTDLaEgIcWIESkr7SvB20bsqF4w7oE4evlc
8WgCAEEn6fwjvWDphgcQc2n+008sEGgAR/ClsiBmoegPEzhYjNFrSdfIZ+qqe897QHP+XnN1SHnr
2uXiicz901bEhQflZ/WQKd1W3e6TESiEYmFDLYNaLd+5I4/a9Pp9u1JHRXWpQnL5jpupEg3sI3nG
waIcmS/Z65GIhpStUl58yDNSDDyV2UT1UyI+aPZkuPlH2O1OhMcpNz+tb7wncOEffJsrEOqj6Kns
q//4bh97rKB+1nj5gMxFILZunOg9o0Vve/D4QQfdQDXahQtOVcBuFWQ9f9+VXm/AqTdAjbmlasnK
z+6LuIzh/C6RpkY3JD4xeNCjChzlMH2rR9B/Uy1dYWCKsI3hoB1ACY5paPhcEfInq9xpGGiBVPJx
SDgmZn7DnexU2zwGECr8hYqcp2sZ4QCL59IC1IdF3ZtCJsoU5eGUNDIxIEufvNQHFV0HAwjZQ01T
cMdSBYSLaV53ONe0QSEpTYmuoZ4hOOvF0x1/WvRcbpjkyBwdwn5thuPdN0N//oJze4hNJMfmE6pc
QmaDfbKGLvcjAD/9Tp/t+dYSeZh4rl0bl0b/XqFlGAAuoIsRIrvSEegAU+KLpSUSRwju36pjQcgl
/7ifSLjN3zXHEzpykNNc+eFTqHAJWLb7PZ8wuYfNlLJGAu+7s6FzBwheZtWkxKA4NZMKaV+U33z9
6H9+L6pnSDQx57sFTYNNHRenxAxT0khkRz30rtiHt66S8FiD/a6CFaffGnqj/urMDMcB//QOCwbw
Yj0GGlRiZO+Jf/luGkip1x3MBauQTXYAL+KZTJxEGUfsh6jEPydL63TnXEHTTm8OfO2WplWcXF30
3LeHwzhp6kSUaj6rSQohqE4a7kGa9pEJ9r5XnJcrAY3FR4h47hVGmCEazb6/syeGMFN4b4KxToSX
AayxWN/aMin2wBPfyI3V1BD2xtZX0SgNvo0ElnxjMTU7dyQAiWtm3F96CkC6ivD9KQ1E+i7DsJq8
30pMfXU1GLuUzSHLo/Y7samSGcjjABFJ+k8GUyK+N8k3cpiK7+Kc2rVZP3B2DmTO1RK5a6/TuEPy
NiZlfDyE1WC3/iXA4c3iijh2qIzq9iS9z+yBtoy3Z3rsqKWSuqleUyfUBY/osl2lPYHzW3Lx6nP8
bgP+oaYrQZ7HxtaIJ+G5tmEVLJMXLGiXHU1TQbvsqlkOxbriPNzU4za0LH48WqYuDtmjmqJGzFH8
6kBhAXMnPi44l735rqBPhWTpr5hIlv6I087Q0W7m2ryqM5AAAHJruyMWi+/V30YUEXn1A0C7BBVY
VQpwAAfOOWBxUEYd1jFMViSf1Adiwe+Gm9AGyJNkROzs+n26m4mtwklenSdzPa8JDMrdXBB+AF+d
/7nGo9VD+uJS/9e0P1fnf8ySzYEE/EQPQvujK4Un4lWlVsUC9K5LErEif/3Gmi7Y3UL96oL8N8Z9
XWXd7IIb1fYFHf8d12vOxnS14wJ8YMzFYzwwmW49e039QDQlv6U06tdrDYHN1iZySIOE69CAAzyI
YnmOS0ejX5CZ8mLZd2HdBVbxd4/wstuDyjJEMNwDNyxiQW/amI10lyjoC+DkHBmktU/BrVmJ22/g
yxJ9Ld2tYf2QdiTbsV/HYCq4gPaL5cvyl4uPYdQVQMspI6OauzI4XZXZv6P2xbhZRWtDligBQgGa
ZR+NWHuCVphOik+JrnJv+fZdGhh+qzOLvXofa/46bLio9YzYcNZv1w6BSXtzV1sljIA0dUjLWmc2
zxv1sLcKdj4eF3IWlhg/pW9EpD5MTIuvxrIS02aI/aa9smgftpHiv9ZahpC5GazuU2nmK7ALfbeT
XXLEY1QpBwyTUvJFogZ/5JJiF/+wsG2pI+8Vt0B18vOSsH3uTjU7PLdU6pzq+0w3Bf2tFTu71Q8D
1BbK9VNdzZHMLktTgBZpMu8u5mWlHGLP0hIiAjGi8bHFqkDoJMkA1qa/AU6Oq3AjAmkEtdx/1Zqi
pHKvEuw8LSgxfoZhaD8cNrWqBJE/usDNfnHtuiM21XyaA1CcEn3gYI887bXh1d5piY1SppuNly1r
ebPKCGhok4nreI8o9xRElWSAwfrJ9ie7m0KCLzLgtIL3FhAMeLIPEj+jjkjirURV+lMoy2CiaeiE
jG0nPZG9OoJjKj6Uqj7wZ+qcWYkJpU66CwKA5wgACzWX72ZNddLFTkklc2BKx6fwtR4LY5PXmdpp
QFrsi7TsvQEtmGgSAEG76AnVzCg+L6XVpExHs+lXT4XG7D5BkuiuCuDS6r88YCvfSnJ2mdTy7QcZ
O1eiVLP9xKKUXzrCRr24qcTCSiy81lF8ZqTQP7VgsyESGR1nVfhWQjIb1vKo3RBh/gYOnlzHWIM3
B6OQaW9CK8zUtW4eCy7FCf5TGzgWSr6A0nWuljCYLPuY9ezdSh6Kve5G32OSNTPXfph3wY4ulCmb
aaTBlmtJ6NbYUz8gjKuntqLMajXrTTSYnS1K20JkuZAzAFbR64CpYlwBoqos13YCHsA9V5Y73mZl
6fzxzb2sB+sZ4yNuWD4XYLFwUcnd211ax33HIQZ+z1EOm4UvM+yEWEBbJYGNTU9VvXaMDRqGZYfD
BEzBu1C0x1gPvi13YDFFGIPMhoEvKvRUUUVmfVqN1t47i0CMQh0Jtju38dRV2d6I3JOGnh18WenT
JW6kXyXFszsCOlkFPcJ8l6DeJ9MZWTW5wgufSPSiitxdVMGivzLQYiIE4SEZtcC54ho2bB9v+KiH
n2TX9Qamzfg8V+3ttCbQZjNAcBBKbyhIRA+gEra0PYPzxETi0jQaNorzpmmciGBMGT2se89vgFeX
krF4D0pSAJeal5PGXTemXjL1xLLW+zE9D5UL4FqkJBHVplJ+dD/k9hyp3QVlSbA01ZiI2AHZ9yDe
ZvFFbqrMOPTfMDXmDT5fjfKtqio1AU+BDP7Jkhw7yFT3CTRFF+febIw9LxT38i45Y3Bd+RhPLJFy
CysCzLEueV9jQR8vEGBfGmXXziC4N5Gcfl4daPuAGlaMSwoFj0KUpuajST5UMTnMQ/AtWdLMKYZj
8xUsyH6wl8/T/zc2hjR1ASwZp+IepxVdO/BvXdrTaMXjWNm1Y65pCIb1UZWgJ7t0kSakDPYAGY6v
aSdmXZ+r6ocmOLyJtjjBU6gNzumXihNQ9vASTk5hAvqeN318r9FCJh9yiFed8OjLC4zxlBa/u7b5
AyvAtvtOXNOkS4cRJzz7EM7l6nIDlDRKXJrg4PxuHAzEs5Km7bg5x2HxmVe2drGyF+aIPBpy3tDo
ryfimkOZ9Z/SUe+Wg5XtInMd9HcaD/cAGLNwfuNMJWD1dZ46k0jwxS7/IWFQ1Hu4b3X8yuSa18We
Ny3F0n65eZP+bNf1PXjajnv5DvM+kCn50Y6/nlmjH9QJslV1JICErpoyqxhuyt90ZLK96vvKoH+8
t1tqqn2mtndqhBgOsYRYGzi2qGLws0CIqGrmpnamOqiaaV6MPzWjXNn4KGsC0QjeWNAf/h1MQsAG
+iXN+jVLWzKnrURP8wzXfUWWt0Z2GQHmE+VHXkuG7fixRgCtnnpCkts1kU0u3KDG0wcLnvzOMdlQ
ygyMeKHNg34lEYBFr6PJZKrw7SeOyHvF1yNg2zisDm6jZikxJud/UDXIwLQCZvkle1bghL3FbzfT
6dOJFJVp5/GdWeVUs9EwsFOnlrBuJwjG/K3XaTG4DdztoMORNzHnvZ1+ww+48L49H4NYTdZwI+B3
KHkREenBjmILp5E3AMVaIOFihWo+Yop6VPF8ypUUmghSsGItj4IQ/R8DcnsB9ZxWW27OCxB96puM
eFZjrpUru7aSd81qpDivTvbFFHIy7nocfXtuj9U0XUrfNly7WvInouXVJX2Wb4B64wO24OrpmCLV
arHeysz6tq/8Uoz5xv9GSFQm1uxwAUHOHeKfuHoLGxpMLx//GWK1ICABXzUjJqtKpCD9p/d9Ska0
avdFMmSXkRk44imIovnurmyESK54O3lXpA/dHhj2n0Av3QUo6n6jYosxh9nKL1SXpOaPCndJNPdz
/vzbGj0EOtXZnNJy7bDItl4FsDn/A2jRaNzTD/heQ/+VJdnkxW6NI+8Z8hcOzSYYuGP7826iXWKv
XkET1E0U+hAGMD7/Bhli/ZssY7K03RMZ9bGXq6V+RXXbjMkKqaCGavLw7mOzIQSNhaAfm24I9BxE
DyNl0sr+S7gM6ajtIdNkD+yjC++zKIlYJBv83RLPBK31hSip8DbmqRVUcjbIE2qrTl69OVhhhHnN
I4aK6o8kQN/W3KD82EEL1lHD8deSQxsz+USJhkjB0+phX9kFQtqEGjE7REs9u50XJb5fz2OPxeeT
zTksC1Xo6Rlmbpd+5IVPmHP4eGPwBvjrPkvn8R2LbylMFniIYPLZt00Yu2lxMKnF9sdpPibZTHWd
P00RqHs15oOyxWP5fhlzD+MvLilDkHM6h5mzQT01LX70AD1nac7BjK4g7ZNCR3P1SDq1/z+i5gT6
VuuYOanDOG8k3WsdOuYs7+2+UrItvT3EBCZL5Tv+uol+bRG4HKMnFYpkwAW8SrbsS7nRxIoyCu3t
FJY1WWcGXkzdto65KyIN0c6uGYvOY3hSob7A2IiEbghSXEKWF4EXCUdB58ns3hCy54Wo2/4F6nwb
MXDEKMvyVBl4t33vs+r83NyD3K0m+TmB/cScNRW2RUr8Vvk0ybw4m4NZuDxxxXVt3oAhbY/SvWxT
iUMJ6MZUoRas67n5u1OcFB5FKuoWuK8Bw4c9A9B4AxQcEHPnOasTBxTbbmNlysWsBYov2ni0XwUE
7aYj7mzLT7WYeKpbUVSgPoki/y0rQJkgNDlQO9roJONM11oJAJsnsOUh/MjvALsjg5YsAO64Ee0k
cUakGXyhz3uIAEToM+DgLoJs+ISNMq6njJEYWdP3v6fo4finYxeJ5S4wmz5ieG09mZp12O7jQ4nS
Ny7KvUbP2Rqe2DiuIrGYAosUmwVJVwgft/giOzTC1dH3wUfuy++pBGIIQwfuU/Hp3Ns7Tg+ptrdk
EQpf1HdpRZaRlpCbLb3WRDpza2dYa4+VGtwo6z3IJEZQmzfehW3jENbmvMDD4SE4deCE1HG0SE/r
O63nwJ0IE+OaQTHyo2GUiq1gFlMzZ1g5/orJxBv4IKFfqrqR5L3R21XSrlydqAbo3pVHAyUyliE0
OAgqu5I8FmggKU2AIGnq+4yhOEJXG28oWb1O4JiNH8xLX1tggUerKKeEG+dBRSW+jDlku9AROEzQ
JT1ZmqmGv7FLSzZNOWQViq07sX9Aj+gCp9ZBPAcDZZHqScaBkS1ARlcTFuwP1cfumA6GW4j1ZQ83
4rXIXiPna5UzFiVOFNZ2CWYuMkRRsnxc1JF6g1qpz1z82aOuHC+xCA0XFgumL17LvqQRgKNZeWdX
LSCVVz4WqZHxOVVpY/9Pcya5rQeB3eEUprmD8WkTuUnL4Hf+ffLBLclBaFJBIisPCsswKbrNP49+
RNmPgZW9pf/Bk5vc+AUat+aEsIxAp3z3hMWsZkJUyLVCvzN3x+7cnz8rqMPqv2nF+rihllEMgmUC
0Uy8PjETOR02IliPlq4vWUAsKE0XNo3BjRePVXevfkGz1Ves74Lb+gL89YxxyAoGqQs6qd5vjr0Q
5bXVzkJ5FrvgusFg3E09FBrsLxo9WX/WtrpwIqAQvTw5oh0EZcHlm/2XKztKDcGzjw9fjSOxaUH7
3mnq/KLO1EmBVQvTqfvmRN1lpDRRMF40GESF1EB6IRbSZjaf+bzV+HjiOPN1BEfzkx9BhBIg4k/E
AaOs8DzKnZriQF/aUuMHg9R1OCpcyR9dIHC5H36YxH4rhijfV/3ptUeofXABaflaGU9mC29Sc6kT
IMxVHVmNp9GZc+R2UsBExMlpFI2aX7JjMeltkmqfKTrlTno/0u0FYDnd2ncbrYd33chHLhsfF7FU
vkAWhxB2GgpbggJZ6/8ygq2i3pYLaIhLiOfHHTcritUH6hdCDZ1D1Xz9JwTOQCZZ3W+rEPxq5ACn
R1zWAJxphIhQbj7WMzxPUowBcF7pU0rs7QhFeT1C0UA+IOzmRDJkF5BspiDOUwn44S98js1lc4os
5KSC0S0RgTIvXOBr2I1GaENYLWAfJH6hQImPNLIQ7l4k5XmivbXYEbvBrD8rvg3y6LoF8CgjOZSC
nFor2I32qpTZfaGPzkuzG/13X+gSjgoRpxR+KDcgCgnfJKm+alBGOLhxRiHcP7K4R2U8pv3ICu9y
PmHamCODJRitWIGkHPjCl6uNX8wWllZ5dK6dfv8kDXpTgTZoAXuPUnZXWgv5tdfz7qQ04Tp5D9Jk
yItx4i9xkEUfiirwV86nfRHimCOWdQgpff3/YytkzK3+I0K8ap5a0gKLwTVDbkKgKucJX2tk3geP
DJWjcH31KBuJ9Qrae1akKXq/xkzsVzkUISjx+JNhZkmeiAxx0xesaeWlfCzo1B6SihdQf99LFpnJ
i8cdzuDCXd8P7bGVQ+PiT/rt7IZnGYAAJ/XzvCDeCq1fFM+kmKzikmGWMrIheaPA4N55wXMNMMyK
ekVrBm0c/Gqgg91QUPLh9V238jyVXyC+qUownxdkvmmO7jDCyYEsIybZrUJHKKuZiy1o8r0UlIs6
+7HFtvoVFS6RQ3pkQ43JBSFRIaCK0iUlAiMa5YTMB7yBCVXO3zD0kDlZfnGFpYI56lYWLU+AZnMq
f+zxzhhuaw9E1ZefGSOjYbyxAOh3cw31Z9gIInyL/RgZvv4kxBtcm1Ov9eqY8Fr25PqTw7cU4rCq
Ku5wBKms/dmAMXbfi6kKvc/lHLr7teRdQmI4vAEb8ouJhgFGbHqCCVQHG7/K56lJBExwHG+FAdhh
rqrIO8UY6iF2KgclYETUFybLkjbsO7g+hUX/7IkW+SbKd7/kLmhkcKq+RQWhYkcBqsqcnp4Y/cRj
N+3RwaMOpJvIEfsVdf+fk+p2rNlzv/pTR0cjE+VEA0/njeHKxVYZ2e1WM9+3Ss53+dFj9KYQ6rHF
Otr4x5bWAQ2vJ6iUhjttKyOo2DAbe1YQjdvzwIGAbSxRf3rJwxW7vE8dTSc5oeU4sMMCoRBuGgc1
fSz+9C6c/wQ8KoY/xRZ0hOGx3qe1fB9hYt1ltHPVgV2YCKHZwAG/avbXkQ2PNtxUZksf1cuHFhBR
t7rl7P2V4v8D0p/KX7ccN6hzQ5iqJOo5DuP/B/+kxyZyCwzCP5ffzbK+KnRNIIvXQzZkfLVJWDfA
6lRBd8/ZgR870PBbTPwPAUg6qTEI34E1j61WVqp4fAhzhsWOvRjIBbseqIxIz/rP/0w78u8KJMvg
Vm4Q5rkY8UhQ6yHoOEd68AEspEFbYLEB+VzKyzPNQIL6dGQOEYmjQ7WbMeB8ZkMwXB3Lm7lVDrtb
jlpwSSPEWFo4v0ai7XXtxGPha//tCTIupjViqgMtR/LlqrOM1b6wTzRTbGpTOqweTYgQtIo1lkmp
s9VoUKlfj0EFq3G5lLMOmxKymJ09UDBolht3pdOE7yBNTvvopSJue/nHFnqLiDQJporgMmykTsth
l4o5LpoUwh2UikgiJmB1N1qjH7xIctX9m2Ex0dZjZfI+TM/Us9ENMOF+LdiSHsga3g0di8NAlWaz
CX6noyk+VWsAaIZNvFA3gOB1dVoGWXcjCNV198TLSvrewitD2pGJvwKLxdI7biSjGi4dbidWT/BF
P+XtonM/j1d+peNOsKmRuRtWwMM0mejIkB+spIRAKS3xbcmsM54WVhhfe1C6IebnoNup2YzkEnKX
rYPlUwy39bjW3j5GSbJf++oSbKWtAUSzG34g+IBroZywjAiQta/qzF3zUhi8bzL7SV4WENay8zwP
3gl/oK1Px9JdlyNeuBRwV9mfGkuPxIO3LHzD17cVBSQXkC+v1cH74Q2+ZGs/9lSQFjTSVOZSNiIo
BvCKEEq5nC76wVyX29UutaIoJDEjcbzb2MK/YrmCGf9vjUVgPhsq+mTxs8pLJs9JAYTfM9r86L85
4fK/O07TCn7pHtVqefVdaaETUlmQF0ZLgYjZ+uc9R8DYUGy7icuZ71qArSKWNLg5Ay/Fz+HBAtSa
TDA6a1vLdcF5E9ekEIhy2Ycir8F8ewBzhQeKaFrChM76wuvGpTC7qjCidsHCv4OXrzFwWldi3J55
DxXG1vYg0oRc6C415Z8nzCAiCrSbLdUScVFM4rcL6A6NnOV/NMumydHCA/ojMWQkVpFTJ4uH8WsY
UioZKMssLttlbT5DLz2CchWO7S9u0958/Pc9PHZy4yIhwNdI924WYrPi8LK4NA1qvtPlhJI7dI9X
63bI3f3nv16aefcdGnc9ZQ0Hn7E5jA0GS0nzkx7F/RQdvBTiz4htwkzElf58oUv9aKklYi3++SR+
QqO6dt975poK4y4UiGMJP4aUbAXmyrD1mZ9SCEHZvtNdCjpH54UPuxep1CkVJB8p1M7Dp8ko2hD7
NEl2j6w6QzfNaPKwekaAXBhiksV9pSKt/mctlBFAhWB4Ua+CmONCLw2esOLhQZWL5f028A8wARGP
EK2W48ymrWzT98PDcPqQ5jiJsqxUVAx1xGg9Ok7l0zl0ESXgwW5NvrqCKAe7nGirDfaQmu14I90Y
FvYuuaSE+nltB97iL099/HiGkwPLtNsnOMyJSJ9ilZ1hv4ZPKsWxmMULzLdLf5j/nCa1gO35HUqS
Ip7qM09qqMJZmYO80R1vYqFADWJV0NKRU8Iou6as8VUDXBxkqpL/nNUvRBZHg7qF0UPgb7AnZsZ6
PD3VGPBAMBfpaXwq76LJmcDWC8XBnAuXLu419i2up/6VrRMcTWk12hZRGGYq81HaJvy4rqY6I4xX
Izvz8SbK0ak4fbrrDCNlJA3LjJmNd5uMBjrxlP+ULzZKeQCbjTCYbkuurq9UQfDtn/IzZlQtP5+j
9xlHQadzCsmTW02oDf3RWU0VaAAy/2IYTo/AowVQgs7DBT/YeS8ThLRuF2QThL0PRPlcc07HtyRK
eJv1lHtfqoPti4/x8GmgerPVnCVdwQlpuIcfhjvzD63SWoblk7x0GcPtE2upPGjWNB8zdLePeePt
lNRztuk4fC0qmn1tseAoOdjTE4l34SndLVUzruN9aVp/AZd7u1mUKQCzgYlWZuOWWdkUAwkn8zZw
XIyuIYmUOM11VNMcbveA8i8Y0rSrNK7A0MpOW0fFJ2lo/1YqJ5eUuD0Gld7cX9nqZxEblfgoxUiY
xVS5pSQKS2sKaRhoWC7xKIaOM7NnRuKJZ6czLjqEofdNU8rL5RnFuB9SrzUmf5ymV26ZfvjjLxFK
RRU2vIDELPKX9L1nf6dFKu6R7qKE4RdnVxgV5g4lFbKqYRdUJGnYmFIgsi99ceO050qOddpw6PiT
l0Rq2GJgaGhYOUI+2Q95t8LpZnZncpoi0301bMvwDkbbgghjm+FK8DnhZDIB0Pav5huitzSxqVm6
f5J6n8F3eil0CDVbc9STo+rqY0s7V0D+GXPzsE2yEyTpeOxREbVoGeV/ZIZji5DOxow0TUhBdyuT
PDFTqfyRAMaUARnL67RqGYLVCmvNJm9kLkOCL+m/zafB1Q7ZdK37XOkTQOg9udSdo8cuSvhnSxD5
EERsFuqmAgteeCH38rC3VVEt+harREyH780HQUyqWQaB4LgD1gTbnjGCOgp6KXK/D7HrhQWTjOWX
0MP5v31Aj/apqvf7KdVr8KoyX1vxD2KMR5uu77tnfr9jHXUUdT3oKxOltbQTM9fDx1FreZBonst2
GCdE1G4cxj7UooH8dhhp+sUPgGqLtor2a2L2fSuOq1JILkb4DCDI+BEtpN0IRmodVvPk8giBaUwy
JJj3q20No/dUN6afsOwML7rk1zj48zfndEzJCWqI2LKc6NDk1AjzUMSfUERx/X1pB7h69BMECH7Q
cKH0TwnSqx6+tKS5m0ciuNVvR4iEd/oWlx2s2+g4inRwEzlQ2/Dcc+dU3wgwP9fqPdpokTSdsCuD
FiYU++CzCj9lQ5EntX2m6Q8uYQEfWpNkvrLJXs/r+qu2jk3BDrAjrXAZC+WKGi+aOSa24UHUXnID
MNFQKm1iig6vzZibw2Ohrub7BHSogXzpOGuN2c7q4xBjnLGD9nyhooDgT3K4oDcuQRmXdk+rB949
Mqu0p8Sbh+xB6BBEexnpCi34GVPWLxP/8Bu+lKg2Xd60zQL7+509rnxdzvad5hc+IWXBOWXMJ2ua
QU6mEtkwfLXt2Jnv6+QT7K8TnbYoX5gtgm26C+KkRhilrgH+0TIfwHUPfqmkm0/jtdFi8Xk6jEUj
ZpC15m40MYAx1FJoBw9SE1NrQiB/5pNCMmrDV+39OO6hD04iEr7uHTIt3l3jCFRhQwCbmFQX7i6w
u/tfP8r8XsfGtsTHwbXd91GIyhlNlmQYcheEgmMzCO3lwgha4ncx2SYGJv+fpUErKOgCndJYnsSa
Mw+m+1dHkx1YjqzZ1VqZ+9VmFgyrvjbrrXa5EQ/A0hYvhk4u+XARb1QqNbbjPoebw9z6qIuATVyL
e6Zvnf4z8Q/yldBby8NnlgjcJjvk2EkajcmyAZGgEHGbx09PtDLltON8enAY+AV3H5tbRp6b5gs2
eyLG2XVMhZ/3BH4FEdW17oxH1d8ygwGO1424bS1PXA9ByZmalfaUw/MjV6jDBRfXMvHeTbAAmxxK
V7NI/32XTpfJUqXj4D0lvjyjgKTu2nNUkGyCIUMs/ow4O7Vq7+4mc+haSiPxemFVA/6d39AItVZw
8JoaqPXbKac1SyYEnuPGOrh2fT6prxmfC4DcwA+o6JyCmZ3Oan1cjcX3giSDtjqlmzqh/D9B7RRI
MDmXBKDkl8s43nrf4nOHQO9moqNb/GHwUcgFYhdh1ir2ybbLfN+J16eTa83by5hmWKycfhmfc/Pq
OpvgdZYLiPne0mQHOdaDQipGUWUhbi07w7ohKVOhDmznebQskczG4U9fDgx6mgValoKJKNREe/fX
RysEBYChr8TB3/urPh6sn2Wp3Ip3rk97Vch1GRVaS47iJHo72Hdl4TwKOIyWSeN0/DDGvClj67bP
bOlyafI2I1GPosjRGI2GmkTOXBW8Uj5vSJZGLcCCtrPXYiNd34ttb0WpFqd4x3P5JHKzT5LjfQMq
5rsNZFv0TMfO1Y0CaafDQ9i3lm7V77s7YDcNL4v3k5LYxeyK1dnSlatpJv+0ycbDy8MNYOzpiyRq
mKAsGsqqzbi2eSsnHyFtc34Tu4JHholqPS7kGlGUIE6/3q1qJ19laeV/bb33+oz0Cs8gC1F2XxYy
P0NujL1c0irGAfgvXPIftxFaQ5ZhBeOvbMUxmDw6kIcazn4MJFmbiMc5IkwytB94DHbpcPafiEuC
qopR2gxmrMQei7PE6vYc8v7p0O3TGCwv8a86x87kwVEy7beEYUuFnQTAszbwjVOgKw1FyamS8EfP
YAPbDfPYxGTwKvOdbznc8hbxhIiuxAZEuKF0eXK8bU+A4WuBCxfYKW9rkS/DswOZPFsBs44R0pEU
gySWRI9wkgaTzFEcB8EZBmjDWjqtQGjkuY26KImQpHt2yUC9DPMUcvMW2WFncDXybeIG+oJbRuHa
1Q7pqjC/suOY1G7yg8XolwBsSvz0bS7C5jCsjarc27KBonTGIpfz2AFK1XVm+bToJ/xfDz9dw0r4
sqwtdHoO8Lzz3oWZvNQR8fsc9rBJnvexiQ9TdjkJ5rEiJKJjqMiEfZ1e4bZQgigrKojAL4MdtVmq
BeZrAb8lxZldkeC31bZ2lJ0rM0SEtWqscm6p8irrZBr0swYO5tsM9f5BfEgc2geHDiTZ7BZfj2RZ
PbvBMOOBVx57SVbQT54+JJDJxWnEENSbjaHMiwsfs7s96LdUw8zOqaX5Bb0etxdN4qZQy5R/wyjB
aeGcKq3xLJqnlxS/lyzWBXqhyUO01d7NkqR/pMBMCrvLLoOcEvvPMb3ckDfoVCoapu8+D+gORqv3
trUNOoVqVUznU2tCtljr2/19Kq55ZuKpSGlJMX63f9h3K+ZAJV7vRz0JjSlE8G6HSAQXZFmYVRy6
csn4prRGcgXIKT8lVyTfES1K+2nCsOOYob/MLLJ46KBNYFYZzJOfiGYI7rerbnunsbzmn2B3/m/O
GzsTYbA82hxSozx+PwyfpIy8U7I/wuH/zN4hfHr4+FRtk3ZrazTNQ0JUN4anWoaQANVhH2kC5f8P
lnbp8V88YGe5dGOo4d1CCfSJi910CZaR3EXORPjTxCXe7hx68vjBG/MpVjUKHYdeODApA1WQWiZw
wDUVt4bWV36QpAWQDKMcZDLPcrmaRyU2/UNMd3+OzE3a8rcvqljcaC9gg4Tt/4kbXjAVXwhulplm
M/yt/1jCPmsdIx0qS1M/myjZ8sHgapw3SmlpHmGfLdb+uQVSsZgXOg5bCmuibfNYFVndsTQiD+kJ
QkVVqrFToCbXVVtGnkUuTtQna/YmAptX6h0d21Hl+MCYrJOk7aUMfamCE+2YwF7+UEK9cdRYxo6R
TBnDqHvkPvjKQiqJP8rv2CYJZ8PgfFfizdk/LyiX2hmoB7HaDg5pM3fGW2nudxUcjLS553d0TRkf
sCxZwHZD/5uaHVvkcNQUWAmcy+gSOfuK0rMzHOUAa3BQ/tGwVLSt4Y8iOALLi6de/66XQsjlrYJS
fK3bRLjbeogYRu4g3NN/k8t0W4r5BhlH1XrfxnUsMsBaYtPu6Ul1dNFVyoBPnQxuUTC0AuOpUQ8d
d4QxQpNyoS/sQYef6Q7PEasMxrnIQuiyFr/JXXsm6X/Zz8QiqoHxxWPpbITi9MFkmFlFHqso8y6t
hW/kMUC7W20cQd701xLbUfFOhoWjEI5L5f3eFp/aIxZgxh74rd4EWXJNdba6nuE3Im4a/8Xf1JHE
1dkmcF5Z6RIZUMVrRntMMAXAKtSlfihBSQ2TCuOtudiUAder4xp+Jp7kQEhIMgZok4TlQf5w523L
t38lPtBd2/rR+do+Hgo4PAJuH1Bh5zo81SLAwvRjXfb3GQHBgvlDOIWKwTifBWok5q7bde9SUuLh
E8JrZ0kFrgfxO0s1sqGvkJHvvoXd2/A9sRHAl9uKqyFG1u8MFOTrb3KbdhJsYZe8001BjkUMdav6
/ll+CqCeLeC8MipmvxtZMQPXSF0ApF0AoqVczP0sBrCa0piVqhCmIDejUrAEibFGK13fv0iIffvz
h/OGcAueWVg/FPkAgLoXpcznVInbz2ZDmNpJeUy1jQHQmCLucF481zhKX/E3tSlMjn4Xe7Do+V1A
xOwPBdfC6fj/dJMoMWpCNjSeuOBw8FWFdq+sT5wavYfLRU03YkeZOP+c7ISIX0djNNzDbnLvAZti
xKi2RvA4eTXifTvkVEor1JjAVbXHnqMwqg11x5qCeZim+ci3e4zZhacfuaUjK8eqn0PlOZkv2Kv1
huX4zdupbMLaK882sdYWJSB6ksPaPppGENm7Nz7KgR9m5vFn01RbI2BBDi/BntYHRp0xa0SBRK8b
b1yIXU8hF+1gstrFUX01q2+9MuCoTyLAxnxvXi9Exhtw2bu+I2wv/LCaDjWrEtsDNJj5SVILsImc
ouqHTjZTWQd92pWmSyQwlLrNu9WKcqCWM+HXcxKpbfkvdPJ/LdCuK5wpkRQNoB2sEhZymugI/m9E
yTFxf0eIX3UyOqlmm2tKOrD0A3Wu8nlltsuDwg5hs++Hzc/3wpG7hcNgJ7AbJaUUye++OVj9tRY/
Ty63GRdwdMuWIzVFItaMpZufPT8c+ICMg8rgkn/onfHgYjWSanX7arVTOqAlXvK3VAi5ecdO2BWF
yBs6di72EzIPzSwFQZaVmEH0GYjZPlLotTBEEpPBq6otZw8o3RyCQe+jpBdEJBGPxgtPJLyY+qHk
83ohx1UEBb6ZjHucVfVVtbMU8VwV4gYlDMjml5qjNfS1sffES2KXY8EkIDOetrggWZoQHDJSlarh
3Y2STJLnNqeK6RdGbWE0Tf20SWmFOqFEl/Dv46JzPXC2dbHJvJXa3/AKspDyVDII8A5iMcmhQVRO
RgzUGEHtmqGG7TW17wu/wG6AyaEmC7F1nmFCFulxFZszUbKc9XINJcMowzokMGqW1IiwsDGd0spF
sHDyucSXZ34i55maDMuidZmbEpWsgNmbgIUj+dQGfiu3ff8noBBKFRSCRVyuCXzEEW2Chlrga0Cw
spRFzX/88DzCSJTJfmLFHe2UHBrLehKaecdHhvberu5dNVY8VhcdbyUmW+51oVXHRuXA9v3+1Xqs
AXMW9BkVXjxQtzl2/BuOu+AXSjP+PiO0zvwG2+RBTmfSsvFebAb9C2wIqZPhBI0wz/PnzIaFSewW
O7OxsKJoQ1NXJpzMgG3iQr80JHn/rONBlfbb6Lal9xrL9rJBI1oy0qdMgCJ9R9ESfrvqnf96gAU+
XSRrO4IK/XTrVcnEiWHT63ktktl4JUxuoobKbi95KsWrJjsYI3nyKnKzVn7S01jj4NAS7YFeUV6X
8EzsQpWRxdGZuBcmOBzj6tSKS7ak13ENCJule3U8BaZVRWgP09V4CEw3i9CFUMOegfeuUw3W5Xun
lG2Ogopxh8EeetD8o8sDhK8k6s+qJthhDtnVz9H0jQ6aL3dVvCXr4uygXt6xWpog/yX9u+wGxMuy
8XRIIaHminmzFr1cgCY+z1jrwlMiQV8nAXNZ4m691p1lkfsB5TeKlluGo0bX7uzTzJf1TmmFaZv0
OZdeGs/wr6qBTDoBF2l2QAG+JNLJ8jLPxxLAEwA/yPtvKsNo1S4Df9aAwvlGGMDXxllIf9cCIwNS
urZ9GFQv0+OWf6lKZ6BJWkR/qZ8O3UXSDQ7vzW9f4o++wWzbZxKp/6R8yn5yxY91XFs4yI8pqw85
T90zv0u6Ot6hK0+1te1o0zWsCkRl61f2JvjhIIa0nB3oApMCEzOpSg1ws17DyzukKNXMkTsIcgWX
tkPu/KsgoZ7YsJSR93UaJLODrCley9h0gl6pN/OVOyywUDchNSqbxqL8EzenZIFAPXe5W9Gr3eh+
7zWPfe9HqkOHzFIhnYVSRBiuU++Pstj60pkIn7dQVR7ViopCj9uygs2WQzGdjbUNH2kiUG+nBSk/
z8ouC9UPoGB2gQj9Cp6kdVism5GmdIC2aihpmUl+WcUu4ksq+aHWNkRBfwF6xb/ncRkLKtA/0mzr
W1E7gSEfxhwcXrVRNufFt4v6ckIxHLdOxiIEQ2PjvOS17It++VA4rdFPtnj+WjEmSSdAq54BNQBy
TKD/j3clm3GSV/OerVGPuq5JtV5M3md+P2YJ7VGMfi2UWEjbtfizSm8m8lLU0JDDTRGpB37NXSLD
yXHqTM5W8ZDDi5Wi5A4MMD6WPtZIdiB3+vLgYezdFzDjVzYg3b3jixAbz43n4//0lXocXvs9UcHa
3o9ZZrxExXeH1wh7KDbDGU+aj7clKbgAJUEO6ppZ6PnV7YcWzAgqzCpT/2NcL/FrZ0nyqRmNmU8d
VC727nvIzurrEnuQnNuZCSOx1axvzAg/mDeOUwmHM20RhK3KNsPRMEupLG7dJFoqs6WdJKIyoekk
Sf1dsvsY/CbiXt/DSud4BooI8dNNzbHkib2gr+3c4WnTuGUwpEKoc1BoRKcfKSj3lcYTVTcQJWH5
lQqZHUjQs1pWUbf4CPrOTxAVk4r/u/nZ43XojIfNworXN+4vOAoUKObqtZZd8oxhb9GTHRLs4o9K
jA+ZkiiyegoatKmO3I9hHGLkWNg6BH2mC/hUn6j03Mwt+UHqAD6KRLBtiBuBQAJcG+J7/WaoZrXQ
dHnptxaRFc9F0Lrr7KMwPVXlpoYIQZQVCabV/6vm3PsDmc2y8xBeG2g84OopOFTpN3xsSy4eDXRS
Wwq5GVoaCgY7P9KGfAABC+sVXHKzFHv8PS4kvHb/NZsKh6SDNGPk5+hcp9jqKG9yDjqQwyBEtTud
i7Dc2N0daoRgIlNnOe5SX2XUcUu/lnazSxPHpK7Li8otGuj+garomUdy5satChsMCMMjLqITYxBB
6rsi3Muj+4AD+1a6ng2GzYekWSyg0a2PPEBhoyzukXlH2qwYa05AB2DzrPRju3GpYO8CY4j3zAZY
y1g/vPqIPRcVzJkxucy49xk+uShKbHfj9Lp4BZLvL2xDQZuAon3Q89H9GN+0yoq54htk4cmrkcEl
9isFcMW88Rfod7MtE4kQd0TiUYlEg7k1CJB8kduknYZaMPQOHhygiO5KRdPuDhfQY890sZCyucVg
lY40h0kFxhlMcc5GVW1Ua6hHTkV3Psh/cT9S8WX7V/BA6NyaM8qA5jtBkl6xYJ1CeR1Ltbibws7+
jv8GkIFOh3oOUjp0aBGCZ8opd5+lVSm5BeLMQvgi5XbWBdZzdDWPbqIot1oAdtnsieZFKEyprYnw
IDwQdwijyxujk41GwaTaeBtXqvX9iw8rGCwLeKz2DLK2w5W0wt3pacAOlni2eN30YdxG9tYw+ycp
1k8JpwtRpaIMzxpzMpRZwXpztMYkEIuOXk9mQv2+pahQ6eucFoSNh+wlm+kKs9RQD0JYTh4Bm2vM
NHOEstGKTz4fayJKbIgDF4q8wkwgCXfPtRE13wuxSwWQNERJMY/gZqTYzJCsoB7sKhQEMmmigCRY
Wx5AGIEzSFI5mDLLkY/jhK1IoifClXUo/Kklj6szX+AZJs4HQVsWRAhw8JXp3is+DZFPE34aBD9u
PL6aIVBUH0p4EqjR1mje/BBXr20Nll8RfTzf2MgvK5t32Qp7Eny4TLOHRelTQH0iyBa0NbhLHDbQ
3xjochAF4Bw/0GsCVJdb1A1s0THlclljMGMggCBd1SMvN8sVCTuCfUiFlknCoBWncr9ly3Nk78ha
UEB16WBu0cnBmwZUhmqVEPfp0IWJbF9CdYnO+Qk/SBjBiiD+wuwasC6tHeaZPlKn/b+I7oSxbxNw
vygt/5xxkrrHTUD4x1Mi3irZqrQstf1HqWgjx/Cdk8aeeZBs2ivrnInye+xTN37Yf4HekyPEyo8y
st6CIjv6jDnUFilLiXaqlrWmnw1P/ijOH8pNedPLPGYVegmO1/b4UKeM5cm6QR8m172KnnoLIEs6
ZvI1XutqvWuV+Fqqrmsmc4mxcnC4e4Y/xJdSqZ1XfvwC28IiAxbwGjfZKGHMR5NO2FU9Tu7BFW1L
dvD924U4Iga6Se3zcAh+zGY12+XdjOu7Rmg+50W5zvQ1Axu3bX5yCM6x/JReqrtncq8Rq3uuTjqv
429ffsyDl/tm6rAQ9eCMsSuip3fx0W/9ruZF9qx4HzL4k5LmyC0HUu9AV8q/a3t7KKWgN2Iaumj+
zvDVWi6mMr3jQTXda/56gMl/EmDJSCD+Mlcl0YFgV5aTf0ph8pwSqySEhDOCX12g9DjcC0s83cvU
kHo3FVelr3ARW6HMluHESU1ayP9hzC1QkTBfHl819SGu0v/BFdUV5sxv65E4Y8vzTRSCbJWdayTH
hYNyHAa0VzpkGiQvkPVIBnKvDL7PviqJ9og4ly4xH+8qdhe4zpMxxT2sqzijL2XW7gD3wlgd3oN9
Z0cA+dLpr/pbUTS7wnNxLUl6aaXPeZmwvgtrjcf/1RYEjS1vW9C3pr3M75SNt4ayAtnSoOYM1y/0
x1EfYoP3AqtVfDPWDaQNYQGM7vJhI5OFUBrKtd8SO0zX0fsl03zMByTqyF9ewDlLuX/7pbTFCnCk
jzxGgI9CgpkVjvLUB4OPLu4j1Xg5hUcqkoW9C6wUmVOlJhfsGol/a6motwC7deCpbSuF+ADiTggl
nttegGGKGrQveeshkAGJrD+CvrfhCI/zEnfc70Gh09PlAwFFpyCXblEBPQnxtiVEDXrMBxAtNxkg
cDEJPI18E+1NNx360F+F1sFIZo8kgIkLehFAqr63vPhHGZIOnLEs8X+bIpaS3oqmYCfmI8uFaNws
2ksur0A7O9mH7E579B1mP8Upt3GL/+Gjr00XqNaRDz7XTw4sB44rqaD1AEHTH3lK6r9V/oJecUc4
6LdsFOomQnVdcjDVL8A9aN7Aw1E5vtPLo1b0irB0IDD39sjgvkRe7eL7dcUF2hHK+imsOvUBKItz
mcn3Rsj7RQeYq72AvM7gdhbOnBppNanfuxv7gsUPJho47A0x7+Nxz8lLhtcRw59AcEvb6cI02Ri/
e5uCZUn9hstWS4y15xMcEJogiFdXwpmFSExL8Z+T8h39k0N+H9SLmxzsW4RySQ7xvA7xQGwIpAFF
9zkyLBRheMSqB3OYTBK2N/HXYMUAIvvWzSXcRzKU4jVRPPj3Osdo6aFpaX+J6QBEhiv+z4FVHFhj
xYUwOvJoAs9TS1JcbUoLqquaB3FLbwRiWiotzxY0/ztkCq8F1Z8BlGrBgJqWVKKifbZInrFyp9TZ
KwHGbpAqdJD2xTwz8GbYhfHAlOwSosHWKEYjAd2dY1p3A7Al1TNreB0qZYBLC2TvRL/E5YssZh+x
HyhtnwOvXI/BjdvYtjfmDBJaMKxwgE2pn5MkA9zh89LRpC+C93bggqCASFCedvKSdKaasQ6dNGro
4Y8OJHcOhnwyO2XKy4w26gcD71PQ9RiLikLLDFK4KAjKi8LQWg6/T80l7ZN8khih5DpXdK/NKDLx
w5kc/CPXkxihw+qWDP1I0PFxLdKbfnYDYAOfCCXAjKbfN8QF5rtI9NFFrXIr6wsnbM9NEw1s+K69
Vf5Zy5PJ6KDdIASwkpKQMnxCoBpGfuNW4o3gLwtWte3qdyJ1Kkc7ruXTbtJuZo2lzxUun2R9s587
JZdZSEibzJBFOe2w8nd6QriMwBEGOg8jHWtW5JzgKPGS+Htgp1+iVikX3KtkkxCwiZ342lx1EtTB
XtWAGJr8d3SVwG0FMd1fi855rJnU4Vx+M/hfs7lMTIimQUMbXThRL7Te+Z0oABzPTmUp2VfCXfEo
nQnN9XXi97IHLEjR6i8JzHQe+Oi5xSnsp3cRpcJFOSLIbT8Fw48ytecwa4v5bMz6sNplACuIJI6i
GB/ZJG3w70Kdvtv2iZH1RLT0xJNZuXcg1OTOXMN3pPXZ4i5K2/CL+1ZSpSGLOeg6sPnqGUK3GDsy
x4k/WJ5I79j5ZfCQGoE3ZzueuVHXFSib4jSok6v5WmQfv/qzMRI8E75WeXUVE/8YzdnAdP9J0gNz
KcmoHaaaXsMyCvF+SEQ42YFQim1Wu0SqAmXhF8iwCt06EPaXmFob4ghWV7zj7Q3WTIrk22EsMec/
rmDpWSvzIgQmrzR1LGvZ6q2lBbRDiwzltJGGkErURfA8XzmOcdwdNe16bArh/M2E8QoHO3ouUOdY
F7yXULUD0MLcU28Z9jbO7iJI8EHso6dukd/ZLaNBvex9B8ctchSQEjW9dzsTPpb/n0axlmBzB80S
dHmmIYGYwSMs82ZYZsNYMTyoQTNqYhnt0vOXbuAQzq6QoAyuTnuLU5whMcfP3HdIPXbQA5Sk9vnh
8yFam3JRxpaLqHT+TCfiCfEFq/vJ+Is2bhDeLiY3h+sAAP1KCjfvCKXMLVOuoD5UFnBsmnTpJ8vp
nydB6EGFVAhUZAkXedGo3aLjs2bu1hAzWJGxXFYqpnZcfZxiVAgeAqX9eQaA5hESt6vYz/1uS6fP
5sfOGonpDILDwEOuqFVz45shdLigWtgarIaHdSFijwUusOtYPNBNUxObyGFxWsuFaRLt6dgYxx9K
vYLZ7shAHX7ui70pkc0To8xQsxajki0fjfe/Z7klrVFXUnQ9d+7oc4ZFaSTKYncDfsKPFQYYmXHm
pJ/1o4nL6+X3grlLmcd1z6vAilrmS5gPTcME/2yBxz4gD/bMvVKqhhd3nGDwTmhXkpna5nyuBOrE
6OwbJZHvt9+6UDdBvVR633dK0N01mYPBTaUjxwHt1vO0dMrH6PK4ONbPEVi5HgHGtUlnZ3MJVNu9
tKb+R1uhncjwChv/PNbdeE9KZKveLg/glrMrbgYH1wFbbDtNsb+4YsoSmcmsU2AUKhxqxvXI3af0
J2h2Z5+Ql2ylsAerPKLVfClMS+/zRlRL7tMPIhvQzP86ymgEXKpQqvjfOcwt6x227bRrMG5aPQPj
aJRcl8TfTsH5ZBItq/6iGj3AuzvzZ/zGsSbtg+LJJ/5CJXPwotPWR5t5Wps8u9BK8pS7RamWFozH
UrhjC5kAX7lbUEQzbeA1K1FIzPnqI/zoyJGVYyLCi1jjfHjMIQixN5tvGxUrgn2EQkkuLon699dw
aLuYPXQNzU1Nn9ekKl3gfUUmxvjFzj1lN6x2iyFMg9+tG2hOp8nYdFPP0K1D6MjO4BhoRD5s5SBe
n7bjTyFtLKyjmJM2sdEKFVYIZyrPCZtR6cHa5bddJghF+l2nINEhUJdqdidkoKhypGyVZSVt43ev
HC7Xz7Fg/0UCCCtjpbVLbIin/H57YSHX/jUWoxKYkWkjrXyDZYARLX+wRdpmekcXr7PyblQBJfr8
As8FUz58n0udQMukYOiE1MAW5zgTBaUysdV5JD/HGljHLX/qzKkahj/9be6HEEAUGSN3KBUV1w1R
TfphmnyXePdc8Zy79bn9NZ287uc+WzOo3/E7dAF59mmkOKRYYDABX+AKU9wFdS0pHLlogP4/5S6Y
dkQhLKPny9jpApNFQI53bF0W/NnukzFriUyc3fgVmTc/RSlWMm/JfTiUjh5WXcim2VxjeGEt+IBQ
owuXsENJO8dDweKelT0XF/urLFAedBsIAofpqiUG1P4ROKZVldro1Ve/V/GDBV4piy32IqmDGdna
0JViLrdN+PjGEjy0fwvxjMiguzNZvysyUxcvxDlJAvLiVc24bCY3nBRU3k66BsCwwCZuUK//bEqw
NriHi4ldDOqVz4OS/rqb7M4VnYymC7hmPNKeFQWEiFmuV7a+tQb2vMWDj5uN49YfAW9/PEPQ+Cc+
4P4/f4Bd8PZx/erkZg58qtSUoXGzyow6lUT7s6xOeRNFunu+sup6wSggkAX32BeLaTbIxCER2xaq
ckROBl6XJ4ofxzT7WIaR13pD6F9GHJtelFnqqdq3tS5DfnO69GYeuK40z/qvmh4omDJskIOos7EV
vgA47CZtDq8JWhbYkMRmXJT2eieT1w82j9FtrnwTiuqcd0v9tlrO1Yh+z0zq2tUg0jt4wcFkYse3
lCpFLHuAoQWuwkxAqQm1HgHpCz1YqVQC9uc2s4JqEfiXtKG6qpfvwwI6u4gQNiBvEJoKtpmrIw52
hDNikehMCVou8v2SeX1tbQ2h8Pd32y50fyB9O+A7WOs90OOKrTYGKFKVODbaGkNKo1T0B8g8bbul
VVgiE+yzrssNveMTgD6xirbs56n/jsmWygvZfQUOIBBs+w2mf6iEA5xAYoSpjLxczshm09Dqp6r5
2cZ8XfUs6foqZiw9UltZxe7xk5yX28rcz0KVpgJpRSZggRhgCVJ9uEZLjRO9gwKgu3rTIXwgr93Y
Uwjc+112uJcRmz+fREdhM2s6XImtSCli/EZxCxXtriPaicEEwxXhzalaJun5FwLQN4aEEKQ7azKF
TKvzy4VZkxTtNpNtN88qBTQV6hWL40MNxrO10TBPORGwvwPQ5P2GJtPeWTabRnA73Ti5Kaw7R67t
Ek/I+dF07cOyco1483WUAyQzOo4YUnvjP82gXpVKAZY2vS8tov5fsh6BsgfZ6Cfc4mLzaQe+AR8m
VL791vxcXX+kjN/LiWS7Wc0nTJpgXUtGhmRgNZnF8Opw/T1oTFGdqYwvEavrWDNjUWlnG93l/5cQ
isPcMICrFSpzDQEeckE9AnrTxbgKLSJDmLpz5FblywPQGHhATk/0Z0o+n0sSYKWK4lc2Sux7rEmJ
aSNSUX3V5HY8cz9ETzyDsRsd0UzCqjnfv2DU/WSXo4JrQ6VcsyS2yEo0zj5iXhvGQiI91AwkWmsn
5MeZ3XqP67+vTpsEq0ltYtNSNPxXaJUk8rn0/zbGSVQpF5OetQVaY7teDqD/xCQz+Gu2urGqwDd2
bM+R3N9aZaZLiLEaex23tXCXBd/pJvQuqmlicG/PHpE9zzIW8H0LlFg1Paxpra3M1V/AZK/x0P/k
NVn7V7AUZwTcRKi6eLHx4rBTpWKdF62OBwvuzE1qpCxfZDCpVtqhq7G8l6MwjCOAMH3aRkgtJmEM
/N0xA3WB653o92gD6pOmTY5GY7aRK9WkQIP3bJNVJ2JigrED4xn9L/ROhBMT51k0lCPp0d4Sut+U
Hq2GGktoPF+0U67eBWdLf1FNdb9j3r8CCFBZkq0Iac0QW99R8Rm5JzC83n2eWp5ih5zolK2dhiqs
EQM1P3JULs1+9liliMHwydXwDZexMdJlN/h2RIxV/W3nLUbBOJ/nEOiLVA62CgiuKvzdlqRTw/xJ
vgYqG+ZqhgmahL7x1Ht6C2Ok8rP2phXnBKVRjs/1o7OScLkB1u2fmCY+Z7VLmNSB7YPLAKbVW1jd
O+85rYA+fAbp/bpwkfzwNwae4dYiAvxigiKZgOc/qoNzPv+b8eFjsQsFbRfJKpQgNwJOvRwogAO5
AEzJK48/K2BS2ZOqHm8Ve2qQCiMBtxF0mfkRKKA36AxWR2IC9uIHmqSAAAksZ/Gtm6DgeS1QOi4S
KRqn+2anU4WukUnBH1metCe8vQr1OKEUhwIgfhHx9kUdNPKn1xj7EMfEk6Ej1R5u31oKL72vpJbp
Ol4UNvUkx7IzwYLOHNC9PqVZTCkb3NMhTQ+QhiJttjlPnWKtpRyl7Rks/hDgkOjvKa+xKq1c8Gc7
n77/QJj9T0u0jxn5Crn+dbq4w/kY6RZlmaA3miz3oMsETnsG6q6nm0lHfDKIvbY0IAlg9mdgg++L
G/lwhGr4JzxEPK2qHLUShBk52QTK2+flFwqPQ+oeXW9uWCNoSYZn4F1qimdla9jQyj0JGqw4laAh
568EjbO4HPq3aXReorfF/Le5Lxym32JaQxl4bh1CTrczvisOY4jrWEqDXC5GD7U8t2zj4f1jWwsd
gmu+t6BeSo4Omh47geHZqGgX+xuW2yavDov2HDYFqXOPzjENf3re2g/6V8V5oOOZ1N6AaHnmP2UC
ERhzFpDfSPcVJ4XUiMuoMHB8FUA9A546MUkdjQJWnjoaoM758aduSPFNsv8VC7Uxep87Tjp5UU4+
HgITW1/EugrKaacdPxtpe2sO1z7zWLcQ325MvHQnyBbfRTtGKmWbsF90HXNiLBEHU5UIhIhHwfzE
WbKPYP9cMZXJBrDD/Oii3sJ8QmqVXbDPkN0xfneq6i2ogSNFA6FbvzQjpvKjQdaVWahNoQjuR1ts
RIICUoPRG7rFmewDNgjdwOrR9bH3c7seUppnuK49bJvpb5dl0+MQj/hfKUjyqFUn/2qIXBcPJKfy
zJQMk37Bp0rfYEYo/D81nKZZpBMjRAAPPwTQ1fMlTrJnspU0R0HZ3HPV/NkiXUbz+1iHLFfNDNOF
eVt3Hr2b1/BQG1P7d8s8IdMIEPK1oU+2JzhqWpdP7sVg9KS1YzElcCrhFVdsyK0kMlDe6kB+tcc7
uUhvxYUbHilFMJPVDmHDOlBarYWFMiWsBk/LhLg36OGh6iib5dD0MaBXG5u7IEQMDU8pD8u4FUix
ZIP3VB+Kd1H2EYa3Cu4HTgxvbXJhm61mmpAAzQSHAavbpOC4FKy4O17CWBpIcfTXc58+PxZgBRq+
56wtz8GQRTaN1tMu/mYEstNs0Tfsq8DfOWx1Z4BHYvmAfd1izEjUmVjEk9r2L7skJguLmtel2JoH
Xrkj6NlbkRnS10zuz0l2VIS13qRL5t7rryEn2R7S/j5sNBQlQkc7j8kckfVhZkHICZyZpuVnPCzw
MAgp2n/R2T/NOaovABPylzi02lXfm36EgS0wJFolYdM+yHRuo2x8pIIezEABzoEFkUZHuJPsp5qk
y/HfrWJPbxFhFErNwEOkWzrluTDx+GehFRmvTo+ws5aJn12ke0ytoqkOKJ8A15Du7bnj0G1R2Amu
4IiNvNZ7y7pgtKm5pwevCoARU/v1yT8baXq2FkLvc2I8VAPXvp/d8cm517Y3jGYD+wZkqGLY6p21
ZJqe+KB7b67tePsxoSYY9ti7btniTq/3+vS9YABCA0euA/ZXIRI6sKcfmztmqDTug0oCuLGK8qIT
cFNR75nVJZVmjoh335dLx0WOo6YZmPBbTJF2MFC4TYd6IYW57TDZEgyEzkpnYAchnC1n4VJVK31x
XSS7r8NQGaRO9G+YGafk0koz2OxNcazd85vS/X0ijvAWL29As/IRGiTu7B66kwTaMO0TBBo5V/dY
cOEX8AHu+TJtBOIu74S7El63u0KnF99LXHsqPX9btYB2QrDPt5mVUg/hKxQHYqiEx+Jwc218MUlr
6A5JLE9IUe0AzsZsuPXnpMpzGtR1Y0k/+wmM71sCLU2Uk/mQRYGlVUD1hX12BWmS94YQwOKtig02
MP3y2yg0QSp4wtw2Yk08daQjQnGmhskJLzl8rCGi4MvNR4wRRm/aVBT9b/BG9KDeYORKZz7Mxw++
CX4HgY1/r3afqpHh90SJOQhAOwsw+HMdZcHBjSr5bYhjrf8Tz/9+Wy95NDg7fFL7xJNeN8wl1EN6
aE693MsLc9nq76JybYTz20GSfRM8+abcNJvIT7cWqHHHJIZv10xiwgA/oXwM4dFlLGYMwcMoi3y8
gpCEJOuSjwUzqOetBiMHLOTX2hid0MS3nBUGfQRXyIZggwvWOv+nMRAbXZKZ5E940sMIwmfyYrYA
Lj+IGvoSZo3Z7UFUVaKlGGN8nAmqDv930gOOfzXCtNs0Zi+MeQ4yMy7GK43CAqj7SPG65B9mE9EA
tc1ZLFPF+23e9a2idf5dY2wSULn5xrXbGshQMfvqtlbbZW3CHt9lgdegz3x+QUXVrKr3tEnyZtwz
uNxlL4Uqn42m2yObl1dnDugHEijV1MuT0uBA83hrmw2YG1c6asFpGA/g2VgvMjDT7je6N7h2s4cR
FrrXd+PTMtPYQmH7xrZff6sBVxeRL3/lpLL7Sld2zrfyHqACYiNpsUwiBY32oKBRIy6dYCxqNeLR
mFU4uaN1pFondnX4lCJtoCmmkz+BE0Ho+BcyxGeBZbZnvmuBui/bJBKRhcLNemqDkAjS5CO1uDfR
Y/+vd5wJ2FOvqTbcFCVa+35IAY4OHIr8Bg1+tWA4uiNphk6FFFKd5HIXZ2y40Qw33qZZysFPAWYG
4jeQwwKlaYgcXM+1NE9I+Rr81UNBaRZap6cZqfijJADH0G1UUpM22hi0kockb49EuwU0x+w2baMI
rOOa1vlzkntHSb+DfAikRJJpFBgAYQD8N8+y+6uIDJuF+aD/XeMlkAt9OTE+KhA4KEpIh4WsPJfn
hrVHBVejJGCFWWyNbb4fj/Upy1HasxlDdh1O2KJnDNTPe5f9M+U7OjObNA33h5HnYrvFeD76oAoB
VjTs9r209/xBO5a20IsTmq9fCeyNuY4aYV4iPsNxEnKY/6tBrMWXvcXtXM+TiMa2ZiRNKE5ztl5F
jopk6Q9CUTrZo/81tNv/UbwIRvfwYV24WWrUSG3L5ZMk/0m/6gE5M9A8W7py/GxFuFTdDcj413V4
aNcOrhypVDNsVxAz+GWuonP81JDOaAyh+U3xCFb9Gp/PZRmdnI4OaUggOirUs0Jzj0EgnkpzDbre
rcgZz1PqQ1CagyanRC+XypfxQmNzoI7XvbZfmJAs1TuvYZyhMGSaxBHubWu5sFrytZ51hYmSP1PN
JsckclcEO3SscaiGfLsYYW2AWRXWNVkwFhhaj2iD8dbkQYINUaheKqTwg4kp1KnImXZe3nZ7bV1N
0BYtaNYXu4qsXETalwHRmWzbyKdluEWBK55JxKNXVAsQvkrhJhqDSe5aERX0bLDABjBtc0vuhDB7
hPbRFOoiCH3XwVZB79irSO1HONk8TTJDd45vDZGNtHIL/Fc27+bwg460Fuwsxa8VgQRDE0pAmsOa
Dr3ta+tURQYfOFany1n5SkPhlU2wYoUh7y97scs/GFz58MSHMFc7I3pvt5GE6+7h/iK9grmSSdRu
UKjRKc+S9FJRpjBQ1s1o4veHe9M/rm+DXhEgalwQVnJ0xvj4EQwrkjfOrcnfUOfy5/QoSoJSkzIL
9qAINhT26QKBZgd2OzeDH2ettZFJ8Yk/B26JBnRpenT9WqfQQhojyeCAZALlO9nai/Hd9I/NMmxe
rXlBvDazWuukhatQIFiuJiDqZY3CY2UDbz9136jk1+SOEqGWbwcUWb2r0JYgYJlg0WRe47Oxl9fx
jx1U0PvikAMPMiBB6Xj6cKKT2SihZVdhGIllc6ac9sTT3yEEwqX9Z+ZtY798ZI/JXAklVKnFY30O
7td2Zt2h5vR/PxgyneVBwtc6RKENP5w3dCGw6oBAmNHHUa+sL9eCZtTqJnpkmXxqsEyEZ4iOe17t
GQoaa539gW68EGJ7gcpv04RIJ6mHRlNU99PeZaYX5RIL++IrE1NT5iCptc03OltcCPyOceHU0Ek2
t29LqmiW7osEQ1JGdAx+XG8D7zG61F1N+/Q1TBHOxAE+Xv83b2Jau6ryCbJDLTOhyZCILJYxeddU
TbXhRuciVLJPKyyVXj4DgHcL9q4XPk4IHJe9+lYHJXIewrcDdgWGXeALs+EL1bKQi/fNoBb2o4F2
bxLLsLhO2LWd/XQ0kxqKCoBm1dlKZ3/IAWPUFxePp39YbXJ5VgwS+Sb9QRwAKDB3oli78Y6drOXL
zCWNgg3d54h0SJDMWsLUOFie56MNAIqMMmmkwbOPUtR5fvXmMArCyrdGL8Ljn+jMrAZ4Oy3up3b/
TDwFWuskK8Nk17uPZbSpmtu/3brR98BLkzvuOkivLquNH0eu6dNAv0iaUEFsZNQL29MNE3XiIDf2
MyhrbNeW9Xx59VZz7sB1SPvX9GaVHWTUb+jDpHJUTGiq7bAnT7X05YNpeubyHnwrRMuaf99sAPTW
/rvnsHaZW5LPX4cVTxMfxUSOCJRUTSjjRPShg2J+UMq5ZMV68Stw37eutItzhh8uBwTgCw/8VVY0
5W/u0YdhaY6r6XT9wAGbK+jVDciJxZCzVN55OdqYF5CBQwXuUjq4ENBS9GpAjKrzrjOYzH+9ZYhV
PgZyF3X9euSLnIZwTx6G6i83Cj1W7RHGns3Nn89HzOsxm3DRRmYcdT+vV5fCk20Kjq1gVoAPb38l
He5xqAAhWsatJuGOAjZooACf2Nb9SVG+S9LR40XAt+V77l+5K90DvoC5rOhtrBypCcBAvfQITlbW
07aO60QaX4Mactm6L17xSKzaH+plpI+QeBw+Cz046roqg33QxIWHbrZYA/hSW7V2WtLImJcZzrLf
VofpI8wOC8mpoV/lBkdSAfXbwfgJPHmmrMBcpXt00c1hBMms84IUGgoRxEYXNLAvFEf59OtIakNi
FNRmOwxqEQ/UDccciQp56zJe9Ohbfka1vg8ZLffWRMOg+5PpWqDSmZ6p4d/ZZNylraSixzI8kgo8
QIb92AaA6JflV1/R9rvEyNQGwgvgVE+P4XBn9SsXaEGZ9+yTQNwogENirlSKyCScH0HSycsWTEZf
Wwcwv6M/2oiLcNvba1ge1mH65CsPjwXP3h4Etwjddg/zmrOQm6U/+hIuP9Q1b4DCEgoPsQFag6OC
8M/B7Xur1sK2wWC9i/pyYRXnmNCNE+wGSDkBU3h4/R64wR77NvPwTHKh90Ga5jzhLnkePT4HheH1
+l4ZJy/m9eDHaQ9T9NjOrFnX6cZ+yZSU5Yb6sWWNYDm3vV8eFIFJwHmJ5yAdMtagQkiN6BUVEr0X
IZc32+PlVlPPCoeCxvPB0YWBY2oh1PJjVY2gz5k7s6dnFUPR8XMkWkJBq4XaKzkNFK0sbkCn8lVA
onSjpV6WqgfZ2dFH+XnXo/oJsHgdntky3954FO9OAPZJZnIfgI3Wa9xJ0dlbBX+vSR5hUOIJLmXl
Kan1UafvCdp0h4WH/zWNjGd84mMhCybIfi/ZYC8WoKRiw8c+m9bnsgrjsK7eDAVUMiZ8ddAETlar
WBFnYk4fimT9XRrvgv6hFkmsuNwnpXPZec5N3ijC74V/bEKGwe8oXljXqqp8jUiyOkx2VIl5JNDN
RQViLqMk4Y2oiXaD4MMNePKJDz68l/Umnj2xz+SchuuBCAvVZlOvmBzKgTP0rkmAmCa03QshjNGL
bwvThyLsCqSNkzoddNZ0yFQ518uwOXgzLX7TfZVx6x46DNKLmX/kbGol8AqKdKvUph2AESt5JVoE
nshaHWbOSNmBI3zWqAwi3fH4og2qCTG1vV84BhoRA0DqRNedCDU6SZMnQbWdR8vhM8R9OgvTD9hq
MfjYA6e11RPmRo6gPl0nryNfvH2yikREqmBq6gS8YeIWCHi3Bo8DnPr3N7r2GxwpV2p1+25thWjL
YO9YTQwVAl2rEEuWQkgOgU5/0kbrSlxYSL28xVCwTBFres1XlnFRSq2d99tfjsINdgjCo++lTmey
ZLFP5mLxcZu/iSOcYP9N1ytcAO0Fp8GntYYhB/3Cs1a5B2IfW26MRm//0xepIZZAfLw5KK+vnDvF
TfBfvvoxEb3tg7acwrzrmSOj46O7ADBAEFc/Fzu99se3ji/b9Skfr+rzJuByL2DZ9vG41JN8jteD
0Ci6TmSO06t1JVQ4tagPoGA3R2pOcYJt+6I53KTcUHOVDYffsTZexEdlCk8NgqPJWDfjlmM1Trw8
cs7VpePLouuGJMp95Mgum5Q1e7FpCn6ZFPxptFDjZna8de/Zg8djNKYoN3/MZhXrRo3qZODvgs6M
U4ukleMCWHgKPEBoH1wznJrspd6XUMVNComC5y3TEpA8KkuT6yzHkPRnxKMCmPeIpmxGquGJmD3I
zPv6kM39/CZdKDSUbbk8tRJF7K7sAaEUr8ckGxaG/JDKoURCil2Eje5gWtG97WTyOvX2QpJpEhue
y16jYwoQpHRfvaGqZtW22s5bEA2YDAHySzpfthLTfCn+fa4nq/wAsDYggiif7UI6B7PXj2fMSXA+
Jt7EshML9WgwXKEHQfJkssi3Dju3gyu211PaaXwsyl/Iiwtb0Ua4TTsPwuPXFIHR+udF7DkUMGpx
9rBeLX+GJcWzt/ObO7dkpd0lqtOL1vXxwP0ElTWmV32E54G19pEId6tG59YnNuKvNpg1RfoABjFp
buUZ2Q3bMKhZVOSmpkIzKiNnhnrLFJELfoL499LqMYELVNpQEP/tCRE5iKLATc0/j7f1Hm+c3Xb9
eVefR62/5uZTXEdP/Y65wOFn3PBR/Jtx7Oxe8uo5OZI0HblGJS1FX/3IV3LV99KVP3MaCcAjeNxd
PR7uuKv6dxNGvFkf+FwGirXQ1UaL4VJyy7kJzcN4wz4Yr+FPFUtzHd65SRs+WrGbKlkZFmG2N04W
x7kNRdN2wngqsxkdWwLWxJC2NN19ExLl5OLdfSORgnfXIemPSVrW/uKIVOSaTAO70kMLJiw05tDl
+TKhS7pL3B6zq/ibmAGmB1Nx8DScvRJnrh54FaNap7vBM6HCneCmVhW31EGsKMu59ghZoBqY88u4
eugZ25AbCZze5J6Q5PE5H4S4kwRu+smH+hdXIDrO3WNnB5ZHqYbARkHf0k0ebyu6Xyy0/l/kosup
wdp3E635CBnh1ECNwMTP56z/GM+EPo090QVePJD7ckwxyj7nVMJ7URs3wtn4ua/074T/Ka3SqUVP
VWzJzueYG1kHz5xT+jnBSJEG0a9WihuB77xzfcl2hP+xJg3hiX1NOCKWJl2QPc8oG8BPA6s5TMDd
+3cE0pL3BDMhMTZJSPjsux8Wlj0JQ4ddNFE84jSoDkRk9fTAnBTHd1tBtpnz0yiO54+Aq67AUHRf
vu0SeZK0J9+03CVwd990SpuExGw0S0+1F98GyVFAP5LD5Lkd2TBwVp2Ldw6pfEP5qg+ruSOQHzZG
OqZ1Nokxs08SaL/peXSB6MMjtotV3zlxAUxzGlvZqhrlqodjRx6KwjLiXH70LU3lgXy5ECbOLI6E
Tm5+XgQvKELL4KV0NPgiL777i0Jm8Mt9ly0Fv0/U/sM1j3pAoANAusL8jMcPyBDixPbOXe+vfXjq
ULD8Ih+5/v/rx89uY9q9cHj3B8LSppuZNkJsIz/FRNEeC9VKyF9faY66jFuj5+JcFXgRF1m24x3+
tBq37RmwRHntjqNV1bhHYWMD4yc0WjA9rBTzE1GRKhcekhOhgnFGfk308mp2XAp18Ciu8DJB9MIY
1cLqppYMq1G2o5TLVr5Hf6bpl3oASLSGm8eS3yvFp5k6rIInBZeAJoKKm32CL/Coj898M8WyT+0P
aay3PlIQ4cw83qo2o4e3usQXRhpgtiCtlhdhpu/t/WgJFnxfYoAGtXp3aYQZUFAygQDzAXt4Nvzg
IHCbFuSI2x7J3XKk8GXTeATq9hXRyMLtRwzvHPhQr/FW/lzS4paNjMeYNiwk9m66atJPhGO22qiA
LYmFgGtWGmINpGjRdJNtV/gftTwhC1K8sWCPTrhx0cgVcS9BVkC1dQzUQlZRjsJTZA6BR2A0PVYP
YndZS8T7aT5hXpF3UdXIF82GSUyYllqGqEP4bJ2k5Yhy+S/eTO9i2YNlrEBeH7k5aZQ+0OxfhFUz
wLh+slMFa/vHAjsnAcvzcpjQ1EyVKzj6J0ACVYz3q1UAidP4ZU9FTZVbsOTRABR70ulWigMpRgnc
nxwRxQT5TNAoCtclfTtyRivfK0sz7hA3r7Vls1jbcpHi1ROkMKy1cMSd9nJWcAFeRZyZMo11jUSw
G0DrMkeosQpfHUt907wvN1tHFAI9F05pgCtypgr0ZLFQ6XdX3XDOpsziYC5NiQSfayXalDUxu5sl
GxljiKeYkjrhvRbEBtu3fnk1XAkgcoeN+qZ1/WtX5Lwqx2FkR0IQJ7lPu5m/wtmb/JzJniLir5Ia
RKMoyh3tvrJdv2/qNGNbUaHmWNo2///qOej1ax0qCbO3srcboGl5Lx/F9zKwZJ6iQ0g/HeY5pVx/
svBqelOlIFvueXxc62CALBRz1+6Mhf42lZFaqya2JhBJfHQWtj25swfEcOXY4OeoxUgoKlqsg7Zx
R1EXZZ2uqySH7hFLbG09yn6qP2uDOQW/bYO/ID7+tlIgsCul66H9FuXiiapIJmFCZNZihmDmkQ3M
a/fD6coZ5E4iPJG4gEcXkQS0TBZnB+LCbb+m17g0gRd8cal+OOpYCu1zD9jH/8IES7UAuH403FHq
qbp8N0u0iISIlcnit6ax6kxZB2tCbKtW6bashuaXTeP6ZKblGsVTqORO4CbHxSmYKG4MklV9d9nb
EYUlkJNer3R1xbP216QOE8Txiy2D+07+ZXbKQakqOC0d8zsaPjE72dT8eZxmdW5ihaG2lIf+pnCM
QaMptCHQ4hgZLt3pSYT78t6qFB2wKpx5kdzcJwIx2EkC3z5y/9xXcxjKWjBMOMPPT23V858t75Zk
Wfl4irv7iTizJXQZF1TBNpVe+LJCpq5qsbVWh2/4qXq+RJd3O5vfDw8qb4HKEUCL6o/OGmE1zAq9
ls907g5dcxFb8H4PenS9wHEXlFo/Y8TGG4DyDhaZ4V4PthE/3iglpz6krMznDY61IYn5oG1XT6Ry
dtOvONvgHZel/m/sbiyQiVuGN2agHoibc36AGZhMgUIcj4K22eKHur0yotQ9ZpIZMFG1k88E06/t
bHRICrbru4RKSHSrD6MSFTQ+9mKHMEO2yhbsH0VL3RpkzmpWgUAJ2l2kpOhJTqBG4e5m3EzvNtJM
ENUga5VraWxqVyijykcCEoq71P9JooLHnAHEy2lo5K7NTRCB+WNT0wsbl1XMta3bZCh/yjry7D2+
CmNSBhcCEH43w9PlBJDjicfDSbqzvdB2lX6Ks/t2zQtyuXTwGlWb8FeqypTk0NgcTFQ3jJQlzCPK
hlRdBbOa0dM/gibypbkwtFkc+ya69DVHQZmwduMw00gNiDd1Hs+3jUqd2NQPmpTkDLQGkIph4lCS
//GZ9aCSEQpzFyj2gVj2S3NnGWtkw4tn1bcvYtez5mMWWT5MgNhLEjQIuZRQ0oZjOsnEA3RHqhuE
3GVOS/Tkbf4beoBg0XWRnGKo7LWNGj09+O/GxvzQFP2LA3/+ay64YC/KqXNLfzBIebrPJ7g7foYP
TPIfU7wR7LtEko3GkfDVVQM49dheI20hrBT4j/15BMZJ+CoVdaRm3ycrB6Kth33Kmp3mSs+c3NQM
qxfm8wfZucmgZweTcTycjd86MjVOE6MhJLBQZUVTZ3TGwnCLCrrEPb9jtRR3gugQPQXcydPwSMC8
JBn2s0ex4WQ7Kar9mv041k/zSuRdlumWFlh2N/xnZuyep8HnwATBOicWqRlqbB8SHFnrw6H42MBt
rft8uOIaCWtaf2YdZmtJ+yEZUvmRg/dcJbJG7YQILAAx2NxfLhIqcxZnROJ5bBCwcFyJFtm/echv
30Y5YSrIe5/AiOJTLu7emfqirROdTl+CWOE8I70nXQu3Da1VVXv9be7C08zBoCb0+soodC6EK1Xz
i8KTfP9R++1HVTGdGK+uKvAwJ1+t89bLrrJPfKNDau3K1Vs6IEyi/s+jl9P6/OKgVDvmygrycrIN
qqKe2G0HXZzdNxh5+byMKqT8mA+8pd9lkT3ZQWtGSvlqd0mk9+8uJ2PN49xKu8xbOem76mwRKMt0
NVnMYIgZceyW08YE+nvTjnIyDdxTyKH7bJGumiO1eKN4eA4vbTzq54hUOopElWiAf8pUUA96CMtI
3b8gwa0OvkldozJLTRWUYUbzMf+j4aZic1lnEEladOi4nQfAuusJrU7jP1AsqrcA49cR7JEFUiSn
K2p4mTYekAsUjonVBfWCgzqonabaa6t+pE2aj4xezgMc5VSAVSWGNjWVpzETWVnj4caIDhWP+7F6
c6ngokX/XK2Vez75zIbxrZ04V63fr3h07jRX6744J7l77NyDmDe8gRTBguatqsREKPYw1/Ku8unn
d2JTemRYsRwbD57EIbsdYP+Mycu3snCEdzTTI7k7lsbxSuh0FGV1Ep75bbpf3zmnutE7qBAbx6fv
djMsEJhKRivegeSwU4JtZCoDMvRfe32p3zBMoutEcGM90sMft5ooYyxKS+lJSooM1HPfma7O4YmA
gLJIH+94c/4Of//3C/z2JW8pK2TuHhuAdW47AfgE8OPJqLmkFbl16ZQKbDg0G+eZf2oRBuexq8I0
xBWuk65bZEK+bTnbtInOZ5ADBIuSHqMO4ld2hVx2dxU/rmVlAauv2MG6TlAs0lSiFQpYGpJEhnwd
xO54akkTAm6yrjmmQrydzcL42a/lwyQPQ929H4Ti4CwyZUKjTi+eGhOQg6F24e3ztj2ihLlDWfk5
kuj5fs1tBtWEvqQr+nxdbGh5rKH2GvrJhjGkAUxlpGv2Ol/KzZVeW2kPOqHS92MJDHAb+pKV/iNy
jGhi/clJUV4bjyaCNGPb7mDd7230aeEGj1WZX80VFHs93HT1ucpJYNDXpgygEfsxhqXmYeh7J3b1
4PONMFaO9iEXQ3BigWXQoXFtIky4pP4siUbevEhz1Jus621aMOdIKdaeKEhRHFnHVJU53BdFncvd
CzwcvBidAWM0w7DPJChgt0Au9K4ZvG2lb+z5UcQ/5vN7Zp3qAhYF9XBSrFda5aI87bFb434kgukK
W0+7xZyCtE+y8/D5hdCreJDY8m9daO4SST08MxtNOeEi4uXIFYVrGNgLhDKA12WCsqzTyUqW2AIl
+KvdAGNaQB+5TypLgDDMjuRTeaKIC4z7GtOWLRjRuLu2oD708EYf5NCwNC+Mvusp8zYrcfseRTJi
8mQpaFvua6D2BcPNyiwqe+DBqHNilvwFSxai2gZZYM8J0tXw1VwUemsS0Ls8459B8drB/ytlcOay
VjhVFXKGMvaaX2cTlIKxk2gauTPc6u5bSbBuJfId2J99TRgOMoj+hV87g7KwwUu4sL+X5xEWzGdZ
zShICGtI/uaPPcvrMqv/Ufeluyi/hB/61/qhfpB1pzGIQ6jP6mmC8k0J/3ZewrV+srVg2QHDT/gL
R3eVkCTLvHoRvVE6QBj0ZkAUn3dfUC6iQ1mM6soA6RlQ9nO8LRKiO4xhmpUsaKf6DmUWD1tjJr/b
CGhXlbUBJpXeYdCRYO1w6GTbSMORDQYRKG2e92AxYJAnaY1ssUZU9S80z8FQA9+dpZnhiIcq/DAt
AhWE7jF/YKiAjcFLLJmvku/oqTNqSmzfauiOuEUa7kmzZACF+Pi4SeJQ42GHUgwRoJndNmhDCLxM
PqklQnul2RYt1OtiBtMDqnCxKbUBpUEwF+2cnmnL3niUlPUZhm0ubFEwoLCiL9WZZzs3Z/RAIgW5
t0qWbqRPPqvHjdOn+VkgVtEw1aV3QC3qAZyml1CHJE5t4XTPVaIlcZuvr0fx4PRo2TA/l4AbG1bq
6Qp62VxSlhX3VIthrDnHiz8+CEgJGGIhUSShYMv5b+gP9VCVlD28/AFFcjz4Xx7arloNx9D1+Veq
Kn6b71+lt0bL6NtrX0ZYVB6EwhfLkPdKuZVEc5QQiY1oMe/uMoH1QFzK4zVzNMmAno241IRwtayy
+Ka/9kfPOgnVRZYnYNetSnlP5Fvqd+HhzukKyBTfagEmMsOxWVbtwLwUNKMzOB+ga13B6gbJ3IFn
ji78NmSVKAOE7JpN3D4Vu0vOUVaG6/xGXOw5T05IfnbVcWSwHVVNL3730a8qML3EmovPhWiRhaM2
Hmjg3TIdJwrRV6tnUpyGB9rl4+W3xsBCAxeED7TNmQavlVx3+V3oBVQYCYk3qpPC2PJtBvUrCPkS
c+qZ3yWXU6bg0x+H36wwnp3aeIAoCc7R52lVvkDeEnA0A9ENmrrnIq6UFojrkDt41WBpdQw0sq8J
K/XGHoJdzwB0ZTLLgVNi7DITv/O16/j9HkTQW4bTcEaaKubFz0Xfn5/uCjjJ1HFajLHZ4WugutrY
bV9r8SLSO1PSdcd+P5vjsFzzHTXPGVFFS19ipvwMuaydRZpyk1YtcF4/tq9DD6obxmsr4CweJqg9
t82yrn8MizlNCyWYQYZun7y5wnUFjo/D7tonpBn8aNVKSEBVcuODi5QOSguhV+Tmq+CKUVxFbFdm
DSBZzsAu1N5tGB6a6h/U6ZcsK2wUGy7wB5nZCb+SLTnNkSHdLilUSOqVGjYOmQSy44yrc4r6ETeb
sUANp/x8r7fgMMECCldyFG3wy+tLrcXVPYLWlN9/cyw/otJFcuzIRA0XYK/f0GUqKJ5KWRFVkLrB
t8uKcerNhR7mg3r0fe3NdDQ0Eb4QXskmZPQUmbBxqriQwX4BsJr4IR6GHA2E2oPJ7GB7SsIVPu+u
NxAitnqOgfSAZvOX4fXnyMBD9ed7vkoIkTWhnvt9pL8DVa7ZFwS+E0wUkIVPl0yNWpl+TX98n8RF
VClHwQKknXbZ/7Vr2Yi/28L59o57qIb9V7I55t58TBrFpaAGdEeZxFEu9aomb81iiXF8rnjCsaa7
oNbLdukau7P7mM5LkiukpuGdYM6EqtTYkjR6mS7xM6rrvyuseJFaZZC1EfIMqVyjix0XHKdFdRq2
MG7X0tM0UvbqiQ3meK0xUFwj1YD+2PbMbUanYWRihoUL/FiEYLLtIl1gxM7Cs+MqT8glsww2sjG6
N8nV21B+W9YpPAu8Y/gryD5uuhQl/oFolsVnOn+/5F2OCohh+lXhm3e2rablL+RyL+r57QZI3L2v
8LXYa+0ynfvJ3d59YBX052r9mW6wYBw7G4eI9RBUhXEsSuXOtfp43E6jdkpX7eCJu0eRMi2AGcH0
9lUkv6O+dPJx+M4s58dvHsW9ZMNdGWZdFv+0IAAeEDWdKorOjRxpUzFJd0NYJOLbW6gnE0fJFnsm
0K8P7O1HaEC0bNBSOpMjrWSPnsbrC92gt2pSWdqykohQk0irVmMw7neijue9Rax8zfy9PorM7SMw
9KT/dY3HnRrjpp+GqNkX6rExZHysLHXIY1KKtAIZ7cYlJg94GpBuWZOQENGRwaggj45tkASJpzea
hKu0tfk9TZKZyGQplCFLjxyJfdlsnA0gW+T9QP6Y14OEBcTC/wHx5RdtaHhlK/QVeXTRuIRihBbm
0tHBdJcdJHHi0TsDXZW95pPT+LKvvK5B0CNtyjxcK0f2+mlEwTPgTvURn8OHpBZyl1l6FVN/fSV/
5zIogKSFaa8odUbXwTfxxGzfHhX7sZnHfzNBOU1ZN95U6P/xw+hR0QwSXlYR3UUvHRespEcYfmnR
3218AviFblNCIcjI2+CGK8lNRSodcFq+WKXVLhx1FmBeBwbTl+1v2vvBCtT+FqBij+mAdKHL+ckx
hqle+EakERN8dNvV6Hm/+u9AC0c8OOuL+zhF2RbjzFP0FP1dx6DcnKv0MFf0OeRovjl7MQ7iCPEU
/BS4GGhsldLQdX4oqeJy6h3Rgu1XXHdl7HbsXUjqHtjmixw0Yi9ysW98cJG0EfV3WhRuXzJNMmw3
e5MsvQIoC59QGF4BF1kiqiRtwsXUpy6A0TinbsSnzCTTYXMmYVfZG7VHmGPr8F5qG3B3aQtSOZmg
NquEBcxon9qmAaUDJU6ErDanj8B1AvT/1/3cCq9FNKTpkM22HFMFX/iWO+g6cytGcRxS3+knyAnt
qQ5G1wa9GEcWaxef+sOyewdiR42ZMBECP0x+mOoEgyuRim4b2fRsfZSJGwX7nYIe3yeOW0pVSFNm
B4F62t6GTx/OdCcj+KQOm7Q9CKrn2rU0DYqa8kwm5BnxlKDBWQaQ8ft7zrPwIMXLJI8W8c1pehNn
tT/TbGSIhHHnd2OzSFPLXDojFBhU/6r7lywLwlS7v3NWiu19FDv6VsMrXySkinLWCn+mp0uSmmh+
F+MwY65XMO4PTwd3/vAE0kj4AbQUpg71zBZIe0BVdGCIKS8Sk69QJUHl1mgCZ2eOPyrI+ox3Udi5
XppIOD91R2v5nJz8f99ujLr3xgEZGrO3hrkFwCJR7OZPlJQXDinbxeHy1/oPEmT3pYEzQ4TQO8yE
KXxjvdcpqmLk1jaNnUvSGBJ6CLpyj+zgIYPJhd/yM4IMLnaAf/i4A0pRdz/jxmBTA8Ff5aKVx5LP
yvkjH+pSb1EBsW+og67TIhJtDcusaKMKWp3FRsYnMdPVqRSFNJgSavALceUKgdHWFRp7kT/94Kaa
NinH5Wpn7psg6ig6K6+QujRH0WAbVQfVwjnmSVAXbSY3WdhBjNEVH3ebjQnsazrmrvUzI12wRXQb
9G/eBMv737V+aZDG8HJOurevfWCreFoBf9qdb0hs5hCda8tL2EB6DoK+cDZi2o/WGXL64C998iYw
nv6Lnu64lJDTrEaCoLr1OPt6GDD3DQYY5Bfn4DcLGaxCyYsR4K0jPXICc4T4tc55sB1lVAhkn/Q5
HVK/D7vHQEcTJAIMY0btbco2RSRuZ1DlrCc80KMExka9XtZkf3h1xqvfBRDSyPbsKEy90WUQXS2V
NsVH7z/wLynW3a6Rckqzv4zRClIvrr0xJ2NBIG8r08HzmnWne+IhFFM0DW7PeAo+/mIWnDP+mCzG
DJ1W5CGSpA4KYiogQ+ub0hVung3jXWABNSEUPx+eaSmghC8YkjjJ0/AT5ssp0v6tSf7i9kOZhlZG
a4hUxHDz6XuPS/1wE2d9vvsKuiU4f8R4MZ7WhSV0SnJ66Z0SOuKPzcjVm5IavsghknCle8+LqTow
9yOQUzAoFLCXN3oWfgxIPY2rHpkRQ9tqOdP0O+G0tUymqjNL74fq7VjXALzTVHG4uRXvsSHlNIk1
jIVRJR6HzElq4c1lPBKx/9fqgpghZdukUUhGuvuaKo+/3ttcdLQl4uKvIRJW5xB7mJEk+NqzCF8g
WeMoq/ertJUparVxlkFAi4m0vNR17FLlloFDcRBNt1Dibjaramqi3Kvq0hiNHE7yPVF42lpAbSxG
nB3udR/DRF2bscJOBAapCypA6UkBGAkvZlMIevk7zko7DJEPfhFS0LMpuKdBGy44xO392uWDkckK
1zZemrYwKMX0EwuZaobVwE/+Ro7375fNe6fUBq83I9WwIkGQ6fza3yincpwhx0DWDUVvBbPevcov
OdQVEDp8BChcxBoaOj/9HZyatMQEbDMsVaJazr7O+WCW2zZFEJPYodg+gofPcphXiGUus0xOzZSd
3gAVqd2iiFu7mBUpu7QPDO0LdELK4j/gsTYXP2xRSxkJ2f+RPkx6DuDJHu5VlIKKtWfe17E+yBiA
ZL3bS1xF9Hj9Na3NVhYyQgdZ5RknPHD9Sc9fbxPbsFBsq0jdmovVVGcOXt3jj5P8ajFrRU1PIRNR
F1raJzEkOpaMNsj5ng5vBE6MX7W3v54aGfytZLPlP4Ke9PmoJ1RQ7o6gusgk0rZO/dpN0QVFD1US
7Y8PDib+CQZ1ku5c4a3w6vaT41BSx60QvzAJZ0oGFrjWljmMs78xGjWmVZKj9S/9/Ywttp5w9S4O
5DWuxcmhDR0qFFVMME+iy+We3TPkSQVzazkolE9YtMu+rTTddnoWxmJYmXtd25mJ08lkgo2HZrk1
imAkpCAPuGCotnQ2kMpact6Ocppzxc2FFHCvpaP13QcrD7QE0QNOy0NPrCVeqCK0IzeVwgzsgj+I
gt6J72ihDqwnbKYeyqqU9t1urtVAbHSvonxGr2hTHMZ8tJgb/HMmjScd3B94VCBspDPwHo1v/+Os
13vKg5iRIBVSYrz0FTrPXMJ28TJ04O6KWEMWaQEDcJRzqfqwD3D+A1l7hQ5Mwm85zpK1GnIvNYtm
oJ9sgWBNz+gzgcVB5kOO7VXwXUxKWLcIQjc/hOfweL808eiQdrpP1JeuazjJlB3H7sMAHu9REzSV
kkfPxV2PvH43U/dX/Qkqw4TAWbQYKZLHwX9RuqSocvJj3sh2LskCfzdifrvk2o0QGtpAPwVKDExf
lPecEaB3T/bhgtpPRscHO+Aubua+aXv7fU/4B6v1hveP16XlJuLjgqwcjT4Rlt9Nekkl5TKGn8I7
Bgf+it0zE3zYGmgmwzntMOskLDPPK4V3KLg+DLlwrhEgeEMmDgPGgaRfsVCP/C4I4xQgqG3mVe9o
+IZz9/X8lYqIjCiphe9BdECkWz4K+M0lH6Krf1ozCVuMut3cL7ff1gse3OuU5flM+cP9U3r6JuDl
7Cof/v418d8DTothJhP4l2PgA5TCmKXQMiKQ1agD4xXHbZ1l4RcHDlLKVVmQXPNTOT6+Ww2RHuYp
tYnU1y5yHHdWzALT5WkGohlrKZ3au6zHI6qWXY6l956HfoSB7/VEcuJPYzCvFVAp1VJ9drwLs9c/
HtvhoBS/yl8ATg==
`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:59:33 11/03/2016
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM is
Port (
CLK : in STD_LOGIC;
ACCMEM : in STD_LOGIC;
MEM_WE : in STD_LOGIC;
addr : inout STD_LOGIC_VECTOR (15 downto 0);
data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram1Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1OE : out STD_LOGIC;
Ram1WE : out STD_LOGIC;
Ram1EN : out STD_LOGIC;
wrn : out STD_LOGIC;
rdn : out STD_LOGIC);
end RAM;
architecture Behavioral of RAM is
signal state1 : integer range 0 to 3 := 0;
signal state2 : integer range 0 to 10 := 0;
begin
wrn <= '1';
rdn <= '1';
Ram1Addr(17 downto 16) <= "00";
process(CLK)
begin
if (MEM_WE = '0') and (ACCMEM = '1') then
if (CLK'EVENT) and (CLK = '1') then
case state1 is
when 0 =>
state1 <= 1;
Ram1EN <= '1';
when 1 =>
state1 <= 2;
Ram1EN <= '0';
Ram1OE <= '1';
Ram1WE <= '1';
when 2 =>
state1 <= 3;
RAM1Addr(15 downto 0) <= addr;
RAM1Data <= data;
Ram1WE <= '1';
when 3 =>
Ram1WE <= '0';
state1 <= 0;
when others =>
null;
end case;
end if;
end if;
end process;
process(CLK)
begin
if (MEM_WE = '1') and (ACCMEM = '0') then
if (CLK'EVENT) and (CLK = '1') then
case state2 is
when 0 =>
state2 <= 1;
Ram1EN <= '0';
Ram1OE <= '0';
Ram1WE <= '1';
when 1 =>
state2 <= 2;
RAM1Data <= "ZZZZZZZZZZZZZZZZ";
when 2 =>
state2 <= 3;
RAM1Addr(15 downto 0) <= addr;
when 3 =>
data <= Ram1Data;
state2 <= 0;
when others =>
null;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: FloydSteinberg2PRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FloydSteinberg2PRAM IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END FloydSteinberg2PRAM;
ARCHITECTURE SYN OF floydsteinberg2pram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(4 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 10,
widthad_b => 10,
width_a => 5,
width_b => 5,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => clock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "5120"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "5"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "5"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "5"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "5"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL "data[4..0]"
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 5 0 data 0 0 5 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q_b 0 0 5 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FloydSteinberg2PRAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FloydSteinberg2PRAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FloydSteinberg2PRAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FloydSteinberg2PRAM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FloydSteinberg2PRAM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_ztex
-- File: ahb2mig_ztex.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus.
-------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <belousov.oleg@gmail.com>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_ztex is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
MEMCLK_PERIOD : integer := 5000
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem : in std_logic
);
end ;
architecture rtl of ahb2mig_ztex is
component mig_37
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
signal r, rin : reg_type;
signal i : mcb_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
MCB_inst : entity work.mig_37 generic map(
C3_RST_ACT_LOW => 1,
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_MEMCLK_PERIOD => MEMCLK_PERIOD
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_sys_clk => clk_mem,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity rt_reconf is
port (
-- OSIF FIFO ports
OSIF_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_Sw2Hw_Empty : in std_logic;
OSIF_Sw2Hw_RE : out std_logic;
OSIF_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_Hw2Sw_Full : in std_logic;
OSIF_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_Hwt2Mem_Full : in std_logic;
MEMIF_Hwt2Mem_WE : out std_logic;
MEMIF_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_Mem2Hwt_Empty : in std_logic;
MEMIF_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
HWT_Signal : in std_logic;
DEBUG : out std_logic_vector(110 downto 0)
);
end rt_reconf;
architecture matrixmul of rt_reconf is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of HWT_Clk: SIGNAL is "xilinx.com:signal:clock:1.0 HWT_Clk CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of HWT_Clk: SIGNAL is "ASSOCIATED_RESET HWT_Rst, ASSOCIATED_BUSIF OSIF_Sw2Hw:OSIF_Hw2Sw:MEMIF_Hwt2Mem:MEMIF_Mem2Hwt";
ATTRIBUTE X_INTERFACE_INFO of HWT_Rst: SIGNAL is "xilinx.com:signal:reset:1.0 HWT_Rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER of HWT_Rst: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Sw2Hw_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 OSIF_Sw2Hw FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Sw2Hw_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 OSIF_Sw2Hw FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Sw2Hw_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 OSIF_Sw2Hw FIFO_S_RE";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Hw2Sw_Data: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 OSIF_Hw2Sw FIFO_M_Data";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Hw2Sw_Full: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 OSIF_Hw2Sw FIFO_M_Full";
ATTRIBUTE X_INTERFACE_INFO of OSIF_Hw2Sw_WE: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 OSIF_Hw2Sw FIFO_M_WE";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_Data: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Hwt2Mem FIFO_M_Data";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_Full: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Hwt2Mem FIFO_M_Full";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Hwt2Mem_WE: SIGNAL is "cs.upb.de:reconos:FIFO_M:1.0 MEMIF_Hwt2Mem FIFO_M_WE";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_Data: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Mem2Hwt FIFO_S_Data";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_Empty: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Mem2Hwt FIFO_S_Empty";
ATTRIBUTE X_INTERFACE_INFO of MEMIF_Mem2Hwt_RE: SIGNAL is "cs.upb.de:reconos:FIFO_S:1.0 MEMIF_Mem2Hwt FIFO_S_RE";
type STATE_TYPE is (
STATE_INIT,
STATE_GET_ADDR2MADDRS,
STATE_READ_MADDRS,
STATE_READ_MATRIX_B,
STATE_READ_MATRIX_ROW_FROM_A,
STATE_MULTIPLY_MATRIX_ROW,
STATE_WRITE_MATRIX_ROW_TO_C,
STATE_ACK,
STATE_THREAD_EXIT
);
component matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_WE : out std_logic
);
end component;
constant C_LINE_LEN_MATRIX : integer := 128;
-- const for matrixes A and C
constant C_LOCAL_RAM_SIZE_MATRIX_A_C : integer := C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C : integer := integer(ceil(log2(real(C_LOCAL_RAM_SIZE_MATRIX_A_C))));
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C : integer := 4 * C_LOCAL_RAM_SIZE_MATRIX_A_C;
type LOCAL_MEMORY_TYPE_MATRIX_A_C is array(0 to C_LOCAL_RAM_SIZE_MATRIX_A_C - 1) of std_logic_vector(31 downto 0);
-- const for matrix B
constant C_LOCAL_RAM_SIZE_MATRIX_B : integer := C_LINE_LEN_MATRIX*C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B : integer := integer(ceil(log2(real(C_LOCAL_RAM_SIZE_MATRIX_B))));
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B : integer := 4 * C_LOCAL_RAM_SIZE_MATRIX_B;
type LOCAL_MEMORY_TYPE_MATRIX_B is array(0 to C_LOCAL_RAM_SIZE_MATRIX_B - 1) of std_logic_vector(31 downto 0);
-- communication with microblaze core
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal ignore : std_logic_vector(31 downto 0);
-- maddr is an acronym for "matrix address" (address that points to a matrix)
constant C_MADDRS : integer := 3;
type MADDR_BOX_TYPE is array(0 to C_MADDRS-1) of std_logic_vector(31 downto 0);
-- container for adresses pointing to the first element of matrixes A, B and C
signal maddrs : MADDR_BOX_TYPE;
-- points to pointers to the matrixes
signal addr2maddrs : std_logic_vector(31 downto 0);
-- temporary signals
signal temp_addr_A : std_logic_vector(31 downto 0);
signal temp_addr_C : std_logic_vector(31 downto 0);
-- fsm state
signal state : STATE_TYPE;
-- additional data for memif interfaces
signal len_data_MATRIX_A_C : std_logic_vector(31 downto 0);
signal len_data_MATRIX_B : std_logic_vector(31 downto 0);
-- osif, memif and different local BRAM interfaces
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram_A : i_ram_t;
signal o_ram_A : o_ram_t;
signal i_ram_B : i_ram_t;
signal o_ram_B : o_ram_t;
signal i_ram_C : i_ram_t;
signal o_ram_C : o_ram_t;
signal o_RAM_A_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_A_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_WE_reconos : std_logic;
signal i_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal o_RAM_B_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_WE_reconos : std_logic;
signal i_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_WE_reconos : std_logic;
signal i_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal i_RAM_A_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal i_RAM_B_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_WE_mul : std_logic;
shared variable local_ram_a : LOCAL_MEMORY_TYPE_MATRIX_A_C;
shared variable local_ram_b : LOCAL_MEMORY_TYPE_MATRIX_B;
shared variable local_ram_c : LOCAL_MEMORY_TYPE_MATRIX_A_C;
signal multiplier_start : std_logic;
signal multiplier_done : std_logic;
signal status : std_logic_vector(31 downto 0);
begin
-- local BRAM read and write access
local_ram_ctrl_1 : process (HWT_Clk) is
begin
if (rising_edge(HWT_Clk)) then
if (o_RAM_A_WE_reconos = '1') then
local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_reconos))) := o_RAM_A_Data_reconos;
end if;
if (o_RAM_B_WE_reconos = '1') then
local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_reconos))) := o_RAM_B_Data_reconos;
end if;
if (o_RAM_C_WE_reconos = '0') then
i_RAM_C_Data_reconos <= local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (HWT_Clk) is
begin
if (rising_edge(HWT_Clk)) then
if (o_RAM_C_WE_mul = '1') then
local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_mul))) := o_RAM_C_Data_mul;
else
i_RAM_A_Data_mul <= local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_mul)));
i_RAM_B_Data_mul <= local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_mul)));
end if;
end if;
end process;
-- the matrix multiplication module
matrixmultiplier_i : matrixmultiplier
generic map(
G_LINE_LEN_MATRIX => C_LINE_LEN_MATRIX,
G_RAM_DATA_WIDTH => 32,
G_RAM_SIZE_MATRIX_A_C => C_LOCAL_RAM_SIZE_MATRIX_A_C,
G_RAM_ADDR_WIDTH_MATRIX_A_C => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C,
G_RAM_SIZE_MATRIX_B => C_LOCAL_RAM_SIZE_MATRIX_B,
G_RAM_ADDR_WIDTH_MATRIX_B => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B
)
port map(
clk => HWT_Clk,
reset => HWT_Rst,
start => multiplier_start,
done => multiplier_done,
o_RAM_A_Addr => o_RAM_A_Addr_mul,
i_RAM_A_Data => i_RAM_A_Data_mul,
o_RAM_B_Addr => o_RAM_B_Addr_mul,
i_RAM_B_Data => i_RAM_B_Data_mul,
o_RAM_C_Addr => o_RAM_C_Addr_mul,
o_RAM_C_Data => o_RAM_C_Data_mul,
o_RAM_C_WE => o_RAM_C_WE_mul
);
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_Sw2Hw_Data,
OSIF_Sw2Hw_Empty,
OSIF_Sw2Hw_RE,
OSIF_Hw2Sw_Data,
OSIF_Hw2Sw_Full,
OSIF_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_Mem2Hwt_Data,
MEMIF_Mem2Hwt_Empty,
MEMIF_Mem2Hwt_RE,
MEMIF_Hwt2Mem_Data,
MEMIF_Hwt2Mem_Full,
MEMIF_Hwt2Mem_WE
);
ram_setup (
i_ram_A,
o_ram_A,
o_RAM_A_Addr_reconos_2,
o_RAM_A_Data_reconos,
i_RAM_A_Data_reconos,
o_RAM_A_WE_reconos
);
ram_setup (
i_ram_B,
o_ram_B,
o_RAM_B_Addr_reconos_2,
o_RAM_B_Data_reconos,
i_RAM_B_Data_reconos,
o_RAM_B_WE_reconos
);
ram_setup (
i_ram_C,
o_ram_C,
o_RAM_C_Addr_reconos_2,
o_RAM_C_Data_reconos,
i_RAM_C_Data_reconos,
o_RAM_C_WE_reconos
);
o_RAM_A_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_A_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
o_RAM_B_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1) <= o_RAM_B_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B ) to 31);
o_RAM_C_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_C_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
-- os and memory synchronisation state machine
reconos_fsm : process(HWT_Clk,o_osif,o_memif,o_ram_a,o_ram_b,o_ram_c) is
variable done : boolean;
variable addr_pos : integer;
variable calculated_rows : integer;
begin
if rising_edge(HWT_Clk) then
if HWT_Rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram_A);
ram_reset(o_ram_B);
ram_reset(o_ram_C);
multiplier_start <= '0';
done := false;
calculated_rows := 0;
len_data_MATRIX_A_C <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C, 32);
len_data_MATRIX_B <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B , 32);
-- important to know:
-- maddrs(0) = C, maddrs(1) = B, maddrs(2) = A
addr2maddrs <= (others => '0');
addr_pos := C_MADDRS - 1;
for i in 0 to (C_MADDRS - 1) loop
maddrs(i) <= (others => '0');
end loop;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_INIT;
else
case state is
when STATE_INIT =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
osif_read(i_osif, o_osif, ignore, done);
if done then
state <= STATE_GET_ADDR2MADDRS;
end if;
end if;
-- Get address pointing to the addresses pointing to the 3 matrixes via FSL.
when STATE_GET_ADDR2MADDRS =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
--osif_mbox_get(i_osif, o_osif, MBOX_RECV, addr2maddrs, done);
osif_mbox_tryget(i_osif, o_osif, MBOX_RECV, addr2maddrs, status, done);
if (done) then
if status = x"00000000" then
state <= STATE_GET_ADDR2MADDRS;
else
addr2maddrs <= addr2maddrs(31 downto 2) & "00";
addr_pos := C_MADDRS - 1;
state <= STATE_READ_MADDRS;
end if;
end if;
end if;
-- Read addresses pointing to input matrixes A, B and output matrix C from main memory.
when STATE_READ_MADDRS =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
memif_read_word(i_memif, o_memif, addr2maddrs, maddrs(addr_pos), done);
if done then
if (addr_pos = 0) then
state <= STATE_READ_MATRIX_B;
else
addr_pos := addr_pos - 1;
addr2maddrs <= conv_std_logic_vector(unsigned(addr2maddrs) + 4, 32);
end if;
end if;
end if;
-- Read matrix B from main memory.
when STATE_READ_MATRIX_B =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
memif_read(i_ram_B, o_ram_B, i_memif, o_memif, maddrs(1), X"00000000", len_data_MATRIX_B, done);
if done then
temp_addr_A <= maddrs(2);
temp_addr_C <= maddrs(0);
state <= STATE_READ_MATRIX_ROW_FROM_A;
end if;
end if;
-- Read a row of matrix A.
when STATE_READ_MATRIX_ROW_FROM_A =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
memif_read(i_ram_A, o_ram_A, i_memif, o_memif, temp_addr_A, X"00000000", len_data_MATRIX_A_C, done);
if done then
multiplier_start <= '1';
state <= STATE_MULTIPLY_MATRIX_ROW;
end if;
end if;
-- Multiply row of matrix A with matrix B.
when STATE_MULTIPLY_MATRIX_ROW =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
multiplier_start <= '0';
if (multiplier_done = '1') then
calculated_rows := calculated_rows + 1;
state <= STATE_WRITE_MATRIX_ROW_TO_C;
end if;
end if;
-- Write multiplication result (row of matrix C) to main memory.
when STATE_WRITE_MATRIX_ROW_TO_C =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
memif_write(i_ram_C, o_ram_C, i_memif, o_memif, X"00000000", temp_addr_C, len_data_MATRIX_A_C, done);
if (done) then
if (calculated_rows < C_LINE_LEN_MATRIX) then
-- Calculate new temporary addresses
-- => to fetch next matrix row of matrix A
-- => to store calculated values to next matrix row of matrix C
temp_addr_A <= conv_std_logic_vector(unsigned(temp_addr_A) + C_LINE_LEN_MATRIX*4, 32);
temp_addr_C <= conv_std_logic_vector(unsigned(temp_addr_C) + C_LINE_LEN_MATRIX*4, 32);
state <= STATE_READ_MATRIX_ROW_FROM_A;
else
state <= STATE_ACK;
end if;
end if;
end if;
-- We finished calculating matrix multiplication A * B = C.
when STATE_ACK =>
if HWT_SIGNAL = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
state <= STATE_THREAD_EXIT;
else
osif_mbox_put(i_osif, o_osif, MBOX_SEND, maddrs(addr_pos), ignore, done);
if (done) then
calculated_rows := 0;
addr_pos := C_MADDRS - 1;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
end if;
end if;
-- Terminate hardware thread.
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif, o_osif);
end case;
end if;
end if;
end process;
end architecture matrixmul;
|
-- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ## ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- #####################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ps2 is
generic (FilterSize : positive := 3);
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
CODE : out std_logic_vector(7 downto 0);
DONE : out std_logic;
ERROR : out std_logic );
end ps2;
architecture rtl of ps2 is
signal Filter : unsigned(FilterSize-1 downto 0);
signal Filter_High : unsigned(FilterSize-1 downto 0);
signal Filter_Low : unsigned(FilterSize-1 downto 0);
signal PS2_CLK_LOCK : std_logic;
signal PS2_CLK_TICK : std_logic;
signal shift_state : unsigned(3 downto 0);
signal CODE_TEMP : std_logic_vector(7 downto 0);
signal parity : std_logic;
begin
Filter_High <= (others=>'1');
Filter_Low <= (others=>'0');
clockfilter : process (CLK) -- PS2 Clock Filter
begin
if rising_edge(CLK) then
if RESET = '1' then
Filter <= (others=>'0');
PS2_CLK_LOCK <= '0';
PS2_CLK_TICK <= '1';
else
PS2_CLK_TICK <= '1';
if PS2_CLK = '0' then
if Filter /= Filter_High then
Filter <= Filter + 1;
else
PS2_CLK_LOCK <= '1';
if PS2_CLK_LOCK = '0' then
PS2_CLK_TICK <= '0';
end if;
end if;
else
if Filter /= Filter_Low then
Filter <= Filter - 1;
else
PS2_CLK_LOCK <= '0';
end if;
end if;
end if;
end if;
end process;
shiftregister : process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
shift_state <= "0000";
CODE_TEMP <= "00000000";
DONE <= '0';
ERROR <= '0';
else
DONE <= '0';
ERROR <= '0';
if PS2_CLK_TICK = '0' then -- PS2 Clock Detected
case to_integer(shift_state) is
when 0 => -- start bit
if PS2_DATA = '0' then
shift_state <= "0001";
parity <= '1';
else
shift_state <= "0000"; -- error
ERROR <= '1';
end if;
when 1 to 8 => -- data bits
CODE_TEMP(to_integer(shift_state-1)) <= PS2_DATA;
shift_state <= shift_state + 1;
parity <= parity xor PS2_DATA;
when 9 => -- parity bit
if parity = PS2_DATA then
shift_state <= shift_state + 1;
else
shift_state <= "0000"; -- error
ERROR <= '1';
end if;
when 10 => -- stop bit
if PS2_DATA = '1' then
DONE <= '1';
CODE <= CODE_TEMP;
shift_state <= "0000";
else
shift_state <= "0000"; -- error
ERROR <= '1';
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- $Id: ram_loader-c.vhd,v 1.1 2005-04-10 18:02:32 arniml Exp $
-------------------------------------------------------------------------------
configuration ram_loader_rtl_c0 of ram_loader is
for rtl
end for;
end ram_loader_rtl_c0;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable_n, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable_n <= '0' when address(31 downto 28) = "0000" else '1';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable_n,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
|
/*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with fpgaNES. If not, see <http://www.gnu.org/licenses/>.
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity sequencer is
port
(
i_opcode : in std_logic_vector(7 downto 0);
i_cycle : in std_logic_vector(2 downto 0);
o_ctrl_op : out ctrl_op_t;
o_pc_op : out pc_op_t;
o_in_op : out in_op_t;
o_out_op : out out_op_t;
o_reg_op : out reg_op_t;
o_flags_op : out flags_op_t;
o_alu_op : out alu_op_t;
o_addr_op : out addr_op_t;
o_alu_a_op : out alu_inp_t;
o_alu_b_op : out alu_inp_t;
o_branch_at_cycle_1 : out boolean;
o_branch_at_cycle_2 : out boolean
);
end sequencer;
architecture behavioral of sequencer is
signal s_addr : std_ulogic_vector(10 downto 0);
begin
-- Controller
with s_addr select o_ctrl_op <=
don when b"0110_1001_001", -- ADC / Immediate
don when b"0110_0101_010", -- ADC / Zero Page
don when b"0111_0101_011", -- ADC / Zero Page,X
don when b"0110_1101_011", -- ADC / Absolute
alc when b"0111_1101_010", -- ADC / Absolute,X
don when b"0111_1101_100", -- ADC / Absolute,X
alc when b"0111_1001_010", -- ADC / Absolute,Y
don when b"0111_1001_100", -- ADC / Absolute,Y
don when b"0110_0001_101", -- ADC / (Indirect,X)
alc when b"0111_0001_011", -- ADC / (Indirect),Y
don when b"0111_0001_101", -- ADC / (Indirect),Y
don when b"0010_1001_001", -- AND / Immediate
don when b"0010_0101_010", -- AND / Zero Page
don when b"0011_0101_011", -- AND / Zero Page,X
don when b"0010_1101_011", -- AND / Absolute
alc when b"0011_1101_010", -- AND / Absolute,X
don when b"0011_1101_100", -- AND / Absolute,X
alc when b"0011_1001_010", -- AND / Absolute,Y
don when b"0011_1001_100", -- AND / Absolute,Y
don when b"0010_0001_101", -- AND / (Indirect,X)
alc when b"0011_0001_011", -- AND / (Indirect),Y
don when b"0011_0001_101", -- AND / (Indirect),Y
don when b"0000_1010_001", -- ASL / Accumulator
don when b"0000_0110_100", -- ASL / Zero Page
don when b"0001_0110_101", -- ASL / Zero Page,X
don when b"0000_1110_101", -- ASL / Absolute
don when b"0001_1110_110", -- ASL / Absolute,X
bcc when b"1001_0000_001", -- BCC / Relative
don when b"1001_0000_011", -- BCC / Relative
bcs when b"1011_0000_001", -- BCS / Relative
don when b"1011_0000_011", -- BCS / Relative
beq when b"1111_0000_001", -- BEQ / Relative
don when b"1111_0000_011", -- BEQ / Relative
don when b"0010_0100_010", -- BIT / Zero Page
don when b"0010_1100_011", -- BIT / Absolute
bmi when b"0011_0000_001", -- BMI / Relative
don when b"0011_0000_011", -- BMI / Relative
bne when b"1101_0000_001", -- BNE / Relative
don when b"1101_0000_011", -- BNE / Relative
bpl when b"0001_0000_001", -- BPL / Relative
don when b"0001_0000_011", -- BPL / Relative
don when b"0000_0000_110", -- BRK / Implied
bvc when b"0101_0000_001", -- BVC / Relative
don when b"0101_0000_011", -- BVC / Relative
bvs when b"0111_0000_001", -- BVS / Relative
don when b"0111_0000_011", -- BVS / Relative
don when b"0001_1000_001", -- CLC / Implied
don when b"1101_1000_001", -- CLD / Implied
don when b"0101_1000_001", -- CLI / Implied
don when b"1011_1000_001", -- CLV / Implied
don when b"1100_1001_001", -- CMP / Immediate
don when b"1100_0101_010", -- CMP / Zero Page
don when b"1101_0101_011", -- CMP / Zero Page,X
don when b"1100_1101_011", -- CMP / Absolute
alc when b"1101_1101_010", -- CMP / Absolute,X
don when b"1101_1101_100", -- CMP / Absolute,X
alc when b"1101_1001_010", -- CMP / Absolute,Y
don when b"1101_1001_100", -- CMP / Absolute,Y
don when b"1100_0001_101", -- CMP / (Indirect,X)
alc when b"1101_0001_011", -- CMP / (Indirect),Y
don when b"1101_0001_101", -- CMP / (Indirect),Y
don when b"1110_0000_001", -- CPX / Immediate
don when b"1110_0100_010", -- CPX / Zero Page
don when b"1110_1100_011", -- CPX / Absolute
don when b"1100_0000_001", -- CPY / Immediate
don when b"1100_0100_010", -- CPY / Zero Page
don when b"1100_1100_011", -- CPY / Absolute
don when b"1100_0110_100", -- DEC / Zero Page
don when b"1101_0110_101", -- DEC / Zero Page,X
don when b"1100_1110_101", -- DEC / Absolute
don when b"1101_1110_110", -- DEC / Absolute,X
don when b"1100_1010_001", -- DEX / Implied
don when b"1000_1000_001", -- DEY / Implied
don when b"0100_1001_001", -- EOR / Immediate
don when b"0100_0101_010", -- EOR / Zero Page
don when b"0101_0101_011", -- EOR / Zero Page,X
don when b"0100_1101_011", -- EOR / Absolute
alc when b"0101_1101_010", -- EOR / Absolute,X
don when b"0101_1101_100", -- EOR / Absolute,X
alc when b"0101_1001_010", -- EOR / Absolute,Y
don when b"0101_1001_100", -- EOR / Absolute,Y
don when b"0100_0001_101", -- EOR / (Indirect,X)
alc when b"0101_0001_011", -- EOR / (Indirect),Y
don when b"0101_0001_101", -- EOR / (Indirect),Y
don when b"1110_0110_100", -- INC / Zero Page
don when b"1111_0110_101", -- INC / Zero Page,X
don when b"1110_1110_101", -- INC / Absolute
don when b"1111_1110_110", -- INC / Absolute,X
don when b"0000_0011_110", -- INT / Implied
don when b"1110_1000_001", -- INX / Implied
don when b"1100_1000_001", -- INY / Implied
don when b"0100_1100_010", -- JMP / Absolute
don when b"0110_1100_100", -- JMP / Indirect
don when b"0010_0000_101", -- JSR / Absolute
don when b"1010_1001_001", -- LDA / Immediate
don when b"1010_0101_010", -- LDA / Zero Page
don when b"1011_0101_011", -- LDA / Zero Page,X
don when b"1010_1101_011", -- LDA / Absolute
alc when b"1011_1101_010", -- LDA / Absolute,X
don when b"1011_1101_100", -- LDA / Absolute,X
alc when b"1011_1001_010", -- LDA / Absolute,Y
don when b"1011_1001_100", -- LDA / Absolute,Y
don when b"1010_0001_101", -- LDA / (Indirect,X)
alc when b"1011_0001_011", -- LDA / (Indirect),Y
don when b"1011_0001_101", -- LDA / (Indirect),Y
don when b"1010_0010_001", -- LDX / Immediate
don when b"1010_0110_010", -- LDX / Zero Page
don when b"1011_0110_011", -- LDX / Zero Page,Y
don when b"1010_1110_011", -- LDX / Absolute
alc when b"1011_1110_010", -- LDX / Absolute,Y
don when b"1011_1110_100", -- LDX / Absolute,Y
don when b"1010_0000_001", -- LDY / Immediate
don when b"1010_0100_010", -- LDY / Zero Page
don when b"1011_0100_011", -- LDY / Zero Page,X
don when b"1010_1100_011", -- LDY / Absolute
alc when b"1011_1100_010", -- LDY / Absolute,X
don when b"1011_1100_100", -- LDY / Absolute,X
don when b"0100_1010_001", -- LSR / Accumulator
don when b"0100_0110_100", -- LSR / Zero Page
don when b"0101_0110_101", -- LSR / Zero Page,X
don when b"0100_1110_101", -- LSR / Absolute
don when b"0101_1110_110", -- LSR / Absolute,X
don when b"0000_0100_110", -- NMI / Implied
don when b"1110_1010_001", -- NOP / Implied
don when b"0000_1001_001", -- ORA / Immediate
don when b"0000_0101_010", -- ORA / Zero Page
don when b"0001_0101_011", -- ORA / Zero Page,X
don when b"0000_1101_011", -- ORA / Absolute
alc when b"0001_1101_010", -- ORA / Absolute,X
don when b"0001_1101_100", -- ORA / Absolute,X
alc when b"0001_1001_010", -- ORA / Absolute,Y
don when b"0001_1001_100", -- ORA / Absolute,Y
don when b"0000_0001_101", -- ORA / (Indirect,X)
alc when b"0001_0001_011", -- ORA / (Indirect),Y
don when b"0001_0001_101", -- ORA / (Indirect),Y
don when b"0100_1000_010", -- PHA / Implied
don when b"0000_1000_010", -- PHP / Implied
don when b"0110_1000_011", -- PLA / Implied
don when b"0010_1000_011", -- PLP / Implied
don when b"0010_1010_001", -- ROL / Accumulator
don when b"0010_0110_100", -- ROL / Zero Page
don when b"0011_0110_101", -- ROL / Zero Page,X
don when b"0010_1110_101", -- ROL / Absolute
don when b"0011_1110_110", -- ROL / Absolute,X
don when b"0110_1010_001", -- ROR / Accumulator
don when b"0110_0110_100", -- ROR / Zero Page
don when b"0111_0110_101", -- ROR / Zero Page,X
don when b"0110_1110_101", -- ROR / Absolute
don when b"0111_1110_110", -- ROR / Absolute,X
don when b"0000_0010_011", -- RST / Implied
don when b"0100_0000_101", -- RTI / Implied
don when b"0110_0000_101", -- RTS / Implied
don when b"1110_1001_001", -- SBC / Immediate
don when b"1110_0101_010", -- SBC / Zero Page
don when b"1111_0101_011", -- SBC / Zero Page,X
don when b"1110_1101_011", -- SBC / Absolute
alc when b"1111_1101_010", -- SBC / Absolute,X
don when b"1111_1101_100", -- SBC / Absolute,X
alc when b"1111_1001_010", -- SBC / Absolute,Y
don when b"1111_1001_100", -- SBC / Absolute,Y
don when b"1110_0001_101", -- SBC / (Indirect,X)
alc when b"1111_0001_011", -- SBC / (Indirect),Y
don when b"1111_0001_101", -- SBC / (Indirect),Y
don when b"0011_1000_001", -- SEC / Implied
don when b"1111_1000_001", -- SED / Implied
don when b"0111_1000_001", -- SEI / Implied
don when b"1000_0101_010", -- STA / Zero Page
don when b"1001_0101_011", -- STA / Zero Page,X
don when b"1000_1101_011", -- STA / Absolute
don when b"1001_1101_100", -- STA / Absolute,X
don when b"1001_1001_100", -- STA / Absolute,Y
don when b"1000_0001_101", -- STA / (Indirect,X)
don when b"1001_0001_101", -- STA / (Indirect),Y
don when b"1000_0110_010", -- STX / Zero Page
don when b"1001_0110_011", -- STX / Zero Page,Y
don when b"1000_1110_011", -- STX / Absolute
don when b"1000_0100_010", -- STY / Zero Page
don when b"1001_0100_011", -- STY / Zero Page,X
don when b"1000_1100_011", -- STY / Absolute
don when b"1010_1010_001", -- TAX / Implied
don when b"1010_1000_001", -- TAY / Implied
don when b"1011_1010_001", -- TSX / Implied
don when b"1000_1010_001", -- TXA / Implied
don when b"1001_1010_001", -- TXS / Implied
don when b"1001_1000_001", -- TYA / Implied
nop when others;
-- Program-Counter
with s_addr select o_pc_op <=
inc when b"0110_1001_000", -- ADC / Immediate
inc when b"0110_0101_000", -- ADC / Zero Page
inc when b"0111_0101_000", -- ADC / Zero Page,X
inc when b"0110_1101_000", -- ADC / Absolute
inc when b"0110_1101_001", -- ADC / Absolute
inc when b"0111_1101_000", -- ADC / Absolute,X
inc when b"0111_1101_001", -- ADC / Absolute,X
inc when b"0111_1001_000", -- ADC / Absolute,Y
inc when b"0111_1001_001", -- ADC / Absolute,Y
inc when b"0110_0001_000", -- ADC / (Indirect,X)
inc when b"0111_0001_000", -- ADC / (Indirect),Y
inc when b"0010_1001_000", -- AND / Immediate
inc when b"0010_0101_000", -- AND / Zero Page
inc when b"0011_0101_000", -- AND / Zero Page,X
inc when b"0010_1101_000", -- AND / Absolute
inc when b"0010_1101_001", -- AND / Absolute
inc when b"0011_1101_000", -- AND / Absolute,X
inc when b"0011_1101_001", -- AND / Absolute,X
inc when b"0011_1001_000", -- AND / Absolute,Y
inc when b"0011_1001_001", -- AND / Absolute,Y
inc when b"0010_0001_000", -- AND / (Indirect,X)
inc when b"0011_0001_000", -- AND / (Indirect),Y
inc when b"0000_0110_000", -- ASL / Zero Page
inc when b"0001_0110_000", -- ASL / Zero Page,X
inc when b"0000_1110_000", -- ASL / Absolute
inc when b"0000_1110_001", -- ASL / Absolute
inc when b"0001_1110_000", -- ASL / Absolute,X
inc when b"0001_1110_001", -- ASL / Absolute,X
inc when b"1001_0000_000", -- BCC / Relative
pla when b"1001_0000_001", -- BCC / Relative
pha when b"1001_0000_010", -- BCC / Relative
inc when b"1011_0000_000", -- BCS / Relative
pla when b"1011_0000_001", -- BCS / Relative
pha when b"1011_0000_010", -- BCS / Relative
inc when b"1111_0000_000", -- BEQ / Relative
pla when b"1111_0000_001", -- BEQ / Relative
pha when b"1111_0000_010", -- BEQ / Relative
inc when b"0010_0100_000", -- BIT / Zero Page
inc when b"0010_1100_000", -- BIT / Absolute
inc when b"0010_1100_001", -- BIT / Absolute
inc when b"0011_0000_000", -- BMI / Relative
pla when b"0011_0000_001", -- BMI / Relative
pha when b"0011_0000_010", -- BMI / Relative
inc when b"1101_0000_000", -- BNE / Relative
pla when b"1101_0000_001", -- BNE / Relative
pha when b"1101_0000_010", -- BNE / Relative
inc when b"0001_0000_000", -- BPL / Relative
pla when b"0001_0000_001", -- BPL / Relative
pha when b"0001_0000_010", -- BPL / Relative
enb when b"0000_0000_000", -- BRK / Implied
daq when b"0000_0000_110", -- BRK / Implied
inc when b"0101_0000_000", -- BVC / Relative
pla when b"0101_0000_001", -- BVC / Relative
pha when b"0101_0000_010", -- BVC / Relative
inc when b"0111_0000_000", -- BVS / Relative
pla when b"0111_0000_001", -- BVS / Relative
pha when b"0111_0000_010", -- BVS / Relative
inc when b"1100_1001_000", -- CMP / Immediate
inc when b"1100_0101_000", -- CMP / Zero Page
inc when b"1101_0101_000", -- CMP / Zero Page,X
inc when b"1100_1101_000", -- CMP / Absolute
inc when b"1100_1101_001", -- CMP / Absolute
inc when b"1101_1101_000", -- CMP / Absolute,X
inc when b"1101_1101_001", -- CMP / Absolute,X
inc when b"1101_1001_000", -- CMP / Absolute,Y
inc when b"1101_1001_001", -- CMP / Absolute,Y
inc when b"1100_0001_000", -- CMP / (Indirect,X)
inc when b"1101_0001_000", -- CMP / (Indirect),Y
inc when b"1110_0000_000", -- CPX / Immediate
inc when b"1110_0100_000", -- CPX / Zero Page
inc when b"1110_1100_000", -- CPX / Absolute
inc when b"1110_1100_001", -- CPX / Absolute
inc when b"1100_0000_000", -- CPY / Immediate
inc when b"1100_0100_000", -- CPX / Zero Page
inc when b"1100_1100_000", -- CPX / Absolute
inc when b"1100_1100_001", -- CPX / Absolute
inc when b"1100_0110_000", -- DEC / Zero Page
inc when b"1101_0110_000", -- DEC / Zero Page,X
inc when b"1100_1110_000", -- DEC / Absolute
inc when b"1100_1110_001", -- DEC / Absolute
inc when b"1101_1110_000", -- DEC / Absolute,X
inc when b"1101_1110_001", -- DEC / Absolute,X
inc when b"0100_1001_000", -- EOR / Immediate
inc when b"0100_0101_000", -- EOR / Zero Page
inc when b"0101_0101_000", -- EOR / Zero Page,X
inc when b"0100_1101_000", -- EOR / Absolute
inc when b"0100_1101_001", -- EOR / Absolute
inc when b"0101_1101_000", -- EOR / Absolute,X
inc when b"0101_1101_001", -- EOR / Absolute,X
inc when b"0101_1001_000", -- EOR / Absolute,Y
inc when b"0101_1001_001", -- EOR / Absolute,Y
inc when b"0100_0001_000", -- EOR / (Indirect,X)
inc when b"0101_0001_000", -- EOR / (Indirect),Y
inc when b"1110_0110_000", -- INC / Zero Page
inc when b"1111_0110_000", -- INC / Zero Page,X
inc when b"1110_1110_000", -- INC / Absolute
inc when b"1110_1110_001", -- INC / Absolute
inc when b"1111_1110_000", -- INC / Absolute,X
inc when b"1111_1110_001", -- INC / Absolute,X
daq when b"0000_0011_110", -- INT / Implied
inc when b"0100_1100_000", -- JMP / Absolute
inc when b"0100_1100_001", -- JMP / Absolute
daq when b"0100_1100_010", -- JMP / Absolute
inc when b"0110_1100_000", -- JMP / Indirect
inc when b"0110_1100_001", -- JMP / Indirect
daq when b"0110_1100_100", -- JMP / Indirect
inc when b"0010_0000_000", -- JSR / Absolute
daq when b"0010_0000_101", -- JSR / Absolute
inc when b"1010_1001_000", -- LDA / Immediate
inc when b"1010_0101_000", -- LDA / Zero Page
inc when b"1011_0101_000", -- LDA / Zero Page,X
inc when b"1010_1101_000", -- LDA / Absolute
inc when b"1010_1101_001", -- LDA / Absolute
inc when b"1011_1101_000", -- LDA / Absolute,X
inc when b"1011_1101_001", -- LDA / Absolute,X
inc when b"1011_1001_000", -- LDA / Absolute,Y
inc when b"1011_1001_001", -- LDA / Absolute,Y
inc when b"1010_0001_000", -- LDA / (Indirect,X)
inc when b"1011_0001_000", -- LDA / (Indirect),Y
inc when b"1010_0010_000", -- LDX / Immediate
inc when b"1010_0110_000", -- LDX / Zero Page
inc when b"1011_0110_000", -- LDX / Zero Page,Y
inc when b"1010_1110_000", -- LDX / Absolute
inc when b"1010_1110_001", -- LDX / Absolute
inc when b"1011_1110_000", -- LDX / Absolute,Y
inc when b"1011_1110_001", -- LDX / Absolute,Y
inc when b"1010_0000_000", -- LDY / Immediate
inc when b"1010_0100_000", -- LDY / Zero Page
inc when b"1011_0100_000", -- LDY / Zero Page,X
inc when b"1010_1100_000", -- LDY / Absolute
inc when b"1010_1100_001", -- LDY / Absolute
inc when b"1011_1100_000", -- LDY / Absolute,X
inc when b"1011_1100_001", -- LDY / Absolute,X
inc when b"0100_0110_000", -- LSR / Zero Page
inc when b"0101_0110_000", -- LSR / Zero Page,X
inc when b"0100_1110_000", -- LSR / Absolute
inc when b"0100_1110_001", -- LSR / Absolute
inc when b"0101_1110_000", -- LSR / Absolute,X
inc when b"0101_1110_001", -- LSR / Absolute,X
daq when b"0000_0100_110", -- NMI / Implied
inc when b"0000_1001_000", -- ORA / Immediate
inc when b"0000_0101_000", -- ORA / Zero Page
inc when b"0001_0101_000", -- ORA / Zero Page,X
inc when b"0000_1101_000", -- ORA / Absolute
inc when b"0000_1101_001", -- ORA / Absolute
inc when b"0001_1101_000", -- ORA / Absolute,X
inc when b"0001_1101_001", -- ORA / Absolute,X
inc when b"0001_1001_000", -- ORA / Absolute,Y
inc when b"0001_1001_001", -- ORA / Absolute,Y
inc when b"0000_0001_000", -- ORA / (Indirect,X)
inc when b"0001_0001_000", -- ORA / (Indirect),Y
inc when b"0010_0110_000", -- ROL / Zero Page
inc when b"0011_0110_000", -- ROL / Zero Page,X
inc when b"0010_1110_000", -- ROL / Absolute
inc when b"0010_1110_001", -- ROL / Absolute
inc when b"0011_1110_000", -- ROL / Absolute,X
inc when b"0011_1110_001", -- ROL / Absolute,X
inc when b"0110_0110_000", -- ROR / Zero Page
inc when b"0111_0110_000", -- ROR / Zero Page,X
inc when b"0110_1110_000", -- ROR / Absolute
inc when b"0110_1110_001", -- ROR / Absolute
inc when b"0111_1110_000", -- ROR / Absolute,X
inc when b"0111_1110_001", -- ROR / Absolute,X
daq when b"0000_0010_011", -- RST / Implied
daq when b"0100_0000_101", -- RTI / Implied
daq when b"0110_0000_100", -- RTS / Implied
inc when b"0110_0000_101", -- RTS / Implied
inc when b"1110_1001_000", -- SBC / Immediate
inc when b"1110_0101_000", -- SBC / Zero Page
inc when b"1111_0101_000", -- SBC / Zero Page,X
inc when b"1110_1101_000", -- SBC / Absolute
inc when b"1110_1101_001", -- SBC / Absolute
inc when b"1111_1101_000", -- SBC / Absolute,X
inc when b"1111_1101_001", -- SBC / Absolute,X
inc when b"1111_1001_000", -- SBC / Absolute,Y
inc when b"1111_1001_001", -- SBC / Absolute,Y
inc when b"1110_0001_000", -- SBC / (Indirect,X)
inc when b"1111_0001_000", -- SBC / (Indirect),Y
inc when b"1000_0101_000", -- STA / Zero Page
inc when b"1001_0101_000", -- STA / Zero Page,X
inc when b"1000_1101_000", -- STA / Absolute
inc when b"1000_1101_001", -- STA / Absolute
inc when b"1001_1101_000", -- STA / Absolute,X
inc when b"1001_1101_001", -- STA / Absolute,X
inc when b"1001_1001_000", -- STA / Absolute,Y
inc when b"1001_1001_001", -- STA / Absolute,Y
inc when b"1000_0001_000", -- STA / (Indirect,X)
inc when b"1001_0001_000", -- STA / (Indirect),Y
inc when b"1000_0110_000", -- STX / Zero Page
inc when b"1001_0110_000", -- STX / Zero Page,Y
inc when b"1000_1110_000", -- STX / Absolute
inc when b"1000_1110_001", -- STX / Absolute
inc when b"1000_0100_000", -- STY / Zero Page
inc when b"1001_0100_000", -- STY / Zero Page,X
inc when b"1000_1100_000", -- STY / Absolute
inc when b"1000_1100_001", -- STY / Absolute
nop when others;
-- Input
with s_addr select o_in_op <=
ena when b"0111_1101_001", -- ADC / Absolute,X
ena when b"0111_1101_010", -- ADC / Absolute,X
ena when b"0111_1001_001", -- ADC / Absolute,Y
ena when b"0111_1001_010", -- ADC / Absolute,Y
ena when b"0110_0001_010", -- ADC / (Indirect,X)
ena when b"0110_0001_011", -- ADC / (Indirect,X)
ena when b"0111_0001_010", -- ADC / (Indirect),Y
ena when b"0111_0001_011", -- ADC / (Indirect),Y
ena when b"0011_1101_001", -- AND / Absolute,X
ena when b"0011_1101_010", -- AND / Absolute,X
ena when b"0011_1001_001", -- AND / Absolute,Y
ena when b"0011_1001_010", -- AND / Absolute,Y
ena when b"0010_0001_010", -- AND / (Indirect,X)
ena when b"0010_0001_011", -- AND / (Indirect,X)
ena when b"0011_0001_010", -- AND / (Indirect),Y
ena when b"0011_0001_011", -- AND / (Indirect),Y
alq when b"0000_0110_001", -- ASL / Zero Page
alq when b"0001_0110_010", -- ASL / Zero Page,X
ena when b"0000_1110_001", -- ASL / Absolute
ena when b"0001_1110_001", -- ASL / Absolute,X
ena when b"0001_1110_010", -- ASL / Absolute,X
ald when b"0001_1110_011", -- ASL / Absolute,X
fff when b"0000_0000_000", -- BRK / Implied
ena when b"0000_0000_101", -- BRK / Implied
ena when b"1101_1101_001", -- CMP / Absolute,X
ena when b"1101_1101_010", -- CMP / Absolute,X
ena when b"1101_1001_001", -- CMP / Absolute,Y
ena when b"1101_1001_010", -- CMP / Absolute,Y
ena when b"1100_0001_010", -- CMP / (Indirect,X)
ena when b"1100_0001_011", -- CMP / (Indirect,X)
ena when b"1101_0001_010", -- CMP / (Indirect),Y
ena when b"1101_0001_011", -- CMP / (Indirect),Y
ena when b"1100_0110_001", -- DEC / Zero Page
ena when b"1101_0110_001", -- DEC / Zero Page,X
alq when b"1101_0110_010", -- DEC / Zero Page,X
ena when b"1100_1110_001", -- DEC / Absolute
ena when b"1101_1110_001", -- DEC / Absolute,X
ena when b"1101_1110_010", -- DEC / Absolute,X
ald when b"1101_1110_011", -- DEC / Absolute,X
ena when b"0101_1101_001", -- EOR / Absolute,X
ena when b"0101_1101_010", -- EOR / Absolute,X
ena when b"0101_1001_001", -- EOR / Absolute,Y
ena when b"0101_1001_010", -- EOR / Absolute,Y
ena when b"0100_0001_010", -- EOR / (Indirect,X)
ena when b"0100_0001_011", -- EOR / (Indirect,X)
ena when b"0101_0001_010", -- EOR / (Indirect),Y
ena when b"0101_0001_011", -- EOR / (Indirect),Y
ena when b"1110_0110_001", -- INC / Zero Page
ena when b"1111_0110_001", -- INC / Zero Page,X
alq when b"1111_0110_010", -- INC / Zero Page,X
ena when b"1110_1110_001", -- INC / Absolute
ena when b"1111_1110_001", -- INC / Absolute,X
ena when b"1111_1110_010", -- INC / Absolute,X
ald when b"1111_1110_011", -- INC / Absolute,X
fff when b"0000_0011_000", -- INT / Implied
ena when b"0000_0011_101", -- INT / Implied
ena when b"0110_1100_010", -- JMP / Indirect
ena when b"0110_1100_011", -- JMP / Indirect
ena when b"0110_1100_100", -- JMP / Indirect
ena when b"0010_0000_001", -- JSR / Absolute
ena when b"1011_1101_001", -- LDA / Absolute,X
ena when b"1011_1101_010", -- LDA / Absolute,X
ena when b"1011_1001_001", -- LDA / Absolute,Y
ena when b"1011_1001_010", -- LDA / Absolute,Y
ena when b"1010_0001_010", -- LDA / (Indirect,X)
ena when b"1010_0001_011", -- LDA / (Indirect,X)
ena when b"1011_0001_010", -- LDA / (Indirect),Y
ena when b"1011_0001_011", -- LDA / (Indirect),Y
ena when b"1011_1110_001", -- LDX / Absolute,Y
ena when b"1011_1110_010", -- LDX / Absolute,Y
ena when b"1011_1100_001", -- LDY / Absolute,X
ena when b"1011_1100_010", -- LDY / Absolute,X
alq when b"0100_0110_001", -- LSR / Zero Page
alq when b"0101_0110_010", -- LSR / Zero Page,X
ena when b"0100_1110_001", -- LSR / Absolute
ena when b"0101_1110_001", -- LSR / Absolute,X
ena when b"0101_1110_010", -- LSR / Absolute,X
ald when b"0101_1110_011", -- LSR / Absolute,X
fff when b"0000_0100_000", -- NMI / Implied
ena when b"0000_0100_101", -- NMI / Implied
ena when b"0001_1101_001", -- ORA / Absolute,X
ena when b"0001_1101_010", -- ORA / Absolute,X
ena when b"0001_1001_001", -- ORA / Absolute,Y
ena when b"0001_1001_010", -- ORA / Absolute,Y
ena when b"0000_0001_010", -- ORA / (Indirect,X)
ena when b"0000_0001_011", -- ORA / (Indirect,X)
ena when b"0001_0001_010", -- ORA / (Indirect),Y
ena when b"0001_0001_011", -- ORA / (Indirect),Y
alq when b"0010_0110_001", -- ROL / Zero Page
alq when b"0011_0110_010", -- ROL / Zero Page,X
ena when b"0010_1110_001", -- ROL / Absolute
ena when b"0011_1110_001", -- ROL / Absolute,X
ena when b"0011_1110_010", -- ROL / Absolute,X
ald when b"0011_1110_011", -- ROL / Absolute,X
alq when b"0110_0110_001", -- ROR / Zero Page
alq when b"0111_0110_010", -- ROR / Zero Page,X
ena when b"0110_1110_001", -- ROR / Absolute
ena when b"0111_1110_001", -- ROR / Absolute,X
ena when b"0111_1110_010", -- ROR / Absolute,X
ald when b"0111_1110_011", -- ROR / Absolute,X
fff when b"0000_0010_000", -- RST / Implied
ena when b"0000_0010_010", -- RST / Implied
ena when b"0100_0000_100", -- RTI / Implied
ena when b"0110_0000_011", -- RTS / Implied
ena when b"1111_1101_001", -- SBC / Absolute,X
ena when b"1111_1101_010", -- SBC / Absolute,X
ena when b"1111_1001_001", -- SBC / Absolute,Y
ena when b"1111_1001_010", -- SBC / Absolute,Y
ena when b"1110_0001_010", -- SBC / (Indirect,X)
ena when b"1110_0001_011", -- SBC / (Indirect,X)
ena when b"1111_0001_010", -- SBC / (Indirect),Y
ena when b"1111_0001_011", -- SBC / (Indirect),Y
ena when b"1001_1101_001", -- STA / Absolute,X
ena when b"1001_1101_010", -- STA / Absolute,X
ena when b"1001_1001_001", -- STA / Absolute,Y
ena when b"1001_1001_010", -- STA / Absolute,Y
ena when b"1000_0001_010", -- STA / (Indirect,X)
ena when b"1000_0001_011", -- STA / (Indirect,X)
ena when b"1001_0001_010", -- STA / (Indirect),Y
ena when b"1001_0001_011", -- STA / (Indirect),Y
nop when others;
-- Output
with s_addr select o_out_op <=
ena when b"0000_0110_010", -- ASL / Zero Page
ena when b"0000_0110_011", -- ASL / Zero Page
ena when b"0001_0110_011", -- ASL / Zero Page,X
ena when b"0001_0110_100", -- ASL / Zero Page,X
din when b"0000_1110_011", -- ASL / Absolute
ena when b"0000_1110_100", -- ASL / Absolute
din when b"0001_1110_100", -- ASL / Absolute,X
ena when b"0001_1110_101", -- ASL / Absolute,X
pch when b"0000_0000_001", -- BRK / Implied
pcl when b"0000_0000_010", -- BRK / Implied
flg when b"0000_0000_011", -- BRK / Implied
ena when b"1100_0110_010", -- DEC / Zero Page
ena when b"1100_0110_011", -- DEC / Zero Page
ena when b"1101_0110_011", -- DEC / Zero Page,X
ena when b"1101_0110_100", -- DEC / Zero Page,X
din when b"1100_1110_011", -- DEC / Absolute
ena when b"1100_1110_100", -- DEC / Absolute
din when b"1101_1110_100", -- DEC / Absolute,X
ena when b"1101_1110_101", -- DEC / Absolute,X
ena when b"1110_0110_010", -- INC / Zero Page
ena when b"1110_0110_011", -- INC / Zero Page
ena when b"1111_0110_011", -- INC / Zero Page,X
ena when b"1111_0110_100", -- INC / Zero Page,X
din when b"1110_1110_011", -- INC / Absolute
ena when b"1110_1110_100", -- INC / Absolute
din when b"1111_1110_100", -- INC / Absolute,X
ena when b"1111_1110_101", -- INC / Absolute,X
pch when b"0000_0011_001", -- INT / Implied
pcl when b"0000_0011_010", -- INT / Implied
flg when b"0000_0011_011", -- INT / Implied
pch when b"0010_0000_010", -- JSR / Absolute
pcl when b"0010_0000_011", -- JSR / Absolute
ena when b"0100_0110_010", -- LSR / Zero Page
ena when b"0100_0110_011", -- LSR / Zero Page
ena when b"0101_0110_011", -- LSR / Zero Page,X
ena when b"0101_0110_100", -- LSR / Zero Page,X
din when b"0100_1110_011", -- LSR / Absolute
ena when b"0100_1110_100", -- LSR / Absolute
din when b"0101_1110_100", -- LSR / Absolute,X
ena when b"0101_1110_101", -- LSR / Absolute,X
pch when b"0000_0100_001", -- NMI / Implied
pcl when b"0000_0100_010", -- NMI / Implied
flg when b"0000_0100_011", -- NMI / Implied
arg when b"0100_1000_001", -- PHA / Implied
flg when b"0000_1000_001", -- PHP / Implied
ena when b"0010_0110_010", -- ROL / Zero Page
ena when b"0010_0110_011", -- ROL / Zero Page
ena when b"0011_0110_011", -- ROL / Zero Page,X
ena when b"0011_0110_100", -- ROL / Zero Page,X
din when b"0010_1110_011", -- ROL / Absolute
ena when b"0010_1110_100", -- ROL / Absolute
din when b"0011_1110_100", -- ROL / Absolute,X
ena when b"0011_1110_101", -- ROL / Absolute,X
ena when b"0110_0110_010", -- ROR / Zero Page
ena when b"0110_0110_011", -- ROR / Zero Page
ena when b"0111_0110_011", -- ROR / Zero Page,X
ena when b"0111_0110_100", -- ROR / Zero Page,X
din when b"0110_1110_011", -- ROR / Absolute
ena when b"0110_1110_100", -- ROR / Absolute
din when b"0111_1110_100", -- ROR / Absolute,X
ena when b"0111_1110_101", -- ROR / Absolute,X
arg when b"1000_0101_001", -- STA / Zero Page
arg when b"1001_0101_010", -- STA / Zero Page,X
arg when b"1000_1101_010", -- STA / Absolute
arg when b"1001_1101_011", -- STA / Absolute,X
arg when b"1001_1001_011", -- STA / Absolute,Y
arg when b"1000_0001_100", -- STA / (Indirect,X)
arg when b"1001_0001_100", -- STA / (Indirect),Y
xrg when b"1000_0110_001", -- STX / Zero Page
xrg when b"1001_0110_010", -- STX / Zero Page,Y
xrg when b"1000_1110_010", -- STX / Absolute
yrg when b"1000_0100_001", -- STY / Zero Page
yrg when b"1001_0100_010", -- STY / Zero Page,X
yrg when b"1000_1100_010", -- STY / Absolute
nop when others;
-- Flags
with s_addr select o_flags_op <=
nvzc when b"0110_1001_001", -- ADC / Immediate
nvzc when b"0110_0101_010", -- ADC / Zero Page
nvzc when b"0111_0101_011", -- ADC / Zero Page,X
nvzc when b"0110_1101_011", -- ADC / Absolute
nvzc when b"0111_1101_100", -- ADC / Absolute,X
nvzc when b"0111_1001_100", -- ADC / Absolute,Y
nvzc when b"0110_0001_101", -- ADC / (Indirect,X)
nvzc when b"0111_0001_101", -- ADC / (Indirect),Y
nz when b"0010_1001_001", -- AND / Immediate
nz when b"0010_0101_010", -- AND / Zero Page
nz when b"0011_0101_011", -- AND / Zero Page,X
nz when b"0010_1101_011", -- AND / Absolute
nz when b"0011_1101_100", -- AND / Absolute,X
nz when b"0011_1001_100", -- AND / Absolute,Y
nz when b"0010_0001_101", -- AND / (Indirect,X)
nz when b"0011_0001_101", -- AND / (Indirect),Y
nzc when b"0000_1010_001", -- ASL / Accumulator
nzc when b"0000_0110_011", -- ASL / Zero Page
nzc when b"0001_0110_100", -- ASL / Zero Page,X
nzc when b"0000_1110_100", -- ASL / Absolute
nzc when b"0001_1110_101", -- ASL / Absolute,X
nzv when b"0010_0100_010", -- BIT / Zero Page
nzv when b"0010_1100_011", -- BIT / Absolute
sei when b"0000_0000_011", -- BRK / Implied
clc when b"0001_1000_000", -- CLC / Implied
cld when b"1101_1000_000", -- CLD / Implied
cli when b"0101_1000_000", -- CLI / Implied
clv when b"1011_1000_000", -- CLV / Implied
nzc when b"1100_1001_001", -- CMP / Immediate
nzc when b"1100_0101_010", -- CMP / Zero Page
nzc when b"1101_0101_011", -- CMP / Zero Page,X
nzc when b"1100_1101_011", -- CMP / Absolute
nzc when b"1101_1101_100", -- CMP / Absolute,X
nzc when b"1101_1001_100", -- CMP / Absolute,Y
nzc when b"1100_0001_101", -- CMP / (Indirect,X)
nzc when b"1101_0001_101", -- CMP / (Indirect),Y
nzc when b"1110_0000_001", -- CPX / Immediate
nzc when b"1110_0100_010", -- CPX / Zero Page
nzc when b"1110_1100_011", -- CPX / Absolute
nzc when b"1100_0000_001", -- CPY / Immediate
nzc when b"1100_0100_010", -- CPY / Zero Page
nzc when b"1100_1100_011", -- CPY / Absolute
nz when b"1100_0110_011", -- DEC / Zero Page
nz when b"1101_0110_100", -- DEC / Zero Page,X
nz when b"1100_1110_100", -- DEC / Absolute
nz when b"1101_1110_101", -- DEC / Absolute,X
nz when b"1100_1010_001", -- DEX / Implied
nz when b"1000_1000_001", -- DEY / Implied
nz when b"0100_1001_001", -- EOR / Immediate
nz when b"0100_0101_010", -- EOR / Zero Page
nz when b"0101_0101_011", -- EOR / Zero Page,X
nz when b"0100_1101_011", -- EOR / Absolute
nz when b"0101_1101_100", -- EOR / Absolute,X
nz when b"0101_1001_100", -- EOR / Absolute,Y
nz when b"0100_0001_101", -- EOR / (Indirect,X)
nz when b"0101_0001_101", -- EOR / (Indirect),Y
nz when b"1110_0110_011", -- INC / Zero Page
nz when b"1111_0110_100", -- INC / Zero Page,X
nz when b"1110_1110_100", -- INC / Absolute
nz when b"1111_1110_101", -- INC / Absolute,X
sei when b"0000_0011_011", -- INT / Implied
nz when b"1110_1000_001", -- INX / Implied
nz when b"1100_1000_001", -- INY / Implied
nz when b"1010_1001_001", -- LDA / Immediate
nz when b"1010_0101_010", -- LDA / Zero Page
nz when b"1011_0101_011", -- LDA / Zero Page,X
nz when b"1010_1101_011", -- LDA / Absolute
nz when b"1011_1101_100", -- LDA / Absolute,X
nz when b"1011_1001_100", -- LDA / Absolute,Y
nz when b"1010_0001_101", -- LDA / (Indirect,X)
nz when b"1011_0001_101", -- LDA / (Indirect),Y
nz when b"1010_0010_001", -- LDX / Immediate
nz when b"1010_0110_010", -- LDX / Zero Page
nz when b"1011_0110_011", -- LDX / Zero Page,Y
nz when b"1010_1110_011", -- LDX / Absolute
nz when b"1011_1110_100", -- LDX / Absolute,Y
nz when b"1010_0000_001", -- LDY / Immediate
nz when b"1010_0100_010", -- LDY / Zero Page
nz when b"1011_0100_011", -- LDY / Zero Page,X
nz when b"1010_1100_011", -- LDY / Absolute
nz when b"1011_1100_100", -- LDY / Absolute,X
nzc when b"0100_1010_001", -- LSR / Accumulator
nzc when b"0100_0110_011", -- LSR / Zero Page
nzc when b"0101_0110_100", -- LSR / Zero Page,X
nzc when b"0100_1110_100", -- LSR / Absolute
nzc when b"0101_1110_101", -- LSR / Absolute,X
sei when b"0000_0100_011", -- NMI / Implied
nz when b"0000_1001_001", -- ORA / Immediate
nz when b"0000_0101_010", -- ORA / Zero Page
nz when b"0001_0101_011", -- ORA / Zero Page,X
nz when b"0000_1101_011", -- ORA / Absolute
nz when b"0001_1101_100", -- ORA / Absolute,X
nz when b"0001_1001_100", -- ORA / Absolute,Y
nz when b"0000_0001_101", -- ORA / (Indirect,X)
nz when b"0001_0001_101", -- ORA / (Indirect),Y
nz when b"0110_1000_011", -- PLA / Implied
din when b"0010_1000_011", -- PLP / Implied
nzc when b"0010_1010_001", -- ROL / Accumulator
nzc when b"0010_0110_011", -- ROL / Zero Page
nzc when b"0011_0110_100", -- ROL / Zero Page,X
nzc when b"0010_1110_100", -- ROL / Absolute
nzc when b"0011_1110_101", -- ROL / Absolute,X
nzc when b"0110_1010_001", -- ROR / Accumulator
nzc when b"0110_0110_011", -- ROR / Zero Page
nzc when b"0111_0110_100", -- ROR / Zero Page,X
nzc when b"0110_1110_100", -- ROR / Absolute
nzc when b"0111_1110_101", -- ROR / Absolute,X
din when b"0100_0000_011", -- RTI / Implied
nvzc when b"1110_1001_001", -- SBC / Immediate
nvzc when b"1110_0101_010", -- SBC / Zero Page
nvzc when b"1111_0101_011", -- SBC / Zero Page,X
nvzc when b"1110_1101_011", -- SBC / Absolute
nvzc when b"1111_1101_100", -- SBC / Absolute,X
nvzc when b"1111_1001_100", -- SBC / Absolute,Y
nvzc when b"1110_0001_101", -- SBC / (Indirect,X)
nvzc when b"1111_0001_101", -- SBC / (Indirect),Y
stc when b"0011_1000_000", -- SEC / Implied
sed when b"1111_1000_000", -- SED / Implied
sei when b"0111_1000_000", -- SEI / Implied
nz when b"1010_1010_001", -- TAX / Implied
nz when b"1010_1000_001", -- TAY / Implied
nz when b"1011_1010_001", -- TSX / Implied
nz when b"1000_1010_001", -- TXA / Implied
nz when b"1001_1000_001", -- TYA / Implied
nop when others;
-- ALU Operation
with s_addr select o_alu_op <=
adc when b"0110_1001_001", -- ADC / Immediate
adc when b"0110_0101_010", -- ADC / Zero Page
add when b"0111_0101_010", -- ADC / Zero Page,X
adc when b"0111_0101_011", -- ADC / Zero Page,X
adc when b"0110_1101_011", -- ADC / Absolute
add when b"0111_1101_010", -- ADC / Absolute,X
add when b"0111_1101_011", -- ADC / Absolute,X
adc when b"0111_1101_100", -- ADC / Absolute,X
add when b"0111_1001_010", -- ADC / Absolute,Y
add when b"0111_1001_011", -- ADC / Absolute,Y
adc when b"0111_1001_100", -- ADC / Absolute,Y
add when b"0110_0001_010", -- ADC / (Indirect,X)
add when b"0110_0001_011", -- ADC / (Indirect,X)
adc when b"0110_0001_101", -- ADC / (Indirect,X)
add when b"0111_0001_010", -- ADC / (Indirect),Y
add when b"0111_0001_011", -- ADC / (Indirect),Y
add when b"0111_0001_100", -- ADC / (Indirect),Y
adc when b"0111_0001_101", -- ADC / (Indirect),Y
ada when b"0010_1001_001", -- AND / Immediate
ada when b"0010_0101_010", -- AND / Zero Page
add when b"0011_0101_010", -- AND / Zero Page,X
ada when b"0011_0101_011", -- AND / Zero Page,X
ada when b"0010_1101_011", -- AND / Absolute
add when b"0011_1101_010", -- AND / Absolute,X
add when b"0011_1101_011", -- AND / Absolute,X
ada when b"0011_1101_100", -- AND / Absolute,X
add when b"0011_1001_010", -- AND / Absolute,Y
add when b"0011_1001_011", -- AND / Absolute,Y
ada when b"0011_1001_100", -- AND / Absolute,Y
add when b"0010_0001_010", -- AND / (Indirect,X)
add when b"0010_0001_011", -- AND / (Indirect,X)
ada when b"0010_0001_101", -- AND / (Indirect,X)
add when b"0011_0001_010", -- AND / (Indirect),Y
add when b"0011_0001_011", -- AND / (Indirect),Y
add when b"0011_0001_100", -- AND / (Indirect),Y
ada when b"0011_0001_101", -- AND / (Indirect),Y
asl when b"0000_1010_001", -- ASL / Accumulator
asl when b"0000_0110_011", -- ASL / Zero Page
add when b"0001_0110_010", -- ASL / Zero Page,X
asl when b"0001_0110_100", -- ASL / Zero Page,X
asl when b"0000_1110_100", -- ASL / Absolute
add when b"0001_1110_010", -- ASL / Absolute,X
add when b"0001_1110_011", -- ASL / Absolute,X
asl when b"0001_1110_101", -- ASL / Absolute,X
add when b"1001_0000_001", -- BCC / Relative
add when b"1001_0000_010", -- BCC / Relative
add when b"1011_0000_001", -- BCS / Relative
add when b"1011_0000_010", -- BCS / Relative
add when b"1111_0000_001", -- BEQ / Relative
add when b"1111_0000_010", -- BEQ / Relative
ada when b"0010_0100_010", -- BIT / Zero Page
ada when b"0010_1100_011", -- BIT / Absolute
add when b"0011_0000_001", -- BMI / Relative
add when b"0011_0000_010", -- BMI / Relative
add when b"1101_0000_001", -- BNE / Relative
add when b"1101_0000_010", -- BNE / Relative
add when b"0001_0000_001", -- BPL / Relative
add when b"0001_0000_010", -- BPL / Relative
sub when b"0000_0000_001", -- BRK / Implied
sub when b"0000_0000_010", -- BRK / Implied
sub when b"0000_0000_011", -- BRK / Implied
add when b"0000_0000_101", -- BRK / Implied
add when b"0101_0000_001", -- BVC / Relative
add when b"0101_0000_010", -- BVC / Relative
add when b"0111_0000_001", -- BVS / Relative
add when b"0111_0000_010", -- BVS / Relative
sub when b"1100_1001_001", -- CMP / Immediate
sub when b"1100_0101_010", -- CMP / Zero Page
add when b"1101_0101_010", -- CMP / Zero Page,X
sub when b"1101_0101_011", -- CMP / Zero Page,X
sub when b"1100_1101_011", -- CMP / Absolute
add when b"1101_1101_010", -- CMP / Absolute,X
add when b"1101_1101_011", -- CMP / Absolute,X
sub when b"1101_1101_100", -- CMP / Absolute,X
add when b"1101_1001_010", -- CMP / Absolute,Y
add when b"1101_1001_011", -- CMP / Absolute,Y
sub when b"1101_1001_100", -- CMP / Absolute,Y
add when b"1100_0001_010", -- CMP / (Indirect,X)
add when b"1100_0001_011", -- CMP / (Indirect,X)
sub when b"1100_0001_101", -- CMP / (Indirect,X)
add when b"1101_0001_010", -- CMP / (Indirect),Y
add when b"1101_0001_011", -- CMP / (Indirect),Y
add when b"1101_0001_100", -- CMP / (Indirect),Y
sub when b"1101_0001_101", -- CMP / (Indirect),Y
sub when b"1110_0000_001", -- CPX / Immediate
sub when b"1110_0100_010", -- CPX / Zero Page
sub when b"1110_1100_011", -- CPX / Absolute
sub when b"1100_0000_001", -- CPY / Immediate
sub when b"1100_0100_010", -- CPY / Zero Page
sub when b"1100_1100_011", -- CPY / Absolute
sub when b"1100_0110_011", -- DEC / Zero Page
add when b"1101_0110_010", -- DEC / Zero Page,X
sub when b"1101_0110_100", -- DEC / Zero Page,X
sub when b"1100_1110_100", -- DEC / Absolute
add when b"1101_1110_010", -- DEC / Absolute,X
add when b"1101_1110_011", -- DEC / Absolute,X
sub when b"1101_1110_101", -- DEC / Absolute,X
sub when b"1100_1010_001", -- DEX / Implied
sub when b"1000_1000_001", -- DEY / Implied
eor when b"0100_1001_001", -- EOR / Immediate
eor when b"0100_0101_010", -- EOR / Zero Page
add when b"0101_0101_010", -- EOR / Zero Page,X
eor when b"0101_0101_011", -- EOR / Zero Page,X
eor when b"0100_1101_011", -- EOR / Absolute
add when b"0101_1101_010", -- EOR / Absolute,X
add when b"0101_1101_011", -- EOR / Absolute,X
eor when b"0101_1101_100", -- EOR / Absolute,X
add when b"0101_1001_010", -- EOR / Absolute,Y
add when b"0101_1001_011", -- EOR / Absolute,Y
eor when b"0101_1001_100", -- EOR / Absolute,Y
add when b"0100_0001_010", -- EOR / (Indirect,X)
add when b"0100_0001_011", -- EOR / (Indirect,X)
eor when b"0100_0001_101", -- EOR / (Indirect,X)
add when b"0101_0001_010", -- EOR / (Indirect),Y
add when b"0101_0001_011", -- EOR / (Indirect),Y
add when b"0101_0001_100", -- EOR / (Indirect),Y
eor when b"0101_0001_101", -- EOR / (Indirect),Y
add when b"1110_0110_011", -- INC / Zero Page
add when b"1111_0110_010", -- INC / Zero Page,X
add when b"1111_0110_100", -- INC / Zero Page,X
add when b"1110_1110_100", -- INC / Absolute
add when b"1111_1110_010", -- INC / Absolute,X
add when b"1111_1110_011", -- INC / Absolute,X
add when b"1111_1110_101", -- INC / Absolute,X
sub when b"0000_0011_001", -- INT / Implied
sub when b"0000_0011_010", -- INT / Implied
sub when b"0000_0011_011", -- INT / Implied
add when b"0000_0011_101", -- INT / Implied
add when b"1110_1000_001", -- INX / Implied
add when b"1100_1000_001", -- INY / Implied
add when b"0110_1100_011", -- JMP / Indirect
sub when b"0010_0000_011", -- JSR / Absolute
sub when b"0010_0000_100", -- JSR / Absolute
add when b"1011_0101_010", -- LDA / Zero Page,X
add when b"1011_1101_010", -- LDA / Absolute,X
add when b"1011_1101_011", -- LDA / Absolute,X
add when b"1011_1001_010", -- LDA / Absolute,Y
add when b"1011_1001_011", -- LDA / Absolute,Y
add when b"1010_0001_010", -- LDA / (Indirect,X)
add when b"1010_0001_011", -- LDA / (Indirect,X)
add when b"1011_0001_010", -- LDA / (Indirect),Y
add when b"1011_0001_011", -- LDA / (Indirect),Y
add when b"1011_0001_100", -- LDA / (Indirect),Y
add when b"1011_0110_010", -- LDX / Zero Page,Y
add when b"1011_1110_010", -- LDX / Absolute,Y
add when b"1011_1110_011", -- LDX / Absolute,Y
add when b"1011_0100_010", -- LDY / Zero Page,X
add when b"1011_1100_010", -- LDY / Absolute,X
add when b"1011_1100_011", -- LDY / Absolute,X
lsr when b"0100_1010_001", -- LSR / Accumulator
lsr when b"0100_0110_011", -- LSR / Zero Page
add when b"0101_0110_010", -- LSR / Zero Page,X
lsr when b"0101_0110_100", -- LSR / Zero Page,X
lsr when b"0100_1110_100", -- LSR / Absolute
add when b"0101_1110_010", -- LSR / Absolute,X
add when b"0101_1110_011", -- LSR / Absolute,X
lsr when b"0101_1110_101", -- LSR / Absolute,X
sub when b"0000_0100_001", -- NMI / Implied
sub when b"0000_0100_010", -- NMI / Implied
sub when b"0000_0100_011", -- NMI / Implied
add when b"0000_0100_101", -- NMI / Implied
ora when b"0000_1001_001", -- ORA / Immediate
ora when b"0000_0101_010", -- ORA / Zero Page
add when b"0001_0101_010", -- ORA / Zero Page,X
ora when b"0001_0101_011", -- ORA / Zero Page,X
ora when b"0000_1101_011", -- ORA / Absolute
add when b"0001_1101_010", -- ORA / Absolute,X
add when b"0001_1101_011", -- ORA / Absolute,X
ora when b"0001_1101_100", -- ORA / Absolute,X
add when b"0001_1001_010", -- ORA / Absolute,Y
add when b"0001_1001_011", -- ORA / Absolute,Y
ora when b"0001_1001_100", -- ORA / Absolute,Y
add when b"0000_0001_010", -- ORA / (Indirect,X)
add when b"0000_0001_011", -- ORA / (Indirect,X)
ora when b"0000_0001_101", -- ORA / (Indirect,X)
add when b"0001_0001_010", -- ORA / (Indirect),Y
add when b"0001_0001_011", -- ORA / (Indirect),Y
add when b"0001_0001_100", -- ORA / (Indirect),Y
ora when b"0001_0001_101", -- ORA / (Indirect),Y
sub when b"0100_1000_010", -- PHA / Implied
sub when b"0000_1000_010", -- PHP / Implied
add when b"0110_1000_010", -- PLA / Implied
add when b"0010_1000_010", -- PLP / Implied
add when b"0000_0010_010", -- RST / Implied
add when b"0100_0000_010", -- RTI / Implied
add when b"0100_0000_011", -- RTI / Implied
add when b"0100_0000_100", -- RTI / Implied
add when b"0110_0000_010", -- RTS / Implied
add when b"0110_0000_011", -- RTS / Implied
rla when b"0010_1010_001", -- ROL / Accumulator
rla when b"0010_0110_011", -- ROL / Zero Page
add when b"0011_0110_010", -- ROL / Zero Page,X
rla when b"0011_0110_100", -- ROL / Zero Page,X
rla when b"0010_1110_100", -- ROL / Absolute
add when b"0011_1110_010", -- ROL / Absolute,X
add when b"0011_1110_011", -- ROL / Absolute,X
rla when b"0011_1110_101", -- ROL / Absolute,X
rra when b"0110_1010_001", -- ROR / Accumulator
rra when b"0110_0110_011", -- ROR / Zero Page
add when b"0111_0110_010", -- ROR / Zero Page,X
rra when b"0111_0110_100", -- ROR / Zero Page,X
rra when b"0110_1110_100", -- ROR / Absolute
add when b"0111_1110_010", -- ROR / Absolute,X
add when b"0111_1110_011", -- ROR / Absolute,X
rra when b"0111_1110_101", -- ROR / Absolute,X
sbc when b"1110_1001_001", -- SBC / Immediate
sbc when b"1110_0101_010", -- SBC / Zero Page
add when b"1111_0101_010", -- SBC / Zero Page,X
sbc when b"1111_0101_011", -- SBC / Zero Page,X
sbc when b"1110_1101_011", -- SBC / Absolute
add when b"1111_1101_010", -- SBC / Absolute,X
add when b"1111_1101_011", -- SBC / Absolute,X
sbc when b"1111_1101_100", -- SBC / Absolute,X
add when b"1111_1001_010", -- SBC / Absolute,Y
add when b"1111_1001_011", -- SBC / Absolute,Y
sbc when b"1111_1001_100", -- SBC / Absolute,Y
add when b"1110_0001_010", -- SBC / (Indirect,X)
add when b"1110_0001_011", -- SBC / (Indirect,X)
sbc when b"1110_0001_101", -- SBC / (Indirect,X)
add when b"1111_0001_010", -- SBC / (Indirect),Y
add when b"1111_0001_011", -- SBC / (Indirect),Y
add when b"1111_0001_100", -- SBC / (Indirect),Y
sbc when b"1111_0001_101", -- SBC / (Indirect),Y
add when b"1000_0101_010", -- STA / Zero Page
add when b"1001_0101_010", -- STA / Zero Page,X
add when b"1001_1101_010", -- STA / Absolute,X
add when b"1001_1101_011", -- STA / Absolute,X
add when b"1001_1001_010", -- STA / Absolute,Y
add when b"1001_1001_011", -- STA / Absolute,Y
add when b"1000_0001_010", -- STA / (Indirect,X)
add when b"1000_0001_011", -- STA / (Indirect,X)
add when b"1001_0001_010", -- STA / (Indirect),Y
add when b"1001_0001_011", -- STA / (Indirect),Y
add when b"1001_0001_100", -- STA / (Indirect),Y
add when b"1000_0110_010", -- STX / Zero Page
add when b"1001_0110_010", -- STX / Zero Page,Y
add when b"1000_0100_010", -- STY / Zero Page
add when b"1001_0100_010", -- STY / Zero Page,X
psa when others;
-- ALU Input A
with s_addr select o_alu_a_op <=
arg when b"0110_1001_001", -- ADC / Immediate
arg when b"0110_0101_010", -- ADC / Zero Page
xrg when b"0111_0101_010", -- ADC / Zero Page,X
arg when b"0111_0101_011", -- ADC / Zero Page,X
arg when b"0110_1101_011", -- ADC / Absolute
xrg when b"0111_1101_010", -- ADC / Absolute,X
val when b"0111_1101_011", -- ADC / Absolute,X
arg when b"0111_1101_100", -- ADC / Absolute,X
yrg when b"0111_1001_010", -- ADC / Absolute,Y
val when b"0111_1001_011", -- ADC / Absolute,Y
arg when b"0111_1001_100", -- ADC / Absolute,Y
xrg when b"0110_0001_010", -- ADC / (Indirect,X)
alq when b"0110_0001_011", -- ADC / (Indirect,X)
val when b"0110_0001_100", -- ADC / (Indirect,X)
arg when b"0110_0001_101", -- ADC / (Indirect,X)
alq when b"0111_0001_010", -- ADC / (Indirect),Y
yrg when b"0111_0001_011", -- ADC / (Indirect),Y
val when b"0111_0001_100", -- ADC / (Indirect),Y
arg when b"0111_0001_101", -- ADC / (Indirect),Y
arg when b"0010_1001_001", -- AND / Immediate
arg when b"0010_0101_010", -- AND / Zero Page
xrg when b"0011_0101_010", -- AND / Zero Page,X
arg when b"0011_0101_011", -- AND / Zero Page,X
arg when b"0010_1101_011", -- AND / Absolute
xrg when b"0011_1101_010", -- AND / Absolute,X
val when b"0011_1101_011", -- AND / Absolute,X
arg when b"0011_1101_100", -- AND / Absolute,X
yrg when b"0011_1001_010", -- AND / Absolute,Y
val when b"0011_1001_011", -- AND / Absolute,Y
arg when b"0011_1001_100", -- AND / Absolute,Y
xrg when b"0010_0001_010", -- AND / (Indirect,X)
alq when b"0010_0001_011", -- AND / (Indirect,X)
val when b"0010_0001_100", -- AND / (Indirect,X)
arg when b"0010_0001_101", -- AND / (Indirect,X)
alq when b"0011_0001_010", -- AND / (Indirect),Y
yrg when b"0011_0001_011", -- AND / (Indirect),Y
val when b"0011_0001_100", -- AND / (Indirect),Y
arg when b"0011_0001_101", -- AND / (Indirect),Y
arg when b"0000_1010_001", -- ASL / Accumulator
xrg when b"0001_0110_010", -- ASL / Zero Page,X
alq when b"0000_1110_011", -- ASL / Absolute
xrg when b"0001_1110_010", -- ASL / Absolute,X
val when b"0001_1110_011", -- ASL / Absolute,X
alq when b"0001_1110_100", -- ASL / Absolute,X
pcl when b"1001_0000_001", -- BCC / Relative
pch when b"1001_0000_010", -- BCC / Relative
pcl when b"1011_0000_001", -- BCS / Relative
pch when b"1011_0000_010", -- BCS / Relative
pcl when b"1111_0000_001", -- BEQ / Relative
pch when b"1111_0000_010", -- BEQ / Relative
arg when b"0010_0100_010", -- BIT / Zero Page
arg when b"0010_1100_011", -- BIT / Absolute
pcl when b"0011_0000_001", -- BMI / Relative
pch when b"0011_0000_010", -- BMI / Relative
pcl when b"1101_0000_001", -- BNE / Relative
pch when b"1101_0000_010", -- BNE / Relative
pcl when b"0001_0000_001", -- BPL / Relative
pch when b"0001_0000_010", -- BPL / Relative
srg when b"0000_0000_000", -- BRK / Implied
alq when b"0000_0000_001", -- BRK / Implied
alq when b"0000_0000_010", -- BRK / Implied
alq when b"0000_0000_011", -- BRK / Implied
brk when b"0000_0000_100", -- BRK / Implied
alq when b"0000_0000_101", -- BRK / Implied
val when b"0000_0000_110", -- BRK / Implied
pcl when b"0101_0000_001", -- BVC / Relative
pch when b"0101_0000_010", -- BVC / Relative
pcl when b"0111_0000_001", -- BVS / Relative
pch when b"0111_0000_010", -- BVS / Relative
arg when b"1100_1001_001", -- CMP / Immediate
arg when b"1100_0101_010", -- CMP / Zero Page
xrg when b"1101_0101_010", -- CMP / Zero Page,X
arg when b"1101_0101_011", -- CMP / Zero Page,X
arg when b"1100_1101_011", -- CMP / Absolute
xrg when b"1101_1101_010", -- CMP / Absolute,X
val when b"1101_1101_011", -- CMP / Absolute,X
arg when b"1101_1101_100", -- CMP / Absolute,X
yrg when b"1101_1001_010", -- CMP / Absolute,Y
val when b"1101_1001_011", -- CMP / Absolute,Y
arg when b"1101_1001_100", -- CMP / Absolute,Y
xrg when b"1100_0001_010", -- CMP / (Indirect,X)
alq when b"1100_0001_011", -- CMP / (Indirect,X)
val when b"1100_0001_100", -- CMP / (Indirect,X)
arg when b"1100_0001_101", -- CMP / (Indirect,X)
alq when b"1101_0001_010", -- CMP / (Indirect),Y
yrg when b"1101_0001_011", -- CMP / (Indirect),Y
val when b"1101_0001_100", -- CMP / (Indirect),Y
arg when b"1101_0001_101", -- CMP / (Indirect),Y
xrg when b"1110_0000_001", -- CPX / Immediate
xrg when b"1110_0100_010", -- CPX / Zero Page
xrg when b"1110_1100_011", -- CPX / Absolute
yrg when b"1100_0000_001", -- CPY / Immediate
yrg when b"1100_0100_010", -- CPY / Zero Page
yrg when b"1100_1100_011", -- CPY / Absolute
xrg when b"1101_0110_010", -- DEC / Zero Page,X
alq when b"1100_1110_011", -- DEC / Absolute
xrg when b"1101_1110_010", -- DEC / Absolute,X
val when b"1101_1110_011", -- DEC / Absolute,X
alq when b"1101_1110_100", -- DEC / Absolute,X
xrg when b"1100_1010_001", -- DEX / Implied
yrg when b"1000_1000_001", -- DEY / Implied
arg when b"0100_1001_001", -- EOR / Immediate
arg when b"0100_0101_010", -- EOR / Zero Page
xrg when b"0101_0101_010", -- EOR / Zero Page,X
arg when b"0101_0101_011", -- EOR / Zero Page,X
arg when b"0100_1101_011", -- EOR / Absolute
xrg when b"0101_1101_010", -- EOR / Absolute,X
val when b"0101_1101_011", -- EOR / Absolute,X
arg when b"0101_1101_100", -- EOR / Absolute,X
yrg when b"0101_1001_010", -- EOR / Absolute,Y
val when b"0101_1001_011", -- EOR / Absolute,Y
arg when b"0101_1001_100", -- EOR / Absolute,Y
xrg when b"0100_0001_010", -- EOR / (Indirect,X)
alq when b"0100_0001_011", -- EOR / (Indirect,X)
val when b"0100_0001_100", -- EOR / (Indirect,X)
arg when b"0100_0001_101", -- EOR / (Indirect,X)
alq when b"0101_0001_010", -- EOR / (Indirect),Y
yrg when b"0101_0001_011", -- EOR / (Indirect),Y
val when b"0101_0001_100", -- EOR / (Indirect),Y
arg when b"0101_0001_101", -- EOR / (Indirect),Y
xrg when b"1111_0110_010", -- INC / Zero Page,X
alq when b"1110_1110_011", -- INC / Absolute
xrg when b"1111_1110_010", -- INC / Absolute,X
val when b"1111_1110_011", -- INC / Absolute,X
alq when b"1111_1110_100", -- INC / Absolute,X
srg when b"0000_0011_000", -- INT / Implied
alq when b"0000_0011_001", -- INT / Implied
alq when b"0000_0011_010", -- INT / Implied
alq when b"0000_0011_011", -- INT / Implied
brk when b"0000_0011_100", -- INT / Implied
alq when b"0000_0011_101", -- INT / Implied
val when b"0000_0011_110", -- INT / Implied
xrg when b"1110_1000_001", -- INX / Implied
yrg when b"1100_1000_001", -- INY / Implied
alq when b"0100_1100_010", -- JMP / Absolute
alq when b"0110_1100_010", -- JMP / Indirect
alq when b"0110_1100_011", -- JMP / Indirect
val when b"0110_1100_100", -- JMP / Indirect
srg when b"0010_0000_001", -- JSR / Absolute
alq when b"0010_0000_010", -- JSR / Absolute
alq when b"0010_0000_011", -- JSR / Absolute
alq when b"0010_0000_100", -- JSR / Absolute
val when b"0010_0000_101", -- JSR / Absolute
xrg when b"1011_0101_010", -- LDA / Zero Page,X
xrg when b"1011_1101_010", -- LDA / Absolute,X
val when b"1011_1101_011", -- LDA / Absolute,X
yrg when b"1011_1001_010", -- LDA / Absolute,Y
val when b"1011_1001_011", -- LDA / Absolute,Y
xrg when b"1010_0001_010", -- LDA / (Indirect,X)
alq when b"1010_0001_011", -- LDA / (Indirect,X)
val when b"1010_0001_100", -- LDA / (Indirect,X)
alq when b"1011_0001_010", -- LDA / (Indirect),Y
yrg when b"1011_0001_011", -- LDA / (Indirect),Y
val when b"1011_0001_100", -- LDA / (Indirect),Y
yrg when b"1011_0110_010", -- LDX / Zero Page,Y
yrg when b"1011_1110_010", -- LDX / Absolute,Y
val when b"1011_1110_011", -- LDX / Absolute,Y
xrg when b"1011_0100_010", -- LDY / Zero Page,X
xrg when b"1011_1100_010", -- LDY / Absolute,X
val when b"1011_1100_011", -- LDY / Absolute,X
arg when b"0100_1010_001", -- LSR / Accumulator
xrg when b"0101_0110_010", -- LSR / Zero Page,X
alq when b"0100_1110_011", -- LSR / Absolute
xrg when b"0101_1110_010", -- LSR / Absolute,X
val when b"0101_1110_011", -- LSR / Absolute,X
alq when b"0101_1110_100", -- LSR / Absolute,X
srg when b"0000_0100_000", -- NMI / Implied
alq when b"0000_0100_001", -- NMI / Implied
alq when b"0000_0100_010", -- NMI / Implied
alq when b"0000_0100_011", -- NMI / Implied
brk when b"0000_0100_100", -- NMI / Implied
alq when b"0000_0100_101", -- NMI / Implied
val when b"0000_0100_110", -- NMI / Implied
arg when b"0000_1001_001", -- ORA / Immediate
arg when b"0000_0101_010", -- ORA / Zero Page
xrg when b"0001_0101_010", -- ORA / Zero Page,X
arg when b"0001_0101_011", -- ORA / Zero Page,X
arg when b"0000_1101_011", -- ORA / Absolute
xrg when b"0001_1101_010", -- ORA / Absolute,X
val when b"0001_1101_011", -- ORA / Absolute,X
arg when b"0001_1101_100", -- ORA / Absolute,X
yrg when b"0001_1001_010", -- ORA / Absolute,Y
val when b"0001_1001_011", -- ORA / Absolute,Y
arg when b"0001_1001_100", -- ORA / Absolute,Y
xrg when b"0000_0001_010", -- ORA / (Indirect,X)
alq when b"0000_0001_011", -- ORA / (Indirect,X)
val when b"0000_0001_100", -- ORA / (Indirect,X)
arg when b"0000_0001_101", -- ORA / (Indirect,X)
alq when b"0001_0001_010", -- ORA / (Indirect),Y
yrg when b"0001_0001_011", -- ORA / (Indirect),Y
val when b"0001_0001_100", -- ORA / (Indirect),Y
arg when b"0001_0001_101", -- ORA / (Indirect),Y
srg when b"0100_1000_001", -- PHA / Implied
alq when b"0100_1000_010", -- PHA / Implied
srg when b"0000_1000_001", -- PHP / Implied
alq when b"0000_1000_010", -- PHP / Implied
srg when b"0110_1000_001", -- PLA / Implied
alq when b"0110_1000_010", -- PLA / Implied
srg when b"0010_1000_001", -- PLP / Implied
alq when b"0010_1000_010", -- PLP / Implied
arg when b"0010_1010_001", -- ROL / Accumulator
xrg when b"0011_0110_010", -- ROL / Zero Page,X
alq when b"0010_1110_011", -- ROL / Absolute
xrg when b"0011_1110_010", -- ROL / Absolute,X
val when b"0011_1110_011", -- ROL / Absolute,X
alq when b"0011_1110_100", -- ROL / Absolute,X
arg when b"0110_1010_001", -- ROR / Accumulator
xrg when b"0111_0110_010", -- ROR / Zero Page,X
alq when b"0110_1110_011", -- ROR / Absolute
xrg when b"0111_1110_010", -- ROR / Absolute,X
val when b"0111_1110_011", -- ROR / Absolute,X
alq when b"0111_1110_100", -- ROR / Absolute,X
brk when b"0000_0010_001", -- RST / Implied
alq when b"0000_0010_010", -- RST / Implied
val when b"0000_0010_011", -- RST / Implied
srg when b"0100_0000_001", -- RTI / Implied
alq when b"0100_0000_010", -- RTI / Implied
alq when b"0100_0000_011", -- RTI / Implied
alq when b"0100_0000_100", -- RTI / Implied
val when b"0100_0000_101", -- RTI / Implied
srg when b"0110_0000_001", -- RTS / Implied
alq when b"0110_0000_010", -- RTS / Implied
alq when b"0110_0000_011", -- RTS / Implied
val when b"0110_0000_100", -- RTS / Implied
arg when b"1110_1001_001", -- SBC / Immediate
arg when b"1110_0101_010", -- SBC / Zero Page
xrg when b"1111_0101_010", -- SBC / Zero Page,X
arg when b"1111_0101_011", -- SBC / Zero Page,X
arg when b"1110_1101_011", -- SBC / Absolute
xrg when b"1111_1101_010", -- SBC / Absolute,X
val when b"1111_1101_011", -- SBC / Absolute,X
arg when b"1111_1101_100", -- SBC / Absolute,X
yrg when b"1111_1001_010", -- SBC / Absolute,Y
val when b"1111_1001_011", -- SBC / Absolute,Y
arg when b"1111_1001_100", -- SBC / Absolute,Y
xrg when b"1110_0001_010", -- SBC / (Indirect,X)
alq when b"1110_0001_011", -- SBC / (Indirect,X)
val when b"1110_0001_100", -- SBC / (Indirect,X)
arg when b"1110_0001_101", -- SBC / (Indirect,X)
alq when b"1111_0001_010", -- SBC / (Indirect),Y
yrg when b"1111_0001_011", -- SBC / (Indirect),Y
val when b"1111_0001_100", -- SBC / (Indirect),Y
arg when b"1111_0001_101", -- SBC / (Indirect),Y
arg when b"1000_0101_010", -- STA / Zero Page
xrg when b"1001_0101_010", -- STA / Zero Page,X
arg when b"1001_0101_011", -- STA / Zero Page,X
arg when b"1000_1101_011", -- STA / Absolute
xrg when b"1001_1101_010", -- STA / Absolute,X
val when b"1001_1101_011", -- STA / Absolute,X
arg when b"1001_1101_100", -- STA / Absolute,X
yrg when b"1001_1001_010", -- STA / Absolute,Y
val when b"1001_1001_011", -- STA / Absolute,Y
arg when b"1001_1001_100", -- STA / Absolute,Y
xrg when b"1000_0001_010", -- STA / (Indirect,X)
alq when b"1000_0001_011", -- STA / (Indirect,X)
val when b"1000_0001_100", -- STA / (Indirect,X)
arg when b"1000_0001_101", -- STA / (Indirect,X)
alq when b"1001_0001_010", -- STA / (Indirect),Y
yrg when b"1001_0001_011", -- STA / (Indirect),Y
val when b"1001_0001_100", -- STA / (Indirect),Y
arg when b"1001_0001_101", -- STA / (Indirect),Y
xrg when b"1000_0110_010", -- STX / Zero Page
yrg when b"1001_0110_010", -- STX / Zero Page,Y
xrg when b"1001_0110_011", -- STX / Zero Page,Y
xrg when b"1000_1110_011", -- STX / Absolute
yrg when b"1000_0100_010", -- STY / Zero Page
xrg when b"1001_0100_010", -- STY / Zero Page,X
yrg when b"1001_0100_011", -- STY / Zero Page,X
yrg when b"1000_1100_011", -- STY / Absolute
arg when b"1010_1010_001", -- TAX / Implied
arg when b"1010_1000_001", -- TAY / Implied
srg when b"1011_1010_001", -- TSX / Implied
xrg when b"1000_1010_001", -- TXA / Implied
xrg when b"1001_1010_001", -- TXS / Implied
yrg when b"1001_1000_001", -- TYA / Implied
din when others;
-- ALU Input B
with s_addr select o_alu_b_op <=
alq when b"0111_0101_010", -- ADC / Zero Page,X
val when b"0111_1101_010", -- ADC / Absolute,X
one when b"0111_1101_011", -- ADC / Absolute,X
val when b"0111_1001_010", -- ADC / Absolute,Y
one when b"0111_1001_011", -- ADC / Absolute,Y
alq when b"0110_0001_010", -- ADC / (Indirect,X)
one when b"0110_0001_011", -- ADC / (Indirect,X)
one when b"0111_0001_010", -- ADC / (Indirect),Y
val when b"0111_0001_011", -- ADC / (Indirect),Y
one when b"0111_0001_100", -- ADC / (Indirect),Y
alq when b"0011_0101_010", -- AND / Zero Page,X
val when b"0011_1101_010", -- AND / Absolute,X
one when b"0011_1101_011", -- AND / Absolute,X
val when b"0011_1001_010", -- AND / Absolute,Y
one when b"0011_1001_011", -- AND / Absolute,Y
alq when b"0010_0001_010", -- AND / (Indirect,X)
one when b"0010_0001_011", -- AND / (Indirect,X)
one when b"0011_0001_010", -- AND / (Indirect),Y
val when b"0011_0001_011", -- AND / (Indirect),Y
one when b"0011_0001_100", -- AND / (Indirect),Y
alq when b"0001_0110_010", -- ASL / Zero Page,X
val when b"0001_1110_010", -- ASL / Absolute,X
auc when b"0001_1110_011", -- ASL / Absolute,X
aci when b"1001_0000_010", -- BCC / Relative
aci when b"1011_0000_010", -- BCS / Relative
aci when b"1111_0000_010", -- BEQ / Relative
aci when b"0011_0000_010", -- BMI / Relative
aci when b"1101_0000_010", -- BNE / Relative
aci when b"0001_0000_010", -- BPL / Relative
one when b"0000_0000_001", -- BRK / Implied
one when b"0000_0000_010", -- BRK / Implied
one when b"0000_0000_011", -- BRK / Implied
one when b"0000_0000_101", -- BRK / Implied
aci when b"0101_0000_010", -- BVC / Relative
aci when b"0111_0000_010", -- BVS / Relative
alq when b"1101_0101_010", -- CMP / Zero Page,X
val when b"1101_1101_010", -- CMP / Absolute,X
one when b"1101_1101_011", -- CMP / Absolute,X
val when b"1101_1001_010", -- CMP / Absolute,Y
one when b"1101_1001_011", -- CMP / Absolute,Y
alq when b"1100_0001_010", -- CMP / (Indirect,X)
one when b"1100_0001_011", -- CMP / (Indirect,X)
one when b"1101_0001_010", -- CMP / (Indirect),Y
val when b"1101_0001_011", -- CMP / (Indirect),Y
one when b"1101_0001_100", -- CMP / (Indirect),Y
one when b"1100_0110_011", -- DEC / Zero Page
val when b"1101_0110_010", -- DEC / Zero Page,X
one when b"1101_0110_100", -- DEC / Zero Page,X
one when b"1100_1110_100", -- DEC / Absolute
val when b"1101_1110_010", -- DEC / Absolute,X
auc when b"1101_1110_011", -- DEC / Absolute,X
one when b"1101_1110_101", -- DEC / Absolute,X
one when b"1100_1010_001", -- DEX / Implied
one when b"1000_1000_001", -- DEY / Implied
alq when b"0101_0101_010", -- EOR / Zero Page,X
val when b"0101_1101_010", -- EOR / Absolute,X
one when b"0101_1101_011", -- EOR / Absolute,X
val when b"0101_1001_010", -- EOR / Absolute,Y
one when b"0101_1001_011", -- EOR / Absolute,Y
alq when b"0100_0001_010", -- EOR / (Indirect,X)
one when b"0100_0001_011", -- EOR / (Indirect,X)
one when b"0101_0001_010", -- EOR / (Indirect),Y
val when b"0101_0001_011", -- EOR / (Indirect),Y
one when b"0101_0001_100", -- EOR / (Indirect),Y
one when b"1110_0110_011", -- INC / Zero Page
val when b"1111_0110_010", -- INC / Zero Page,X
one when b"1111_0110_100", -- INC / Zero Page,X
one when b"1110_1110_100", -- INC / Absolute
val when b"1111_1110_010", -- INC / Absolute,X
auc when b"1111_1110_011", -- INC / Absolute,X
one when b"1111_1110_101", -- INC / Absolute,X
one when b"0000_0011_001", -- INT / Implied
one when b"0000_0011_010", -- INT / Implied
one when b"0000_0011_011", -- INT / Implied
one when b"0000_0011_101", -- INT / Implied
one when b"1110_1000_001", -- INX / Implied
one when b"1100_1000_001", -- INY / Implied
one when b"0110_1100_011", -- JMP / Indirect
one when b"0010_0000_011", -- JSR / Absolute
one when b"0010_0000_100", -- JSR / Absolute
alq when b"1011_0101_010", -- LDA / Zero Page,X
val when b"1011_1101_010", -- LDA / Absolute,X
one when b"1011_1101_011", -- LDA / Absolute,X
val when b"1011_1001_010", -- LDA / Absolute,Y
one when b"1011_1001_011", -- LDA / Absolute,Y
alq when b"1010_0001_010", -- LDA / (Indirect,X)
one when b"1010_0001_011", -- LDA / (Indirect,X)
one when b"1011_0001_010", -- LDA / (Indirect),Y
val when b"1011_0001_011", -- LDA / (Indirect),Y
one when b"1011_0001_100", -- LDA / (Indirect),Y
alq when b"1011_0110_010", -- LDX / Zero Page,Y
val when b"1011_1110_010", -- LDX / Absolute,Y
one when b"1011_1110_011", -- LDX / Absolute,Y
alq when b"1011_0100_010", -- LDY / Zero Page,X
val when b"1011_1100_010", -- LDY / Absolute,X
one when b"1011_1100_011", -- LDY / Absolute,X
alq when b"0101_0110_010", -- LSR / Zero Page,X
val when b"0101_1110_010", -- LSR / Absolute,X
auc when b"0101_1110_011", -- LSR / Absolute,X
one when b"0000_0100_001", -- NMI / Implied
one when b"0000_0100_010", -- NMI / Implied
one when b"0000_0100_011", -- NMI / Implied
one when b"0000_0100_101", -- NMI / Implied
alq when b"0001_0101_010", -- ORA / Zero Page,X
val when b"0001_1101_010", -- ORA / Absolute,X
one when b"0001_1101_011", -- ORA / Absolute,X
val when b"0001_1001_010", -- ORA / Absolute,Y
one when b"0001_1001_011", -- ORA / Absolute,Y
alq when b"0000_0001_010", -- ORA / (Indirect,X)
one when b"0000_0001_011", -- ORA / (Indirect,X)
one when b"0001_0001_010", -- ORA / (Indirect),Y
val when b"0001_0001_011", -- ORA / (Indirect),Y
one when b"0001_0001_100", -- ORA / (Indirect),Y
one when b"0100_1000_010", -- PHA / Implied
one when b"0000_1000_010", -- PHP / Implied
one when b"0110_1000_010", -- PLA / Implied
one when b"0010_1000_010", -- PLP / Implied
alq when b"0011_0110_010", -- ROL / Zero Page,X
val when b"0011_1110_010", -- ROL / Absolute,X
auc when b"0011_1110_011", -- ROL / Absolute,X
alq when b"0111_0110_010", -- ROR / Zero Page,X
val when b"0111_1110_010", -- ROR / Absolute,X
auc when b"0111_1110_011", -- ROR / Absolute,X
one when b"0000_0010_010", -- RST / Implied
one when b"0100_0000_010", -- RTI / Implied
one when b"0100_0000_011", -- RTI / Implied
one when b"0100_0000_100", -- RTI / Implied
one when b"0110_0000_010", -- RTS / Implied
one when b"0110_0000_011", -- RTS / Implied
alq when b"1111_0101_010", -- SBC / Zero Page,X
val when b"1111_1101_010", -- SBC / Absolute,X
one when b"1111_1101_011", -- SBC / Absolute,X
val when b"1111_1001_010", -- SBC / Absolute,Y
one when b"1111_1001_011", -- SBC / Absolute,Y
alq when b"1110_0001_010", -- SBC / (Indirect,X)
one when b"1110_0001_011", -- SBC / (Indirect,X)
one when b"1111_0001_010", -- SBC / (Indirect),Y
val when b"1111_0001_011", -- SBC / (Indirect),Y
one when b"1111_0001_100", -- SBC / (Indirect),Y
alq when b"1001_0101_010", -- STA / Zero Page,X
val when b"1001_1101_010", -- STA / Absolute,X
auc when b"1001_1101_011", -- STA / Absolute,X
val when b"1001_1001_010", -- STA / Absolute,Y
auc when b"1001_1001_011", -- STA / Absolute,Y
alq when b"1000_0001_010", -- STA / (Indirect,X)
one when b"1000_0001_011", -- STA / (Indirect,X)
one when b"1001_0001_010", -- STA / (Indirect),Y
val when b"1001_0001_011", -- STA / (Indirect),Y
auc when b"1001_0001_100", -- STA / (Indirect),Y
alq when b"1001_0110_010", -- STX / Zero Page,Y
alq when b"1001_0100_010", -- STY / Zero Page,X
din when others;
-- Registers
with s_addr select o_reg_op <=
arg when b"0110_1001_001", -- ADC / Immediate
arg when b"0110_0101_010", -- ADC / Zero Page
arg when b"0111_0101_011", -- ADC / Zero Page,X
arg when b"0110_1101_011", -- ADC / Absolute
arg when b"0111_1101_100", -- ADC / Absolute,X
arg when b"0111_1001_100", -- ADC / Absolute,Y
arg when b"0110_0001_101", -- ADC / (Indirect,X)
arg when b"0111_0001_101", -- ADC / (Indirect),Y
arg when b"0010_1001_001", -- AND / Immediate
arg when b"0010_0101_010", -- AND / Zero Page
arg when b"0011_0101_011", -- AND / Zero Page,X
arg when b"0010_1101_011", -- AND / Absolute
arg when b"0011_1101_100", -- AND / Absolute,X
arg when b"0011_1001_100", -- AND / Absolute,Y
arg when b"0010_0001_101", -- AND / (Indirect,X)
arg when b"0011_0001_101", -- AND / (Indirect),Y
arg when b"0000_1010_001", -- ASL / Accumulator
srg when b"0000_0000_011", -- BRK / Implied
xrg when b"1100_1010_001", -- DEX / Implied
yrg when b"1000_1000_001", -- DEY / Implied
arg when b"0100_1001_001", -- EOR / Immediate
arg when b"0100_0101_010", -- EOR / Zero Page
arg when b"0101_0101_011", -- EOR / Zero Page,X
arg when b"0100_1101_011", -- EOR / Absolute
arg when b"0101_1101_100", -- EOR / Absolute,X
arg when b"0101_1001_100", -- EOR / Absolute,Y
arg when b"0100_0001_101", -- EOR / (Indirect,X)
arg when b"0101_0001_101", -- EOR / (Indirect),Y
srg when b"0000_0011_011", -- INT / Implied
xrg when b"1110_1000_001", -- INX / Implied
yrg when b"1100_1000_001", -- INY / Implied
srg when b"0010_0000_100", -- JSR / Absolute
arg when b"1010_1001_001", -- LDA / Immediate
arg when b"1010_0101_010", -- LDA / Zero Page
arg when b"1011_0101_011", -- LDA / Zero Page,X
arg when b"1010_1101_011", -- LDA / Absolute
arg when b"1011_1101_100", -- LDA / Absolute,X
arg when b"1011_1001_100", -- LDA / Absolute,Y
arg when b"1010_0001_101", -- LDA / (Indirect,X)
arg when b"1011_0001_101", -- LDA / (Indirect),Y
xrg when b"1010_0010_001", -- LDX / Immediate
xrg when b"1010_0110_010", -- LDX / Zero Page
xrg when b"1011_0110_011", -- LDX / Zero Page,Y
xrg when b"1010_1110_011", -- LDX / Absolute
xrg when b"1011_1110_100", -- LDX / Absolute,Y
yrg when b"1010_0000_001", -- LDY / Immediate
yrg when b"1010_0100_010", -- LDY / Zero Page
yrg when b"1011_0100_011", -- LDY / Zero Page,X
yrg when b"1010_1100_011", -- LDY / Absolute
yrg when b"1011_1100_100", -- LDY / Absolute,X
arg when b"0100_1010_001", -- LSR / Accumulator
srg when b"0000_0100_011", -- NMI / Implied
arg when b"0000_1001_001", -- ORA / Immediate
arg when b"0000_0101_010", -- ORA / Zero Page
arg when b"0001_0101_011", -- ORA / Zero Page,X
arg when b"0000_1101_011", -- ORA / Absolute
arg when b"0001_1101_100", -- ORA / Absolute,X
arg when b"0001_1001_100", -- ORA / Absolute,Y
arg when b"0000_0001_101", -- ORA / (Indirect,X)
arg when b"0001_0001_101", -- ORA / (Indirect),Y
srg when b"0100_1000_010", -- PHA / Implied
srg when b"0000_1000_010", -- PHP / Implied
srg when b"0110_1000_010", -- PLA / Implied
arg when b"0110_1000_011", -- PLA / Implied
srg when b"0010_1000_010", -- PLP / Implied
arg when b"0010_1010_001", -- ROL / Accumulator
arg when b"0110_1010_001", -- ROR / Accumulator
srg when b"0100_0000_100", -- RTI / Implied
srg when b"0110_0000_011", -- RTS / Implied
arg when b"1110_1001_001", -- SBC / Immediate
arg when b"1110_0101_010", -- SBC / Zero Page
arg when b"1111_0101_011", -- SBC / Zero Page,X
arg when b"1110_1101_011", -- SBC / Absolute
arg when b"1111_1101_100", -- SBC / Absolute,X
arg when b"1111_1001_100", -- SBC / Absolute,Y
arg when b"1110_0001_101", -- SBC / (Indirect,X)
arg when b"1111_0001_101", -- SBC / (Indirect),Y
xrg when b"1010_1010_001", -- TAX / Implied
yrg when b"1010_1000_001", -- TAY / Implied
xrg when b"1011_1010_001", -- TSX / Implied
arg when b"1000_1010_001", -- TXA / Implied
srg when b"1001_1010_001", -- TXS / Implied
arg when b"1001_1000_001", -- TYA / Implied
nop when others;
-- Memory Address
with s_addr select o_addr_op <=
zaq when b"0110_0101_001", -- ADC / Zero Page
zaq when b"0111_0101_001", -- ADC / Zero Page,X
zaq when b"0111_0101_010", -- ADC / Zero Page,X
aqd when b"0110_1101_010", -- ADC / Absolute
daq when b"0111_1101_010", -- ADC / Absolute,X
aqd when b"0111_1101_011", -- ADC / Absolute,X
daq when b"0111_1001_010", -- ADC / Absolute,Y
aqd when b"0111_1001_011", -- ADC / Absolute,Y
zaq when b"0110_0001_001", -- ADC / (Indirect,X)
zaq when b"0110_0001_010", -- ADC / (Indirect,X)
zaq when b"0110_0001_011", -- ADC / (Indirect,X)
daq when b"0110_0001_100", -- ADC / (Indirect,X)
zaq when b"0111_0001_001", -- ADC / (Indirect),Y
zaq when b"0111_0001_010", -- ADC / (Indirect),Y
daq when b"0111_0001_011", -- ADC / (Indirect),Y
aqd when b"0111_0001_100", -- ADC / (Indirect),Y
zaq when b"0010_0101_001", -- AND / Zero Page
zaq when b"0011_0101_001", -- AND / Zero Page,X
zaq when b"0011_0101_010", -- AND / Zero Page,X
aqd when b"0010_1101_010", -- AND / Absolute
daq when b"0011_1101_010", -- AND / Absolute,X
aqd when b"0011_1101_011", -- AND / Absolute,X
daq when b"0011_1001_010", -- AND / Absolute,Y
aqd when b"0011_1001_011", -- AND / Absolute,Y
zaq when b"0010_0001_001", -- AND / (Indirect,X)
zaq when b"0010_0001_010", -- AND / (Indirect,X)
zaq when b"0010_0001_011", -- AND / (Indirect,X)
daq when b"0010_0001_100", -- AND / (Indirect,X)
zaq when b"0011_0001_001", -- AND / (Indirect),Y
zaq when b"0011_0001_010", -- AND / (Indirect),Y
daq when b"0011_0001_011", -- AND / (Indirect),Y
aqd when b"0011_0001_100", -- AND / (Indirect),Y
zaq when b"0000_0110_001", -- ASL / Zero Page
zvl when b"0000_0110_010", -- ASL / Zero Page
zvl when b"0000_0110_011", -- ASL / Zero Page
zaq when b"0001_0110_001", -- ASL / Zero Page,X
zaq when b"0001_0110_010", -- ASL / Zero Page,X
zvl when b"0001_0110_011", -- ASL / Zero Page,X
zvl when b"0001_0110_100", -- ASL / Zero Page,X
aqd when b"0000_1110_010", -- ASL / Absolute
adv when b"0000_1110_011", -- ASL / Absolute
adv when b"0000_1110_100", -- ASL / Absolute
daq when b"0001_1110_010", -- ASL / Absolute,X
aqd when b"0001_1110_011", -- ASL / Absolute,X
adv when b"0001_1110_100", -- ASL / Absolute,X
adv when b"0001_1110_101", -- ASL / Absolute,X
zaq when b"0010_0100_001", -- BIT / Zero Page
aqd when b"0010_1100_010", -- BIT / Absolute
oad when b"0000_0000_001", -- BRK / Implied
oad when b"0000_0000_010", -- BRK / Implied
oad when b"0000_0000_011", -- BRK / Implied
vaq when b"0000_0000_100", -- BRK / Implied
vaq when b"0000_0000_101", -- BRK / Implied
zaq when b"1100_0101_001", -- CMP / Zero Page
zaq when b"1101_0101_001", -- CMP / Zero Page,X
zaq when b"1101_0101_010", -- CMP / Zero Page,X
aqd when b"1100_1101_010", -- CMP / Absolute
daq when b"1101_1101_010", -- CMP / Absolute,X
aqd when b"1101_1101_011", -- CMP / Absolute,X
daq when b"1101_1001_010", -- CMP / Absolute,Y
aqd when b"1101_1001_011", -- CMP / Absolute,Y
zaq when b"1100_0001_001", -- CMP / (Indirect,X)
zaq when b"1100_0001_010", -- CMP / (Indirect,X)
zaq when b"1100_0001_011", -- CMP / (Indirect,X)
daq when b"1100_0001_100", -- CMP / (Indirect,X)
zaq when b"1101_0001_001", -- CMP / (Indirect),Y
zaq when b"1101_0001_010", -- CMP / (Indirect),Y
daq when b"1101_0001_011", -- CMP / (Indirect),Y
aqd when b"1101_0001_100", -- CMP / (Indirect),Y
zaq when b"1110_0100_001", -- CPX / Zero Page
aqd when b"1110_1100_010", -- CPX / Absolute
zaq when b"1100_0100_001", -- CPY / Zero Page
aqd when b"1100_1100_010", -- CPY / Absolute
zaq when b"1100_0110_001", -- DEC / Zero Page
zvl when b"1100_0110_010", -- DEC / Zero Page
zvl when b"1100_0110_011", -- DEC / Zero Page
zaq when b"1101_0110_001", -- DEC / Zero Page,X
zaq when b"1101_0110_010", -- DEC / Zero Page,X
zvl when b"1101_0110_011", -- DEC / Zero Page,X
zvl when b"1101_0110_100", -- DEC / Zero Page,X
aqd when b"1100_1110_010", -- DEC / Absolute
adv when b"1100_1110_011", -- DEC / Absolute
adv when b"1100_1110_100", -- DEC / Absolute
daq when b"1101_1110_010", -- DEC / Absolute,X
aqd when b"1101_1110_011", -- DEC / Absolute,X
adv when b"1101_1110_100", -- DEC / Absolute,X
adv when b"1101_1110_101", -- DEC / Absolute,X
zaq when b"0100_0101_001", -- EOR / Zero Page
zaq when b"0101_0101_001", -- EOR / Zero Page,X
zaq when b"0101_0101_010", -- EOR / Zero Page,X
aqd when b"0100_1101_010", -- EOR / Absolute
daq when b"0101_1101_010", -- EOR / Absolute,X
aqd when b"0101_1101_011", -- EOR / Absolute,X
daq when b"0101_1001_010", -- EOR / Absolute,Y
aqd when b"0101_1001_011", -- EOR / Absolute,Y
zaq when b"0100_0001_001", -- EOR / (Indirect,X)
zaq when b"0100_0001_010", -- EOR / (Indirect,X)
zaq when b"0100_0001_011", -- EOR / (Indirect,X)
daq when b"0100_0001_100", -- EOR / (Indirect,X)
zaq when b"0101_0001_001", -- EOR / (Indirect),Y
zaq when b"0101_0001_010", -- EOR / (Indirect),Y
daq when b"0101_0001_011", -- EOR / (Indirect),Y
aqd when b"0101_0001_100", -- EOR / (Indirect),Y
zaq when b"1110_0110_001", -- INC / Zero Page
zvl when b"1110_0110_010", -- INC / Zero Page
zvl when b"1110_0110_011", -- INC / Zero Page
zaq when b"1111_0110_001", -- INC / Zero Page,X
zaq when b"1111_0110_010", -- INC / Zero Page,X
zvl when b"1111_0110_011", -- INC / Zero Page,X
zvl when b"1111_0110_100", -- INC / Zero Page,X
aqd when b"1110_1110_010", -- INC / Absolute
adv when b"1110_1110_011", -- INC / Absolute
adv when b"1110_1110_100", -- INC / Absolute
daq when b"1111_1110_010", -- INC / Absolute,X
aqd when b"1111_1110_011", -- INC / Absolute,X
adv when b"1111_1110_100", -- INC / Absolute,X
adv when b"1111_1110_101", -- INC / Absolute,X
oad when b"0000_0011_001", -- INT / Implied
oad when b"0000_0011_010", -- INT / Implied
oad when b"0000_0011_011", -- INT / Implied
vaq when b"0000_0011_100", -- INT / Implied
vaq when b"0000_0011_101", -- INT / Implied
daq when b"0110_1100_010", -- JMP / Indirect
vaq when b"0110_1100_011", -- JMP / Indirect
oaq when b"0010_0000_001", -- JSR / Absolute
oaq when b"0010_0000_010", -- JSR / Absolute
oaq when b"0010_0000_011", -- JSR / Absolute
zaq when b"1010_0101_001", -- LDA / Zero Page
zaq when b"1011_0101_001", -- LDA / Zero Page,X
zaq when b"1011_0101_010", -- LDA / Zero Page,X
aqd when b"1010_1101_010", -- LDA / Absolute
daq when b"1011_1101_010", -- LDA / Absolute,X
aqd when b"1011_1101_011", -- LDA / Absolute,X
daq when b"1011_1001_010", -- LDA / Absolute,Y
aqd when b"1011_1001_011", -- LDA / Absolute,Y
zaq when b"1010_0001_001", -- LDA / (Indirect,X)
zaq when b"1010_0001_010", -- LDA / (Indirect,X)
zaq when b"1010_0001_011", -- LDA / (Indirect,X)
daq when b"1010_0001_100", -- LDA / (Indirect,X)
zaq when b"1011_0001_001", -- LDA / (Indirect),Y
zaq when b"1011_0001_010", -- LDA / (Indirect),Y
daq when b"1011_0001_011", -- LDA / (Indirect),Y
aqd when b"1011_0001_100", -- LDA / (Indirect),Y
zaq when b"1010_0110_001", -- LDX / Zero Page
zaq when b"1011_0110_001", -- LDX / Zero Page,Y
zaq when b"1011_0110_010", -- LDX / Zero Page,Y
aqd when b"1010_1110_010", -- LDX / Absolute
daq when b"1011_1110_010", -- LDX / Absolute,Y
aqd when b"1011_1110_011", -- LDX / Absolute,Y
zaq when b"1010_0100_001", -- LDY / Zero Page
zaq when b"1011_0100_001", -- LDY / Zero Page,X
zaq when b"1011_0100_010", -- LDY / Zero Page,X
aqd when b"1010_1100_010", -- LDY / Absolute
daq when b"1011_1100_010", -- LDY / Absolute,X
aqd when b"1011_1100_011", -- LDY / Absolute,X
zaq when b"0100_0110_001", -- LSR / Zero Page
zvl when b"0100_0110_010", -- LSR / Zero Page
zvl when b"0100_0110_011", -- LSR / Zero Page
zaq when b"0101_0110_001", -- LSR / Zero Page,X
zaq when b"0101_0110_010", -- LSR / Zero Page,X
zvl when b"0101_0110_011", -- LSR / Zero Page,X
zvl when b"0101_0110_100", -- LSR / Zero Page,X
aqd when b"0100_1110_010", -- LSR / Absolute
adv when b"0100_1110_011", -- LSR / Absolute
adv when b"0100_1110_100", -- LSR / Absolute
daq when b"0101_1110_010", -- LSR / Absolute,X
aqd when b"0101_1110_011", -- LSR / Absolute,X
adv when b"0101_1110_100", -- LSR / Absolute,X
adv when b"0101_1110_101", -- LSR / Absolute,X
oad when b"0000_0100_001", -- NMI / Implied
oad when b"0000_0100_010", -- NMI / Implied
oad when b"0000_0100_011", -- NMI / Implied
vaq when b"0000_0100_100", -- NMI / Implied
vaq when b"0000_0100_101", -- NMI / Implied
zaq when b"0000_0101_001", -- ORA / Zero Page
zaq when b"0001_0101_001", -- ORA / Zero Page,X
zaq when b"0001_0101_010", -- ORA / Zero Page,X
aqd when b"0000_1101_010", -- ORA / Absolute
daq when b"0001_1101_010", -- ORA / Absolute,X
aqd when b"0001_1101_011", -- ORA / Absolute,X
daq when b"0001_1001_010", -- ORA / Absolute,Y
aqd when b"0001_1001_011", -- ORA / Absolute,Y
zaq when b"0000_0001_001", -- ORA / (Indirect,X)
zaq when b"0000_0001_010", -- ORA / (Indirect,X)
zaq when b"0000_0001_011", -- ORA / (Indirect,X)
daq when b"0000_0001_100", -- ORA / (Indirect,X)
zaq when b"0001_0001_001", -- ORA / (Indirect),Y
zaq when b"0001_0001_010", -- ORA / (Indirect),Y
daq when b"0001_0001_011", -- ORA / (Indirect),Y
aqd when b"0001_0001_100", -- ORA / (Indirect),Y
oaq when b"0100_1000_001", -- PHA / Implied
oaq when b"0000_1000_001", -- PHP / Implied
oaq when b"0110_1000_001", -- PLA / Implied
oaq when b"0110_1000_010", -- PLA / Implied
oaq when b"0010_1000_001", -- PLP / Implied
oaq when b"0010_1000_010", -- PLP / Implied
zaq when b"0010_0110_001", -- ROL / Zero Page
zvl when b"0010_0110_010", -- ROL / Zero Page
zvl when b"0010_0110_011", -- ROL / Zero Page
zaq when b"0011_0110_001", -- ROL / Zero Page,X
zaq when b"0011_0110_010", -- ROL / Zero Page,X
zvl when b"0011_0110_011", -- ROL / Zero Page,X
zvl when b"0011_0110_100", -- ROL / Zero Page,X
aqd when b"0010_1110_010", -- ROL / Absolute
adv when b"0010_1110_011", -- ROL / Absolute
adv when b"0010_1110_100", -- ROL / Absolute
daq when b"0011_1110_010", -- ROL / Absolute,X
aqd when b"0011_1110_011", -- ROL / Absolute,X
adv when b"0011_1110_100", -- ROL / Absolute,X
adv when b"0011_1110_101", -- ROL / Absolute,X
zaq when b"0110_0110_001", -- ROR / Zero Page
zvl when b"0110_0110_010", -- ROR / Zero Page
zvl when b"0110_0110_011", -- ROR / Zero Page
zaq when b"0111_0110_001", -- ROR / Zero Page,X
zaq when b"0111_0110_010", -- ROR / Zero Page,X
zvl when b"0111_0110_011", -- ROR / Zero Page,X
zvl when b"0111_0110_100", -- ROR / Zero Page,X
aqd when b"0110_1110_010", -- ROR / Absolute
adv when b"0110_1110_011", -- ROR / Absolute
adv when b"0110_1110_100", -- ROR / Absolute
daq when b"0111_1110_010", -- ROR / Absolute,X
aqd when b"0111_1110_011", -- ROR / Absolute,X
adv when b"0111_1110_100", -- ROR / Absolute,X
adv when b"0111_1110_101", -- ROR / Absolute,X
vaq when b"0000_0010_001", -- RST / Implied
vaq when b"0000_0010_010", -- RST / Implied
oaq when b"0100_0000_001", -- RTI / Implied
oaq when b"0100_0000_010", -- RTI / Implied
oaq when b"0100_0000_011", -- RTI / Implied
oaq when b"0100_0000_100", -- RTI / Implied
oaq when b"0110_0000_001", -- RTS / Implied
oaq when b"0110_0000_010", -- RTS / Implied
oaq when b"0110_0000_011", -- RTS / Implied
zaq when b"1110_0101_001", -- SBC / Zero Page
zaq when b"1111_0101_001", -- SBC / Zero Page,X
zaq when b"1111_0101_010", -- SBC / Zero Page,X
aqd when b"1110_1101_010", -- SBC / Absolute
daq when b"1111_1101_010", -- SBC / Absolute,X
aqd when b"1111_1101_011", -- SBC / Absolute,X
daq when b"1111_1001_010", -- SBC / Absolute,Y
aqd when b"1111_1001_011", -- SBC / Absolute,Y
zaq when b"1110_0001_001", -- SBC / (Indirect,X)
zaq when b"1110_0001_010", -- SBC / (Indirect,X)
zaq when b"1110_0001_011", -- SBC / (Indirect,X)
daq when b"1110_0001_100", -- SBC / (Indirect,X)
zaq when b"1111_0001_001", -- SBC / (Indirect),Y
zaq when b"1111_0001_010", -- SBC / (Indirect),Y
daq when b"1111_0001_011", -- SBC / (Indirect),Y
aqd when b"1111_0001_100", -- SBC / (Indirect),Y
zaq when b"1000_0101_001", -- STA / Zero Page
zaq when b"1001_0101_001", -- STA / Zero Page,X
zaq when b"1001_0101_010", -- STA / Zero Page,X
aqd when b"1000_1101_010", -- STA / Absolute
daq when b"1001_1101_010", -- STA / Absolute,X
aqd when b"1001_1101_011", -- STA / Absolute,X
daq when b"1001_1001_010", -- STA / Absolute,Y
aqd when b"1001_1001_011", -- STA / Absolute,Y
zaq when b"1000_0001_001", -- STA / (Indirect,X)
zaq when b"1000_0001_010", -- STA / (Indirect,X)
zaq when b"1000_0001_011", -- STA / (Indirect,X)
daq when b"1000_0001_100", -- STA / (Indirect,X)
zaq when b"1001_0001_001", -- STA / (Indirect),Y
zaq when b"1001_0001_010", -- STA / (Indirect),Y
daq when b"1001_0001_011", -- STA / (Indirect),Y
aqd when b"1001_0001_100", -- STA / (Indirect),Y
zaq when b"1000_0110_001", -- STX / Zero Page
zaq when b"1001_0110_001", -- STX / Zero Page,Y
zaq when b"1001_0110_010", -- STX / Zero Page,Y
aqd when b"1000_1110_010", -- STX / Absolute
zaq when b"1000_0100_001", -- STY / Zero Page
zaq when b"1001_0100_001", -- STY / Zero Page,X
zaq when b"1001_0100_010", -- STY / Zero Page,X
aqd when b"1000_1100_010", -- STY / Absolute
nop when others;
-- Branching
o_branch_at_cycle_1 <= (s_addr(7 downto 0) = b"1_0000_001");
o_branch_at_cycle_2 <= (s_addr(7 downto 0) = b"1_0000_010");
s_addr <= std_ulogic_vector(i_opcode & i_cycle);
end;
|
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity fmc116_ltc2175_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000005";
PRESEL : std_logic_vector(7 downto 0) := x"00"
);
port (
rst : in std_logic;
clk : in std_logic;
serial_clk : in std_logic;
sclk_ext : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end fmc116_ltc2175_ctrl;
architecture fmc116_ltc2175_ctrl_syn of fmc116_ltc2175_ctrl is
component fmc11x_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component ltc2175_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(2 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000005";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000004";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0000004";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
--signal sclk_prebuf : std_logic;
--signal serial_clk : std_logic;
--signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal out_reg_val_ack : std_logic;
signal wr_ack : std_logic;
signal serial_val_ack : std_logic;
signal serial_val_ack_sclk : std_logic;
signal busy_del1 : std_logic;
signal busy_del2 : std_logic;
signal init_done_sclk_del : std_logic;
signal wr_cmd_ack : std_logic;
signal wr_ack_requested : std_logic;
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(2 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(15+PRESEL'length downto 0);
signal init_address : std_logic_vector(2 downto 0);
signal init_data : std_logic_vector(15 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 6.66MHz, due to Tddata of 75ns)
----------------------------------------------------------------------------------------------------
-- process (clk)
-- -- Divide by 2^5 = 32, CLKmax = 32 x 6.66MHz
-- variable clk_div : std_logic_vector(4 downto 0) := (others => '0');
-- begin
-- if (rising_edge(clk)) then
-- clk_div := clk_div + '1';
-- -- The slave samples the data on the rising edge of SCLK.
-- -- therefore we make sure the external clock is slightly
-- -- after the internal clock.
-- sclk_ext <= clk_div(clk_div'length-1);
-- sclk_prebuf <= sclk_ext;
-- end if;
-- end process;
--
-- bufg_sclk : bufg
-- port map (
-- i => sclk_prebuf,
-- o => serial_clk
-- );
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc11x_stellar_cmd_inst : fmc11x_stellar_cmd
generic map
(
start_addr =>start_addr,
stop_addr =>stop_addr
)
port map
(
reset =>rst,
--command if
clk_cmd =>clk_cmd,
out_cmd =>out_cmd,
out_cmd_val =>out_cmd_val,
in_cmd =>in_cmd,
in_cmd_val =>in_cmd_val,
--register interface
clk_reg =>clk_cmd,
out_reg =>out_reg,
out_reg_val =>out_reg_val,
out_reg_val_ack =>out_reg_val_ack,
out_reg_addr =>out_reg_addr,
in_reg =>in_reg,
in_reg_val =>in_reg_val,
in_reg_req =>in_reg_req,
in_reg_addr =>in_reg_addr,
wr_ack => wr_ack,
mbx_in_reg =>(others=>'0'),
mbx_in_val =>'0'
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
wr_ack <= '0';
wr_cmd_ack <= '0';
wr_ack_requested <= '0';
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_GLOBAL) then
wr_cmd_ack <= '1';
else
wr_cmd_ack <= '0';
end if;
-- only send a write Ack on request:
if (out_reg_val_ack = '1') then
wr_ack_requested <= '1';
elsif(wr_ack = '1') then
wr_ack_requested <= '0';
end if;
if (wr_cmd_ack = '1' and wr_ack_requested = '1') then
wr_ack <= '1';
elsif(serial_val_ack = '1' and inst_rw = '0' and wr_ack_requested = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & '0' & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(2 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(2 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
-- Detect the end of a serial write, don't send an Ack after completing the initialisation.
process (serial_clk)
begin
if (rising_edge(serial_clk)) then
busy_del1 <= busy;
busy_del2 <= busy_del1;
init_done_sclk_del <= init_done_sclk;
if(busy_del2 = '1' and busy_del1 = '0' and init_done_sclk_del = '1' and init_done_sclk = '1') then
serial_val_ack_sclk <= '1';
elsif(busy_del2 = '1' and busy_del1 = '0' and init_done_sclk_del = '0' and init_done_sclk = '0') then
serial_val_ack_sclk <= '1';
else
serial_val_ack_sclk <= '0';
end if;
end if;
end process;
-- Transfer end write pulse to other clock domain
pulse2pulse_inst2 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => serial_val_ack_sclk,
pulseout => serial_val_ack,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= PRESEL & '0' & "0000" & init_data(10 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(10 downto 8) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= PRESEL & inst_rw & "0000" & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length-2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
ltc2175_init_mem_inst : ltc2175_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc116_ltc2175_ctrl_syn;
|
-------------------------------------------------------------------------------
--
-- $Id: t48_comp_pack-p.vhd,v 1.12 2008-05-01 19:28:41 arniml Exp $
--
-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_alu_pack.alu_op_t;
use work.t48_cond_branch_pack.branch_conditions_t;
use work.t48_cond_branch_pack.comp_value_t;
use work.t48_decoder_pack.mnemonic_t;
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;
use work.t48_pack.dmem_addr_t;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.mstate_t;
use work.t48_pack.word_t;
use work.t48_pack.nibble_t;
package t48_comp_pack is
component t48_alu
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_accu_i : in boolean;
write_shadow_i : in boolean;
write_temp_reg_i : in boolean;
read_alu_i : in boolean;
carry_i : in std_logic;
carry_o : out std_logic;
aux_carry_o : out std_logic;
alu_op_i : in alu_op_t;
use_carry_i : in boolean;
da_high_i : in boolean;
da_overflow_o : out boolean;
accu_low_i : in boolean;
p06_temp_reg_i : in boolean;
p60_temp_reg_i : in boolean
);
end component;
component t48_bus_mux
port (
alu_data_i : in word_t;
bus_data_i : in word_t;
dec_data_i : in word_t;
dm_data_i : in word_t;
pm_data_i : in word_t;
p1_data_i : in word_t;
p2_data_i : in word_t;
psw_data_i : in word_t;
tim_data_i : in word_t;
data_o : out word_t
);
end component;
component t48_clock_ctrl
generic (
xtal_div_3_g : integer := 1
);
port (
clk_i : in std_logic;
xtal_i : in std_logic;
xtal_en_i : in boolean;
res_i : in std_logic;
en_clk_i : in boolean;
xtal3_o : out boolean;
t0_o : out std_logic;
multi_cycle_i : in boolean;
assert_psen_i : in boolean;
assert_prog_i : in boolean;
assert_rd_i : in boolean;
assert_wr_i : in boolean;
mstate_o : out mstate_t;
second_cycle_o : out boolean;
ale_o : out boolean;
psen_o : out boolean;
prog_o : out boolean;
rd_o : out boolean;
wr_o : out boolean
);
end component;
component t48_cond_branch
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
compute_take_i : in boolean;
branch_cond_i : in branch_conditions_t;
take_branch_o : out boolean;
accu_i : in word_t;
t0_i : in std_logic;
t1_i : in std_logic;
int_n_i : in std_logic;
f0_i : in std_logic;
f1_i : in std_logic;
tf_i : in std_logic;
carry_i : in std_logic;
comp_value_i : in comp_value_t
);
end component;
component t48_db_bus
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
ea_i : in std_logic;
data_i : in word_t;
data_o : out word_t;
write_bus_i : in boolean;
read_bus_i : in boolean;
output_pcl_i : in boolean;
bidir_bus_i : in boolean;
pcl_i : in word_t;
db_i : in word_t;
db_o : out word_t;
db_dir_o : out std_logic
);
end component;
component t48_decoder
generic (
register_mnemonic_g : integer := 1
);
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
ea_i : in std_logic;
ale_i : in boolean;
int_n_i : in std_logic;
t0_dir_o : out std_logic;
data_i : in word_t;
data_o : out word_t;
alu_write_accu_o : out boolean;
alu_write_shadow_o : out boolean;
alu_write_temp_reg_o : out boolean;
alu_read_alu_o : out boolean;
bus_write_bus_o : out boolean;
bus_read_bus_o : out boolean;
dm_write_dmem_addr_o : out boolean;
dm_write_dmem_o : out boolean;
dm_read_dmem_o : out boolean;
p1_write_p1_o : out boolean;
p1_read_p1_o : out boolean;
p2_write_p2_o : out boolean;
p2_write_exp_o : out boolean;
p2_read_p2_o : out boolean;
pm_write_pcl_o : out boolean;
pm_read_pcl_o : out boolean;
pm_write_pch_o : out boolean;
pm_read_pch_o : out boolean;
pm_read_pmem_o : out boolean;
psw_read_psw_o : out boolean;
psw_read_sp_o : out boolean;
psw_write_psw_o : out boolean;
psw_write_sp_o : out boolean;
alu_carry_i : in std_logic;
alu_op_o : out alu_op_t;
alu_da_high_o : out boolean;
alu_accu_low_o : out boolean;
alu_da_overflow_i : in boolean;
alu_p06_temp_reg_o : out boolean;
alu_p60_temp_reg_o : out boolean;
alu_use_carry_o : out boolean;
bus_output_pcl_o : out boolean;
bus_bidir_bus_o : out boolean;
clk_multi_cycle_o : out boolean;
clk_assert_psen_o : out boolean;
clk_assert_prog_o : out boolean;
clk_assert_rd_o : out boolean;
clk_assert_wr_o : out boolean;
clk_mstate_i : in mstate_t;
clk_second_cycle_i : in boolean;
cnd_compute_take_o : out boolean;
cnd_branch_cond_o : out branch_conditions_t;
cnd_take_branch_i : in boolean;
cnd_comp_value_o : out comp_value_t;
cnd_f1_o : out std_logic;
cnd_tf_o : out std_logic;
dm_addr_type_o : out dmem_addr_ident_t;
tim_read_timer_o : out boolean;
tim_write_timer_o : out boolean;
tim_start_t_o : out boolean;
tim_start_cnt_o : out boolean;
tim_stop_tcnt_o : out boolean;
p1_read_reg_o : out boolean;
p2_read_reg_o : out boolean;
p2_read_exp_o : out boolean;
p2_output_pch_o : out boolean;
pm_inc_pc_o : out boolean;
pm_write_pmem_addr_o : out boolean;
pm_addr_type_o : out pmem_addr_ident_t;
psw_special_data_o : out std_logic;
psw_carry_i : in std_logic;
psw_aux_carry_i : in std_logic;
psw_f0_i : in std_logic;
psw_inc_stackp_o : out boolean;
psw_dec_stackp_o : out boolean;
psw_write_carry_o : out boolean;
psw_write_aux_carry_o : out boolean;
psw_write_f0_o : out boolean;
psw_write_bs_o : out boolean;
tim_overflow_i : in boolean
);
end component;
component t48_dmem_ctrl
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
write_dmem_addr_i : in boolean;
write_dmem_i : in boolean;
read_dmem_i : in boolean;
addr_type_i : in dmem_addr_ident_t;
bank_select_i : in std_logic;
data_o : out word_t;
dmem_data_i : in word_t;
dmem_addr_o : out dmem_addr_t;
dmem_we_o : out std_logic;
dmem_data_o : out word_t
);
end component;
component t48_int
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
clk_mstate_i : in mstate_t;
jtf_executed_i : in boolean;
tim_overflow_i : in boolean;
tf_o : out std_logic;
en_tcnti_i : in boolean;
dis_tcnti_i : in boolean;
int_n_i : in std_logic;
ale_i : in boolean;
last_cycle_i : in boolean;
en_i_i : in boolean;
dis_i_i : in boolean;
ext_int_o : out boolean;
tim_int_o : out boolean;
retr_executed_i : in boolean;
int_executed_i : in boolean;
int_pending_o : out boolean;
int_in_progress_o : out boolean
);
end component;
component t48_timer
generic (
sample_t1_state_g : integer := 4
);
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
t1_i : in std_logic;
clk_mstate_i : in mstate_t;
data_i : in word_t;
data_o : out word_t;
read_timer_i : in boolean;
write_timer_i : in boolean;
start_t_i : in boolean;
start_cnt_i : in boolean;
stop_tcnt_i : in boolean;
overflow_o : out std_logic
);
end component;
component t48_p1
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
p1_i : in word_t;
p1_o : out word_t;
p1_low_imp_o : out std_logic
);
end component;
component t48_p2
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
xtal_i : in std_logic;
xtal_en_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_p2_i : in boolean;
write_exp_i : in boolean;
read_p2_i : in boolean;
read_reg_i : in boolean;
read_exp_i : in boolean;
output_pch_i : in boolean;
pch_i : in nibble_t;
p2_i : in word_t;
p2_o : out word_t;
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic
);
end component;
component t48_pmem_ctrl
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
write_pcl_i : in boolean;
read_pcl_i : in boolean;
write_pch_i : in boolean;
read_pch_i : in boolean;
inc_pc_i : in boolean;
write_pmem_addr_i : in boolean;
addr_type_i : in pmem_addr_ident_t;
read_pmem_i : in boolean;
pmem_addr_o : out pmem_addr_t;
pmem_data_i : in word_t
);
end component;
component t48_psw
port (
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
data_i : in word_t;
data_o : out word_t;
read_psw_i : in boolean;
read_sp_i : in boolean;
write_psw_i : in boolean;
write_sp_i : in boolean;
special_data_i : in std_logic;
inc_stackp_i : in boolean;
dec_stackp_i : in boolean;
write_carry_i : in boolean;
write_aux_carry_i : in boolean;
write_f0_i : in boolean;
write_bs_i : in boolean;
carry_o : out std_logic;
aux_carry_i : in std_logic;
aux_carry_o : out std_logic;
f0_o : out std_logic;
bs_o : out std_logic
);
end component;
end t48_comp_pack;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top mig_wrap_proc_sys_reset_1_0 -prefix
-- mig_wrap_proc_sys_reset_1_0_ mig_wrap_proc_sys_reset_0_0_stub.vhdl
-- Design : mig_wrap_proc_sys_reset_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mig_wrap_proc_sys_reset_1_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_proc_sys_reset_1_0;
architecture stub of mig_wrap_proc_sys_reset_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2016.4";
begin
end;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: RANDOM_DECODER_FIFO
-- AUTHORS: Vojtěch Jeřábek <xjerab17@stud.feec.vutbr.cz>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RANDOM_DECODER_FIFO is
Port(
CLK : in std_logic;
RST : in std_logic;
GENERATE_NEW : in std_logic; -- enable generate one random component
GENERATE_FIVE : in std_logic; -- enable generate five random components
KOMP0 : out std_logic_vector(5 downto 0); -- nejnovejci trubka
KOMP1 : out std_logic_vector(5 downto 0); -- ||
KOMP2 : out std_logic_vector(5 downto 0); -- posouva se dolu
KOMP3 : out std_logic_vector(5 downto 0); -- \/
KOMP4 : out std_logic_vector(5 downto 0) -- nejstarsi trubka, vklada se do hraciho pole
);
end RANDOM_DECODER_FIFO;
architecture Behavioral of RANDOM_DECODER_FIFO is
signal generate_random : std_logic;
signal generate_random_1 : std_logic;
signal generate_random_2 : std_logic;
signal fifo_move : std_logic;
signal generate_random_five : unsigned(11 downto 0);
signal fifo_input : std_logic_vector(3 downto 0);
signal komp0_sig : std_logic_vector(5 downto 0);
signal komp1_sig : std_logic_vector(5 downto 0);
signal komp2_sig : std_logic_vector(5 downto 0);
signal komp3_sig : std_logic_vector(5 downto 0);
signal komp4_sig : std_logic_vector(5 downto 0);
signal komp_sig : std_logic_vector(5 downto 0);
begin
--------------------------------------------------------------------------------
-- vygenerovani 5-ti nahodnych komponent za sebou
process (CLK, RST)
begin
if (RST = '1') then
generate_random_five <= (others=>'0');
generate_random_1 <='0';
elsif(rising_edge(CLK)) then
if (GENERATE_FIVE='1') then
generate_random_five <= "000000000001";
generate_random_1<='0';
else
if (generate_random_five=4096) then
generate_random_five <= (others=>'0');
generate_random_1<='0';
elsif (generate_random_five=0) then
generate_random_1<='0';
generate_random_five <= (others=>'0');
elsif (generate_random_five=237) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=1638) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=2484) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=3186) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=4001) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
else
generate_random_1<='0';
generate_random_five <= generate_random_five + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- vygenerovani 1 nahodne komponenty
process (CLK, RST)
begin
if (RST = '1') then
generate_random_2 <= '0';
elsif (rising_edge(CLK)) then
if (GENERATE_NEW = '1') then
generate_random_2 <= '1';
else
generate_random_2 <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- vygenerovani prirazeni nahodneho cila na KOMP0_sig a posuv ostatnich. KOPM4_sig zanika
process (CLK, RST)
begin
if (RST = '1') then
komp0_sig <= (others=>'0');
komp1_sig <= (others=>'0');
komp2_sig <= (others=>'0');
komp3_sig <= (others=>'0');
komp4_sig <= (others=>'0');
elsif (rising_edge(CLK)) then
if (fifo_move = '1') then
komp0_sig <= komp_sig;
komp1_sig <= komp0_sig;
komp2_sig <= komp1_sig;
komp3_sig <= komp2_sig;
komp4_sig <= komp3_sig;
end if;
end if;
end process;
KOMP0 <= komp0_sig;
KOMP1 <= komp1_sig;
KOMP2 <= komp2_sig;
KOMP3 <= komp3_sig;
KOMP4 <= komp4_sig;
--------------------------------------------------------------------------------
-- prepocet kombinacni logiky nahodneho cisla
with fifo_input select
komp_sig <= "000001" when "0000",
"000001" when "0001",
"010001" when "0010",
"010001" when "0011", --rovne trubky
"000010" when "0100",
"010010" when "0101",
"100010" when "0110",
"110010" when "0111", --zahla trubka
"000011" when "1000",
"000011" when "1001", --kriz, je 2x kvuli lepsi cetnosti
"111111" when "1111",
"000000" when others;
--------------------------------------------------------------------------------
-- instancovani komponenty RANDOM_GENERATOR
random_generator_i: entity work.RANDOM_GENERATOR
generic map (
Number_of_options => 10,
Flip_Flops => 4
)
port map (
CLK => CLK,
RST => RST,
RANDOM_PULSE => generate_random,
RANDOM_OUT => fifo_input,
ENABLE_OUT => fifo_move
);
generate_random <= generate_random_1 OR generate_random_2;
end Behavioral;
|
--------------------------------------------------------------------------------
--! @file top.vhd
--! @brief Toplevel module for KC705 eval board.
--! @author Yuan Mei
--!
--! Target Devices: Kintex-7 XC7K325T-FFG900-2
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
LIBRARY work;
USE work.utility.ALL;
ENTITY top IS
GENERIC (
ENABLE_DEBUG : boolean := false;
ENABLE_GIG_ETH : boolean := true;
ENABLE_TEN_GIG_ETH : boolean := true
);
PORT (
SYS_RST : IN std_logic;
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
USER_CLK_P : IN std_logic; --! 156.250 MHz
USER_CLK_N : IN std_logic;
SGMIICLK_Q0_P : IN std_logic; --! 125 MHz, for GTP/GTH/GTX
SGMIICLK_Q0_N : IN std_logic;
--
LED8Bit : OUT std_logic_vector(7 DOWNTO 0);
DIPSw4Bit : IN std_logic_vector(3 DOWNTO 0);
BTN5Bit : IN std_logic_vector(4 DOWNTO 0);
USER_SMA_CLOCK_P : OUT std_logic;
USER_SMA_CLOCK_N : OUT std_logic;
USER_SMA_GPIO_P : OUT std_logic;
USER_SMA_GPIO_N : OUT std_logic;
-- UART via usb
USB_RX : OUT std_logic;
USB_TX : IN std_logic;
-- SFP
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS_LS : IN std_logic;
SFP_TX_DISABLE_N : OUT std_logic;
-- Gigbit eth interface (RGMII)
PHY_RESET_N : OUT std_logic;
RGMII_TXD : OUT std_logic_vector(3 DOWNTO 0);
RGMII_TX_CTL : OUT std_logic;
RGMII_TXC : OUT std_logic;
RGMII_RXD : IN std_logic_vector(3 DOWNTO 0);
RGMII_RX_CTL : IN std_logic;
RGMII_RXC : IN std_logic;
MDIO : INOUT std_logic;
MDC : OUT std_logic;
-- SDRAM
DDR3_DQ : INOUT std_logic_vector(63 DOWNTO 0);
DDR3_DQS_P : INOUT std_logic_vector(7 DOWNTO 0);
DDR3_DQS_N : INOUT std_logic_vector(7 DOWNTO 0);
-- Outputs
DDR3_ADDR : OUT std_logic_vector(13 DOWNTO 0);
DDR3_BA : OUT std_logic_vector(2 DOWNTO 0);
DDR3_RAS_N : OUT std_logic;
DDR3_CAS_N : OUT std_logic;
DDR3_WE_N : OUT std_logic;
DDR3_RESET_N : OUT std_logic;
DDR3_CK_P : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CK_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CKE : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CS_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_DM : OUT std_logic_vector(7 DOWNTO 0);
DDR3_ODT : OUT std_logic_vector(0 DOWNTO 0);
--
I2C_SCL : INOUT std_logic;
I2C_SDA : INOUT std_logic;
-- FMC HPC
FMC_HPC_HA_P :INOUT std_logic_vector(23 DOWNTO 0);
FMC_HPC_HA_N :INOUT std_logic_vector(23 DOWNTO 0);
FMC_HPC_LA_P :INOUT std_logic_vector(33 DOWNTO 0);
FMC_HPC_LA_N :INOUT std_logic_vector(33 DOWNTO 0);
FMC_HPC_CLK1_M2C_P : INOUT std_logic;
FMC_HPC_CLK1_M2C_N : INOUT std_logic;
-- FMC LPC
FMC_LPC_LA_P :INOUT std_logic_vector(33 DOWNTO 0);
FMC_LPC_LA_N :INOUT std_logic_vector(33 DOWNTO 0)
);
END top;
ARCHITECTURE Behavioral OF top IS
-- Components
COMPONENT global_clock_reset
PORT (
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
FORCE_RST : IN std_logic;
-- output
GLOBAL_RST : OUT std_logic;
SYS_CLK : OUT std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
CLK_OUT3 : OUT std_logic;
CLK_OUT4 : OUT std_logic
);
END COMPONENT;
---------------------------------------------< ten_gig_eth
COMPONENT ten_gig_eth
PORT (
REFCLK_P : IN std_logic; -- 156.25MHz for transceiver
REFCLK_N : IN std_logic;
RESET : IN std_logic;
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS : IN std_logic; -- loss of receiver signal
SFP_TX_DISABLE : OUT std_logic;
-- clk156 domain, clock generated by the core
CLK156 : OUT std_logic;
PCS_PMA_CORE_STATUS : OUT std_logic_vector(7 DOWNTO 0);
TX_STATISTICS_VECTOR : OUT std_logic_vector(25 DOWNTO 0);
TX_STATISTICS_VALID : OUT std_logic;
RX_STATISTICS_VECTOR : OUT std_logic_vector(29 DOWNTO 0);
RX_STATISTICS_VALID : OUT std_logic;
PAUSE_VAL : IN std_logic_vector(15 DOWNTO 0);
PAUSE_REQ : IN std_logic;
TX_IFG_DELAY : IN std_logic_vector(7 DOWNTO 0);
-- emac control interface
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WDATA : IN std_logic_vector(31 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN : IN std_logic;
TX_AXIS_FIFO_ACLK : IN std_logic;
TX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
TX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
TX_AXIS_FIFO_TVALID : IN std_logic;
TX_AXIS_FIFO_TLAST : IN std_logic;
TX_AXIS_FIFO_TREADY : OUT std_logic;
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN : IN std_logic;
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : OUT std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : OUT std_logic;
RX_AXIS_FIFO_TLAST : OUT std_logic;
RX_AXIS_FIFO_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_packet_gen
PORT (
RESET : IN std_logic;
MEM_CLK : IN std_logic;
MEM_WE : IN std_logic; -- memory write enable
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_D : IN std_logic_vector(31 DOWNTO 0); -- memory data
--
TX_AXIS_ACLK : IN std_logic;
TX_START : IN std_logic;
TX_BYTES : IN std_logic_vector(15 DOWNTO 0); -- number of bytes to send
TX_AXIS_TDATA : OUT std_logic_vector(63 DOWNTO 0);
TX_AXIS_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
TX_AXIS_TVALID : OUT std_logic;
TX_AXIS_TLAST : OUT std_logic;
TX_AXIS_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_rx_parser
PORT (
RESET : IN std_logic;
RX_AXIS_FIFO_ARESETN : OUT std_logic;
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : IN std_logic;
RX_AXIS_FIFO_TLAST : IN std_logic;
RX_AXIS_FIFO_TREADY : OUT std_logic;
-- Constants
SRC_MAC : IN std_logic_vector(47 DOWNTO 0);
SRC_IP : IN std_logic_vector(31 DOWNTO 0);
SRC_PORT : IN std_logic_vector(15 DOWNTO 0);
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q : OUT std_logic_vector(127 DOWNTO 0);
CMD_FIFO_EMPTY : OUT std_logic;
CMD_FIFO_RDREQ : IN std_logic;
CMD_FIFO_RDCLK : IN std_logic
);
END COMPONENT;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gig_eth
COMPONENT gig_eth
PORT (
-- asynchronous reset
GLBL_RST : IN std_logic;
-- clocks
GTX_CLK : IN std_logic; -- 125MHz
REF_CLK : IN std_logic; -- 200MHz for IODELAY
-- PHY interface
PHY_RESETN : OUT std_logic;
-- RGMII Interface
RGMII_TXD : OUT std_logic_vector(3 DOWNTO 0);
RGMII_TX_CTL : OUT std_logic;
RGMII_TXC : OUT std_logic;
RGMII_RXD : IN std_logic_vector(3 DOWNTO 0);
RGMII_RX_CTL : IN std_logic;
RGMII_RXC : IN std_logic;
-- MDIO Interface
MDIO : INOUT std_logic;
MDC : OUT std_logic;
-- TCP
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
TCP_CONNECTION_RESET : IN std_logic;
TX_TDATA : IN std_logic_vector(7 DOWNTO 0);
TX_TVALID : IN std_logic;
TX_TREADY : OUT std_logic;
RX_TDATA : OUT std_logic_vector(7 DOWNTO 0);
RX_TVALID : OUT std_logic;
RX_TREADY : IN std_logic;
-- FIFO
TCP_USE_FIFO : IN std_logic;
TX_FIFO_WRCLK : IN std_logic;
TX_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
TX_FIFO_WREN : IN std_logic;
TX_FIFO_FULL : OUT std_logic;
RX_FIFO_RDCLK : IN std_logic;
RX_FIFO_Q : OUT std_logic_vector(31 DOWNTO 0);
RX_FIFO_RDEN : IN std_logic;
RX_FIFO_EMPTY : OUT std_logic
);
END COMPONENT;
---------------------------------------------> gig_eth
---------------------------------------------< TOP_SR
COMPONENT Top_SR IS
GENERIC (
WIDTH : positive := 130;
CNT_WIDTH : positive := 8;
DIV_WIDTH : positive := 6;
COUNT_WIDTH : positive := 64;
SHIFT_DIRECTION : positive := 1;
READ_TRIG_SRC : natural := 0;
READ_DELAY : natural := 1
);
PORT (
clk_in :IN std_logic;
rst :IN std_logic;
start :IN std_logic;
din :IN std_logic_vector(129 DOWNTO 0);
data_in_p :IN std_logic;
data_in_n :IN std_logic;
div :IN std_logic_vector(5 DOWNTO 0);
clk :OUT std_logic;
clk_sr_p :OUT std_logic;
clk_sr_n :OUT std_logic;
data_out_p :OUT std_logic;
data_out_n :OUT std_logic;
load_sr_p :OUT std_logic;
load_sr_n :OUT std_logic;
valid :OUT std_logic;
dout :OUT std_logic_vector(129 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------> TOP_SR
---------------------------------------------< PULSE_SYNCHRONISE
COMPONENT pulse_synchronise
PORT (
pulse_in :IN std_logic;
clk_in :IN std_logic;
clk_out :IN std_logic;
rst :IN std_logic;
pulse_out :OUT std_logic
);
END COMPONENT;
---------------------------------------------> PULSE_SYNCHRONISE
---------------------------------------------< shiftreg driver for DAC8568
COMPONENT fifo2shiftreg
GENERIC (
DATA_WIDTH : positive := 32; -- parallel data width
CLK_DIV_WIDTH : positive := 16;
DELAY_AFTER_SYNCn : natural := 0; --number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL : std_logic := '0'; --High or low for SCLK when not switching
DOUT_DRIVE_EDGE : std_logic := '1'; -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE : std_logic := '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
);
PORT (
CLK : IN std_logic; -- clock
RESET : IN std_logic; -- reset
-- input data interface
WR_CLK : IN std_logic; -- FIFO write clock
DINFIFO : IN std_logic_vector(15 DOWNTO 0);
WR_EN : IN std_logic;
WR_PULSE : IN std_logic; -- one pulse writes one word, regardless of pulse duration
FULL : OUT std_logic;
-- captured data
BUSY : OUT std_logic;
DATAOUT : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
-- serial interface
CLK_DIV : IN std_logic_vector(CLK_DIV_WIDTH-1 DOWNTO 0); -- SCLK freq is CLK / 2**(CLK_DIV)
SCLK : OUT std_logic;
DOUT : OUT std_logic;
SYNCn : OUT std_logic;
DIN : IN std_logic
);
END COMPONENT;
---------------------------------------------> shiftreg driver for DAC8568
---------------------------------------------< UART/RS232
COMPONENT control_interface
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- system clock
-- From FPGA to PC
FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- interface fifo data output port
FIFO_EMPTY : OUT std_logic; -- interface fifo "emtpy" signal
FIFO_RDREQ : IN std_logic; -- interface fifo read request
FIFO_RDCLK : IN std_logic; -- interface fifo read clock
-- From PC to FPGA, FWFT
CMD_FIFO_Q : IN std_logic_vector(35 DOWNTO 0); -- interface command fifo data out port
CMD_FIFO_EMPTY : IN std_logic; -- interface command fifo "emtpy" signal
CMD_FIFO_RDREQ : OUT std_logic; -- interface command fifo read request
-- Digital I/O
CONFIG_REG : OUT std_logic_vector(511 DOWNTO 0); -- thirtytwo 16bit registers
PULSE_REG : OUT std_logic_vector(15 DOWNTO 0); -- 16bit pulse register
STATUS_REG : IN std_logic_vector(175 DOWNTO 0); -- eleven 16bit registers
-- Memory interface
MEM_WE : OUT std_logic; -- memory write enable
MEM_ADDR : OUT std_logic_vector(31 DOWNTO 0);
MEM_DIN : OUT std_logic_vector(31 DOWNTO 0); -- memory data input
MEM_DOUT : IN std_logic_vector(31 DOWNTO 0); -- memory data output
-- Data FIFO interface, FWFT
DATA_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
DATA_FIFO_EMPTY : IN std_logic;
DATA_FIFO_RDREQ : OUT std_logic;
DATA_FIFO_RDCLK : OUT std_logic
);
END COMPONENT;
---------------------------------------------> UART/RS232
---------------------------------------------< SDRAM
COMPONENT sdram_ddr3
GENERIC (
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 32;
APP_ADDR_WIDTH : positive := 28;
APP_DATA_WIDTH : positive := 512;
APP_MASK_WIDTH : positive := 64;
APP_ADDR_BURST : positive := 8
);
PORT (
CLK : IN std_logic; -- system clock, must be the same as intended in MIG
REFCLK : IN std_logic; -- 200MHz for iodelay
RESET : IN std_logic;
-- SDRAM_DDR3
-- Inouts
DDR3_DQ : INOUT std_logic_vector(63 DOWNTO 0);
DDR3_DQS_P : INOUT std_logic_vector(7 DOWNTO 0);
DDR3_DQS_N : INOUT std_logic_vector(7 DOWNTO 0);
-- Outputs
DDR3_ADDR : OUT std_logic_vector(13 DOWNTO 0);
DDR3_BA : OUT std_logic_vector(2 DOWNTO 0);
DDR3_RAS_N : OUT std_logic;
DDR3_CAS_N : OUT std_logic;
DDR3_WE_N : OUT std_logic;
DDR3_RESET_N : OUT std_logic;
DDR3_CK_P : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CK_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CKE : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CS_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_DM : OUT std_logic_vector(7 DOWNTO 0);
DDR3_ODT : OUT std_logic_vector(0 DOWNTO 0);
-- Status Outputs
INIT_CALIB_COMPLETE : OUT std_logic;
-- Internal data r/w interface
UI_CLK : OUT std_logic;
--
CTRL_RESET : IN std_logic;
WR_START : IN std_logic;
WR_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_STOP : IN std_logic;
WR_WRAP_AROUND : IN std_logic;
POST_TRIGGER : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_BUSY : OUT std_logic;
WR_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
TRIGGER_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_WRAPPED : OUT std_logic;
RD_START : IN std_logic;
RD_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_ADDR_END : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_BUSY : OUT std_logic;
--
DATA_FIFO_RESET : IN std_logic;
INDATA_FIFO_WRCLK : IN std_logic;
INDATA_FIFO_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
INDATA_FIFO_FULL : OUT std_logic;
INDATA_FIFO_WREN : IN std_logic;
--
OUTDATA_FIFO_RDCLK : IN std_logic;
OUTDATA_FIFO_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0);
OUTDATA_FIFO_EMPTY : OUT std_logic;
OUTDATA_FIFO_RDEN : IN std_logic;
--
DBG_APP_ADDR : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
DBG_APP_EN : OUT std_logic;
DBG_APP_RDY : OUT std_logic;
DBG_APP_WDF_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
DBG_APP_WDF_END : OUT std_logic;
DBG_APP_WDF_WREN : OUT std_logic;
DBG_APP_WDF_RDY : OUT std_logic;
DBG_APP_RD_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
DBG_APP_RD_DATA_VALID : OUT std_logic
);
END COMPONENT;
---------------------------------------------> SDRAM
---------------------------------------------< debug : ILA and VIO (`Chipscope')
COMPONENT dbg_ila
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(63 DOWNTO 0);
PROBE1 : IN std_logic_vector(79 DOWNTO 0);
PROBE2 : IN std_logic_vector(79 DOWNTO 0);
PROBE3 : IN std_logic_vector(2047 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_ila1
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(15 DOWNTO 0);
PROBE1 : IN std_logic_vector(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_vio
PORT (
CLK : IN std_logic;
PROBE_IN0 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN1 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN2 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN3 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN4 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN5 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN6 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN7 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN8 : IN std_logic_vector(35 DOWNTO 0);
PROBE_OUT0 : OUT std_logic_vector(63 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------> debug : ila and vio (`chipscope')
-- Signals
SIGNAL reset : std_logic;
SIGNAL sys_clk : std_logic;
SIGNAL clk_50MHz : std_logic;
SIGNAL clk_100MHz : std_logic;
SIGNAL clk_125MHz : std_logic;
SIGNAL clk_200MHz : std_logic;
SIGNAL clk_250MHz : std_logic;
SIGNAL clk156 : std_logic;
SIGNAL clk_sgmii_i : std_logic;
SIGNAL clk_sgmii : std_logic;
---------------------------------------------< UART/RS232
SIGNAL uart_rx_data : std_logic_vector(7 DOWNTO 0);
SIGNAL uart_rx_rdy : std_logic;
SIGNAL control_clk : std_logic;
SIGNAL control_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL control_fifo_rdreq : std_logic;
SIGNAL control_fifo_empty : std_logic;
SIGNAL control_fifo_rdclk : std_logic;
SIGNAL cmd_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL cmd_fifo_empty : std_logic;
SIGNAL cmd_fifo_rdreq : std_logic;
-- thirtytwo 16bit registers
SIGNAL config_reg : std_logic_vector(511 DOWNTO 0);
-- 16bit pulse register
SIGNAL pulse_reg : std_logic_vector(15 DOWNTO 0);
-- eleven 16bit registers
SIGNAL status_reg : std_logic_vector(175 DOWNTO 0) := (OTHERS => '0');
SIGNAL control_mem_we : std_logic;
SIGNAL control_mem_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL control_mem_din : std_logic_vector(31 DOWNTO 0);
---------------------------------------------> UART/RS232
---------------------------------------------< ten_gig_eth
SIGNAL sfp_tx_disable_i : std_logic;
SIGNAL sPcs_pma_core_status : std_logic_vector(7 DOWNTO 0);
SIGNAL sEmac_status_vector : std_logic_vector(1 DOWNTO 0);
SIGNAL sTx_axis_fifo_aresetn : std_logic;
SIGNAL sTx_axis_fifo_aclk : std_logic;
SIGNAL sTx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sTx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sTx_axis_fifo_tvalid : std_logic;
SIGNAL sTx_axis_fifo_tlast : std_logic;
SIGNAL sTx_axis_fifo_tready : std_logic;
SIGNAL sRx_axis_fifo_aresetn : std_logic;
SIGNAL sRx_axis_fifo_aclk : std_logic;
SIGNAL sRx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sRx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sRx_axis_fifo_tvalid : std_logic;
SIGNAL sRx_axis_fifo_tlast : std_logic;
SIGNAL sRx_axis_fifo_tready : std_logic;
-- control interface
SIGNAL s_axi_aclk : std_logic;
SIGNAL s_axi_aresetn : std_logic;
SIGNAL s_axi_awaddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_awvalid : std_logic;
SIGNAL s_axi_awready : std_logic;
SIGNAL s_axi_wdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_wvalid : std_logic;
SIGNAL s_axi_wready : std_logic;
SIGNAL s_axi_bresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_bvalid : std_logic;
SIGNAL s_axi_bready : std_logic;
SIGNAL s_axi_araddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_arvalid : std_logic;
SIGNAL s_axi_arready : std_logic;
SIGNAL s_axi_rdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_rresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_rvalid : std_logic;
SIGNAL s_axi_rready : std_logic;
-- packets
SIGNAL ten_gig_eth_tx_start : std_logic;
SIGNAL tge_cmd_fifo_q : std_logic_vector(127 DOWNTO 0);
SIGNAL tge_cmd_fifo_empty : std_logic;
SIGNAL tge_cmd_fifo_rdreq : std_logic;
---------------------------------------------> ten_gig_eth
SIGNAL usr_data_output : std_logic_vector (7 DOWNTO 0);
---------------------------------------------< gig_eth
SIGNAL gig_eth_mac_addr : std_logic_vector(47 DOWNTO 0);
SIGNAL gig_eth_ipv4_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_subnet_mask : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_gateway_ip_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_tdata : std_logic_vector(7 DOWNTO 0);
SIGNAL gig_eth_tx_tvalid : std_logic;
SIGNAL gig_eth_tx_tready : std_logic;
SIGNAL gig_eth_rx_tdata : std_logic_vector(7 DOWNTO 0);
SIGNAL gig_eth_rx_tvalid : std_logic;
SIGNAL gig_eth_rx_tready : std_logic;
SIGNAL gig_eth_tcp_use_fifo : std_logic;
SIGNAL gig_eth_tx_fifo_wrclk : std_logic;
SIGNAL gig_eth_tx_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_fifo_wren : std_logic;
SIGNAL gig_eth_tx_fifo_full : std_logic;
SIGNAL gig_eth_rx_fifo_rdclk : std_logic;
SIGNAL gig_eth_rx_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_rx_fifo_rden : std_logic;
SIGNAL gig_eth_rx_fifo_empty : std_logic;
---------------------------------------------> gig_eth
---------------------------------------------< SDRAM
SIGNAL sdram_app_addr : std_logic_vector(28-1 DOWNTO 0);
SIGNAL sdram_app_en : std_logic;
SIGNAL sdram_app_rdy : std_logic;
SIGNAL sdram_app_wdf_data : std_logic_vector(512-1 DOWNTO 0);
SIGNAL sdram_app_wdf_end : std_logic;
SIGNAL sdram_app_wdf_wren : std_logic;
SIGNAL sdram_app_wdf_rdy : std_logic;
SIGNAL sdram_app_rd_data : std_logic_vector(512-1 DOWNTO 0);
SIGNAL sdram_app_rd_data_valid : std_logic;
---------------------------------------------> SDRAM
---------------------------------------------< IDATA
SIGNAL TRIG_OUT_0 : std_logic;
SIGNAL idata_cmd_out : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_out_val : std_logic;
SIGNAL idata_cmd_in : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_in_val : std_logic;
SIGNAL idata_adc_data_clk : std_logic;
SIGNAL idata_adc_refout_clkdiv : std_logic;
SIGNAL idata_adc_data0 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data1 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data2 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data3 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data4 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data5 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data6 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data7 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data8 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data9 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data10 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data11 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_data_fifo_reset : std_logic;
SIGNAL idata_data_fifo_rdclk : std_logic;
SIGNAL idata_data_fifo_din : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outdata_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outvalid : std_logic;
SIGNAL idata_data_fifo_wren : std_logic;
SIGNAL idata_data_fifo_rden : std_logic;
SIGNAL idata_data_fifo_dout : std_logic_vector(31 DOWNTO 0);
SIGNAL idata_data_fifo_full : std_logic;
SIGNAL idata_data_fifo_empty : std_logic;
SIGNAL idata_idata_fifo_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_idata_fifo_wren : std_logic;
SIGNAL idata_idata_fifo_rden : std_logic;
SIGNAL idata_idata_fifo_full : std_logic;
SIGNAL idata_idata_fifo_empty : std_logic;
SIGNAL idata_trig_allow : std_logic;
SIGNAL idata_trig_in : std_logic;
SIGNAL idata_trig_synced : std_logic;
SIGNAL idata_data_wr_start : std_logic;
SIGNAL idata_data_wr_busy : std_logic;
SIGNAL idata_data_wr_wrapped : std_logic;
---------------------------------------------> IDATA
---------------------------------------------< debug
SIGNAL dbg_ila_probe0 : std_logic_vector (63 DOWNTO 0);
SIGNAL dbg_ila_probe1 : std_logic_vector (79 DOWNTO 0);
SIGNAL dbg_ila_probe2 : std_logic_vector (79 DOWNTO 0);
SIGNAL dbg_ila_probe3 : std_logic_vector (2047 DOWNTO 0);
SIGNAL dbg_vio_probe_out0 : std_logic_vector (63 DOWNTO 0);
SIGNAL dbg_ila1_probe0 : std_logic_vector (15 DOWNTO 0);
SIGNAL dbg_ila1_probe1 : std_logic_vector (15 DOWNTO 0);
ATTRIBUTE mark_debug : string;
ATTRIBUTE keep : string;
ATTRIBUTE mark_debug OF USB_TX : SIGNAL IS "true";
ATTRIBUTE mark_debug OF uart_rx_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF uart_rx_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_rdreq : SIGNAL IS "true";
ATTRIBUTE mark_debug OF config_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF status_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF pulse_reg : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_we : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_addr : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_din : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF sPcs_pma_core_status : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sEmac_status_vector : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tready : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF ten_gig_eth_tx_start : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_rdreq : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF gig_eth_tx_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_fifo_q : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF sdram_app_addr : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_en : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_end : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_wren : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rd_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rd_data_valid : SIGNAL IS "true";
---------------------------------------------> debug
---------------------------------------------< TOP_SR
SIGNAL div : std_logic_vector (5 DOWNTO 0);
SIGNAL din : std_logic_vector (129 DOWNTO 0);
SIGNAL dout : std_logic_vector( 129 DOWNTO 0);
SIGNAL valid : std_logic;
SIGNAL clk_sr_contr : std_logic;
---------------------------------------------> TOP_SR
---------------------------------------------< PULSE_SYNCHRONISE
SIGNAL pulse_in : std_logic;
SIGNAL clk_out : std_logic;
SIGNAL pulse_out : std_logic;
---------------------------------------------> PULSE_SYNCHRONISE
---------------------------------------------< shiftreg driver for DAC8568
SIGNAL spi_sclk : std_logic;
SIGNAL spi_dout : std_logic;
SIGNAL spi_din : std_logic;
SIGNAL spi_sync_n : std_logic;
---------------------------------------------> shiftreg driver for DAC8568
---------------------------------------------< Sigma-Delta
SIGNAL clk_sync_buf : std_logic;
SIGNAL sdm_clk_disable : std_logic;
SIGNAL sdm_clk_c_en : std_logic;
SIGNAL sdm_out1 : std_logic;
SIGNAL sdm_out2 : std_logic;
---------------------------------------------> Sigma-Delta
BEGIN
---------------------------------------------< Clock
global_clock_reset_inst : global_clock_reset
PORT MAP (
SYS_CLK_P => SYS_CLK_P,
SYS_CLK_N => SYS_CLK_N,
FORCE_RST => SYS_RST,
-- output
GLOBAL_RST => reset,
SYS_CLK => sys_clk,
CLK_OUT1 => clk_50MHz,
CLK_OUT2 => clk_100MHz,
CLK_OUT3 => OPEN,
CLK_OUT4 => clk_250MHz
);
-- gtx/gth reference clock can be used as general purpose clock this way
sgmiiclk_ibufds_inst : IBUFDS_GTE2
PORT MAP (
O => clk_sgmii_i,
ODIV2 => OPEN,
CEB => '0',
I => SGMIICLK_Q0_P,
IB => SGMIICLK_Q0_N
);
sgmiiclk_bufg_inst : BUFG
PORT MAP (
I => clk_sgmii_i,
O => clk_sgmii
);
clk_125MHz <= clk_sgmii;
---------------------------------------------> Clock
---------------------------------------------< debug : ILA and VIO (`Chipscope')
dbg_cores : IF ENABLE_DEBUG GENERATE
dbg_ila_inst : dbg_ila
PORT MAP (
CLK => sys_clk,
PROBE0 => dbg_ila_probe0,
PROBE1 => dbg_ila_probe1,
PROBE2 => dbg_ila_probe2,
PROBE3 => dbg_ila_probe3
);
dbg_vio_inst : dbg_vio
PORT MAP (
CLK => sys_clk,
PROBE_IN0 => config_reg(64*1-1 DOWNTO 64*0),
PROBE_IN1 => config_reg(64*2-1 DOWNTO 64*1),
PROBE_IN2 => config_reg(64*3-1 DOWNTO 64*2),
PROBE_IN3 => config_reg(64*4-1 DOWNTO 64*3),
PROBE_IN4 => config_reg(64*5-1 DOWNTO 64*4),
PROBE_IN5 => config_reg(64*6-1 DOWNTO 64*5),
PROBE_IN6 => config_reg(64*7-1 DOWNTO 64*6),
PROBE_IN7 => x"00000000000000" & sPcs_pma_core_status, -- config_reg(64*8-1 DOWNTO 64*7),
PROBE_IN8 => cmd_fifo_q,
PROBE_OUT0 => dbg_vio_probe_out0
);
--dbg_ila1_inst : dbg_ila1
-- PORT MAP (
-- CLK => sys_clk,
-- PROBE0 => dbg_ila1_probe0,
-- PROBE1 => dbg_ila1_probe1
-- );
END GENERATE dbg_cores;
---------------------------------------------> debug : ILA and VIO (`Chipscope')
---------------------------------------------< UART/RS232
uart_cores : IF false GENERATE
uartio_inst : uartio
GENERIC MAP (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH => 6,
DIVISOR => 1208*2
)
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
TX_DATA => "0000" & DIPSw4Bit,
TX_EN => '1',
TX_RDY => dbg_ila_probe0(2),
-- serial lines
RX_PIN => USB_TX, -- notice the pin swap
TX_PIN => USB_RX
);
--dbg_ila1_probe0(7 DOWNTO 0) <= uart_rx_data;
--dbg_ila1_probe0(8) <= uart_rx_rdy;
--dbg_ila1_probe0(9) <= USB_TX;
-- dbg_ila_probe0(63 DOWNTO 32) <= cmd_fifo_q(31 DOWNTO 0);
dbg_ila_probe0(31) <= cmd_fifo_empty;
dbg_ila_probe0(30) <= cmd_fifo_rdreq;
byte2cmd_inst : byte2cmd
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
-- byte in
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
-- cmd out
CMD_FIFO_Q => OPEN,-- cmd_fifo_q,
CMD_FIFO_EMPTY => OPEN,-- cmd_fifo_empty,
CMD_FIFO_RDCLK => control_clk,
CMD_FIFO_RDREQ => '0' -- cmd_fifo_rdreq
);
END GENERATE uart_cores;
control_clk <= clk_100MHz;
control_interface_inst : control_interface
PORT MAP (
RESET => reset,
CLK => control_clk,
-- From FPGA to PC
FIFO_Q => control_fifo_q,
FIFO_EMPTY => control_fifo_empty,
FIFO_RDREQ => control_fifo_rdreq,
FIFO_RDCLK => control_fifo_rdclk,
-- From PC to FPGA, FWFT
CMD_FIFO_Q => cmd_fifo_q,
CMD_FIFO_EMPTY => cmd_fifo_empty,
CMD_FIFO_RDREQ => cmd_fifo_rdreq,
-- Digital I/O
CONFIG_REG => config_reg,
PULSE_REG => pulse_reg,
STATUS_REG => status_reg,
-- Memory interface
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_DIN => control_mem_din,
MEM_DOUT => (OTHERS => '0'),
-- Data FIFO interface, FWFT
DATA_FIFO_Q => idata_data_fifo_dout,
DATA_FIFO_EMPTY => idata_data_fifo_empty,
DATA_FIFO_RDREQ => idata_data_fifo_rden,
DATA_FIFO_RDCLK => idata_data_fifo_rdclk
);
dbg_ila_probe0(18 DOWNTO 3) <= pulse_reg;
---------------------------------------------> UART/RS232
---------------------------------------------< ten_gig_eth
ten_gig_eth_cores : IF ENABLE_TEN_GIG_ETH GENERATE
ten_gig_eth_inst : ten_gig_eth
PORT MAP (
REFCLK_P => USER_CLK_P, -- 156.25MHz for transceiver
REFCLK_N => USER_CLK_N,
RESET => reset,
SFP_TX_P => SFP_TX_P,
SFP_TX_N => SFP_TX_N,
SFP_RX_P => SFP_RX_P,
SFP_RX_N => SFP_RX_N,
SFP_LOS => SFP_LOS_LS, -- loss of receiver signal
SFP_TX_DISABLE => sfp_tx_disable_i,
-- clk156 domain, clock generated by the core
CLK156 => clk156,
PCS_PMA_CORE_STATUS => sPcs_pma_core_status,
TX_STATISTICS_VECTOR => OPEN,
TX_STATISTICS_VALID => OPEN,
RX_STATISTICS_VECTOR => OPEN,
RX_STATISTICS_VALID => OPEN,
PAUSE_VAL => (OTHERS => '0'),
PAUSE_REQ => '0',
TX_IFG_DELAY => x"ff",
-- emac control interface
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN => sTx_axis_fifo_aresetn,
Tx_AXIS_FIFO_ACLK => sTx_axis_fifo_aclk,
TX_AXIS_FIFO_TDATA => sTx_axis_fifo_tdata,
TX_AXIS_FIFO_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_FIFO_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_FIFO_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_FIFO_TREADY => sTx_axis_fifo_tready,
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready
);
SFP_TX_DISABLE_N <= NOT sfp_tx_disable_i;
LED8Bit(7) <= sPcs_pma_core_status(0);
LED8Bit(6) <= NOT sfp_tx_disable_i;
LED8Bit(5) <= NOT SFP_LOS_LS;
s_axi_aclk <= clk_50MHz;
sTx_axis_fifo_aclk <= clk_200MHz;
sRx_axis_fifo_aclk <= sTx_axis_fifo_aclk;
s_axi_aresetn <= '1';
sTx_axis_fifo_aresetn <= '1';
-- sRx_axis_fifo_aresetn <= '1';
ten_gig_eth_packet_gen_inst : ten_gig_eth_packet_gen
PORT MAP (
RESET => reset,
MEM_CLK => control_clk,
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_D => control_mem_din,
--
TX_AXIS_ACLK => sTx_axis_fifo_aclk,
TX_START => ten_gig_eth_tx_start,
TX_BYTES => config_reg(15 DOWNTO 0),
TX_AXIS_TDATA => OPEN, -- sTx_axis_fifo_tdata,
TX_AXIS_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_TREADY => sTx_axis_fifo_tready
);
ten_gig_eth_rx_parser_inst : ten_gig_eth_rx_parser
PORT MAP (
RESET => reset,
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready,
-- Constants
SRC_MAC => x"000a3502a759",
SRC_IP => x"c0a80302",
SRC_PORT => x"ea62",
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q => tge_cmd_fifo_q,
CMD_FIFO_EMPTY => tge_cmd_fifo_empty,
CMD_FIFO_RDREQ => '1',
CMD_FIFO_RDCLK => clk_200MHz
);
--pulsegen_inst : pulsegen
-- GENERIC MAP (
-- COUNTER_WIDTH => 16
-- )
-- PORT MAP (
-- CLK => sTx_axis_fifo_aclk,
-- PERIOD => config_reg(31 DOWNTO 16),
-- I => pulse_reg(0),
-- O => ten_gig_eth_tx_start
-- );
ten_gig_eth_tx_start <= pulse_reg(0);
dbg_ila_probe0(0) <= clk156;
dbg_ila_probe0(1) <= ten_gig_eth_tx_start;
dbg_ila_probe1(79 DOWNTO 16) <= sTx_axis_fifo_tdata;
dbg_ila_probe1(15 DOWNTO 8) <= sTx_axis_fifo_tkeep;
dbg_ila_probe1(7) <= sTx_axis_fifo_tvalid;
dbg_ila_probe1(6) <= sTx_axis_fifo_tlast;
dbg_ila_probe1(5) <= sTx_axis_fifo_tready;
--dbg_ila_probe2(79 DOWNTO 16) <= sRx_axis_fifo_tdata;
--dbg_ila_probe2(79 DOWNTO 48) <= control_mem_addr;
--dbg_ila_probe2(47 DOWNTO 16) <= control_mem_din;
--dbg_ila_probe2(15 DOWNTO 8) <= sRx_axis_fifo_tkeep;
dbg_ila_probe2(7) <= sRx_axis_fifo_tvalid;
dbg_ila_probe2(6) <= sRx_axis_fifo_tlast;
dbg_ila_probe2(5) <= sRx_axis_fifo_tready;
dbg_ila_probe2(4) <= control_mem_we;
--
--dbg_ila_probe3(127 DOWNTO 0) <= tge_cmd_fifo_q;
--dbg_ila_probe3(128) <= tge_cmd_fifo_empty;
END GENERATE ten_gig_eth_cores;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gig_eth
gig_eth_cores : IF ENABLE_GIG_ETH GENERATE
gig_eth_mac_addr(gig_eth_mac_addr'length-1 DOWNTO 4) <= x"000a3502a75";
gig_eth_mac_addr(3 DOWNTO 0) <= DIPSw4Bit;
gig_eth_ipv4_addr(gig_eth_ipv4_addr'length-1 DOWNTO 4) <= x"c0a8020";
gig_eth_ipv4_addr(3 DOWNTO 0) <= DIPSw4Bit;
gig_eth_subnet_mask <= x"ffffff00";
gig_eth_gateway_ip_addr <= x"c0a80201";
gig_eth_inst : gig_eth
PORT MAP (
-- asynchronous reset
GLBL_RST => reset,
-- clocks
GTX_CLK => clk_125MHz,
REF_CLK => sys_clk, -- 200MHz for IODELAY
-- PHY interface
PHY_RESETN => PHY_RESET_N,
-- RGMII Interface
RGMII_TXD => RGMII_TXD,
RGMII_TX_CTL => RGMII_TX_CTL,
RGMII_TXC => RGMII_TXC,
RGMII_RXD => RGMII_RXD,
RGMII_RX_CTL => RGMII_RX_CTL,
RGMII_RXC => RGMII_RXC,
-- MDIO Interface
MDIO => MDIO,
MDC => MDC,
-- TCP
MAC_ADDR => gig_eth_mac_addr,
IPv4_ADDR => gig_eth_ipv4_addr,
IPv6_ADDR => (OTHERS => '0'),
SUBNET_MASK => gig_eth_subnet_mask,
GATEWAY_IP_ADDR => gig_eth_gateway_ip_addr,
TCP_CONNECTION_RESET => '0',
TX_TDATA => gig_eth_tx_tdata,
TX_TVALID => gig_eth_tx_tvalid,
TX_TREADY => gig_eth_tx_tready,
RX_TDATA => gig_eth_rx_tdata,
RX_TVALID => gig_eth_rx_tvalid,
RX_TREADY => gig_eth_rx_tready,
-- FIFO
TCP_USE_FIFO => gig_eth_tcp_use_fifo,
TX_FIFO_WRCLK => gig_eth_tx_fifo_wrclk,
TX_FIFO_Q => gig_eth_tx_fifo_q,
TX_FIFO_WREN => gig_eth_tx_fifo_wren,
TX_FIFO_FULL => gig_eth_tx_fifo_full,
RX_FIFO_RDCLK => gig_eth_rx_fifo_rdclk,
RX_FIFO_Q => gig_eth_rx_fifo_q,
RX_FIFO_RDEN => gig_eth_rx_fifo_rden,
RX_FIFO_EMPTY => gig_eth_rx_fifo_empty
);
dbg_ila_probe0(26 DOWNTO 19) <= gig_eth_rx_tdata;
dbg_ila_probe0(27) <= gig_eth_rx_tvalid;
dbg_ila_probe0(28) <= gig_eth_rx_tready;
-- loopback
--gig_eth_tx_tdata <= gig_eth_rx_tdata;
--gig_eth_tx_tvalid <= gig_eth_rx_tvalid;
--gig_eth_rx_tready <= gig_eth_tx_tready;
-- receive to cmd_fifo
gig_eth_tcp_use_fifo <= '1';
gig_eth_rx_fifo_rdclk <= control_clk;
cmd_fifo_q(31 DOWNTO 0) <= gig_eth_rx_fifo_q;
dbg_ila_probe0(63 DOWNTO 32) <= gig_eth_rx_fifo_q;
cmd_fifo_empty <= gig_eth_rx_fifo_empty;
gig_eth_rx_fifo_rden <= cmd_fifo_rdreq;
-- send control_fifo data through gig_eth_tx_fifo
gig_eth_tx_fifo_wrclk <= clk_125MHz;
-- connect FWFT fifo interface
control_fifo_rdclk <= gig_eth_tx_fifo_wrclk;
gig_eth_tx_fifo_q <= control_fifo_q(31 DOWNTO 0);
gig_eth_tx_fifo_wren <= NOT control_fifo_empty;
control_fifo_rdreq <= NOT gig_eth_tx_fifo_full;
END GENERATE gig_eth_cores;
---------------------------------------------> gig_eth
---------------------------------------------< SDRAM
sdram_ddr3_inst : sdram_ddr3
PORT MAP (
CLK => sys_clk, -- system clock, must be the same as intended in MIG
REFCLK => sys_clk, -- 200MHz for iodelay
RESET => reset,
-- SDRAM_DDR3
-- Inouts
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
-- Outputs
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
-- Status Outputs
INIT_CALIB_COMPLETE => LED8Bit(4),
-- Internal data r/w interface
UI_CLK => clk_200MHz,
--
CTRL_RESET => pulse_reg(6),
WR_START => idata_data_wr_start,
WR_ADDR_BEGIN => config_reg(32*4+27 DOWNTO 32*4),
WR_STOP => pulse_reg(4),
WR_WRAP_AROUND => config_reg(32*4+28),
POST_TRIGGER => config_reg(32*5+27 DOWNTO 32*5),
WR_BUSY => idata_data_wr_busy,
WR_POINTER => OPEN,
--TRIGGER_POINTER => status_reg(64*2+27 DOWNTO 64*2),
WR_WRAPPED => idata_data_wr_wrapped,
RD_START => pulse_reg(5),
RD_ADDR_BEGIN => (OTHERS => '0'),
RD_ADDR_END => config_reg(32*6+27 DOWNTO 32*6),
--RD_BUSY => status_reg(64*2+30),
--
DATA_FIFO_RESET => idata_data_fifo_reset,
INDATA_FIFO_WRCLK => idata_adc_data_clk,
INDATA_FIFO_Q => idata_idata_fifo_q,
INDATA_FIFO_FULL => idata_idata_fifo_full,
INDATA_FIFO_WREN => idata_idata_fifo_wren,
--
OUTDATA_FIFO_RDCLK => idata_data_fifo_rdclk,
OUTDATA_FIFO_Q => idata_data_fifo_dout,
OUTDATA_FIFO_EMPTY => idata_data_fifo_empty,
OUTDATA_FIFO_RDEN => idata_data_fifo_rden,
--
DBG_APP_ADDR => sdram_app_addr,
DBG_APP_EN => sdram_app_en,
DBG_APP_RDY => sdram_app_rdy,
DBG_APP_WDF_DATA => sdram_app_wdf_data,
DBG_APP_WDF_END => sdram_app_wdf_end,
DBG_APP_WDF_WREN => sdram_app_wdf_wren,
DBG_APP_WDF_RDY => sdram_app_wdf_rdy,
DBG_APP_RD_DATA => sdram_app_rd_data,
DBG_APP_RD_DATA_VALID => sdram_app_rd_data_valid
);
idata_data_fifo_reset <= pulse_reg(2);
--status_reg(64*2+28) <= idata_data_wr_busy;
--status_reg(64*2+29) <= idata_data_wr_wrapped;
--
channel_sel_inst : channel_sel
PORT MAP (
CLK => idata_adc_data_clk, -- fifo wrclk
RESET => reset,
SEL => config_reg(32*7+7 DOWNTO 32*7),
--
DATA_FIFO_RESET => idata_data_fifo_reset,
--
INDATA_Q => idata_channel_avg_outdata_q,
DATA_FIFO_WREN => idata_data_fifo_wren,
DATA_FIFO_FULL => idata_data_fifo_full,
--
OUTDATA_FIFO_Q => idata_idata_fifo_q,
DATA_FIFO_RDEN => idata_idata_fifo_rden,
DATA_FIFO_EMPTY => idata_idata_fifo_empty
);
idata_idata_fifo_rden <= NOT idata_idata_fifo_full;
idata_idata_fifo_wren <= NOT idata_idata_fifo_empty;
idata_data_fifo_wren <= config_reg(32*6+31) AND idata_channel_avg_outvalid;
--
channel_avg_inst : channel_avg
PORT MAP (
RESET => reset,
CLK => idata_adc_data_clk,
-- high 4-bit is offset, 2**(low 4-bit) is number of points to average
CONFIG => config_reg(32*7+15 DOWNTO 32*7+8),
TRIG => idata_data_wr_start,
INDATA_Q => idata_data_fifo_din,
OUTVALID => idata_channel_avg_outvalid,
OUTDATA_Q => idata_channel_avg_outdata_q
);
--
dbg_ila_probe3(27 DOWNTO 0) <= sdram_app_addr;
dbg_ila_probe3(28) <= sdram_app_en;
dbg_ila_probe3(29) <= sdram_app_rdy;
dbg_ila_probe3(30) <= sdram_app_wdf_wren;
dbg_ila_probe3(31) <= sdram_app_wdf_rdy;
dbg_ila_probe3(32) <= sdram_app_wdf_end;
dbg_ila_probe3(1023 DOWNTO 512) <= sdram_app_wdf_data;
dbg_ila_probe3(1024+1023 DOWNTO 1024+512) <= sdram_app_rd_data;
dbg_ila_probe3(33) <= sdram_app_rd_data_valid;
dbg_ila_probe3(511 DOWNTO 336) <= status_reg;
---------------------------------------------> SDRAM
-- clock output
refout_clk_div_inst : clk_div
PORT MAP (
RESET => reset,
CLK => idata_adc_data_clk,
DIV => config_reg(16*15+3 DOWNTO 16*15),
CLK_DIV => idata_adc_refout_clkdiv
);
clk_fwd_inst : clk_fwd
PORT MAP (R => reset, I => idata_adc_refout_clkdiv, O => USER_SMA_CLOCK_P);
clk_fwd_inst1 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => idata_adc_refout_clkdiv, O => USER_SMA_CLOCK_N);
clk_fwd_inst2 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => idata_adc_data_clk, O => USER_SMA_GPIO_N);
-- capture the rising edge of trigger
trig_edge_sync_inst : edge_sync
PORT MAP (
RESET => reset,
CLK => control_clk,
EI => idata_trig_in,
SO => idata_trig_synced
);
idata_trig_allow <= config_reg(32*6+30);
idata_data_wr_start <= pulse_reg(3) OR (idata_trig_synced AND idata_trig_allow
AND (NOT idata_data_wr_busy)
AND (NOT idata_data_wr_wrapped));
USER_SMA_GPIO_P <= idata_trig_synced;
dbg_ila1_probe0 <= idata_adc_data0;
dbg_ila1_probe1 <= idata_adc_data4;
--led_obufs : FOR i IN 0 TO 7 GENERATE
-- led_obuf : OBUF
-- PORT MAP (
-- I => usr_data_output(i),
-- O => LED8Bit(i)
-- );
--END GENERATE led_obufs;
--LED8Bit(5 DOWNTO 1) <= (OTHERS => '0');
---------------------------------------------< TOP_SR
div <= config_reg(135 DOWNTO 130);
din <= config_reg(129 DOWNTO 0);
status_reg(129 DOWNTO 0) <= dout(129 DOWNTO 0);
status_reg(130) <= valid;
Top_SR_0 : Top_SR
GENERIC MAP (
WIDTH => 130 ,
CNT_WIDTH => 8 ,
DIV_WIDTH => 6 ,
COUNT_WIDTH => 64 ,
SHIFT_DIRECTION => 1 ,
READ_TRIG_SRC => 0 ,
READ_DELAY => 1
)
PORT MAP (
clk_in => clk_100MHz,
rst => reset,
start => pulse_out,
din => din,
data_in_p => FMC_HPC_LA_P(10),
data_in_n => FMC_HPC_LA_N(10),
div => div,
clk => clk_sr_contr,
clk_sr_p => FMC_HPC_LA_P(8),
clk_sr_n => FMC_HPC_LA_N(8),
data_out_p => FMC_HPC_LA_P(9),
data_out_n => FMC_HPC_LA_N(9),
load_sr_p => FMC_HPC_LA_P(7),
load_sr_n => FMC_HPC_LA_N(7),
valid => valid,
dout => dout
);
---------------------------------------------> TOP_SR
---------------------------------------------< PULSE_SYNCHRONISE
pulse_in <= pulse_reg(0);
pulse_synchronise_0 : pulse_synchronise
PORT MAP (
pulse_in => pulse_in,
clk_in => control_clk,
clk_out => clk_sr_contr,
rst => reset,
pulse_out => pulse_out
);
---------------------------------------------> PULSE_SYNCHRONISE
---------------------------------------------< shiftreg driver for DAC8568
dac8568_inst : fifo2shiftreg
GENERIC MAP (
DATA_WIDTH => 32, -- parallel data width
CLK_DIV_WIDTH => 16,
DELAY_AFTER_SYNCn => 0, -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL => '0', -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE => '1', -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE => '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
)
PORT MAP (
CLK => control_clk, -- clock
RESET => reset, -- reset
-- input data interface
WR_CLK => control_clk, -- FIFO write clock
DINFIFO => config_reg(15 DOWNTO 0),
WR_EN => '0',
WR_PULSE => pulse_reg(1), -- one pulse writes one word, regardless of pulse duration
FULL => OPEN,
-- captured data
BUSY => status_reg(16*9-1),
DATAOUT => status_reg(16*9+31 DOWNTO 16*9),
-- serial interface
CLK_DIV => x"0002",
SCLK => spi_sclk,
DOUT => spi_dout,
SYNCn => spi_sync_n,
DIN => spi_din
);
spi_sclk_obufds_inst : OBUFDS
GENERIC MAP (
IOSTANDARD => "LVDS"
)
PORT MAP (
O => FMC_HPC_LA_P(14), -- Diff_p output (connect directly to top-level port)
OB => FMC_HPC_LA_N(14), -- Diff_n output (connect directly to top-level port)
I => spi_sclk
);
spi_dout_obufds_inst : OBUFDS
GENERIC MAP (
IOSTANDARD => "LVDS"
)
PORT MAP (
O => FMC_HPC_LA_P(13), -- Diff_p output (connect directly to top-level port)
OB => FMC_HPC_LA_N(13), -- Diff_n output (connect directly to top-level port)
I => spi_dout
);
spi_sync_n_obufds_inst : OBUFDS
GENERIC MAP (
IOSTANDARD => "LVDS"
)
PORT MAP (
O => FMC_HPC_LA_P(12), -- Diff_p output (connect directly to top-level port)
OB => FMC_HPC_LA_N(12), -- Diff_n output (connect directly to top-level port)
I => spi_sync_n
);
---------------------------------------------> shiftreg driver for DAC8568
---------------------------------------------< Sigma-Delta
clk_sync_ibufds_inst : IBUFDS
GENERIC MAP (
DQS_BIAS => "FALSE"
)
PORT MAP (
I => FMC_HPC_LA_P(6),
IB => FMC_HPC_LA_N(6),
O => clk_sync_buf
);
sdm_clk_inst : IOBUFDS
GENERIC MAP (
DQS_BIAS => "FALSE"
)
PORT MAP (
IO => FMC_HPC_LA_P(5),
IOB => FMC_HPC_LA_N(5),
I => clk_sync_buf,
O => OPEN,
T => sdm_clk_disable
);
sdm_clk_disable <= NOT config_reg(16*9 + 0); -- bit 0 of register 9
sdm_clk_c_en_obufds_inst : OBUFDS
GENERIC MAP (
IOSTANDARD => "LVDS"
)
PORT MAP (
O => FMC_HPC_LA_P(11), -- Diff_p output (connect directly to top-level port)
OB => FMC_HPC_LA_N(11), -- Diff_n output (connect directly to top-level port)
I => sdm_clk_c_en
);
sdm_clk_c_en <= config_reg(16*9 + 1); -- bit 1 of register 9
--
sdm_out1_ibufds_inst : IBUFDS
GENERIC MAP (
DQS_BIAS => "FALSE"
)
PORT MAP (
I => FMC_HPC_LA_P(4),
IB => FMC_HPC_LA_N(4),
O => sdm_out1
);
sdm_out2_ibufds_inst : IBUFDS
GENERIC MAP (
DQS_BIAS => "FALSE"
)
PORT MAP (
I => FMC_HPC_LA_P(2),
IB => FMC_HPC_LA_N(2),
O => sdm_out2
);
dbg_cores1 : IF ENABLE_DEBUG GENERATE
dbg_ila1_inst : dbg_ila1
PORT MAP (
CLK => clk_sync_buf,
PROBE0 => (1 => sdm_out2, 0 => sdm_out1, OTHERS => '0'),
PROBE1 => (OTHERS => '0')
);
END GENERATE dbg_cores1;
---------------------------------------------> Sigma-Delte
END Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:21 03/22/2014
-- Design Name:
-- Module Name: wishbone_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity wishbone_pmic is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
sample_rate : positive := 48_000;
sclk_period_ns : positive := 80
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
ss, sck : out std_logic ;
miso : in std_logic
);
end wishbone_pmic;
architecture Behavioral of wishbone_pmic is
component ADCS7476_ctrl is
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833
);
port(
clk, resetn : in std_logic;
sclk, ss : out std_logic ;
miso : in std_logic ;
sample_out : out std_logic_vector(11 downto 0);
sample_valid : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
constant time_between_sample_ns : positive := (1_000_000_000/sample_rate);
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- fifo signals
signal reset_fifo : std_logic ;
signal fifo_empty, fifo_full, pop_fifo, push_fifo : std_logic ;
signal fifo_out : std_logic_vector(15 downto 0);
signal fifo_in : std_logic_vector(15 downto 0);
signal enable_fifo, sample_valid : std_logic ;
signal read_ack_old : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
reset_fifo <= wbs_writedata(0);
enable_fifo <= wbs_writedata(1);
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0' ;
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1') then
read_ack <= '1';
else
read_ack <= '0';
end if;
read_ack_old <= read_ack ;
end if;
end process read_bloc;
wbs_readdata <= (NOT fifo_empty) & fifo_full & "00" & fifo_out(11 downto 0);
pop_fifo <= '1' when read_ack = '0' and read_ack_old = '1' else
'0' ;
mi_0 : ADCS7476_ctrl
generic map(clk_period_ns => 10,
sclk_period_ns => sclk_period_ns,
time_between_sample_ns => time_between_sample_ns
)
port map(
clk => gls_clk,
resetn => reset_fifo,
sclk => sck,
ss => ss,
miso => miso,
sample_out => fifo_in(11 downto 0),
sample_valid => sample_valid
);
push_fifo <= enable_fifo and sample_valid ;
fifo0 : small_fifo
generic map( WIDTH => 16, DEPTH => 512)
port map(clk => gls_clk,
resetn => reset_fifo,
empty => fifo_empty,
full => fifo_full,
push => push_fifo, pop => pop_fifo,
data_in => fifo_in,
data_out => fifo_out
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:21 03/22/2014
-- Design Name:
-- Module Name: wishbone_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity wishbone_pmic is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
sample_rate : positive := 48_000;
sclk_period_ns : positive := 80
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
ss, sck : out std_logic ;
miso : in std_logic
);
end wishbone_pmic;
architecture Behavioral of wishbone_pmic is
component ADCS7476_ctrl is
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833
);
port(
clk, resetn : in std_logic;
sclk, ss : out std_logic ;
miso : in std_logic ;
sample_out : out std_logic_vector(11 downto 0);
sample_valid : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
constant time_between_sample_ns : positive := (1_000_000_000/sample_rate);
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- fifo signals
signal reset_fifo : std_logic ;
signal fifo_empty, fifo_full, pop_fifo, push_fifo : std_logic ;
signal fifo_out : std_logic_vector(15 downto 0);
signal fifo_in : std_logic_vector(15 downto 0);
signal enable_fifo, sample_valid : std_logic ;
signal read_ack_old : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
reset_fifo <= wbs_writedata(0);
enable_fifo <= wbs_writedata(1);
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
read_ack <= '0' ;
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1') then
read_ack <= '1';
else
read_ack <= '0';
end if;
read_ack_old <= read_ack ;
end if;
end process read_bloc;
wbs_readdata <= (NOT fifo_empty) & fifo_full & "00" & fifo_out(11 downto 0);
pop_fifo <= '1' when read_ack = '0' and read_ack_old = '1' else
'0' ;
mi_0 : ADCS7476_ctrl
generic map(clk_period_ns => 10,
sclk_period_ns => sclk_period_ns,
time_between_sample_ns => time_between_sample_ns
)
port map(
clk => gls_clk,
resetn => reset_fifo,
sclk => sck,
ss => ss,
miso => miso,
sample_out => fifo_in(11 downto 0),
sample_valid => sample_valid
);
push_fifo <= enable_fifo and sample_valid ;
fifo0 : small_fifo
generic map( WIDTH => 16, DEPTH => 512)
port map(clk => gls_clk,
resetn => reset_fifo,
empty => fifo_empty,
full => fifo_full,
push => push_fifo, pop => pop_fifo,
data_in => fifo_in,
data_out => fifo_out
);
end Behavioral;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when(rd_en = '1') else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when(rd_en = '1') else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when(rd_en = '1') else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when(rd_en = '1') else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when(rd_en = '1') else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when(rd_en = '1') else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulate_network_write_data is
end entity stimulate_network_write_data;
architecture writer of stimulate_network_write_data is
begin
process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open write_mode is "test packets";
begin
write(stimulus_file, X"6C");
write(stimulus_file, X"05");
write(stimulus_file, X"3");
wait;
end process;
end architecture writer;
entity stimulate_network is
end entity stimulate_network;
architecture test of stimulate_network is
signal stimulus_network, stimulus_clock : bit;
begin
clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
-- code from book
stimulate_network : process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open read_mode is "test packets";
-- variable packet : bit_vector(1 to 2048);
-- not in book (for testing only)
variable packet : bit_vector(1 to 8);
-- end not in book
variable packet_length : natural;
begin
while not endfile(stimulus_file) loop
read(stimulus_file, packet, packet_length);
if packet_length > packet'length then
report "stimulus packet too long - ignored" severity warning;
else
for bit_index in 1 to packet_length loop
wait until stimulus_clock = '1';
stimulus_network <= not stimulus_network;
wait until stimulus_clock = '0';
stimulus_network <= stimulus_network xor packet(bit_index);
end loop;
end if;
end loop;
wait; -- end of stimulation: wait forever
end process stimulate_network;
-- code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulate_network_write_data is
end entity stimulate_network_write_data;
architecture writer of stimulate_network_write_data is
begin
process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open write_mode is "test packets";
begin
write(stimulus_file, X"6C");
write(stimulus_file, X"05");
write(stimulus_file, X"3");
wait;
end process;
end architecture writer;
entity stimulate_network is
end entity stimulate_network;
architecture test of stimulate_network is
signal stimulus_network, stimulus_clock : bit;
begin
clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
-- code from book
stimulate_network : process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open read_mode is "test packets";
-- variable packet : bit_vector(1 to 2048);
-- not in book (for testing only)
variable packet : bit_vector(1 to 8);
-- end not in book
variable packet_length : natural;
begin
while not endfile(stimulus_file) loop
read(stimulus_file, packet, packet_length);
if packet_length > packet'length then
report "stimulus packet too long - ignored" severity warning;
else
for bit_index in 1 to packet_length loop
wait until stimulus_clock = '1';
stimulus_network <= not stimulus_network;
wait until stimulus_clock = '0';
stimulus_network <= stimulus_network xor packet(bit_index);
end loop;
end if;
end loop;
wait; -- end of stimulation: wait forever
end process stimulate_network;
-- code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity stimulate_network_write_data is
end entity stimulate_network_write_data;
architecture writer of stimulate_network_write_data is
begin
process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open write_mode is "test packets";
begin
write(stimulus_file, X"6C");
write(stimulus_file, X"05");
write(stimulus_file, X"3");
wait;
end process;
end architecture writer;
entity stimulate_network is
end entity stimulate_network;
architecture test of stimulate_network is
signal stimulus_network, stimulus_clock : bit;
begin
clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
-- code from book
stimulate_network : process is
type packet_file is file of bit_vector;
file stimulus_file : packet_file open read_mode is "test packets";
-- variable packet : bit_vector(1 to 2048);
-- not in book (for testing only)
variable packet : bit_vector(1 to 8);
-- end not in book
variable packet_length : natural;
begin
while not endfile(stimulus_file) loop
read(stimulus_file, packet, packet_length);
if packet_length > packet'length then
report "stimulus packet too long - ignored" severity warning;
else
for bit_index in 1 to packet_length loop
wait until stimulus_clock = '1';
stimulus_network <= not stimulus_network;
wait until stimulus_clock = '0';
stimulus_network <= stimulus_network xor packet(bit_index);
end loop;
end if;
end loop;
wait; -- end of stimulation: wait forever
end process stimulate_network;
-- code from book
end architecture test;
|
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "900p_edid.txt"; -- Select EDID file to use
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(0); -- blue is channel 0
pData(15 downto 8) <= pDataIn(1); -- green is channel 1
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNMQPB5LUF is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>b) or (a=b)) and ((a<c) or (a=c))";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNMQPB5LUF is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>b) or (a=b)) and ((a<c) or (a=c))) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNMQPB5LUF is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>b) or (a=b)) and ((a<c) or (a=c))";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNMQPB5LUF is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>b) or (a=b)) and ((a<c) or (a=c))) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNMQPB5LUF is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>b) or (a=b)) and ((a<c) or (a=c))";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNMQPB5LUF is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>b) or (a=b)) and ((a<c) or (a=c))) ;
true <= result;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNMQPB5LUF is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>b) or (a=b)) and ((a<c) or (a=c))";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNMQPB5LUF is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>b) or (a=b)) and ((a<c) or (a=c))) ;
true <= result;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2245.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02245ent IS
END c07s02b06x00p01n01i02245ent;
ARCHITECTURE c07s02b06x00p01n01i02245arch OF c07s02b06x00p01n01i02245ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := B"1010101010" rem X"FFFF";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02245 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02245arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2245.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02245ent IS
END c07s02b06x00p01n01i02245ent;
ARCHITECTURE c07s02b06x00p01n01i02245arch OF c07s02b06x00p01n01i02245ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := B"1010101010" rem X"FFFF";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02245 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02245arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2245.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02245ent IS
END c07s02b06x00p01n01i02245ent;
ARCHITECTURE c07s02b06x00p01n01i02245arch OF c07s02b06x00p01n01i02245ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := B"1010101010" rem X"FFFF";
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02245 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02245arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm_32_16 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm_32_16;
architecture BEHAVIORAL of dcm_32_16 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 16.000 = 32.000 * 10/20
CLKFX_DIVIDE => 20,
CLKFX_MULTIPLY => 10,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(19-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(19-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(19-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(19-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dgen
GENERIC MAP (
C_DIN_WIDTH => 19,
C_DOUT_WIDTH => 19,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_dverif
GENERIC MAP (
C_DOUT_WIDTH => 19,
C_DIN_WIDTH => 19,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 19,
C_DIN_WIDTH => 19,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_2_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_init_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = _mutex_owner( mutex->num );
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
-------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of dual Nios CN design
--
--! @details This is the toplevel of the dual Nios CN FPGA design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2015
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_LINK_n : in std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- 64 MBx2 SDRAM
SDRAM_CLK : out std_logic;
SDRAM_CAS_n : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CS_n : out std_logic;
SDRAM_RAS_n : out std_logic;
SDRAM_WE_n : out std_logic;
SDRAM_ADDR : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQM : out std_logic_vector(3 downto 0);
SDRAM_DQ : inout std_logic_vector(31 downto 0);
-- FLASH 8Mx8
CFI_FLASH_ADDR : out std_logic_vector(22 downto 0);
CFI_FLASH_DATA : inout std_logic_vector(7 downto 0);
CFI_FLASH_WE_n : out std_logic;
CFI_FLASH_CE_n : out std_logic;
CFI_FLASH_OE_n : out std_logic;
CFI_FLASH_RESET_n : out std_logic;
CFI_FLASH_WP_n : out std_logic;
CFI_FLASH_RY : in std_logic;
-- NODE_SWITCH
NODE_SWITCH : in std_logic_vector(7 downto 0);
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- KEY
KEY_n : in std_logic_vector(3 downto 0);
-- HEX LED
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
-- BENCHMARK
BENCHMARK : out std_logic_vector(7 downto 0);
-- BENCHMARK_AP
BENCHMARK_AP : out std_logic_vector(7 downto 0)
);
end toplevel;
architecture rtl of toplevel is
component cnDualHostifGpio is
port (
clk25_clk : in std_logic;
clk50_clk : in std_logic := 'X';
clk100_clk : in std_logic;
reset_reset_n : in std_logic := 'X';
tri_state_sram_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_sram_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_sram_0_tcm_read_n_out : out std_logic;
tri_state_sram_0_tcm_write_n_out : out std_logic;
tri_state_sram_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_sram_0_tcm_chipselect_n_out : out std_logic;
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_pktactivity_export : out std_logic;
powerlink_led_export : out std_logic_vector(1 downto 0);
host_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
node_switch_pio_export : in std_logic_vector(7 downto 0) := (others => 'X');
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
sdram_0_addr : out std_logic_vector(12 downto 0);
sdram_0_ba : out std_logic_vector(1 downto 0);
sdram_0_cas_n : out std_logic;
sdram_0_cke : out std_logic;
sdram_0_cs_n : out std_logic;
sdram_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X');
sdram_0_dqm : out std_logic_vector(3 downto 0);
sdram_0_ras_n : out std_logic;
sdram_0_we_n : out std_logic;
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
-- CPU RESET REQUEST
pcp_0_cpu_resetrequest_resetrequest : in std_logic := 'X';
pcp_0_cpu_resetrequest_resettaken : out std_logic;
-- CFI FLASH FOR HOST
tristate_cfi_flash_0_tcm_address_out : out std_logic_vector(22 downto 0);
tristate_cfi_flash_0_tcm_read_n_out : out std_logic;
tristate_cfi_flash_0_tcm_write_n_out : out std_logic;
tristate_cfi_flash_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X');
tristate_cfi_flash_0_tcm_chipselect_n_out : out std_logic;
-- Application ports
app_pio_in_port : in std_logic_vector(31 downto 0) := (others => 'X');
app_pio_out_port : out std_logic_vector(31 downto 0)
);
end component cnDualHostifGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal clk100_p : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
signal openmac_activity : std_logic;
type tSevenSegArray is array (natural range <>) of std_logic_vector(6 downto 0);
constant cNumberOfHex : natural := 8;
signal hex : std_logic_vector(cNumberOfHex*4-1 downto 0);
signal sevenSegArray : tSevenSegArray(cNumberOfHex-1 downto 0);
signal app_input : std_logic_vector(31 downto 0);
signal app_output : std_logic_vector(31 downto 0);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
SDRAM_CLK <= clk100_p;
CFI_FLASH_RESET_n <= cnInactivated;
CFI_FLASH_WP_n <= cnInactivated;
---------------------------------------------------------------------------
-- Green LED assignments
LEDG <= plk_status_error(0) & -- POWERLINK Status LED
"000" & -- Reserved
(openmac_activity and not PHY_LINK_n(0)) & -- Gated activity
not PHY_LINK_n(0) & -- Link
(openmac_activity and not PHY_LINK_n(1)) & -- Gated activity
not PHY_LINK_n(1); -- Link
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Red LED assignments
LEDR <= x"000" & -- Reserved
"000" & -- Reserved
plk_status_error(1); -- POWERLINK Error LED
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Application Input and Output assignments
-- Input: Map KEY nibble to Application Input
app_input <= x"0000000" & not KEY_n;
-- Output: Map Application Output to HEX LEDs
hex <= app_output;
---------------------------------------------------------------------------
inst : component cnDualHostifGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
pcp_0_cpu_resetrequest_resetrequest => '0',
pcp_0_cpu_resetrequest_resettaken => open,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
openmac_0_pktactivity_export => openmac_activity,
tri_state_sram_0_tcm_address_out => sramAddr,
tri_state_sram_0_tcm_read_n_out => SRAM_OE_n,
tri_state_sram_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_sram_0_tcm_write_n_out => SRAM_WE_n,
tri_state_sram_0_tcm_data_out => SRAM_DQ,
tri_state_sram_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
node_switch_pio_export => NODE_SWITCH,
powerlink_led_export => plk_status_error,
host_0_benchmark_pio_export => BENCHMARK_AP,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
sdram_0_addr => SDRAM_ADDR,
sdram_0_ba => SDRAM_BA,
sdram_0_cas_n => SDRAM_CAS_n,
sdram_0_cke => SDRAM_CKE,
sdram_0_cs_n => SDRAM_CS_n,
sdram_0_dq => SDRAM_DQ,
sdram_0_dqm => SDRAM_DQM,
sdram_0_ras_n => SDRAM_RAS_n,
sdram_0_we_n => SDRAM_WE_n,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
tristate_cfi_flash_0_tcm_address_out => CFI_FLASH_ADDR,
tristate_cfi_flash_0_tcm_read_n_out => CFI_FLASH_OE_n,
tristate_cfi_flash_0_tcm_write_n_out => CFI_FLASH_WE_n,
tristate_cfi_flash_0_tcm_data_out => CFI_FLASH_DATA,
tristate_cfi_flash_0_tcm_chipselect_n_out => CFI_FLASH_CE_n,
app_pio_in_port => app_input,
app_pio_out_port => app_output
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => clk100_p,
locked => pllLocked
);
-- bcd to 7 segment
genBcdTo7Seg : for i in cNumberOfHex-1 downto 0 generate
signal tmpHex : std_logic_vector(3 downto 0);
signal tmpSev : std_logic_vector(6 downto 0);
begin
tmpHex <= hex((i+1)*4-1 downto i*4);
sevenSegArray(i) <= tmpSev;
bcdTo7Seg0 : entity libcommon.bcd2led
port map (
iBcdVal => tmpHex,
oLed => open,
onLed => tmpSev
);
end generate genBcdTo7Seg;
-- assign outports to array
HEX0 <= sevenSegArray(0);
HEX1 <= sevenSegArray(1);
HEX2 <= sevenSegArray(2);
HEX3 <= sevenSegArray(3);
HEX4 <= sevenSegArray(4);
HEX5 <= sevenSegArray(5);
HEX6 <= sevenSegArray(6);
HEX7 <= sevenSegArray(7);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity xwb_fabric_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
-- Decoded & buffered fabric
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end xwb_fabric_source;
architecture rtl of xwb_fabric_source is
constant c_fifo_width : integer := 16 + 2 + 4;
signal q_valid, full, we, rd, rd_d0 : std_logic;
signal fin, fout : std_logic_vector(c_fifo_width-1 downto 0);
signal pre_dvalid : std_logic;
signal pre_eof : std_logic;
signal pre_data : std_logic_vector(15 downto 0);
signal pre_addr : std_logic_vector(1 downto 0);
signal post_dvalid, post_eof, post_bytesel, post_sof : std_logic;
signal err_status : t_wrf_status_reg;
signal cyc_int : std_logic;
begin -- rtl
err_status.error <= '1';
dreq_o <= not full;
rd <= not src_i.stall;
we <= sof_i or eof_i or error_i or dvalid_i;
pre_dvalid <= dvalid_i or error_i;
pre_data <= data_i when (error_i = '0') else f_marshall_wrf_status(err_status);
pre_addr <= addr_i when (error_i = '0') else c_WRF_STATUS;
pre_eof <= error_i or eof_i;
fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => 16)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid);
post_sof <= fout(21);
post_eof <= fout(20);
post_dvalid <= fout(18);
p_gen_cyc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_int <= '0';
else
if(src_i.stall = '0' and q_valid = '1') then
if(post_sof = '1')then
cyc_int <= '1';
elsif(post_eof = '1') then
cyc_int <= '0';
end if;
end if;
end if;
end if;
end process;
src_o.cyc <= cyc_int or post_sof;
src_o.we <= '1';
src_o.stb <= post_dvalid and q_valid;
src_o.sel <= '1' & not fout(19);
src_o.dat <= fout(15 downto 0);
src_o.adr <= fout(17 downto 16);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.wr_fabric_pkg.all;
entity wb_fabric_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
-- Decoded & buffered fabric
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end wb_fabric_source;
architecture wrapper of wb_fabric_source is
component xwb_fabric_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(15 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
signal src_in : t_wrf_source_in;
signal src_out : t_wrf_source_out;
begin -- wrapper
U_Wrapped_Source : xwb_fabric_source
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
src_i => src_in,
src_o => src_out,
addr_i => addr_i,
data_i => data_i,
dvalid_i => dvalid_i,
sof_i => sof_i,
eof_i => eof_i,
error_i => error_i,
bytesel_i => bytesel_i,
dreq_o => dreq_o);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_sel_o <= src_out.sel;
src_adr_o <= src_out.adr;
src_dat_o <= src_out.dat;
src_in.rty <= '0';
src_in.err <= src_err_i;
src_in.ack <= src_ack_i;
src_in.stall <= src_stall_i;
end wrapper;
|
----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: ddr3k7-core
-- Module Name: ddr3_read_core - Behavioral
-- Project Name: YARR
-- Target Devices: xc7k160t
-- Tool Versions: Vivado v2016.2 (64 bit)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ddr3_read_core is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64;
g_NOT_CONSECUTIVE_DETECTION : boolean := false
);
Port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
wb_clk_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (g_MASK_SIZE - 1 downto 0);
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_adr_i : in STD_LOGIC_VECTOR (32 - 1 downto 0);
wb_dat_i : in STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_dat_o : out STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_stall_o : out STD_LOGIC;
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_req_o : out std_logic;
ddr_gnt_i : in std_logic
);
end ddr3_read_core;
architecture Behavioral of ddr3_read_core is
--------------------------------------
-- Components
--------------------------------------
COMPONENT fifo_29x32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(28 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_8x32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_256x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
--------------------------------------
-- Constants
--------------------------------------
constant c_read_wait_time : unsigned(7 downto 0) := TO_UNSIGNED(15, 8);
constant c_register_shift_size : integer := 8;
--------------------------------------
-- Types
--------------------------------------
type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0);
type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0);
--------------------------------------
-- Signals
--------------------------------------
signal rst_s : std_logic;
signal wb_sel_s : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal wb_cyc_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_we_s : std_logic;
signal wb_adr_s : std_logic_vector(32 - 1 downto 0);
signal wb_dat_s : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal wb_ack_s : std_logic;
signal wb_stall_s : std_logic;
signal wb_rd_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_data_shift_a : data_array;
signal wb_ack_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_addr_shift_a : addr_array;
signal wb_rd_addr_shift_next_a : addr_array;
signal wb_rd_addr_ref_a : addr_array;
signal wb_rd_shifting_s : std_logic;
signal wb_rd_aligned_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_row_a : row_array;
signal wb_rd_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_several_row_s : std_logic;
signal wb_rd_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_shift_flush_s : std_logic;
signal wb_rd_shift_flush_1_s : std_logic;
signal fifo_wb_rd_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_wr_s : std_logic;
signal fifo_wb_rd_addr_rd_s : std_logic;
signal fifo_wb_rd_addr_dout_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_full_s : std_logic;
signal fifo_wb_rd_addr_almost_full_s : std_logic;
signal fifo_wb_rd_addr_empty_s : std_logic;
signal fifo_wb_rd_mask_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_wr_s : std_logic;
signal fifo_wb_rd_mask_rd_s : std_logic;
signal fifo_wb_rd_mask_dout_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_full_s : std_logic;
signal fifo_wb_rd_mask_almost_full_s : std_logic;
signal fifo_wb_rd_mask_empty_s : std_logic;
signal fifo_wb_rd_mask_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal fifo_wb_rd_data_din_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_wr_s : std_logic;
signal fifo_wb_rd_data_rd_s : std_logic;
signal fifo_wb_rd_data_dout_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_dout_a : data_array;
signal fifo_wb_rd_data_full_s : std_logic;
signal fifo_wb_rd_data_almost_full_s : std_logic;
signal fifo_wb_rd_data_empty_s : std_logic;
signal fifo_wb_rd_data_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
--------------------------------------
-- Counter
--------------------------------------
signal wb_read_wait_cnt : unsigned(7 downto 0);
begin
rst_s <= not rst_n_i;
--------------------------------------
-- Wishbone input delay
--------------------------------------
p_wb_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_sel_s <= (others =>'0');
wb_cyc_s <= '0';
wb_stb_s <= '0';
wb_we_s <= '0';
wb_adr_s <= (others =>'0');
wb_dat_s <= (others =>'0');
elsif rising_edge(wb_clk_i) then
wb_sel_s <= wb_sel_i;
wb_cyc_s <= wb_cyc_i;
wb_stb_s <= wb_stb_i;
wb_we_s <= wb_we_i;
wb_adr_s <= wb_adr_i;
wb_dat_s <= wb_dat_i;
end if;
end process p_wb_in;
--------------------------------------
-- Wishbone ouput
--------------------------------------
wb_ack_o <= wb_ack_s;
detection_gen : if (g_NOT_CONSECUTIVE_DETECTION = true) generate
wb_stall_s <= fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s or wb_rd_several_row_s;
end generate;
no_dectection_gen : if (g_NOT_CONSECUTIVE_DETECTION = false) generate
wb_stall_s <= fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s;
end generate;
wb_stall_o <= wb_stall_s;
--------------------------------------
-- Wishbone read
--------------------------------------
p_wb_read : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
wb_read_wait_cnt <= c_read_wait_time;
wb_rd_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_a(i) <= (others => '0');
end loop;
elsif rising_edge(wb_clk_i) then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
if (wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '0') then
wb_read_wait_cnt <= c_read_wait_time;
else
if(wb_rd_valid_shift_s /= (wb_rd_valid_shift_s'range => '0')) then
if (wb_read_wait_cnt /= 0) then
wb_read_wait_cnt <= wb_read_wait_cnt - 1;
end if;
end if;
end if;
if(wb_rd_shift_flush_s = '1') then
wb_read_wait_cnt <= c_read_wait_time;
end if;
wb_rd_addr_shift_a <= wb_rd_addr_shift_next_a;
wb_rd_valid_shift_s <= wb_rd_valid_shift_next_s;
end if;
end process p_wb_read;
p_wb_read_rtl : process (wb_read_wait_cnt,wb_rd_addr_shift_a,wb_rd_addr_ref_a,wb_rd_valid_shift_s,wb_rd_shift_flush_s,wb_rd_global_row_s,wb_rd_addr_shift_a,wb_rd_row_a,wb_rd_first_row_s)
begin
fifo_wb_rd_addr_s <= (others => '0');
wb_rd_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_rd_global_row_s(i) = '1' then
fifo_wb_rd_addr_s <= wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_rd_first_row_s <= wb_rd_row_a(i);
end if;
end loop;
if((wb_rd_global_row_s /= wb_rd_first_row_s) and (wb_rd_global_row_s /= (wb_rd_global_row_s'range => '0'))) then
wb_rd_several_row_s <= '1';
else
wb_rd_several_row_s <= '0';
end if;
end process p_wb_read_rtl;
wb_rd_shifting_s <= --'0' when wb_rd_several_row_s = '1' else
'1' when wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '0' else--and wb_stall_s = '0' else
'1' when wb_read_wait_cnt = 0 else
'0';
wb_rd_global_row_s <= wb_rd_aligned_s and wb_rd_valid_shift_s;
wb_rd_flush_v_s <= wb_rd_first_row_s;
rd_match_g:for i in 0 to c_register_shift_size-1 generate
wb_rd_aligned_s(i) <= '1' when wb_rd_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
rd_row_g:for j in 0 to c_register_shift_size-1 generate
wb_rd_row_a(i)(j) <= '1' when wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_rd_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_rd_aligned_s(i) = '1' and wb_rd_aligned_s(j) = '1' and wb_rd_valid_shift_s(i) = '1' and wb_rd_valid_shift_s(j) = '1' else
'0';
end generate;
end generate;
p_wb_read_shift: process (wb_rd_shifting_s,wb_rd_addr_shift_a,wb_rd_valid_shift_s,wb_adr_s,wb_dat_s,wb_sel_s,wb_rd_flush_v_s)
begin
if(wb_rd_shifting_s = '1') then
wb_rd_addr_shift_next_a(c_register_shift_size-1) <= wb_adr_s(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_rd_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_s and wb_stb_s and not wb_we_s;
for i in 1 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i-1) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i-1) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_read_shift;
p_wb_read_data : process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= (others => '0');
wb_ack_shift_s(i) <= '0';
end loop;
elsif rising_edge(wb_clk_i) then
if(fifo_wb_rd_data_rd_s = '1') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= fifo_wb_rd_data_dout_s(63+(i*64) downto 0+(i*64));
wb_ack_shift_s(i) <= fifo_wb_rd_mask_dout_s(i); -- The data are reversed
end loop;
else
wb_rd_data_shift_a(c_register_shift_size-1) <= (others => '0');
wb_ack_shift_s(c_register_shift_size-1) <= '0';
for i in 0 to c_register_shift_size-2 loop
wb_rd_data_shift_a(i) <= wb_rd_data_shift_a(i+1);
wb_ack_shift_s(i) <= wb_ack_shift_s(i+1);
end loop;
end if;
end if;
end process p_wb_read_data;
fifo_rd_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_rd_addr_din_s <= (others => '0');
fifo_wb_rd_mask_din_s <= (others => '0');
fifo_wb_rd_addr_wr_s <= '0';
fifo_wb_rd_mask_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_rd_addr_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_mask_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_addr_din_s <= fifo_wb_rd_addr_s;
fifo_wb_rd_mask_din_s <= fifo_wb_rd_addr_s & wb_rd_valid_shift_s;
end if;
end process;
fifo_wb_rd_data_rd_s <= '1' when wb_ack_shift_s(c_register_shift_size-1 downto 1) = "0000000" and fifo_wb_rd_mask_empty_s = '0' and fifo_wb_rd_data_empty_s = '0' else
'0';
fifo_wb_rd_mask_rd_s <= fifo_wb_rd_data_rd_s;
wb_dat_o <= wb_rd_data_shift_a(0);
wb_ack_s <= wb_ack_shift_s(0);
wb_rd_shift_flush_s <= '1' when wb_rd_flush_v_s /= (wb_rd_flush_v_s'range => '0') else
'0';
fifo_wb_read_addr : fifo_29x32
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_rd_addr_din_s,
wr_en => fifo_wb_rd_addr_wr_s,
rd_en => fifo_wb_rd_addr_rd_s,
dout => fifo_wb_rd_addr_dout_s,
full => fifo_wb_rd_addr_full_s,
almost_full => fifo_wb_rd_addr_almost_full_s,
empty => fifo_wb_rd_addr_empty_s
);
fifo_wb_read_mask : fifo_8x32
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_mask_din_s(7 downto 0),
wr_en => fifo_wb_rd_mask_wr_s,
rd_en => fifo_wb_rd_mask_rd_s,
dout => fifo_wb_rd_mask_dout_s,
--dout(7 downto 0) => fifo_wb_rd_mask_dout_s,
--dout(36 downto 8) => open,--ddr_wb_rd_mask_addr_dout_do,
full => fifo_wb_rd_mask_full_s,
almost_full => fifo_wb_rd_mask_almost_full_s,
empty => fifo_wb_rd_mask_empty_s,
rd_data_count => fifo_wb_rd_mask_rd_data_count_s
);
fifo_wb_read_data : fifo_256x16
PORT MAP (
rst => rst_s,
wr_clk => ddr_ui_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_data_din_s,
wr_en => fifo_wb_rd_data_wr_s,
rd_en => fifo_wb_rd_data_rd_s,
dout => fifo_wb_rd_data_dout_s,
full => fifo_wb_rd_data_full_s,
almost_full => fifo_wb_rd_data_almost_full_s,
empty => fifo_wb_rd_data_empty_s,
rd_data_count => fifo_wb_rd_data_rd_data_count_s
);
--------------------------------------
-- DDR CMD
--------------------------------------
ddr_addr_o <= fifo_wb_rd_addr_dout_s;
ddr_cmd_o <= "001";
ddr_cmd_en_o<= fifo_wb_rd_addr_rd_s;
ddr_req_o <= not fifo_wb_rd_addr_empty_s;
--------------------------------------
-- DDR Data in
--------------------------------------
fifo_wb_rd_addr_rd_s <= ddr_rdy_i and (not fifo_wb_rd_addr_empty_s) and (not fifo_wb_rd_data_almost_full_s) and ddr_gnt_i; -- and (not fifo_wb_rd_mask_full_s);
fifo_wb_rd_data_wr_s <= ddr_rd_data_valid_i and ddr_rd_data_end_i;
fifo_wb_rd_data_din_s <= ddr_rd_data_i;
end Behavioral;
|
-------------------------------------------------------------------------------
-- qspi_core_interface Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_core_interface.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_quad_spi.
--
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - First version of axi_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 11/12/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Update the core with SPI perormance. Removed idle time between each SPI transfer.
-- 2. added async FIFO for transmit and receive FIFO.
-- 3. added CDC logic for FIFO exists and no FIFO mode.
-- 4. added support of AXI Lite, AXI4 full and XIP mode support.
-- ~~~~~~
--
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.srl_fifo_f;
use proc_common_v4_0.async_fifo_fg;-- 1/8/2013
library interrupt_control_v3_0;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
-------------------------------------------------------------------------------
entity qspi_core_interface is
generic(
C_FAMILY : string;
C_SUB_FAMILY : string;
C_S_AXI_DATA_WIDTH : integer;
----------------------
-- local parameters
C_NUM_CE_SIGNALS : integer;
----------------------
-- SPI parameters
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_FIFO_DEPTH : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_TYPE_OF_AXI4_INTERFACE : integer;
----------------------
-- local constants
C_FIFO_EXIST : integer;
C_SPI_NUM_BITS_REG : integer;
C_OCCUPANCY_NUM_BITS : integer;
----------------------
-- local constants
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE;
----------------------
-- local constants
C_SPICR_REG_WIDTH : integer;
C_SPISR_REG_WIDTH : integer
);
port(
EXT_SPI_CLK : in std_logic;
------------------------------------------------
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
------------------------------------------------
Bus2IP_BE : in std_logic_vector(0 to ((C_S_AXI_DATA_WIDTH/8)-1));
Bus2IP_RdCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_WrCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------------------------------
IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
------------------------------------------------
burst_tr : in std_logic;
rready : in std_logic;
WVALID : in std_logic;
--SPI Ports
SCK_I : in std_logic;
SCK_O : out std_logic;
SCK_T : out std_logic;
------------------------------------------------
IO0_I : in std_logic;
IO0_O : out std_logic;
IO0_T : out std_logic;
------------------------------------------------
IO1_I : in std_logic;
IO1_O : out std_logic;
IO1_T : out std_logic;
------------------------------------------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
------------------------------------------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
------------------------------------------------
SPISEL : in std_logic;
------------------------------------------------
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
------------------------------------------------
IP2INTC_Irpt : out std_logic
------------------------------------------------
);
end entity qspi_core_interface;
-------------------------------------------------------------------------------
------------
architecture imp of qspi_core_interface is
------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- function definition
----------------------
-------------------------------------------------------------------------------
-- constant definition
constant NEW_LOGIC : integer := 0;
-- These constants are indices into the "CE" arrays for the various registers.
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant SWRESET : natural := 16; -- at address C_BASEADDR + 40 h
constant SPICR : natural := 24; -- 17; -- at address C_BASEADDR + 60 h
constant SPISR : natural := 25; -- 18;
constant SPIDTR : natural := 26; -- 19;
constant SPIDRR : natural := 27; -- 20;
constant SPISSR : natural := 28; -- 21;
constant SPITFOR : natural := 29; -- 22;
constant SPIRFOR : natural := 30; -- 23; -- at address C_BASEADDR + 78 h
constant REG_HOLE : natural := 31; -- 24; -- at address C_BASEADDR + 7C h
--SPI MODULE SIGNALS
signal spiXfer_done_int : std_logic;
signal dtr_underrun_int : std_logic;
signal modf_strobe_int : std_logic;
signal slave_MODF_strobe_int : std_logic;
--OR REGISTER/FIFO SIGNALS
--TO/FROM REG/FIFO DATA
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Extra bit required for signal Register_Data_ctrl
signal register_Data_cntrl_int :std_logic_vector(0 to (C_SPI_NUM_BITS_REG+1));
signal register_Data_slvsel_int:std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_SPICR_Data_int :std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal IP2Bus_SPISR_Data_int :std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
signal IP2Bus_Receive_Reg_Data_int :std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal IP2Bus_Data_received_int:
std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal IP2Bus_SPISSR_Data_int : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
--STATUS REGISTER SIGNALS
signal sr_3_MODF_int : std_logic;
signal Tx_FIFO_Full_int : std_logic;
signal sr_5_Tx_Empty_int : std_logic;
signal sr_6_Rx_Full_int : std_logic;
signal Rc_FIFO_Empty_int : std_logic;
--RECEIVE AND TRANSMIT REGISTER SIGNALS
signal drr_Overrun_int : std_logic;
signal dtr_Underrun_strobe_int : std_logic;
--FIFO SIGNALS
signal rc_FIFO_Full_strobe_int : std_logic;
signal rc_FIFO_occ_Reversed_int :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_occ_Reversed_int_2 :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_Data_Out_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_6_Rx_Full_int_1 : std_logic;
signal FIFO_Empty_rx_1 : std_logic;
signal FIFO_Empty_rx : std_logic;
signal data_Exists_RcFIFO_int : std_logic;
signal tx_FIFO_Empty_strobe_int : std_logic;
signal tx_FIFO_occ_Reversed_int : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal tx_FIFO_occ_Reversed_int_2 : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal data_Exists_TxFIFO_int : std_logic;
signal data_Exists_TxFIFO_int_1 : std_logic;
signal data_From_TxFIFO_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_FIFO_less_half_int : std_logic;
signal Tx_FIFO_Full_int_1 : std_logic;
signal FIFO_Empty_tx : std_logic;
signal data_From_TxFIFO_int_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_occ_msb : std_logic;
signal tx_occ_msb_1 : std_logic:= '0';
signal tx_occ_msb_2 : std_logic;
signal tx_occ_msb_3 : std_logic;
signal tx_occ_msb_4 : std_logic;
signal reset_TxFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal ip2Bus_Data_Reg_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_occupancy_int: std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_SS_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
-- interface between signals on instance basis
signal bus2IP_Reset_int : std_logic;
signal bus2IP_Data_for_interrupt_core : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2Bus_Error_int : std_logic;
signal ip2Bus_WrAck_int : std_logic;-- := '0';
signal ip2Bus_RdAck_int : std_logic;-- := '0';
signal ip2Bus_IntrEvent_int : std_logic_vector
(0 to (C_IP_INTR_MODE_ARRAY'length-1));
signal transmit_ip2bus_error : std_logic;
signal receive_ip2bus_error : std_logic;
-- SOFT RESET SIGNALS
signal reset2ip_reset_int : std_logic;
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
-- INTERRUPT SIGNALS
signal intr_ip2bus_data : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_error : std_logic;
signal ip2bus_error_RdWr : std_logic;
--
signal wr_ce_reduce_ack_gen: std_logic;
--
signal rd_ce_reduce_ack_gen : std_logic;
--
signal control_bit_7_8_int : std_logic_vector(0 to 1);
signal spisel_pulse_o_int : std_logic;
signal spisel_d1_reg : std_logic;
signal Mst_N_Slv_mode : std_logic;
-----
signal bus2ip_intr_rdce : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_intr_wrce : std_logic_vector(INTR_LO to INTR_HI);
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal intr_controller_rd_ce_or_reduce : std_logic;
signal intr_controller_wr_ce_or_reduce : std_logic;
signal wr_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_WrAck_core_reg_d1 : std_logic;
signal ip2Bus_WrAck_core_reg : std_logic;
signal rd_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_RdAck_core_reg_d1 : std_logic;
signal ip2Bus_RdAck_core_reg : std_logic;
signal SPISR_0_CMD_Error_int : std_logic;
signal SPISR_1_LOOP_Back_Error_int : std_logic;
signal SPISR_2_MSB_Error_int : std_logic;
signal SPISR_3_Slave_Mode_Error_int : std_logic;
signal SPISR_4_CPOL_CPHA_Error_int : std_logic;
signal SPISR_Ext_SPISEL_slave_int : std_logic;
signal SPICR_5_TXFIFO_RST_int : std_logic;
-- signal SPICR_6_RXFIFO_RST_int : std_logic;
signal pr_state_idle_int : std_logic;
signal Quad_Phase_int : std_logic;
signal SPICR_0_LOOP_frm_axi :std_logic;
signal SPICR_0_LOOP_to_spi :std_logic;
signal SPICR_1_SPE_frm_axi :std_logic;
signal SPICR_1_SPE_to_spi :std_logic;
signal SPICR_2_MST_N_SLV_frm_axi :std_logic;
signal SPICR_2_MST_N_SLV_to_spi :std_logic;
signal SPICR_3_CPOL_frm_axi :std_logic;
signal SPICR_3_CPOL_to_spi :std_logic;
signal SPICR_4_CPHA_frm_axi :std_logic;
signal SPICR_4_CPHA_to_spi :std_logic;
signal SPICR_5_TXFIFO_frm_axi :std_logic;
signal SPICR_5_TXFIFO_to_spi :std_logic;
--signal SPICR_6_RXFIFO_RST_frm_axi:std_logic;
--signal SPICR_6_RXFIFO_RST_to_spi :std_logic;
signal SPICR_7_SS_frm_axi :std_logic;
signal SPICR_7_SS_to_spi :std_logic;
signal SPICR_8_TR_INHIBIT_frm_axi:std_logic;
signal SPICR_8_TR_INHIBIT_to_spi :std_logic;
signal SPICR_9_LSB_frm_axi :std_logic;
signal SPICR_9_LSB_to_spi :std_logic;
signal SPICR_bits_7_8_frm_spi :std_logic;
signal SPICR_bits_7_8_to_axi :std_logic;
signal Rx_FIFO_Empty : std_logic;
signal rx_fifo_full_to_axi_clk : std_logic;
signal tx_fifo_empty_to_axi_clk : std_logic;
signal tx_fifo_full : std_logic;
signal spisel_d1_reg_to_axi_clk : std_logic;
signal spicr_bits_7_8_frm_axi_clk : std_logic_vector(1 downto 0);
signal spicr_8_tr_inhibit_to_spi_clk : std_logic;
signal spicr_9_lsb_to_spi_clk : std_logic;
signal spicr_bits_7_8_to_spi_clk : std_logic_vector(0 to 1);
signal spicr_0_loop_frm_axi_clk : std_logic;
signal spicr_1_spe_frm_axi_clk : std_logic;
signal spicr_2_mst_n_slv_frm_axi_clk : std_logic;
signal spicr_3_cpol_frm_axi_clk : std_logic;
signal spicr_4_cpha_frm_axi_clk : std_logic;
signal spicr_5_txfifo_rst_frm_axi_clk : std_logic;
signal spicr_6_rxfifo_rst_frm_axi_clk : std_logic;
signal spicr_7_ss_frm_axi_clk : std_logic;
signal spicr_8_tr_inhibit_frm_axi_clk : std_logic;
signal spicr_9_lsb_frm_axi_clk : std_logic;
signal Tx_FIFO_wr_ack_1 : std_logic;
signal rst_to_spi_int : std_logic;
signal spicr_0_loop_to_spi_clk : std_logic;
signal spicr_1_spe_to_spi_clk : std_logic;
signal spicr_2_mas_n_slv_to_spi_clk : std_logic;
signal spicr_3_cpol_to_spi_clk : std_logic;
signal spicr_4_cpha_to_spi_clk : std_logic;
signal spicr_5_txfifo_rst_to_spi_clk : std_logic;
signal spicr_6_rxfifo_rst_to_spi_clk : std_logic;
signal spicr_7_ss_to_spi_clk : std_logic;
signal sr_3_modf_to_spi_clk : std_logic;
signal sr_3_modf_frm_axi_clk : std_logic;
signal data_from_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Bus2IP_WrCE_d1 : std_logic;
signal Bus2IP_WrCE_d2 : std_logic;
signal Bus2IP_WrCE_d3 : std_logic;
signal Bus2IP_WrCE_pulse_1 : std_logic;
signal Bus2IP_WrCE_pulse_2 : std_logic;
signal Bus2IP_WrCE_pulse_3 : std_logic;
signal data_to_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_fifo_wr_ack : std_logic;
-- signal ext_spi_clk : std_logic;
signal tx_fifo_rd_ack_open : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal c_wr_count_width : std_logic;
signal rx_fifo_wr_ack_open : std_logic;
signal data_from_rx_fifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal rx_fifo_rd_ack : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal SPISSR_frm_axi_clk : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal modf_strobe_frm_spi_clk : std_logic;
signal modf_strobe_to_axi_clk : std_logic;
signal dtr_underrun_frm_spi_clk : std_logic;
signal dtr_underrun_to_axi_clk : std_logic;
signal data_to_rx_fifo : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_d1_reg_frm_spi_clk : std_logic;
signal Mst_N_Slv_mode_frm_spi_clk: std_logic;
signal Mst_N_Slv_mode_to_axi_clk : std_logic;
signal SPICR_2_MST_N_SLV_to_spi_clk : std_logic;
signal spicr_5_txfifo_frm_axi_clk : std_logic;
signal spicr_5_txfifo_to_spi_clk: std_logic;
signal reset_RcFIFO_ptr_frm_axi_clk : std_logic;
-- signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal SPIXfer_done_Rx_Wr_en, SPIXfer_done_rd_tx_en: std_logic;
signal Tx_FIFO_Empty_SPISR_frm_spi_clk : std_logic;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : std_logic;
signal Tx_FIFO_Empty_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_int,Rx_FIFO_Full_i,RX_one_less_than_full : std_logic;
signal updown_cnt_en_tx, updown_cnt_en_rx : std_logic;
signal TX_one_less_than_full : std_logic;
signal tx_cntr_xfer_done : std_logic;
signal Tx_FIFO_one_less_to_Empty, Tx_FIFO_Full_i: std_logic;
signal Tx_FIFO_Empty_i, Tx_FIFO_Empty_int : std_logic;
signal Tx_FIFO_Empty_frm_axi_clk : std_logic;
signal rx_fifo_empty_i : std_logic;
signal Rx_FIFO_Empty_int : std_logic;
signal IP2Bus_WrAck_1 : std_logic;
signal ip2Bus_WrAck_core_reg_1 : std_logic;
signal IP2Bus_RdAck_1 : std_logic;
signal ip2Bus_RdAck_core_reg_1 : std_logic;
signal IP2Bus_Error_1 : std_logic;
signal ip2Bus_Data_1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)) ;
signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
signal rx_fifo_reset, tx_fifo_reset : std_logic;
signal reg_hole_wr_ack: std_logic;
signal reg_hole_rd_ack: std_logic;
signal read_ack_delay_1: std_logic;
signal read_ack_delay_2: std_logic;
signal read_ack_delay_3: std_logic;
signal read_ack_delay_4: std_logic;
signal read_ack_delay_5: std_logic;
signal read_ack_delay_6: std_logic;
signal read_ack_delay_7: std_logic;
signal read_ack_delay_8: std_logic;
signal write_ack_delay_1: std_logic;
signal write_ack_delay_2: std_logic;
signal write_ack_delay_3: std_logic;
signal write_ack_delay_4: std_logic;
signal write_ack_delay_5: std_logic;
signal write_ack_delay_6: std_logic;
signal write_ack_delay_7: std_logic;
signal write_ack_delay_8: std_logic;
signal error_ack_delay_1: std_logic;
signal error_ack_delay_2: std_logic;
signal error_ack_delay_3: std_logic;
signal error_ack_delay_4: std_logic;
signal error_ack_delay_5: std_logic;
signal error_ack_delay_6: std_logic;
signal error_ack_delay_7: std_logic;
signal error_ack_delay_8: std_logic;
--------------------------------------------------------------------------------
begin
-----
-----------------------------------
-- Combinatorial operations for SPI
-----------------------------------
---- A write to read only register wont have any effect on register.
---- The transaction is completed by generating WrAck only.
LEGACY_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error_1 <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
REG_ERR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_Error <= '0';
else
IP2Bus_Error <= IP2Bus_Error_1;
end if;
end if;
end process REG_ERR_ACK_P;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
Bus2IP_WrCE(SPIDTR) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
--end generate WR_ACK_OR_REDUCE_FIFO_1_GEN;
-----------------------------------------
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg_1;
-------------------------------------------------
-- common WrAck to IPIF
IP2Bus_WrAck_1 <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
ip2Bus_WrAck_core_reg;-- or
--Tx_FIFO_wr_ack; -- newly added
REG_WR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_WrAck <= '0';
else
IP2Bus_WrAck <= IP2Bus_WrAck_1;
end if;
end if;
end process REG_WR_ACK_P;
-------------------------------------------------
--end generate LEGACY_MD_WR_ACK_GEN;
-------------------------------------------------
--LEGACY_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
--begin
-----
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck_1 <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg;
REG_RD_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_RdAck <= '0';
else
IP2Bus_RdAck <= IP2Bus_RdAck_1;
end if;
end if;
end process REG_RD_ACK_P;
---------------------------------------------------
end generate LEGACY_MD_WR_RD_ACK_GEN;
-------------------------------------------------
ENHANCED_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
Bus2IP_WrCE(SPIDTR) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register; -- register hole
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg;--_1;
-------------------------------------------------
-- common WrAck to IPIF
-- in the enhanced mode for FIFO, the IP2bus_Wrack is provided by the enhanced mode statemachine only.
IP2Bus_WrAck <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
(ip2Bus_WrAck_core_reg and (not burst_tr));-- or
--(Tx_FIFO_wr_ack and burst_tr); -- newly added
-------------------------------------------------
--ENHANCED_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
--begin
-----
FIFO_NO_RD_CE_GEN: if C_FIFO_EXIST = 0 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_NO_RD_CE_GEN;
FIFO_YES_RD_CE_GEN: if C_FIFO_EXIST = 1 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
--Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_YES_RD_CE_GEN;
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
--ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg; --_1;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg or
(Rx_FIFO_rd_ack and rready);
-----------------------------------------------------
end generate ENHANCED_MD_WR_RD_ACK_GEN;
-------------------------------------------------
--=============================================================================
TX_FIFO_OCC_DATA_FIFO_16: if C_FIFO_DEPTH = 16 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty); --(FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_16;
--------------------------------------
TX_FIFO_OCC_DATA_FIFO_256: if C_FIFO_DEPTH = 256 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(4)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(5)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(6)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(7)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);-- (FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(4)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(5)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(6)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(7)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_256;
--*****************************************************************************
ip2Bus_Data_occupancy_int(0 to (C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS-1))
<= (others => '0');
ip2Bus_Data_occupancy_int((C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS)
to (C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 or
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1;
-------------------------------------------------------------------------------
-- SPECIAL_CASE_WHEN_SS_NOT_EQL_32 : The Special case is executed whenever
-- C_NUM_SS_BITS is less than 32
-------------------------------------------------------------------------------
SPECIAL_CASE_WHEN_SS_NOT_EQL_32: if(C_NUM_SS_BITS /= 32) generate
-----
begin
-----
ip2Bus_Data_SS_int(0 to (C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS-1))
<= (others => '0');
end generate SPECIAL_CASE_WHEN_SS_NOT_EQL_32;
---------------------------------------------
ip2Bus_Data_SS_int((C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS) to
(C_S_AXI_DATA_WIDTH-1)) <= IP2Bus_SPISSR_Data_int;
-------------------------------------------------------------------------------
ip2Bus_Data_Reg_int(0 to C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH-1) <= (others => '0');
ip2Bus_Data_Reg_int(C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH to C_S_AXI_DATA_WIDTH-1)
<= IP2Bus_SPISR_Data_int or -- SPISR - 11 bit
('0' & IP2Bus_SPICR_Data_int); -- SPICR - 10 bit
-------------------------------------------------------------------------------
-----------------------
Receive_Reg_width_is_32: if(C_NUM_TRANSFER_BITS = 32) generate
-----------------------
begin
-----
IP2Bus_Data_received_int <= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_32;
-----------------------------------------
---------------------------
Receive_Reg_width_is_not_32: if(C_NUM_TRANSFER_BITS /= 32) generate
---------------------------
begin
-----
IP2Bus_Data_received_int(0 to C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS-1)
<= (others => '0');
IP2Bus_Data_received_int((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to
(C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_not_32;
-----------------------------------------
-------------------------------------------------------------------------------
LEGACY_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
ip2Bus_Data_1 <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
REG_IP2BUS_DATA_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_Data <= (others => '0');
else
ip2Bus_Data <= ip2Bus_Data_1;
end if;
end if;
end process REG_IP2BUS_DATA_P;
end generate LEGACY_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
ENHANCED_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
ip2Bus_Data <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
end generate ENHANCED_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_1.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
--Bus2IP_Clk => Bus2IP_Clk ,-- in std_logic;
Soft_Reset_frm_axi => reset2ip_reset_int,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------
-- NO_FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 0
--------------------------------------
NO_FIFO_EXISTS: if(C_FIFO_EXIST = 0) generate
----------------------------------
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal modf_strobe_frm_spi_clk : std_logic;
-- signal modf_strobe_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal receive_data_frm_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_data_to_axi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_frm_axi_clk: std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_to_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_fifo_0 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal drr_Overrun_int_frm_spi_clk: std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
-----
begin
-----
Rx_FIFO_rd_ack <= '0';
--------------------------------------------------------------------------
-- I_RECEIVE_REG : INSTANTIATE RECEIVE REGISTER
--------------------------------------------------------------------------
QSPI_RX_TX_REG: entity axi_quad_spi_v3_1.qspi_receive_transmit_reg
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int, -- in
--SPI Receiver signals -- From AXI clock
Bus2IP_Receive_Reg_RdCE => Bus2IP_RdCE(SPIDRR), -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
IP2Bus_Receive_Reg_Data => IP2Bus_Receive_Reg_Data_int, -- out
--SPI module ports From SPI clock
SPIXfer_done => spiXfer_done_to_axi_clk,--spiXfer_done_int,-- in
SPI_Received_Data => receive_data_to_axi_clk,--receive_Data_int,-- in vec
-- receive & transmit reg signals
-- DRR_Overrun => drr_Overrun_int,-- drr_Overrun_int,-- out
SR_7_Rx_Empty => Rx_FIFO_Empty_i, -- out
-- From AXI clock
Bus2IP_Transmit_Reg_Data=> Bus2IP_Data, -- in vec
Bus2IP_Transmit_Reg_WrCE=> Bus2IP_WrCE(SPIDTR), -- in
Wr_ce_reduce_ack_gen => wr_ce_reduce_ack_gen, -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen, -- in
--SPI Transmitter signals from AXI clock
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
--SPI module ports
DTR_underrun => dtr_underrun_to_axi_clk,--dtr_underrun_int,-- in
SR_5_Tx_Empty => sr_5_Tx_Empty_int, -- out
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
Transmit_Reg_Data_Out => transmit_Data_fifo_0--transmit_Data_int -- out vec
);
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
spiXfer_done_frm_spi_clk <= spiXfer_done_int ;-- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int ;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int;-- from SPI module
receive_data_frm_spi_clk <= Data_To_Rx_FIFO ; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
transmit_Data_frm_axi_clk <= transmit_Data_fifo_0; -- From AXI clock
Tx_FIFO_Empty_frm_axi_clk <= sr_5_Tx_Empty_int;
Tx_FIFO_Empty_SPISR_frm_spi_clk <= sr_5_Tx_Empty_int;
--Rx_FIFO_Empty_int <= Rx_FIFO_Empty;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty_i;
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
CROSS_CLK_FIFO_0_INST:entity axi_quad_spi_v3_1.cross_clk_sync_fifo_0
generic map(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
--C_AXI_SPI_CLK_EQ_DIFF => C_AXI_SPI_CLK_EQ_DIFF,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK,
Bus2IP_Clk => Bus2IP_Clk ,
Soft_Reset_op => reset2ip_reset_int,
Rst_from_axi_cdc_to_spi => Rst_to_spi_int, -- out std_logic;
----------------------------------------------------------
Tx_FIFO_Empty_cdc_from_axi => Tx_FIFO_Empty_frm_axi_clk,
Tx_FIFO_Empty_cdc_to_spi => Tx_FIFO_Empty,
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------------------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk , -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk , -- out
----------------------------------------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk, -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------------------------------------
Slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk ,-- out
----------------------------------------------------------
receive_Data_cdc_from_spi => receive_Data_frm_spi_clk, -- in
receive_Data_cdc_to_axi => receive_data_to_axi_clk, -- out
----------------------------------------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk, -- in
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk, -- out
----------------------------------------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk, -- out
----------------------------------------------------------
transmit_Data_cdc_from_axi => transmit_Data_frm_axi_clk, -- in
transmit_Data_cdc_to_spi => transmit_Data_to_spi_clk, -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk ,-- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int -- out
----------------------------
);
Data_From_TxFIFO <= transmit_Data_to_spi_clk;
rc_FIFO_Full_strobe_int <= '0';
rc_FIFO_occ_Reversed_int <= (others => '0');
rc_FIFO_Data_Out_int <= (others => '0');
data_Exists_RcFIFO_int <= '0';
tx_FIFO_Empty_strobe_int <= '0';
tx_FIFO_occ_Reversed_int <= (others => '0');
data_Exists_TxFIFO_int <= '0';
data_From_TxFIFO_int <= (others => '0');
tx_FIFO_less_half_int <= '0';
reset_TxFIFO_ptr_int <= '0';
reset_RcFIFO_ptr_int <= '0';
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
Tx_FIFO_Full_int <= not(sr_5_Tx_Empty_int); -- Tx_FIFO_Empty_to_axi_clk);
Rx_FIFO_Full_int <= not(Rx_FIFO_Empty_i);
--------------------------------------------------------------------------
bus2IP_Data_for_interrupt_core(0 to 14) <= Bus2IP_Data(0 to 14);
bus2IP_Data_for_interrupt_core(15 to 22) <= (others => '0');
-- below code manipulates the bus2ip_data going towards interrupt control
-- unit. In FIFO=0, case bit 23 and 25 of IPIER are not applicable.
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 22 23 31
-- <---NA---> <-used->
-- 23 24 25 26 27 28 29 30 31
-- DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- NA-fifo-0 NA -fifo-0
bus2IP_Data_for_interrupt_core(23) <= '0'; -- DRR_Not_Empty bit in IPIER/IPISR
bus2IP_Data_for_interrupt_core(24) <= Bus2IP_Data(24);
bus2IP_Data_for_interrupt_core(25) <= '0'; -- Tx FIFO Half Empty
bus2IP_Data_for_interrupt_core(26 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(26 to (C_S_AXI_DATA_WIDTH-1));
--------------------------------------------------------------------------
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(12) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(11) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(10) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(9) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(8) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk; -- spisel_pulse_o_int;
ip2Bus_IntrEvent_int(6) <= '0'; --
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int_to_axi_clk;
ip2Bus_IntrEvent_int(4) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int;
ip2Bus_IntrEvent_int(2) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; -- slave_MODF_strobe_int;
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int;
end generate NO_FIFO_EXISTS;
-------------------------------------------------------------------------------
-- FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 1
-------------------------------------------------------------------------------
FIFO_EXISTS: if(C_FIFO_EXIST = 1) generate
------------------------------
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant TX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
constant ZERO_TX_FIFO_CNT : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d1: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d2: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal Tx_FIFO_Empty_1 : std_logic;
signal Tx_FIFO_Empty_intr : std_logic;
signal IP2Bus_RdAck_receive_enable : std_logic;
signal IP2Bus_WrAck_transmit_enable : std_logic;
constant ALL_0 : std_logic_vector(0 to TX_FIFO_CNTR_WIDTH-1)
:= (others => '1');
signal data_Exists_RcFIFO_int_d1: std_logic;
signal data_Exists_RcFIFO_pulse : std_logic;
--signal FIFO_Empty_rx : std_logic;
--signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
--signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
--signal spisel_d1_reg_frm_spi_clk : std_logic;
--signal spisel_d1_reg_to_axi_clk : std_logic;
signal tx_occ_msb_111 : std_logic:= '0';
signal tx_occ_msb_11 : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal Rx_FIFO_Empty_frm_axi_clk : std_logic;
signal Rx_FIFO_Empty_to_spi_clk : std_logic;
signal Tx_FIFO_Full_frm_axi_clk : std_logic;
signal Tx_FIFO_Full_to_spi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal SR_3_modf_frm_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal spiXfer_done_to_axi_d1 : std_logic;
signal updown_cnt_en : std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
signal drr_Overrun_int_frm_spi_clk: std_logic;
-----
begin
-----
SPISR_0_CMD_Error_frm_spi_clk <= SPISR_0_CMD_Error_int;
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int; -- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int; -- spi module
Rx_FIFO_Full_frm_spi_clk <= Rx_FIFO_Full; -- from Async Receive FIFO
Tx_FIFO_Empty_frm_spi_clk <= Tx_FIFO_Empty_intr; -- Tx_FIFO_Empty; -- from Async Transmit FIFO
spiXfer_done_frm_spi_clk <= spiXfer_done_int; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
Tx_FIFO_Empty_SPISR_frm_spi_clk <= Tx_FIFO_Empty;-- from TX FIFO for SPI Status register
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
-- SPICR_6_RXFIFO_RST_frm_axi_clk<= SPICR_6_RXFIFO_RST_frm_axi_clk; -- from SPICR
reset_RcFIFO_ptr_frm_axi_clk <= reset_RcFIFO_ptr_int; -- from AXI clock
Rx_FIFO_Empty_frm_axi_clk <= Rx_FIFO_Empty; -- from Async Receive FIFO AXI side
Tx_FIFO_Full_frm_axi_clk <= Tx_FIFO_Full; -- from Async Transmit FIFO AXI side
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
--CLK_CROSS_I:
CLK_CROSS_I:entity axi_quad_spi_v3_1.cross_clk_sync_fifo_1
generic map(
C_FAMILY => C_FAMILY ,
C_FIFO_DEPTH => C_FIFO_DEPTH ,
C_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK , -- in std_logic;
Bus2IP_Clk => Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => reset2ip_reset_int ,
--Soft_Reset_op => Soft_Reset_op , -- in std_logic;
Rst_cdc_to_spi => Rst_to_spi_int , -- out std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi => SPISR_0_CMD_Error_frm_spi_clk ,
SPISR_0_CMD_Error_cdc_to_axi => SPISR_0_CMD_Error_to_axi_clk ,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------
Mst_N_Slv_mode_cdc_from_spi => Mst_N_Slv_mode_frm_spi_clk , -- in
Mst_N_Slv_mode_cdc_to_axi => Mst_N_Slv_mode_to_axi_clk , -- out
----------------------------
slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk, -- in
slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk , -- out
----------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk , -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk, -- in
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk , -- out
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full_frm_spi_clk, -- in
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk , -- out
----------------------------
reset_RcFIFO_ptr_cdc_from_axi => reset_RcFIFO_ptr_frm_axi_clk, -- in
reset_RcFIFO_ptr_cdc_to_spi => reset_RcFIFO_ptr_to_spi_clk , -- out
----------------------------
Rx_FIFO_Empty_cdc_from_axi => Rx_FIFO_Empty_frm_axi_clk , -- in
Rx_FIFO_Empty_cdc_to_spi => Rx_FIFO_Empty_to_spi_clk , -- out
----------------------------
Tx_FIFO_Empty_cdc_from_spi => Tx_FIFO_Empty_frm_spi_clk, -- in
Tx_FIFO_Empty_cdc_to_axi => Tx_FIFO_Empty_to_Axi_clk, -- out
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_cdc_from_axi => Tx_FIFO_Full_frm_axi_clk,-- in
Tx_FIFO_Full_cdc_to_spi => Tx_FIFO_Full_to_spi_clk ,-- out
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk, -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk, -- out
----------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk , -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int, -- out
----------------------------
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1,
----------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk,
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk
----------------------------
);
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 17 18 31
-- <---NA---> <-used->
-- 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-- CMD_ Loop_Bk MSB Slave_Mode CPOL_CPHA DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- Error Error Error Error Error _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- In Slave
-- mode_only
-- <---------------------------------------> <------------------------------------------------------------->
-- In C_SPI_MODE 1 or 2 only Present in all conditions
-- IPISR Write
-- when FIFO = 1,all other the IPIER, IPISR interrupt bits are applicable based upon the SPI mode.
-- DRR_Not_Empty bit (bit 23) - available only in case of core is selected in
-- slave mode and control register mst_n_slv bit is '0'.
-- Slave_select_mode bit-available only in case of core is selected in slave mode
-- common assignment to SPI_MODE 1/2 and SPI_MODE = 0
bus2IP_Data_for_interrupt_core(0 to 17) <= Bus2IP_Data(0 to 17);
DUAL_MD_IPISR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22) <= Bus2IP_Data(18 to 22);
end generate DUAL_MD_IPISR_GEN;
---------------------------------------------
STD_MD_IPISR_GEN: if C_SPI_MODE = 0 generate
-----------------------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22)<= (others => '0');
end generate STD_MD_IPISR_GEN;
------------------------------------------------
bus2IP_Data_for_interrupt_core(23) <= Bus2IP_Data(23) and -- exists only when FIFO = exists AND
((not spisel_d1_reg_to_axi_clk) --spisel_d1_reg)
or -- core is selected by asserting SPISEL by ext. master AND
(not Mst_N_Slv_mode) --Mst_N_Slv_mode) -- core is in slave mode
);
bus2IP_Data_for_interrupt_core(24 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(24 to (C_S_AXI_DATA_WIDTH-1));
--
----------------------------------------------------
-- _____|------------- data_Exists_RcFIFO_int
-- ________|---------- data_Exists_RcFIFO_int_d1
-- _____|--|__________ data_Exists_RcFIFO_pulse
----------------------------------------------------
DRR_NOT_EMPTY_PULSE_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
data_Exists_RcFIFO_int_d1 <= '0';
else
data_Exists_RcFIFO_int_d1 <= not rx_fifo_empty_i; -- data_Exists_RcFIFO_int;
end if;
end if;
end process DRR_NOT_EMPTY_PULSE_P;
------------------------------------
data_Exists_RcFIFO_pulse <= not rx_fifo_empty_i and
(not data_Exists_RcFIFO_int_d1);
------------------------------------
---------------------------------------------------------------------------
DUAL_MD_INTR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
signal SPISR_4_CPOL_CPHA_Error_d1 : std_logic;
signal SPISR_3_Slave_Mode_Error_d1 : std_logic;
signal SPISR_2_MSB_Error_d1 : std_logic;
signal SPISR_1_LOOP_Back_Error_d1 : std_logic;
signal SPISR_0_CMD_Error_d1 : std_logic;
signal SPISR_4_CPOL_CPHA_Error_pulse : std_logic;
signal SPISR_3_Slave_Mode_Error_pulse: std_logic;
signal SPISR_2_MSB_Error_pulse : std_logic;
signal SPISR_1_LOOP_Back_Error_pulse : std_logic;
signal SPISR_0_CMD_Error_pulse : std_logic;
-----
begin
-----
INTR_UPPER_BITS_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
SPISR_0_CMD_Error_d1 <= '0';
SPISR_1_LOOP_Back_Error_d1 <= '0';
SPISR_2_MSB_Error_d1 <= '0';
SPISR_3_Slave_Mode_Error_d1 <= '0';
SPISR_4_CPOL_CPHA_Error_d1 <= '0';
else
SPISR_0_CMD_Error_d1 <= SPISR_0_CMD_Error_to_axi_clk; -- SPISR_0_CMD_Error_int;
SPISR_1_LOOP_Back_Error_d1 <= SPISR_1_LOOP_Back_Error_int; -- from SPICR
SPISR_2_MSB_Error_d1 <= SPISR_2_MSB_Error_int; -- from SPICR
SPISR_3_Slave_Mode_Error_d1 <= SPISR_3_Slave_Mode_Error_int;-- from SPICR
SPISR_4_CPOL_CPHA_Error_d1 <= SPISR_4_CPOL_CPHA_Error_int; -- from SPICR
end if;
end if;
end process INTR_UPPER_BITS_P;
------------------------------------
SPISR_0_CMD_Error_pulse <= SPISR_0_CMD_Error_to_axi_clk -- SPISR_0_CMD_Error_int
and (not SPISR_0_CMD_Error_d1);
SPISR_1_LOOP_Back_Error_pulse <= SPISR_1_LOOP_Back_Error_int
and (not SPISR_1_LOOP_Back_Error_d1);
SPISR_2_MSB_Error_pulse <= SPISR_2_MSB_Error_int
and (not SPISR_2_MSB_Error_d1);
SPISR_3_Slave_Mode_Error_pulse <= SPISR_3_Slave_Mode_Error_int
and (not SPISR_3_Slave_Mode_Error_d1);
SPISR_4_CPOL_CPHA_Error_pulse <= SPISR_4_CPOL_CPHA_Error_int
and (not SPISR_4_CPOL_CPHA_Error_d1);
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= SPISR_0_CMD_Error_pulse;
ip2Bus_IntrEvent_int(12) <= SPISR_1_LOOP_Back_Error_pulse;
ip2Bus_IntrEvent_int(11) <= SPISR_2_MSB_Error_pulse;
ip2Bus_IntrEvent_int(10) <= SPISR_3_Slave_Mode_Error_pulse;
ip2Bus_IntrEvent_int(9) <= SPISR_4_CPOL_CPHA_Error_pulse ;
end generate DUAL_MD_INTR_GEN;
--------------------------------------------
STD_MD_INTR_GEN: if C_SPI_MODE = 0 generate
-----------------------
begin
-----
ip2Bus_IntrEvent_int(13) <= '0';
ip2Bus_IntrEvent_int(12) <= '0';
ip2Bus_IntrEvent_int(11) <= '0';
ip2Bus_IntrEvent_int(10) <= '0';
ip2Bus_IntrEvent_int(9) <= '0';
end generate STD_MD_INTR_GEN;
-----------------------------------------------
ip2Bus_IntrEvent_int(8) <= data_Exists_RcFIFO_pulse and
((not spisel_d1_reg_to_axi_clk) -- spisel_d1_reg)
or
(not SPICR_2_MST_N_SLV_frm_axi_clk) -- Mst_N_Slv_mode)
);
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk;-- and not SPICR_2_MST_N_SLV_frm_axi_clk; -- spisel_pulse_o_int;-- spi_module
ip2Bus_IntrEvent_int(6) <= tx_FIFO_less_half_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(4) <= rc_FIFO_Full_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(2) <= tx_FIFO_Empty_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; --slave_MODF_strobe_int;-- spi_module
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int; -- spi_module
--Combinatorial operations
reset_TxFIFO_ptr_int <= reset2ip_reset_int or SPICR_5_TXFIFO_RST_frm_axi_clk;
--reset_RcFIFO_ptr_int <= Rst_to_spi_int or SPICR_6_RXFIFO_RST_to_spi_clk; -- SPICR_6_RXFIFO_RST_int;
reset_RcFIFO_ptr_int <= reset2ip_reset_int or SPICR_6_RXFIFO_RST_frm_axi_clk;
sr_5_Tx_Empty_int <= not (data_Exists_TxFIFO_int);
Rc_FIFO_Empty_int <= Rx_FIFO_Empty;--not (data_Exists_RcFIFO_int);
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
RX_RD_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_RdAck_receive_enable <= (rd_ce_reduce_ack_gen and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_LEG_MD_GEN;
RX_RD_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
begin
-----
IP2Bus_RdAck_receive_enable <= --(rd_ce_reduce_ack_gen and
(rready and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_ENHAN_MD_GEN;
-- Receive FIFO Logic
rx_fifo_reset <= Rst_to_spi_int or reset_RcFIFO_ptr_to_spi_clk;
RX_FIFO_II: entity proc_common_v4_0.async_fifo_fg --axi_quad_spi_v3_1.async_fifo_fg --proc_common_v4_0.async_fifo_fg
generic map(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => spiXfer_done_int, --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => Rx_FIFO_wr_ack_open , -- : out std_logic;
------
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => IP2Bus_RdAck_receive_enable , -- : in std_logic := '0';
Rd_clk => Bus2IP_Clk , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Full => open, --Rx_FIFO_Full , -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => Rx_FIFO_occ_Reversed , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => rx_fifo_reset, -- reset_RcFIFO_ptr_to_spi_clk ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
RX_FIFO_FULL_CNTR_I : entity proc_common_v4_0.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => reset_RcFIFO_ptr_int, -- in
----------------
Count_Down => IP2Bus_RdAck_receive_enable, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= IP2Bus_RdAck_receive_enable or spiXfer_done_to_axi_1;
RX_one_less_than_full <= and_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto RX_FIFO_CNTR_WIDTH-RX_FIFO_CNTR_WIDTH+1)) and
(not rx_fifo_count(0))and spiXfer_done_to_axi_1;
RX_FULL_EMP_MD_12_INTR_GEN: if C_SPI_MODE /= 0 generate
-----
--signal rx_fifo_empty_i : std_logic;
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
RX_FIFO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then --(drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(RX_one_less_than_full = '1' and
spiXfer_done_to_axi_1 = '1' and
rx_fifo_empty_i = '0')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
end generate RX_FULL_EMP_MD_12_INTR_GEN;
------------------------------------
RX_FULL_EMP_MD_0_GEN: if C_SPI_MODE = 0 generate
--signal rx_fifo_empty_i : std_logic;
-----
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
-------------------------------------------
RX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_i <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(Rx_FIFO_Full_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(RX_one_less_than_full = '1')then
Rx_FIFO_Full_i <= '1';
end if;
end if;
end process RX_FIFO_ABT_TO_FULL_P;
-------------------------------------
RX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_i = '1')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
---------------------------------
Rx_FIFO_Full <= Rx_FIFO_Full_int;
end generate RX_FULL_EMP_MD_0_GEN;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty or Rx_FIFO_Empty_i;
-----------------------------------------------------------------------------
-- AXI Clk domain -- __________________ SPI clk domain
--Din --|AXI clk |-- Dout
--Wr_en --| |-- Rd_en
--Wr_clk --| |-- Rd_clk
--| |--
--Tx_FIFO_Full --| Tx FIFO |-- Tx_FIFO_Empty
--Tx_FIFO_almost_Full --| |-- Tx_FIFO_almost_Empty
--Tx_FIFO_occ_Reversed --| |-- Tx_FIFO_rd_ack
--Tx_FIFO_wr_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
TX_TR_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
Bus2IP_WrCE(SPIDTR)
) and
(not Tx_FIFO_Full);-- after 100 ps;
end generate TX_TR_EN_LEG_MD_GEN;
TX_TR_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
signal local_tr_en : std_logic;
begin
-----
--IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
-- Bus2IP_WrCE(SPIDTR)
-- ) and
-- (not Tx_FIFO_Full)
-- when burst_tr = '0' else
-- (Bus2IP_WrCE(SPIDTR)
-- and
-- (not Tx_FIFO_Full));-- after 100 ps;
local_tr_en <= Bus2IP_WrCE(SPIDTR) and (not Tx_FIFO_Full);
--local_tr_en1 <= Bus2IP_WrCE_d1 and (not Tx_FIFO_Full);
TR_EN_P:process(wr_ce_reduce_ack_gen,
local_tr_en,
burst_tr,
WVALID)is
begin
if(burst_tr = '1') then
IP2Bus_WrAck_transmit_enable <= local_tr_en and WVALID; -- Bus2IP_WrCE_d1 and (not Tx_FIFO_Full); --local_tr_en;
else
IP2Bus_WrAck_transmit_enable <= local_tr_en and wr_ce_reduce_ack_gen;
end if;
end process TR_EN_P;
end generate TX_TR_EN_ENHAN_MD_GEN;
Data_To_TxFIFO <= Bus2IP_Data((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to(C_S_AXI_DATA_WIDTH-1));-- after 100 ps;
-- Transmit FIFO Logic
tx_fifo_reset <= reset2ip_reset_int or reset_TxFIFO_ptr_int;
TX_FIFO_II: entity proc_common_v4_0.async_fifo_fg -- entity axi_quad_spi_v3_1.async_fifo_fg -- proc_common_v4_0.async_fifo_fg
generic map
(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map
(
-- writing will be through AXI clock
Wr_clk => Bus2IP_Clk , -- : in std_logic := '1';
Din => Data_To_TxFIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => IP2Bus_WrAck_transmit_enable, -- : in std_logic := '1';
Wr_ack => Tx_FIFO_wr_ack , -- : out std_logic;
------
-- reading will be through SPI clock
Rd_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Dout => Data_From_TxFIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => SPIXfer_done_rd_tx_en , -- : in std_logic := '0';
Rd_ack => Tx_FIFO_rd_ack_open , -- : out std_logic;
------
Full => Tx_FIFO_Full , -- : out std_logic;
Empty => Tx_FIFO_Empty , -- : out std_logic;
Almost_full => Tx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Tx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => reset_TxFIFO_ptr_int ,--Tx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => Tx_FIFO_occ_Reversed , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
--tx_occ_msb <= tx_fifo_count(TX_FIFO_CNTR_WIDTH-1); -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
--tx_occ_msb_1 <= (tx_fifo_count(TX_FIFO_CNTR_WIDTH-1));-- and not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-2 downto 0))) ;--
--and not Tx_FIFO_Empty_SPISR_to_axi_clk;-- and not Tx_FIFO_Full_int; -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
tx_occ_msb_11 <= (tx_fifo_count);
FIFO_16_OCC_MSB_GEN: if C_FIFO_DEPTH = 16 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(3);
end generate FIFO_16_OCC_MSB_GEN;
FIFO_256_OCC_MSB_GEN: if C_FIFO_DEPTH = 256 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(7);
end generate FIFO_256_OCC_MSB_GEN;
TX_OCC_MSB_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_occ_msb_2 <= '0';
tx_occ_msb_3 <= '0';
tx_occ_msb_4 <= '0';
else
tx_occ_msb_2 <= tx_occ_msb_1;
tx_occ_msb_3 <= tx_occ_msb_2;
tx_occ_msb_4 <= tx_occ_msb_3;
end if;
end if;
end process TX_OCC_MSB_P;
tx_occ_msb <= tx_occ_msb_4 and not Tx_FIFO_Empty_SPISR_to_axi_clk;
data_Exists_TxFIFO_int <= not (Tx_FIFO_Empty);
-----------------------------------------------------------
TX_FIFO_EMPTY_CNTR_I : entity proc_common_v4_0.counter_f
generic map(
C_NUM_BITS => TX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en, -- in
----------------
Count_Load => reset_TxFIFO_ptr_int, -- in
----------------
Count_Down => spiXfer_done_to_axi_1, -- in
Count_Out => tx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en <= IP2Bus_WrAck_transmit_enable or spiXfer_done_to_axi_1;
----------------------------------------
TX_FULL_EMP_INTR_MD_12_GEN: if C_SPI_MODE /=0 generate
-----
begin
-----
Tx_FIFO_Empty_intr <= not (or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk); -- and ( Tx_FIFO_Empty);
Tx_FIFO_Full_int <= Tx_FIFO_Full;
end generate TX_FULL_EMP_INTR_MD_12_GEN;
----------------------------------------
----------------------------------------
TX_FULL_EMP_INTR_MD_0_GEN: if C_SPI_MODE =0 generate
-----
begin
-----
-- Tx_FIFO_one_less_to_Empty <= not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- --and (tx_fifo_count(0))
-- and spiXfer_done_to_axi_1;--tx_cntr_xfer_done_to_axi_1_clk; --
-- --------------------------------------------
-- TX_FIFO_ABT_TO_EMPTY_P:process(Bus2IP_Clk)is
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_Empty_int = '1')then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_one_less_to_Empty = '1') or then
-- Tx_FIFO_Empty_i <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_ABT_TO_EMPTY_P;
-- --------------------------------------
-- TX_FIFO_EMPTY_P: process(Bus2IP_Clk)is
-- begin
-- -----
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_int = '1' and spiXfer_done_to_axi_1 = '1')then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_i = '1')then
-- Tx_FIFO_Empty_int <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_EMPTY_P;
--------------------------------
-- Tx_FIFO_Empty_intr <= Tx_FIFO_Empty_int and spiXfer_done_to_axi_1;
--------------------------------
TX_FIFO_CNTR_DELAY_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_fifo_count_d1 <= (others => '0');
tx_fifo_count_d2 <= (others => '0');
spiXfer_done_to_axi_d1 <= '0';
else
tx_fifo_count_d1 <= tx_fifo_count;
tx_fifo_count_d2 <= tx_fifo_count_d1;
spiXfer_done_to_axi_d1 <= spiXfer_done_to_axi_1;
end if;
end if;
end process TX_FIFO_CNTR_DELAY_P;
Tx_FIFO_Empty_intr <= (not (or_reduce(tx_fifo_count_d2(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_d1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk));
TX_one_less_than_full <= and_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto TX_FIFO_CNTR_WIDTH-TX_FIFO_CNTR_WIDTH+1)) and
(not tx_fifo_count(0))and IP2Bus_WrAck_transmit_enable;
-------------------------------------------
TX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_i <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(Tx_FIFO_Full_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(TX_one_less_than_full = '1')then
Tx_FIFO_Full_i <= '1';
end if;
end if;
end process TX_FIFO_ABT_TO_FULL_P;
----------------------------------
TX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_int <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_int = '1' and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_i = '1') then -- and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '1';
end if;
end if;
end process TX_FIFO_FULL_P;
---------------------------
end generate TX_FULL_EMP_INTR_MD_0_GEN;
----------------------------------------
-------------------------------------------------------------------------------
-- I_FIFO_IF_MODULE : INSTANTIATE FIFO INTERFACE MODULE
-------------------------------------------------------------------------------
FIFO_IF_MODULE_I: entity axi_quad_spi_v3_1.qspi_fifo_ifmodule
generic map
(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int, -- in
-- Slave attachment ports from AXI clock
Bus2IP_RcFIFO_RdCE => Bus2IP_RdCE(SPIDRR),-- axiclk -- in
Bus2IP_TxFIFO_WrCE => Bus2IP_WrCE(SPIDTR),-- axi clk -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen,-- axi clk -- in
-- FIFO ports
Data_From_TxFIFO => Data_From_TxFIFO ,-- spi clk -- in vec
Data_From_Rc_FIFO => Data_From_Rx_FIFO ,-- axi clk -- in vec
Tx_FIFO_Data_WithZero => transmit_Data_int ,-- spi clk -- out vec
IP2Bus_RX_FIFO_Data => IP2Bus_Receive_Reg_Data_int, -- out vec
---------------------
Rc_FIFO_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full_strobe => rc_FIFO_Full_strobe_int, -- out
---------------------
Tx_FIFO_Empty => Tx_FIFO_Empty_intr , -- Tx_FIFO_Empty_to_Axi_clk, -- sr_5_Tx_Empty_int,-- spi clk -- in
Tx_FIFO_Empty_strobe => tx_FIFO_Empty_strobe_int, -- out
---------------------
Rc_FIFO_Empty => Rx_FIFO_Empty_int, -- 13-09-2012 rx_fifo_empty_i, -- Rx_FIFO_Empty , -- Rc_FIFO_Empty_int, -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
Tx_FIFO_Full => Tx_FIFO_Full_int, -- in
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
---------------------
Tx_FIFO_Occpncy_MSB => tx_occ_msb, -- in
Tx_FIFO_less_half => tx_FIFO_less_half_int, -- out
---------------------
DTR_underrun => dtr_underrun_to_axi_clk,-- dtr_underrun_int,-- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
---------------------
SPIXfer_done => spiXfer_done_to_axi_1, -- spiXfer_done_int, -- in
rready => rready
-- DRR_Overrun_reg => drr_Overrun_int -- out
);
-------------------------------------------------------------------------------
-- TX_OCCUPANCY_I : INSTANTIATE TRANSMIT OCCUPANCY REGISTER
-------------------------------------------------------------------------------
TX_OCCUPANCY_I: entity axi_quad_spi_v3_1.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPITFOR), -- in
--FIFO port
IP2Reg_OCC_Data => tx_fifo_count, -- tx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Tx_FIFO_OCC_Reg_Data_int -- out vec
);
-------------------------------------------------------------------------------
-- RX_OCCUPANCY_I : INSTANTIATE RECEIVE OCCUPANCY REGISTER
-------------------------------------------------------------------------------
RX_OCCUPANCY_I: entity axi_quad_spi_v3_1.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS--,
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPIRFOR), -- in
--FIFO port
IP2Reg_OCC_Data => rx_fifo_count, --rx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Rx_FIFO_OCC_Reg_Data_int -- out vec
);
end generate FIFO_EXISTS;
--------------------------------------------
-- LOGIC_FOR_MD_0_GEN: in stantiate the original SPI module when the core is configured in Standard SPI mode.
------------------------------
LOGIC_FOR_MD_0_GEN: if C_SPI_MODE = 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
-----
begin
-----
-- un used IO2 and IO3 O/P ports are tied to 0 and T ports are tied to '1'
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SPISR_0_CMD_Error_int <= '0'; -- no command error when C_SPI_MODE= 0
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_1.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => Rst_to_spi_int
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
----------------------------------------------------------------------------
-- SPI_MODULE_I : INSTANTIATE SPI MODULE
----------------------------------------------------------------------------
SPI_MODULE_I: entity axi_quad_spi_v3_1.qspi_mode_0_module
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_FIFO_EXIST => C_FIFO_EXIST
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK, -- in
Soft_Reset_op => Rst_to_spi_int, -- in
------------------------
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk,--_int,
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk,--_int,
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int,
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk,--_int,
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk,--_int,
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_to_spi_clk, -- SPICR_5_TXFIFO_RST_to_spi_clk,--_int,
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int,
SPICR_7_SS => SPICR_7_SS_to_spi_clk,--_int,
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int,
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk,--_int,
------------------------
SR_3_MODF => SR_3_modf_to_spi_clk, -- in
SR_5_Tx_Empty => Tx_FIFO_Empty, -- sr_5_Tx_Empty_int, -- in
Slave_MODF_strobe => slave_MODF_strobe_int, -- out
MODF_strobe => modf_strobe_int, -- out
Slave_Select_Reg => register_Data_slvsel_int, -- already updated -- in vec
Transmit_Data => Data_From_TxFIFO, -- transmit_Data_int, -- in vec
Receive_Data => Data_To_Rx_FIFO, -- receive_Data_int, -- out vec
SPIXfer_done => spiXfer_done_int, -- out
-- SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
DTR_underrun => dtr_underrun_int, -- out
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--SPI Ports
SCK_I => SCK_I, -- in
SCK_O_reg => SCK_O_int, -- out
SCK_T => SCK_T, -- out
MISO_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in
MISO_O => IO1_O, -- MISO_O, -- out
MISO_T => IO1_T, -- MISO_T, -- out
MOSI_I => IO0_I, -- MOSI_I, -- in
MOSI_O => IO0_O, -- MOSI_O, -- out
MOSI_T => IO0_T, -- MOSI_T, -- out
SPISEL => SPISEL, -- in
SS_I => SS_I, -- in
SS_O => SS_O, -- out
SS_T => SS_T, -- out
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
control_bit_7_8 => SPICR_bits_7_8_to_spi_clk, -- in vec
Mst_N_Slv_mode => Mst_N_Slv_mode ,
Rx_FIFO_Full => Rx_FIFO_Full,
DRR_Overrun_reg => drr_Overrun_int, -- out
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk,
tx_cntr_xfer_done => tx_cntr_xfer_done
);
-------------
end generate LOGIC_FOR_MD_0_GEN;
----------------------------------------
-- LOGIC_FOR_MD_12_GEN: to generate the functionality for mode 1 and 2.
------------------------------
LOGIC_FOR_MD_12_GEN: if C_SPI_MODE /= 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
signal Data_Dir_int : std_logic;
signal Data_Mode_1_int : std_logic;
signal Data_Mode_0_int : std_logic;
signal Data_Phase_int : std_logic;
signal Addr_Mode_1_int : std_logic;
signal Addr_Mode_0_int : std_logic;
signal Addr_Bit_int : std_logic;
signal Addr_Phase_int : std_logic;
signal CMD_Mode_1_int : std_logic;
signal CMD_Mode_0_int : std_logic;
signal CMD_Error_int : std_logic;
signal CMD_decoded_int : std_logic;
signal Dummy_Bits_int : std_logic_vector(3 downto 0);
signal IO2_O_int : std_logic;
signal IO2_T_int : std_logic;
signal IO3_O_int : std_logic;
signal IO3_T_int : std_logic;
signal IO2_I_int : std_logic;
signal IO3_I_int : std_logic;
-----
begin
-----
LOGIC_FOR_C_SPI_MODE_1_GEN: if C_SPI_MODE = 1 generate
-------
begin
-------
IO2_O <= '0'; -- not used in the logic
IO3_O <= '0'; -- not used in the logic
IO2_T <= '1'; -- disable the tri-state buffers
IO3_T <= '1'; -- disable the tri-state buffers
IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
end generate LOGIC_FOR_C_SPI_MODE_1_GEN;
---------------------------------------
LOGIC_FOR_C_SPI_MODE_2_GEN: if C_SPI_MODE = 2 generate
-------
begin
-------
IO2_I_int <= IO2_I; -- assign this bit from the top level port
IO2_O <= IO2_O_int;
IO2_T <= IO2_T_int;
IO3_I_int <= IO3_I; -- assign this bit from the top level port
IO3_O <= IO3_O_int;
IO3_T <= IO3_T_int;
end generate LOGIC_FOR_C_SPI_MODE_2_GEN;
---------------------------------------
SPISR_0_CMD_Error_int <= CMD_Error_int;
dtr_underrun_int <= '0'; -- SPI MODE 1 & 2 are master modes, so DTR under run wont be present
slave_MODF_strobe_int <= '0'; -- SPI MODE 1 & 2 are master modes, so the slave mode fault error wont appear
Mst_N_Slv_mode <= '1';
-------------------------------------------------------
-- SCK_O <= SCK_O_int; -- output from the core
-- MISO_I_int <= IO1_I; -- input to the core
-- *
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_1.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => Rst_to_spi_int
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
-- *
-- Add instance for Look up table logic
SPI_MODE_1_LUT_LOGIC_I: entity axi_quad_spi_v3_1.qspi_look_up_logic
-------------
generic map
(
C_FAMILY => C_FAMILY ,
C_SPI_MODE => C_SPI_MODE ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int , -- : in std_logic;
TXFIFO_RST => reset_TxFIFO_ptr_int, -- : in std_logic;
-------------------- --
DTR_FIFO_Data_Exists=> data_Exists_TxFIFO_int, -- : in std_logic;
Data_From_TxFIFO => Data_From_TxFIFO , -- : in std_logic_vector
-- (0 to (C_NUM_TRANSFER_BITS-1))
pr_state_idle => pr_state_idle_int , --
-------------------- --
Data_Dir => Data_Dir_int , -- : out std_logic;
Data_Mode_1 => Data_Mode_1_int , -- : out std_logic;
Data_Mode_0 => Data_Mode_0_int , -- : out std_logic;
Data_Phase => Data_Phase_int , -- : out std_logic;
-------------------- --
Quad_Phase => Quad_Phase_int ,
-------------------- --
Addr_Mode_1 => Addr_Mode_1_int , -- : out std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- : out std_logic;
Addr_Bit => Addr_Bit_int , -- : out std_logic;
Addr_Phase => Addr_Phase_int , -- : out std_logic;
-------------------- --
CMD_Mode_1 => CMD_Mode_1_int , -- : out std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- : out std_logic;
CMD_Error => CMD_Error_int , -- : out std_logic;
-------------------- -- -
CMD_decoded => CMD_decoded_int -- : out std_logic
);
---------
SPI_MODE_CONTROL_LOGIC_I: entity axi_quad_spi_v3_1.qspi_mode_control_logic
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SUB_FAMILY => C_SUB_FAMILY
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK , -- Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => Rst_to_spi_int , -- in std_logic;
-------------------- , --
DTR_FIFO_Data_Exists => data_Exists_TxFIFO_int , -- in std_logic;
Slave_Select_Reg => register_Data_slvsel_int , -- already updated -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data => Data_From_TxFIFO,--transmit_Data_int , -- already updated -- in std_logic_vector(0 to (C_NUM_TRANSFER_BITS
Receive_Data => Data_To_Rx_FIFO , -- out std_logic_vector(0 to (C_NUM_TRANSFER_BITS
--Data_To_Rx_FIFO_1 => Data_To_Rx_FIFO_1,
SPIXfer_done => spiXfer_done_int , -- already updated -- out std_logic;
SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
MODF_strobe => modf_strobe_int , -- already updated
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--------------------- --
SR_3_MODF => SR_3_modf_to_spi_clk , -- in std_logic;
SR_5_Tx_Empty => Tx_FIFO_Empty , -- sr_5_Tx_Empty_int -- in std_logic;
--SR_6_Rx_Full => Rx_FIFO_Full , -- in
pr_state_idle => pr_state_idle_int , --
--------------------- -- from control register
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk ,--SPICR_0_LOOP_int , -- in std_logic;
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk ,--_int , -- in std_logic;
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int , -- in std_logic;
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk ,--_int , -- in std_logic;
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk ,--_int , -- in std_logic;
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_7_SS => SPICR_7_SS_to_spi_clk ,--_int , -- in std_logic;
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int , -- in std_logic;
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk ,--_int , -- in std_logic;
--------------------- --
--------------------- -- from look up table
Data_Dir => Data_Dir_int , -- in std_logic;
Data_Mode_1 => Data_Mode_1_int , -- in std_logic;
Data_Mode_0 => Data_Mode_0_int , -- in std_logic;
Data_Phase => Data_Phase_int ,
---------------------
--Dummy_Bits => Dummy_Bits_int , -- in std_logic_vector(3 downto 0);
Quad_Phase => Quad_Phase_int ,
--------------------- -- in std_logic;
Addr_Mode_1 => Addr_Mode_1_int , -- in std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- in std_logic;
Addr_Bit => Addr_Bit_int , -- in std_logic;
Addr_Phase => Addr_Phase_int , -- in std_logic;
---------------------
CMD_Mode_1 => CMD_Mode_1_int , -- in std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- in std_logic;
CMD_Error => CMD_Error_int , -- in std_logic;
--------------------- --
CMD_decoded => CMD_decoded_int , -- in std_logic;
--SPI Interface --
SCK_I => SCK_I, -- in std_logic;
SCK_O_reg => SCK_O_int, -- out std_logic;
SCK_T => SCK_T, -- out std_logic;
--
IO0_I => IO0_I, -- MOSI_I, -- in std_logic; -- MISO
IO0_O => IO0_O, -- MOSI_O, -- out std_logic;
IO0_T => IO0_T, -- MOSI_T, -- out std_logic;
IO1_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
IO1_O => IO1_O, -- MISO_O, -- out std_logic; -- MOSI
IO1_T => IO1_T, -- MISO_T, -- out std_logic;
--
IO2_I => IO2_I_int, -- -- in std_logic;
IO2_O => IO2_O_int, -- -- out std_logic;
IO2_T => IO2_T_int, -- -- out std_logic;
--
IO3_I => IO3_I_int, -- -- in std_logic;
IO3_O => IO3_O_int, -- -- out std_logic;
IO3_T => IO3_T_int, -- -- out std_logic;
--
SPISEL => SPISEL, -- in std_logic;
--
SS_I => SS_I, -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_O => SS_O, -- out std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_T => SS_T, -- out std_logic;
--
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
Control_bit_7_8 => SPICR_bits_7_8_to_spi_clk , -- in std_logic_vector(0 to 1) --(7 to 8)
Rx_FIFO_Full => Rx_FIFO_Full,
DRR_Overrun_reg => drr_Overrun_int,
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk
);
-------------
end generate LOGIC_FOR_MD_12_GEN;
------------------------------------------
--------------------------------------------------------------------------------
CONTROL_REG_I: entity axi_quad_spi_v3_1.qspi_cntrl_reg
generic map
(
--------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
--------------------------
-- Number of bits in regis
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
--------------------------
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH,
--------------------------
C_SPI_MODE => C_SPI_MODE
--------------------------
)
port map
( -- in
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int,
---------------------------
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen, -- in
Bus2IP_SPICR_WrCE => Bus2IP_WrCE(SPICR), -- in
Bus2IP_SPICR_RdCE => Bus2IP_RdCE(SPICR), -- in
Bus2IP_SPICR_data => Bus2IP_Data, -- in vec
---------------------------
SPICR_0_LOOP => SPICR_0_LOOP_frm_axi_clk, -- out
SPICR_1_SPE => SPICR_1_SPE_frm_axi_clk, -- out
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_frm_axi_clk, -- out
SPICR_3_CPOL => SPICR_3_CPOL_frm_axi_clk, -- out
SPICR_4_CPHA => SPICR_4_CPHA_frm_axi_clk, -- out
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_frm_axi_clk, -- out
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_frm_axi_clk, -- out
SPICR_7_SS => SPICR_7_SS_frm_axi_clk, -- out
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_frm_axi_clk, -- out
SPICR_9_LSB => SPICR_9_LSB_frm_axi_clk, -- out
-- to Status Register
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int, -- out
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int, -- out
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int, -- out
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int, -- out
---------------------------
IP2Bus_SPICR_Data => IP2Bus_SPICR_Data_int, -- out vec
---------------------------
Control_bit_7_8 => SPICR_bits_7_8_frm_axi_clk -- out vec
---------------------------
);
-------------------------------------------------------------------------------
-- STATUS_REG_I : INSTANTIATE STATUS REGISTER
-------------------------------------------------------------------------------
STATUS_REG_MODE_0_GEN: if C_SPI_MODE = 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_1.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => '0' , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_0_GEN;
STATUS_REG_MODE_12_GEN: if C_SPI_MODE /= 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_1.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => SPISR_0_CMD_Error_to_axi_clk , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_12_GEN;
-------------------------------------------------------------------------------
-- SOFT_RESET_I : INSTANTIATE SOFT RESET
-------------------------------------------------------------------------------
SOFT_RESET_I: entity proc_common_v4_0.soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the PLBv46 Slave Single Bus
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => Bus2IP_Reset, -- in
Bus2IP_WrCE => Bus2IP_WrCE(SWRESET), -- in
Bus2IP_Data => Bus2IP_Data, -- in
Bus2IP_BE => Bus2IP_BE, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset_int, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
-------------------------------------------------------------------------------
-- INTERRUPT_CONTROL_I : INSTANTIATE INTERRUPT CONTROLLER
-------------------------------------------------------------------------------
bus2ip_intr_rdce <= "0000000" &
Bus2IP_RdCE(7) &
Bus2IP_RdCE(8) &
'0' &
Bus2IP_RdCE(10)&
"00000";
bus2ip_intr_wrce <= "0000000" &
Bus2IP_WrCE(7) &
Bus2IP_WrCE(8) &
'0' &
Bus2IP_WrCE(10)&
"00000";
------------------------------------------------------------------------------
intr_controller_rd_ce_or_reduce <= or_reduce(Bus2IP_RdCE(0 to 6)) or
Bus2IP_RdCE(9) or
or_reduce(Bus2IP_RdCE(11 to 15));
------------------------------------------------------------------------------
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_controller_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_controller_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
------------------------------------------------------------------------------
intr_controller_wr_ce_or_reduce <= or_reduce(Bus2IP_WrCE(0 to 6)) or
Bus2IP_WrCE(9) or
or_reduce(Bus2IP_WrCE(11 to 15));
------------------------------------------------------------------------------
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_controller_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_controller_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
------------------------------------------------------------------------------
INTERRUPT_CONTROL_I: entity interrupt_control_v3_0.interrupt_control
generic map
(
C_NUM_CE => 16,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => false,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => reset2ip_reset_int, -- in
Bus2IP_Data => bus2IP_Data_for_interrupt_core, -- in vec
Bus2IP_BE => Bus2IP_BE, -- in vec
Interrupt_RdCE => bus2ip_intr_rdce, -- in vec
Interrupt_WrCE => bus2ip_intr_wrce, -- in vec
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intrs
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => ip2Bus_IntrEvent_int, -- in
Intr2Bus_DevIntr => IP2INTC_Irpt, -- out
Intr2Bus_DBus => intr_ip2bus_data, -- out vec
Intr2Bus_WrAck => intr_ip2bus_wrack, -- out
Intr2Bus_RdAck => intr_ip2bus_rdack, -- out
Intr2Bus_Error => intr_ip2bus_error, -- out
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
--------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
library IEEE;
use IEEE.Std_Logic_1164.all;
--Multiplexador 2x1 10bits
entity mux2x1_10 is
port (IN0,IN1: in std_logic_vector(9 downto 0);
REG: out std_logic_vector(9 downto 0);
SW: in std_logic
);
end mux2x1_10;
--Definicao Arquitetura
architecture circuito of mux2x1_10 is
begin
REG <= IN0 when SW = '0' else
IN1;
end circuito; |
--
-- SRAM controller for Papilio Duo
--
-- based on 'FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version' by Pong P. Chu
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sram is port (
-- interface
clk : in std_logic;
mem : in std_logic;
rw : in std_logic; -- read '1' / write '0'
ready : out std_logic;
addr : in std_logic_vector(20 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
-- SRAM interface
SRAM_ADDR : out std_logic_vector (20 downto 0);
SRAM_DATA : inout std_logic_vector (7 downto 0);
SRAM_CE : out std_logic;
SRAM_WE : out std_logic;
SRAM_OE : out std_logic);
end sram;
architecture Behavioral of sram is
type state_t is (idle, read1, read2, write1, write2);
signal state : state_t := idle;
begin
SRAM_CE <= '0'; -- sram always enabled
--SRAM_OE <= '1';
process(clk) begin
if rising_edge(clk) then
case state is
when idle =>
ready <= '1';
SRAM_DATA <= "ZZZZZZZZ";
SRAM_WE <= '1';
SRAM_OE <= '1';
if mem = '1' then
SRAM_ADDR <= addr;
if rw = '1' then
state <= read1;
else
state <= write1;
SRAM_DATA <= din;
end if;
end if;
when read1 =>
ready <= '0';
SRAM_OE <= '0';
state <= read2;
when read2 =>
SRAM_OE <= '0';
dout <= SRAM_DATA;
state <= idle;
when write1 =>
ready <= '0';
SRAM_WE <= '0';
state <= write2;
when write2 =>
SRAM_DATA <= din;
state <= idle;
end case;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity and_or_top_Testbench is
end and_or_top_Testbench;
architecture behavior of and_or_top_Testbench is
component ALU_Ctrl_top is
Port (
Op5 : in STD_LOGIC;
Op4 : in STD_LOGIC;
Op3 : in STD_LOGIC;
Op2 : in STD_LOGIC;
Op1 : in STD_LOGIC;
Op0 : in STD_LOGIC;
RegDst : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
Branch : out STD_LOGIC;
ALUOp1 : out STD_LOGIC;
ALUOp0 : out STD_LOGIC
);
end component;
signal Op5: std_logic := '0';
signal Op4: std_logic := '0';
signal Op3: std_logic := '0';
signal Op2: std_logic := '0';
signal Op1: std_logic := '0';
signal Op0: std_logic := '0';
signal RegDst : STD_LOGIC;
signal ALUSrc : STD_LOGIC;
signal MemtoReg : STD_LOGIC;
signal RegWrite : STD_LOGIC;
signal MemRead : STD_LOGIC;
signal MemWrite : STD_LOGIC;
signal Branch : STD_LOGIC;
signal ALUOp1 : STD_LOGIC;
signal ALUOp0 : STD_LOGIC;
begin
-- Component Instantiation
UUT : ALU_Ctrl_top port map(Op5 => Op5,
Op4 => Op4,
Op3 => Op3,
Op2 => Op2,
Op1 => Op1,
Op0 => Op0,
RegDst => RegDst,
ALUSrc => ALUSrc,
MemtoReg => MemtoReg,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
Branch => Branch,
ALUOp1 => ALUOp1,
ALUOp0 => ALUOp0);
-- Cycle through test vectors and evaluate the results
-- the four cases in the Truth Table
process
begin
Op5 <= '0';
Op4 <= '0';
Op3 <= '0';
Op2 <= '0';
Op1 <= '0';
Op0 <= '0';
wait for 10 ns;
Op5 <= '1';
Op4 <= '0';
Op3 <= '0';
Op2 <= '0';
Op1 <= '1';
Op0 <= '1';
wait for 10 ns;
Op5 <= '1';
Op4 <= '0';
Op3 <= '1';
Op2 <= '0';
Op1 <= '1';
Op0 <= '1';
wait for 10 ns;
Op5 <= '0';
Op4 <= '0';
Op3 <= '0';
Op2 <= '1';
Op1 <= '0';
Op0 <= '0';
wait for 10 ns;
wait;
end process;
END;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package stimulus_types is
constant stimulus_vector_length : positive := 4;
type stimulus_element is record
application_time : delay_length;
pattern : real_vector(0 to stimulus_vector_length - 1);
end record stimulus_element;
function stimulus_key ( stimulus : stimulus_element ) return delay_length;
end package stimulus_types;
----------------------------------------------------------------
package body stimulus_types is
function stimulus_key ( stimulus : stimulus_element ) return delay_length is
begin
return stimulus.application_time;
end function stimulus_key;
end package body stimulus_types;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package stimulus_types is
constant stimulus_vector_length : positive := 4;
type stimulus_element is record
application_time : delay_length;
pattern : real_vector(0 to stimulus_vector_length - 1);
end record stimulus_element;
function stimulus_key ( stimulus : stimulus_element ) return delay_length;
end package stimulus_types;
----------------------------------------------------------------
package body stimulus_types is
function stimulus_key ( stimulus : stimulus_element ) return delay_length is
begin
return stimulus.application_time;
end function stimulus_key;
end package body stimulus_types;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package stimulus_types is
constant stimulus_vector_length : positive := 4;
type stimulus_element is record
application_time : delay_length;
pattern : real_vector(0 to stimulus_vector_length - 1);
end record stimulus_element;
function stimulus_key ( stimulus : stimulus_element ) return delay_length;
end package stimulus_types;
----------------------------------------------------------------
package body stimulus_types is
function stimulus_key ( stimulus : stimulus_element ) return delay_length is
begin
return stimulus.application_time;
end function stimulus_key;
end package body stimulus_types;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:25:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_rgb888_mux_2_0_0 -prefix
-- system_rgb888_mux_2_0_0_ system_rgb888_mux_2_0_0_stub.vhdl
-- Design : system_rgb888_mux_2_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb888_mux_2_0_0 is
Port (
clk : in STD_LOGIC;
sel : in STD_LOGIC;
rgb888_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb888_mux_2_0_0;
architecture stub of system_rgb888_mux_2_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,sel,rgb888_0[23:0],rgb888_1[23:0],rgb888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb888_mux_2,Vivado 2016.4";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ClkDividerN is
generic(divFactor : natural);
port(clkIn : in std_logic;
clkOut : out std_logic);
end ClkDividerN;
architecture RTL of ClkDividerN is
signal s_divCounter : natural;
begin
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter = divFactor - 1) then
clkOut <= '0';
s_divCounter <= 0;
else
if (s_divCounter = (divFactor / 2 - 1)) then
clkOut <= '1';
end if;
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ClkDividerN is
generic(divFactor : natural);
port(clkIn : in std_logic;
clkOut : out std_logic);
end ClkDividerN;
architecture RTL of ClkDividerN is
signal s_divCounter : natural;
begin
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter = divFactor - 1) then
clkOut <= '0';
s_divCounter <= 0;
else
if (s_divCounter = (divFactor / 2 - 1)) then
clkOut <= '1';
end if;
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ClkDividerN is
generic(divFactor : natural);
port(clkIn : in std_logic;
clkOut : out std_logic);
end ClkDividerN;
architecture RTL of ClkDividerN is
signal s_divCounter : natural;
begin
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter = divFactor - 1) then
clkOut <= '0';
s_divCounter <= 0;
else
if (s_divCounter = (divFactor / 2 - 1)) then
clkOut <= '1';
end if;
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
end RTL;
|
entity FIFO is
end entity;
entity FIFO is
end entity;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-- $Id: fx2_2fifo_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifo_core - sim
-- Description: Cypress EZ-USB FX2 (2 fifo core model)
--
-- Dependencies: memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.0.1 proc_ifclk: remove clock stop (not needed anymore)
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
use work.fx2lib.all;
use work.memlib.all;
entity fx2_2fifo_core is -- EZ-USB FX2 (2 fifo core model)
port (
CLK : in slbit; -- uplink clock
RESET : in slbit; -- reset
RXDATA : in slv8; -- rx data (ext->fx2)
RXENA : in slbit; -- rx enable
RXBUSY : out slbit; -- rx busy
TXDATA : out slv8; -- tx data (fx2->ext)
TXVAL : out slbit; -- tx valid
IFCLK : out slbit; -- fx2 interface clock
FIFO : in slv2; -- fx2 fifo address
FLAG : out slv4; -- fx2 fifo flags
SLRD_N : in slbit; -- fx2 read enable (act.low)
SLWR_N : in slbit; -- fx2 write enable (act.low)
SLOE_N : in slbit; -- fx2 output enable (act.low)
PKTEND_N : in slbit; -- fx2 packet end (act.low)
DATA : inout slv8 -- fx2 data lines
);
end fx2_2fifo_core;
architecture sim of fx2_2fifo_core is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
constant bufsize : positive := 1024;
constant datzero : slv(DATA'range) := (others=>'0');
type buf_type is array (0 to bufsize-1) of slv(DATA'range);
signal CLK30 : slbit := '0';
signal RXFIFO_DO : slv8 := (others=>'0');
signal RXFIFO_VAL : slbit := '0';
signal RXFIFO_HOLD : slbit := '0';
signal TXFIFO_DI : slv8 := (others=>'0');
signal TXFIFO_ENA : slbit := '0';
signal TXFIFO_BUSY : slbit := '0';
signal R_FLAG : slv4 := (others=>'0');
signal R_DATA : slv8 := (others=>'0');
-- added for debug purposes
signal R_rxbuf_rind : natural := 0;
signal R_rxbuf_wind : natural := 0;
signal R_rxbuf_nbyt : natural := 0;
signal R_txbuf_rind : natural := 0;
signal R_txbuf_wind : natural := 0;
signal R_txbuf_nbyt : natural := 0;
begin
RXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => CLK30,
RESETW => '0',
RESETR => '0',
DI => RXDATA,
ENA => RXENA,
BUSY => RXBUSY,
DO => RXFIFO_DO,
VAL => RXFIFO_VAL,
HOLD => RXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
TXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK30,
CLKR => CLK,
RESETW => '0',
RESETR => '0',
DI => TXFIFO_DI,
ENA => TXFIFO_ENA,
BUSY => TXFIFO_BUSY,
DO => TXDATA,
VAL => TXVAL,
HOLD => '0',
SIZEW => open,
SIZER => open
);
proc_ifclk: process
constant offset : Delay_length := 200 ns;
constant halfperiod_7 : Delay_length := 16700 ps;
constant halfperiod_6 : Delay_length := 16600 ps;
begin
CLK30 <= '0';
wait for offset;
loop
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_6;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_6;
end loop;
end process proc_ifclk;
proc_state: process (CLK30)
variable rxbuf : buf_type := (others=>datzero);
variable rxbuf_rind : natural := 0;
variable rxbuf_wind : natural := 0;
variable rxbuf_nbyt : natural := 0;
variable txbuf : buf_type := (others=>datzero);
variable txbuf_rind : natural := 0;
variable txbuf_wind : natural := 0;
variable txbuf_nbyt : natural := 0;
variable oline : line;
begin
if rising_edge(CLK30) then
RXFIFO_HOLD <= '0';
TXFIFO_ENA <= '0';
-- rxfifo -> rxbuf
if RXFIFO_VAL = '1' then
if rxbuf_nbyt < bufsize then
rxbuf(rxbuf_wind) := RXFIFO_DO;
rxbuf_wind := (rxbuf_wind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt + 1;
else
RXFIFO_HOLD <= '1';
end if;
end if;
-- txbuf -> txfifo
if txbuf_nbyt>0 and TXFIFO_BUSY='0' then
TXFIFO_DI <= txbuf(txbuf_rind);
TXFIFO_ENA <= '1';
txbuf_rind := (txbuf_rind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt - 1;
end if;
-- slrd cycle: rxbuf -> data
if SLRD_N = '0' then
if rxbuf_nbyt > 0 then
rxbuf_rind := (rxbuf_rind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt - 1;
else
write(oline, string'("fx2_2fifo_core: SLRD_N=0 when rxbuf empty"));
writeline(output, oline);
end if;
end if;
R_DATA <= rxbuf(rxbuf_rind);
-- slwr cycle: data -> txbuf
if SLWR_N = '0' then
if txbuf_nbyt < bufsize then
txbuf(txbuf_wind) := DATA;
txbuf_wind := (txbuf_wind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt + 1;
else
write(oline, string'("fx2_2fifo_core: SLWR_N=0 when txbuf full"));
writeline(output, oline);
end if;
end if;
-- prepare flags (note that FLAGs are act.low!)
R_FLAG <= (others=>'1');
-- FLAGA = indexed, PF
-- rx endpoint -> PF 'almost empty' at 3 bytes to go
if FIFO = c_rxfifo then
if rxbuf_nbyt < 4 then
R_FLAG(0) <= '0';
end if;
-- tx endpoint -> PF 'almost full' at 3 bytes to go
elsif FIFO = c_txfifo then
if txbuf_nbyt > bufsize-4 then
R_FLAG(0) <= '0';
end if;
end if;
-- FLAGB = EP6 FF
if txbuf_nbyt = bufsize then
R_FLAG(1) <= '0';
end if;
-- FLAGC = EP4 EF
if rxbuf_nbyt = 0 then
R_FLAG(2) <= '0';
end if;
-- FLAGD = EP8 FF
R_FLAG(3) <= '1';
-- added for debug purposes
R_rxbuf_rind <= rxbuf_rind;
R_rxbuf_wind <= rxbuf_wind;
R_rxbuf_nbyt <= rxbuf_nbyt;
R_txbuf_rind <= txbuf_rind;
R_txbuf_wind <= txbuf_wind;
R_txbuf_nbyt <= txbuf_nbyt;
end if;
end process proc_state;
IFCLK <= CLK30;
FLAG <= R_FLAG;
proc_data: process (SLOE_N, R_DATA)
begin
if SLOE_N = '1' then
DATA <= (others=>'Z');
else
DATA <= R_DATA;
end if;
end process proc_data;
end sim;
|
-- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
|
-- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
|
-- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
|
-- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
|
-- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
|
-- AHB status register
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 09:11:16 AM
-- Design Name:
-- Module Name: mmc_cmd_if - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.mmc_core_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mmc_cmd_if is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
mmc_cmd_i : in std_logic;
mmc_cmd_o : out std_logic;
send_cmd_trigger_i : in std_logic;
receive_cmd_trigger_i : in std_logic;
send_cmd_busy_o : out std_logic;
receive_cmd_busy_o : out std_logic;
crc7_calc_en_i : in std_logic;
response_i : in std_logic_vector (2 downto 0);
cmd_shift_outval_i : in std_logic_vector (47 downto 0);
cmd_shift_inval_o : out std_logic_vector (135 downto 0);
mmc_crc7_out_o : out std_logic_vector (6 downto 0)
);
end mmc_cmd_if;
architecture rtl of mmc_cmd_if is
component mmc_crc7 is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
enable : in std_logic;
serial_in : in std_logic;
crc7_out : out std_logic_vector (6 downto 0)
);
end component;
signal send_bit_counter : integer range 0 to 47 := 0;
signal receive_bit_counter : integer range 0 to 135 := 0;
signal cmd_shift_out : std_logic_vector (47 downto 0) := (others => '1');
signal cmd_shift_in : std_logic_vector (135 downto 0) := (others => '1');
signal send_cmd_busy : std_logic := '0';
signal receive_cmd_busy : std_logic := '0';
signal receive_wait_start : std_logic := '0';
signal send_cmd_crc : std_logic := '0';
signal receive_cmd_crc : std_logic := '0';
signal send_reset_crc : std_logic := '0';
signal receive_reset_crc : std_logic := '0';
signal reset_crc : std_logic;
signal crc7_en : std_logic := '0';
signal crc7_source : std_logic;
signal crc7_out : std_logic_vector (6 downto 0);
begin
cmd_shift_inval_o <= cmd_shift_in;
receive_cmd_busy_o <= receive_cmd_busy;
send_cmd_busy_o <= send_cmd_busy;
mmc_cmd_o <= cmd_shift_out (47);
mmc_crc7_out_o <= crc7_out;
--MMC CMD out
process
begin
wait until rising_edge(clk);
send_reset_crc <= '0';
if reset='1' then
send_bit_counter <= 0;
elsif clk_en='1' then
if send_cmd_trigger_i='1' and receive_cmd_busy='0' then
cmd_shift_out <= cmd_shift_outval_i;
send_bit_counter <= 47;
send_cmd_busy <= '1';
send_cmd_crc <= '1';
else
if send_bit_counter = 0 then
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
send_cmd_busy <= '0';
elsif send_bit_counter = 7 then
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
send_bit_counter <= send_bit_counter - 1;
send_reset_crc <= '1';
elsif send_bit_counter = 8 then
send_bit_counter <= send_bit_counter - 1;
send_cmd_crc <= '0';
if crc7_calc_en_i='1' then
cmd_shift_out (41 downto 0) <= (others => '1');
cmd_shift_out (47 downto 41) <= crc7_out;
else
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
end if;
else
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
send_bit_counter <= send_bit_counter - 1;
send_cmd_busy <= '1';
end if;
end if;
end if;
end process;
-- MMC CMD in
process
begin
wait until rising_edge(clk);
if reset='1' then
receive_cmd_busy <= '0';
receive_bit_counter <= 0;
receive_wait_start <= '0';
elsif clk_en='1' then
if receive_cmd_trigger_i='1' and send_cmd_busy='0' then
receive_cmd_busy <= '1';
receive_wait_start <= '1';
if response_i=RESP_R2 then
receive_bit_counter <= 135;
receive_cmd_crc <='0';
else
receive_bit_counter <= 47;
receive_cmd_crc <='1';
end if;
elsif receive_wait_start='1' then
if mmc_cmd_i='0' then
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
receive_wait_start <= '0';
receive_reset_crc <= '0';
else
receive_reset_crc <= '1';
end if;
elsif receive_bit_counter=128 then
receive_cmd_crc <='1';
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
elsif receive_bit_counter=8 then
receive_cmd_crc <='0';
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
elsif receive_bit_counter=0 then
if receive_cmd_busy='1' then
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
receive_cmd_busy <= '0';
end if;
else
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
end if;
end if;
end process;
crc7_source <= cmd_shift_out (47) when send_cmd_busy='1' else
mmc_cmd_i when receive_cmd_busy='1' else
'0';
crc7_en <= send_cmd_crc or receive_cmd_crc;
reset_crc <= send_reset_crc or receive_reset_crc;
u_mmc_crc7 : mmc_crc7
Port map (
clk => clk,
clk_en => clk_en,
reset => reset_crc,
enable => crc7_en,
serial_in => crc7_source,
crc7_out => crc7_out
);
end rtl;
|
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package msx_pack is
-- Actual version
constant actual_version : std_logic_vector(7 downto 0) := X"13";
type volumes_t is record
beep : std_logic_vector(7 downto 0);
ear : std_logic_vector(7 downto 0);
psg : std_logic_vector(7 downto 0);
scc : std_logic_vector(7 downto 0);
opll : std_logic_vector(7 downto 0);
aux1 : std_logic_vector(7 downto 0);
end record;
constant default_vol_beep : integer := 128;
constant default_vol_ear : integer := 20;
constant default_vol_psg : integer := 240;
constant default_vol_scc : integer := 255;
constant default_vol_opll : integer := 255;
constant default_vol_aux1 : integer := 255;
end package;
|
-- Listado del detector de flancos
--------------------------------------------------------
-- INSTANCE TEMPLATE
--------------------------------------------------------
--Edge_inst :entity work.edge_detect
-- port map (
-- c => MCLK,
-- level => , --in
-- tick => --out
-- );
library ieee;
use ieee.std_logic_1164.all;
entity edge_detect is
generic (N: NATURAL := 3 );
port(
c : in std_logic;
level : in std_logic;
tick : out std_logic
);
end edge_detect;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- NO MODIFICAR ---------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture BlackBox of edge_detect is
signal Mshreg_sync_1_0 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal sync : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
sync_0 : FD
port map (
C => c,
D => sync(1),
Q => sync(0)
);
tick1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sync(1),
I1 => sync(0),
O => tick
);
XST_GND : GND
port map (
G => N0
);
Mshreg_sync_1 : SRL16
generic map(
INIT => X"0000"
)
port map (
A0 => N0,
A1 => N0,
A2 => N0,
A3 => N0,
CLK => c,
D => level,
Q => Mshreg_sync_1_0
);
sync_1 : FD
port map (
C => c,
D => Mshreg_sync_1_0,
Q => sync(1)
);
end BlackBox;
|
-------------------------------------------------------------------------------
--! @project Unrolled (6) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Fullrounds is
port(
Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out : in std_logic_vector(63 downto 0);
RoundNr : in std_logic;
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4 : out std_logic_vector(63 downto 0));
end entity Fullrounds;
architecture structural of Fullrounds is
signal RoundNr_0, RoundNr_1, RoundNr_2, RoundNr_3, RoundNr_4, RoundNr_5 : std_logic_vector(3 downto 0);
signal SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4 : std_logic_vector(63 downto 0);
signal SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4 : std_logic_vector(63 downto 0);
signal SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4 : std_logic_vector(63 downto 0);
signal SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4 : std_logic_vector(63 downto 0);
signal SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4 : std_logic_vector(63 downto 0);
signal SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4 : std_logic_vector(63 downto 0);
signal DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4 : std_logic_vector(63 downto 0);
signal DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4 : std_logic_vector(63 downto 0);
signal DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4 : std_logic_vector(63 downto 0);
signal DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4 : std_logic_vector(63 downto 0);
signal DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4 : std_logic_vector(63 downto 0);
begin
-- declare and connect all sub entities
sbox1: entity work.Sbox port map(Reg0Out,Reg1Out,Reg2Out,Reg3Out,Reg4Out,RoundNr_0,
SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4);
difflayer1: entity work.FullDiffusionLayer port map(SboxOut0_0,SboxOut0_1,SboxOut0_2,SboxOut0_3,SboxOut0_4,
DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4);
sbox2: entity work.Sbox port map(DiffOut0_0,DiffOut0_1,DiffOut0_2,DiffOut0_3,DiffOut0_4,RoundNr_1,
SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4);
difflayer2: entity work.FullDiffusionLayer port map(SboxOut1_0,SboxOut1_1,SboxOut1_2,SboxOut1_3,SboxOut1_4,
DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4);
sbox3: entity work.Sbox port map(DiffOut1_0,DiffOut1_1,DiffOut1_2,DiffOut1_3,DiffOut1_4,RoundNr_2,
SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4);
difflayer3: entity work.FullDiffusionLayer port map(SboxOut2_0,SboxOut2_1,SboxOut2_2,SboxOut2_3,SboxOut2_4,
DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4);
sbox4: entity work.Sbox port map(DiffOut2_0,DiffOut2_1,DiffOut2_2,DiffOut2_3,DiffOut2_4,RoundNr_3,
SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4);
difflayer4: entity work.FullDiffusionLayer port map(SboxOut3_0,SboxOut3_1,SboxOut3_2,SboxOut3_3,SboxOut3_4,
DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4);
sbox5: entity work.Sbox port map(DiffOut3_0,DiffOut3_1,DiffOut3_2,DiffOut3_3,DiffOut3_4,RoundNr_4,
SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4);
difflayer5: entity work.FullDiffusionLayer port map(SboxOut4_0,SboxOut4_1,SboxOut4_2,SboxOut4_3,SboxOut4_4,
DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4);
sbox6: entity work.Sbox port map(DiffOut4_0,DiffOut4_1,DiffOut4_2,DiffOut4_3,DiffOut4_4,RoundNr_5,
SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4);
difflayer6: entity work.FullDiffusionLayer port map(SboxOut5_0,SboxOut5_1,SboxOut5_2,SboxOut5_3,SboxOut5_4,
RoundOut0,RoundOut1,RoundOut2,RoundOut3,RoundOut4);
roundnrgen: process(RoundNr) is
begin
if RoundNr = '0' then
RoundNr_0 <= "0000";
RoundNr_1 <= "0001";
RoundNr_2 <= "0010";
RoundNr_3 <= "0011";
RoundNr_4 <= "0100";
RoundNr_5 <= "0101";
else
RoundNr_0 <= "0110";
RoundNr_1 <= "0111";
RoundNr_2 <= "1000";
RoundNr_3 <= "1001";
RoundNr_4 <= "1010";
RoundNr_5 <= "1011";
end if;
end process;
end architecture structural;
|
--------------------------------------------------------------------------------------------------
-- Clock generator for test-benches
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package tb_clockgen_pkg is
component tb_clockgen is
generic( PERIOD : time := 30ns;
DUTY_CYCLE : real := 0.50);
port( clk : out std_logic);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Clock generator for test-benches/simulations. Do not use for synthesis designs. When used
-- simultaneously with other clock-generators should result in phase-aligned clocks.
entity tb_clockgen is
generic( --Duration of one clock cycle in seconds. Cycle starts at low logic.
PERIOD : time := 30ns;
--Percentage of the cycle spent at high logic. Valid Values between 0 and 1.
DUTY_CYCLE : real := 0.50);
port( --The generated clock signal
clk : out std_logic);
end tb_clockgen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of tb_clockgen is
signal clock : std_logic;
begin
clk <= clock;
tictoc: process
begin
clock <= '1';
wait for (PERIOD - (PERIOD * DUTY_CYCLE));
clock <= '0';
wait for (PERIOD * DUTY_CYCLE);
end process;
end behave; |
library ieee;
use ieee.std_logic_1164.all;
entity func04 is
port (a : std_logic_vector (7 downto 0);
b : std_logic_vector (7 downto 0);
r : out std_logic_vector (7 downto 0));
end func04;
architecture behav of func04 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (len - 1 downto 0);
begin
res := (0 | 1 => '0', others => '1');
return res;
end gen_mask;
constant mask : std_logic_vector(7 downto 0) := not gen_mask (8);
begin
r <= (a and mask) or (b and gen_mask (8));
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity synk_JK is
PORT (J: in std_logic;
K: in std_logic;
CLK: in std_logic;
PRST: in std_logic;
CLR: in std_logic;
Q: out std_logic;
QB: out std_logic);
end synk_JK;
Architecture Arch_synk_JK of synk_JK is
begin
JK: process (CLK, CLR, PRST)
variable x: std_logic;
begin
if (CLR='0') then
x:='0';
elsif (PRST='0') then
x:='1';
elsif (CLK='1' and CLK'EVENT) then
if (J='0' and K='0') then
x:=x;
elsif (J='1' and K='1') then
x:= not x;
elsif (J='0' and K='1') then
x:='0';
else
x:='1';
end if;
end if;
Q <= x;
QB <= not x;
end process JK;
end Arch_synk_JK; |
--Practica4 de Diseño Automatico de Sistemas
--Cronometro.
--Manejo display 7-SEGMENTOS.
--Desarrollada por Héctor Gutiérrez Palancarejo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity switch2display7seg is
port(
a : in std_logic_vector(3 downto 0);
b : out std_logic_vector(6 downto 0)
);
end switch2display7seg;
architecture rtl of switch2display7seg is
constant zero : std_logic_vector(6 downto 0) := "0000001"; -- 0
constant one : std_logic_vector(6 downto 0) := "1001111";
constant two : std_logic_vector(6 downto 0) := "0010010";
constant three : std_logic_vector(6 downto 0) := "0000110";
constant four : std_logic_vector(6 downto 0) := "1001100";
constant five : std_logic_vector(6 downto 0) := "0100100";
constant six : std_logic_vector(6 downto 0) := "0100000";
constant seven : std_logic_vector(6 downto 0) := "0001111";
constant eight : std_logic_vector(6 downto 0) := "0000000";
constant nine : std_logic_vector(6 downto 0) := "0001100";
constant ten : std_logic_vector(6 downto 0) := "0001000";
constant eleven : std_logic_vector(6 downto 0) := "1100000";
constant twelve : std_logic_vector(6 downto 0) := "0110001";
constant thirteen : std_logic_vector(6 downto 0) := "1000010";
constant fourteen : std_logic_vector(6 downto 0) := "0110000";
constant fiveteen : std_logic_vector(6 downto 0) := "0111000"; -- 15
begin
b <= not(zero) when a = "0000" else
not(one) when a = "0001" else
not(two) when a = "0010" else
not(three) when a = "0011" else
not(four) when a = "0100" else
not(five) when a = "0101" else
not(six) when a = "0110" else
not(seven) when a = "0111" else
not(eight) when a = "1000" else
not(nine) when a = "1001" else
not(ten) when a = "1010" else
not(eleven) when a = "1011" else
not(twelve) when a = "1100" else
not(thirteen) when a = "1101" else
not(fourteen) when a = "1110" else
not(fiveteen);
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
entity spi_top is
generic(
tx_ram_depth : integer;
tx_max_block_size : integer;
cpol : integer;
cpha : integer
);
port(
ctrl : in ctrl_t;
--hardware interface
cs_n : in std_logic;
sclk : in std_logic;
mosi : in std_logic;
miso : out std_logic;
-- internal receive interface
new_mcu_to_fpga_data : out std_logic;
mcu_to_fpga_data : out std_logic_vector(spi_word_length - 1 downto 0);
-- internal tx interface
enqueue_fpga_to_mcu_data : in std_logic;
fpga_to_mcu_data : in std_logic_vector(15 downto 0);
-- debug from transmitter
full : out std_logic;
contents_count : out integer range 0 to tx_ram_depth
);
end spi_top;
architecture rtl of spi_top is
--signal data_tentatively_latched : std_logic;
signal data_fully_latched : std_logic;
signal header_byte : std_logic_vector(7 downto 0);
signal next_tx_word : std_logic_vector(15 downto 0);
signal tx_header_byte : std_logic;
signal tx_byte : std_logic_vector(7 downto 0);
signal latched_data : std_logic_vector(7 downto 0);
signal dequeue : std_logic;
signal empty : std_logic;
signal contents_count_int : integer range 0 to tx_ram_depth;
signal new_mcu_to_fpga_data_from_rx : std_logic;
signal remaining_bytes : integer range 0 to 255;
signal mcu_to_fpga_data_int : std_logic_vector(7 downto 0);
begin
spi_tx_1 : entity virtual_button_lib.spi_tx
generic map (
cpol => cpol,
cpha => cpha)
port map (
ctrl => ctrl,
cs_n => cs_n,
sclk => sclk,
miso => miso,
data => tx_byte,
latched_data => latched_data,
data_fully_latched => data_fully_latched);
tx_fifo : entity work.circular_queue
generic map(
queue_depth => tx_ram_depth,
queue_width => 16
)
port map (
ctrl => ctrl,
enqueue => enqueue_fpga_to_mcu_data,
dequeue => dequeue,
write_in_data => std_logic_vector(fpga_to_mcu_data),
read_out_data => next_tx_word,
empty => empty,
full => full,
contents_count => contents_count_int);
tx_controller : entity virtual_button_lib.spi_tx_ram_controller
generic map(
tx_max_block_size => tx_max_block_size)
port map(
ctrl => ctrl,
contents_count => contents_count_int,
data_fully_latched => data_fully_latched,
next_tx_word => next_tx_word,
latched_data => latched_data,
tx_byte => tx_byte,
dequeue => dequeue
);
contents_count <= contents_count_int;
spi_rx_1 : entity virtual_button_lib.spi_rx
generic map (
cpol => cpol,
cpha => cpha)
port map (
ctrl => ctrl,
sclk => sclk,
cs_n => cs_n,
mosi => mosi,
data => mcu_to_fpga_data_int,
new_data => new_mcu_to_fpga_data_from_rx);
-- spi_rx does not know about data framing. This process does.
-- WOrks out if if a received byte is data or framing-information. If it is
-- data, then flats it to the rest of the fpga through new_mcu_to_fpga_data
decode_rx_frame : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
remaining_bytes <= 0;
new_mcu_to_fpga_data <= '0';
else
new_mcu_to_fpga_data <= '0';
if new_mcu_to_fpga_data_from_rx = '1' and remaining_bytes = 0 then
remaining_bytes <= to_integer(unsigned(mcu_to_fpga_data_int));
elsif new_mcu_to_fpga_data_from_rx = '1' and remaining_bytes > 0 then
remaining_bytes <= remaining_bytes - 1;
new_mcu_to_fpga_data <= '1';
end if;
end if;
end if;
end process;
mcu_to_fpga_data <= mcu_to_fpga_data_int;
end rtl;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_arty_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fir is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (31 downto 0);
y_ap_vld : OUT STD_LOGIC;
c_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
c_ce0 : OUT STD_LOGIC;
c_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x : IN STD_LOGIC_VECTOR (31 downto 0);
x_ap_vld : IN STD_LOGIC );
end;
architecture behav of fir is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.912000,HLS_SYN_LAT=67,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=561,HLS_SYN_LUT=266}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv5_A : STD_LOGIC_VECTOR (4 downto 0) := "01010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv5_1F : STD_LOGIC_VECTOR (4 downto 0) := "11111";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal x_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal x_in_sig : STD_LOGIC_VECTOR (31 downto 0);
signal x_ap_vld_preg : STD_LOGIC := '0';
signal x_ap_vld_in_sig : STD_LOGIC;
signal shift_reg_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal shift_reg_ce0 : STD_LOGIC;
signal shift_reg_we0 : STD_LOGIC;
signal shift_reg_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal shift_reg_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal x_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal i_cast_fu_143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_reg_190 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_1_fu_155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_199 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_147_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal grp_fu_136_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal i_1_reg_218 : STD_LOGIC_VECTOR (4 downto 0);
signal c_load_reg_223 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal grp_fu_174_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_228 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal acc_1_fu_179_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal acc_reg_101 : STD_LOGIC_VECTOR (31 downto 0);
signal i_phi_fu_118_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal i_reg_114 : STD_LOGIC_VECTOR (4 downto 0);
signal data1_reg_126 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_161_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_166_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_170_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_136_p0 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
component fir_mul_32s_32s_3bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component fir_shift_reg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
shift_reg_U : component fir_shift_reg
generic map (
DataWidth => 32,
AddressRange => 11,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => shift_reg_address0,
ce0 => shift_reg_ce0,
we0 => shift_reg_we0,
d0 => shift_reg_d0,
q0 => shift_reg_q0);
fir_mul_32s_32s_3bkb_U1 : component fir_mul_32s_32s_3bkb
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => c_load_reg_223,
din1 => data1_reg_126,
ce => ap_const_logic_1,
dout => grp_fu_174_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
x_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
x_ap_vld_preg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_ap_vld_preg <= x_ap_vld;
end if;
end if;
end if;
end process;
x_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
x_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = x_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
x_preg <= x;
end if;
end if;
end if;
end process;
acc_reg_101_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
acc_reg_101 <= acc_1_fu_179_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
acc_reg_101 <= ap_const_lv32_0;
end if;
end if;
end process;
data1_reg_126_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_199 = ap_const_lv1_0))) then
data1_reg_126 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
data1_reg_126 <= x_in_sig;
end if;
end if;
end process;
i_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
i_reg_114 <= i_1_reg_218;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
i_reg_114 <= ap_const_lv5_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
c_load_reg_223 <= c_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_1_reg_218 <= grp_fu_136_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_cast_reg_190 <= i_cast_fu_143_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0))) then
tmp_1_reg_199 <= tmp_1_fu_155_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
tmp_6_reg_228 <= grp_fu_174_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, x_ap_vld_in_sig, ap_CS_fsm_state2, tmp_fu_147_p3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
acc_1_fu_179_p2 <= std_logic_vector(unsigned(tmp_6_reg_228) + unsigned(acc_reg_101));
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_block_state1_assign_proc : process(ap_start, x_ap_vld_in_sig)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = x_ap_vld_in_sig));
end process;
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_5_fu_170_p1(4 - 1 downto 0);
c_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
grp_fu_136_p0_assign_proc : process(ap_CS_fsm_state2, ap_CS_fsm_state3, i_phi_fu_118_p4, i_reg_114)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
grp_fu_136_p0 <= i_reg_114;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
grp_fu_136_p0 <= i_phi_fu_118_p4;
else
grp_fu_136_p0 <= "XXXXX";
end if;
end process;
grp_fu_136_p2 <= std_logic_vector(unsigned(grp_fu_136_p0) + unsigned(ap_const_lv5_1F));
i_cast_fu_143_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(i_reg_114),32));
i_phi_fu_118_p4 <= i_reg_114;
shift_reg_address0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3, tmp_3_fu_161_p1, tmp_4_fu_166_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_address0 <= tmp_4_fu_166_p1(4 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
shift_reg_address0 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_0))) then
shift_reg_address0 <= tmp_3_fu_161_p1(4 - 1 downto 0);
else
shift_reg_address0 <= "XXXX";
end if;
end process;
shift_reg_ce0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_0)) or (ap_const_logic_1 = ap_CS_fsm_state3) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1)))) then
shift_reg_ce0 <= ap_const_logic_1;
else
shift_reg_ce0 <= ap_const_logic_0;
end if;
end process;
shift_reg_d0_assign_proc : process(x_in_sig, shift_reg_q0, ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
shift_reg_d0 <= shift_reg_q0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1))) then
shift_reg_d0 <= x_in_sig;
else
shift_reg_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
shift_reg_we0_assign_proc : process(ap_CS_fsm_state2, tmp_1_fu_155_p2, tmp_1_reg_199, tmp_fu_147_p3, ap_CS_fsm_state3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_1_reg_199 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_0) and (tmp_1_fu_155_p2 = ap_const_lv1_1)))) then
shift_reg_we0 <= ap_const_logic_1;
else
shift_reg_we0 <= ap_const_logic_0;
end if;
end process;
tmp_1_fu_155_p2 <= "1" when (i_reg_114 = ap_const_lv5_0) else "0";
tmp_3_fu_161_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(grp_fu_136_p2),64));
tmp_4_fu_166_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_190),64));
tmp_5_fu_170_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_cast_reg_190),64));
tmp_fu_147_p3 <= i_reg_114(4 downto 4);
x_ap_vld_in_sig_assign_proc : process(x_ap_vld, x_ap_vld_preg)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_ap_vld_in_sig <= x_ap_vld;
else
x_ap_vld_in_sig <= x_ap_vld_preg;
end if;
end process;
x_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, x_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
x_blk_n <= x_ap_vld;
else
x_blk_n <= ap_const_logic_1;
end if;
end process;
x_in_sig_assign_proc : process(x, x_preg, x_ap_vld)
begin
if ((ap_const_logic_1 = x_ap_vld)) then
x_in_sig <= x;
else
x_in_sig <= x_preg;
end if;
end process;
y <= acc_reg_101;
y_ap_vld_assign_proc : process(ap_CS_fsm_state2, tmp_fu_147_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_147_p3 = ap_const_lv1_1))) then
y_ap_vld <= ap_const_logic_1;
else
y_ap_vld <= ap_const_logic_0;
end if;
end process;
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity alu is
port (
alu_ctrl : in std_logic_vector(3 downto 0);
alu_src1, alu_src2 : in std_logic_vector(31 downto 0);
alu_zero : out std_logic;
alu_result : out std_logic_vector(31 downto 0);
alu_carry : out std_logic
);
end alu;
architecture behavioral of alu is
begin
process(alu_src1, alu_src2, alu_ctrl)
variable src1, src2, result : signed(31 downto 0 );
variable zero : std_logic;
begin
--
src1 := signed(alu_src1);
src2 := signed(alu_src2);
result := (others => '0');
zero := '0';
--
case alu_ctrl is
--AND
when "0000" =>
result := src1 and src2;
--OR
when "0001" =>
result := src1 or src2;
--ADD
when "0010" =>
result := src1 + src2;
--SUB
when "0110" =>
result := src1 - src2;
--SLT
when "0111" =>
if src1 < src2 then result(0) := '1';
else result(0) := '0';
end if;
--NOR
when "1100" =>
result := src1 nor src2;
--error
when others =>
result := (others => '0');
end case;
if to_integer(result) = 0 then zero := '1';
else zero := '0';
end if;
alu_result <= std_logic_vector(result);
alu_zero <= zero;
end process;
end behavioral; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PC_tb IS
END PC_tb;
ARCHITECTURE behavior OF PC_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PC
PORT(
rst : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
DataOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal dataIn : std_logic_vector(31 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal DataOut : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PC PORT MAP (
rst => rst,
dataIn => dataIn,
CLK => CLK,
DataOut => DataOut
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
dataIn<="00100010001000100010001000100010";
wait for 40 ns;
dataIn<="00000000000000000000000000000011";
wait for 80 ns;
rst<='1';
dataIn<="00100010001000100010001000100010";
wait for 40 ns;
dataIn<="00000000000000000000000000000011";
wait for 80 ns;
rst<='0';
dataIn<="11100010001000100010001111100010";
wait for 40 ns;
dataIn<="00000000000000111111100001111111";
wait for 40 ns;
dataIn<="01010010100101001100100100010010";
wait for 40 ns;
dataIn<="01011110100001011110100001101000";
wait for 20 ns;
dataIn<="00000000000000000000000000111010";
wait;
end process;
END;
|
-------------------------------------------------------------------------------
-- axi_vdma_sts_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_sts_mngr is
port (
-- system signals
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- dma control and sg engine status signals --
run_stop : in std_logic ; --
regdir_idle : in std_logic ; --
ftch_idle : in std_logic ; --
cmnd_idle : in std_logic ; --
sts_idle : in std_logic ; --
line_buffer_empty : in std_logic ; --
dwidth_fifo_pipe_empty : in std_logic ; --
video_prmtrs_valid : in std_logic ; --
prmtr_update_complete : in std_logic ; --CR605424
--
-- stop and halt control/status --
stop : in std_logic ; --
halt : in std_logic ; -- CR 625278
halt_cmplt : in std_logic ; --
--
-- system state and control --
all_idle : out std_logic ; --
ftchcmdsts_idle : out std_logic ; --
cmdsts_idle : out std_logic ; --
halted_clr : out std_logic ; --
halted_set : out std_logic ; --
idle_set : out std_logic ; --
idle_clr : out std_logic --
);
end axi_vdma_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal ftch_idle_d1 : std_logic := '0';
signal ftch_idle_re : std_logic := '0';
signal ftch_idle_fe : std_logic := '0';
signal datamover_idle : std_logic := '0';
--signal cmdstsfifo_idle : std_logic := '0';
signal halted_set_i : std_logic := '0';
--signal datamover_idle_i : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- CR573389 - modified all_idle output to look at sg engine ftch idle only
-- if video parameters are NOT valid, else ignore ftchidle. this fixes
-- issue of xfer pausing while descriptors are being fetched.
-- all_idle only used for frame sync determination
ALL_IDLE_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
all_idle <= '1';
-- Qualify all idle with sg engine fetch idle when
-- no video parameters are valid
elsif(video_prmtrs_valid = '0')then
all_idle <= ftch_idle
and cmnd_idle
and sts_idle
and line_buffer_empty
and dwidth_fifo_pipe_empty
and regdir_idle -- Reg Direct idle (for fsync only)
and prmtr_update_complete; -- CR605424 idle needs to account for lutram copy
-- Otherwise if we have valid video parameters then do
-- not stall transfers in free-run mode due to sg engine fetches
else
all_idle <= cmnd_idle
and sts_idle
and dwidth_fifo_pipe_empty
and line_buffer_empty;
end if;
end if;
end process ALL_IDLE_PROCESS;
-- Idle for soft_reset determination
-- Note Line buffer is not looked at because do not want to stall soft reset if external
-- stream target does not accept data from line buffer.
ftchcmdsts_idle <= ftch_idle
and cmnd_idle
and sts_idle;
-- Command/Status Idle (Used for s2mm linebuffer reset qualification on shut down)
cmdsts_idle <= cmnd_idle
and sts_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
-- CR 625278
--datamover_idle <= '1' when (stop = '1' and halt_cmplt = '1')
-- or (stop = '0')
-- else '0';
--
-- Need to sample and hold for cases when user clears run/stop starting
-- a shutdown phase, then an error occurs (stop=1) causing a second
-- shutdown phase to start. previous the halt complete was missed by datamove_idle
-- because stop asserted after the halt complete asserted due to the first
-- shutdown phase.
DATAMOVER_IDLE_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
datamover_idle <= '0';
-- if dm being halted and halt is completed then
-- set and hold datamover idle.
elsif(halt = '1' and halt_cmplt = '1')then
datamover_idle <= '1';
-- clear datamove_idle if running and dm not
-- being halted.
elsif(halt = '0' and run_stop = '1')then
datamover_idle <= '0';
end if;
end if;
end process DATAMOVER_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
-- Everything is idle when everything is idle used for setting halt flag.
all_is_idle <= ftch_idle
and cmnd_idle
and sts_idle
and dwidth_fifo_pipe_empty
and line_buffer_empty;
HALT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
halted_set_i <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(run_stop = '0' and all_is_idle = '1' and datamover_idle = '1')then
halted_set_i <= '1';
else
halted_set_i <= '0';
end if;
end if;
end process HALT_PROCESS;
halted_set <= halted_set_i;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
halted_clr <= '0';
elsif(run_stop = '1')then
halted_clr <= '1';
else
halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ftch_idle_d1 <= '0';
else
ftch_idle_d1 <= ftch_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
ftch_idle_re <= ftch_idle and not ftch_idle_d1;
ftch_idle_fe <= not ftch_idle and ftch_idle_d1;
-- Set or Clear IDLE bit in DMASR
idle_set <= ftch_idle_re and run_stop;
idle_clr <= ftch_idle_fe;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_sts_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_sts_mngr is
port (
-- system signals
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- dma control and sg engine status signals --
run_stop : in std_logic ; --
regdir_idle : in std_logic ; --
ftch_idle : in std_logic ; --
cmnd_idle : in std_logic ; --
sts_idle : in std_logic ; --
line_buffer_empty : in std_logic ; --
dwidth_fifo_pipe_empty : in std_logic ; --
video_prmtrs_valid : in std_logic ; --
prmtr_update_complete : in std_logic ; --CR605424
--
-- stop and halt control/status --
stop : in std_logic ; --
halt : in std_logic ; -- CR 625278
halt_cmplt : in std_logic ; --
--
-- system state and control --
all_idle : out std_logic ; --
ftchcmdsts_idle : out std_logic ; --
cmdsts_idle : out std_logic ; --
halted_clr : out std_logic ; --
halted_set : out std_logic ; --
idle_set : out std_logic ; --
idle_clr : out std_logic --
);
end axi_vdma_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal ftch_idle_d1 : std_logic := '0';
signal ftch_idle_re : std_logic := '0';
signal ftch_idle_fe : std_logic := '0';
signal datamover_idle : std_logic := '0';
--signal cmdstsfifo_idle : std_logic := '0';
signal halted_set_i : std_logic := '0';
--signal datamover_idle_i : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- CR573389 - modified all_idle output to look at sg engine ftch idle only
-- if video parameters are NOT valid, else ignore ftchidle. this fixes
-- issue of xfer pausing while descriptors are being fetched.
-- all_idle only used for frame sync determination
ALL_IDLE_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
all_idle <= '1';
-- Qualify all idle with sg engine fetch idle when
-- no video parameters are valid
elsif(video_prmtrs_valid = '0')then
all_idle <= ftch_idle
and cmnd_idle
and sts_idle
and line_buffer_empty
and dwidth_fifo_pipe_empty
and regdir_idle -- Reg Direct idle (for fsync only)
and prmtr_update_complete; -- CR605424 idle needs to account for lutram copy
-- Otherwise if we have valid video parameters then do
-- not stall transfers in free-run mode due to sg engine fetches
else
all_idle <= cmnd_idle
and sts_idle
and dwidth_fifo_pipe_empty
and line_buffer_empty;
end if;
end if;
end process ALL_IDLE_PROCESS;
-- Idle for soft_reset determination
-- Note Line buffer is not looked at because do not want to stall soft reset if external
-- stream target does not accept data from line buffer.
ftchcmdsts_idle <= ftch_idle
and cmnd_idle
and sts_idle;
-- Command/Status Idle (Used for s2mm linebuffer reset qualification on shut down)
cmdsts_idle <= cmnd_idle
and sts_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
-- CR 625278
--datamover_idle <= '1' when (stop = '1' and halt_cmplt = '1')
-- or (stop = '0')
-- else '0';
--
-- Need to sample and hold for cases when user clears run/stop starting
-- a shutdown phase, then an error occurs (stop=1) causing a second
-- shutdown phase to start. previous the halt complete was missed by datamove_idle
-- because stop asserted after the halt complete asserted due to the first
-- shutdown phase.
DATAMOVER_IDLE_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
datamover_idle <= '0';
-- if dm being halted and halt is completed then
-- set and hold datamover idle.
elsif(halt = '1' and halt_cmplt = '1')then
datamover_idle <= '1';
-- clear datamove_idle if running and dm not
-- being halted.
elsif(halt = '0' and run_stop = '1')then
datamover_idle <= '0';
end if;
end if;
end process DATAMOVER_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
-- Everything is idle when everything is idle used for setting halt flag.
all_is_idle <= ftch_idle
and cmnd_idle
and sts_idle
and dwidth_fifo_pipe_empty
and line_buffer_empty;
HALT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
halted_set_i <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(run_stop = '0' and all_is_idle = '1' and datamover_idle = '1')then
halted_set_i <= '1';
else
halted_set_i <= '0';
end if;
end if;
end process HALT_PROCESS;
halted_set <= halted_set_i;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
halted_clr <= '0';
elsif(run_stop = '1')then
halted_clr <= '1';
else
halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ftch_idle_d1 <= '0';
else
ftch_idle_d1 <= ftch_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
ftch_idle_re <= ftch_idle and not ftch_idle_d1;
ftch_idle_fe <= not ftch_idle and ftch_idle_d1;
-- Set or Clear IDLE bit in DMASR
idle_set <= ftch_idle_re and run_stop;
idle_clr <= ftch_idle_fe;
end implementation;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_a
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro -nodelta ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-conf-c.vhd,v 1.1 2006/03/16 14:12:15 wig Exp $
-- $Date: 2006/03/16 14:12:15 $
-- $Log: ent_a-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/03/16 14:12:15 wig
-- Added testcase for command line -conf add/overload
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.77 2006/03/14 08:10:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding lot's of testcases
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
ADD_MY_OWN: overloading my own macro -- adding my own macro
MY_TICK_IN_TEST: has a ' inside -- has a ' inside
MY_TICK_FIRST_TEST: ' start with tick -- ' start with tick
MY_TICK_LAST_TEST: ends with ' -- ends with '
MY_DQUOTE_IN_TEST: has a " inside -- has a " inside
MY_DQUOTE_FIRST_TEST: " start with tick -- " start with tick
MY_DQUOTE_LAST_TEST: ends with " -- ends with "
MY_DQUOTE_TICK_TEST: has a ' and a " here ' " more -- has a ' and a " here ' " more
MY_SOME_SEPS: special " $ & ' \n and more -- special " $ & ' \n and more
-- END
--
-- Start of Generated Configuration ent_a_rtl_conf / ent_a
--
configuration ent_a_rtl_conf of ent_a is
for rtl
-- Generated Configuration
for inst_aa : ent_aa
use configuration work.ent_aa_rtl_conf;
end for;
for inst_ab : ent_ab
use configuration work.ent_ab_rtl_conf;
end for;
for inst_ac : ent_ac
use configuration work.ent_ac_rtl_conf;
end for;
for inst_ad : ent_ad
use configuration work.ent_ad_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ae : ent_ae
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_ae_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end ent_a_rtl_conf;
--
-- End of Generated Configuration ent_a_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_color_test:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_color_test_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_color_test_0_0;
ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_color_test IS
GENERIC (
H_SIZE : INTEGER;
V_SIZE : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_color_test;
BEGIN
U0 : vga_color_test
GENERIC MAP (
H_SIZE => 640,
V_SIZE => 480
)
PORT MAP (
clk_25 => clk_25,
xaddr => xaddr,
yaddr => yaddr,
rgb => rgb
);
END system_vga_color_test_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_color_test:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_color_test_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_color_test_0_0;
ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_color_test IS
GENERIC (
H_SIZE : INTEGER;
V_SIZE : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_color_test;
BEGIN
U0 : vga_color_test
GENERIC MAP (
H_SIZE => 640,
V_SIZE => 480
)
PORT MAP (
clk_25 => clk_25,
xaddr => xaddr,
yaddr => yaddr,
rgb => rgb
);
END system_vga_color_test_0_0_arch;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.math_real.all;
USE work.FIR_constants.all;
ENTITY FIR_filter IS
PORT(
CLK, RST_n: IN STD_LOGIC;
VIN: IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
Coeffs: IN STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0); --# of coeffs IS Ord+1
VOUT: OUT STD_LOGIC;
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE beh_fir OF FIR_filter IS
TYPE sum_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
TYPE sig_array IS ARRAY (Ord DOWNTO 0) OF STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SIGNAL Bi: sig_array; -- there IS Ord instead of Ord-1 becaUSE the coeffs are Ord+1
SIGNAL REG_OUT_array: sig_array;
SIGNAL SUM_OUT_array: sum_array;
SIGNAL VIN_delay_line: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL Coeffs_delayed: STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0);
SIGNAL DIN_mult: STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0);
SIGNAL mult_ext: STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
COMPONENT Cell IS
PORT(
CLK, RST_n, EN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SUM_IN: IN STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0);
Bi: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
REG_OUT : OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
ADD_OUT: OUT STD_LOGIC_VECTOR(Nbadder-1 DOWNTO 0) -- aggiunti 9 bit di guardia
);
END COMPONENT;
COMPONENT Reg_n IS
GENERIC(Nb: INTEGER :=9);
PORT(
CLK, RST_n, EN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT mult_n IS
GENERIC(
Nb: INTEGER := 9
);
PORT(
in_a: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
in_b: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
mult_out: OUT STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
-----------------------------------------------------------
------------------------ Input Buffers --------------------
In_buffers_1: IF IO_buffers GENERATE
VIN_delay_line(0) <= VIN;
data_in_reg: Reg_n GENERIC MAP (Nb => Nb)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN,
DIN => DIN,
DOUT => REG_OUT_array(0)
);
Coeffs_in_reg: Reg_n GENERIC MAP (Nb => ((Ord+1)*Nb))
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN,
DIN => Coeffs,
DOUT => Coeffs_delayed
);
VIN_in_reg: Reg_n GENERIC MAP (Nb => 1)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => '1',
DIN => VIN_delay_line(0 DOWNTO 0),
DOUT => VIN_delay_line(1 DOWNTO 1)
);
END GENERATE;
In_buffers_0: IF NOT(IO_buffers) GENERATE
Coeffs_delayed <= Coeffs;
REG_OUT_array(0) <= DIN;
VIN_delay_line(1) <= VIN;
END GENERATE;
--------------------------------------------------------------
------------------------ First Multiplier --------------------
Coeff_gen: FOR i IN 0 to Ord GENERATE
Bi(i) <= Coeffs_delayed(((i+1)*Nb)-1 DOWNTO (i*Nb));
END GENERATE;
DIN_mult_gen: mult_n GENERIC MAP(Nb => Nb)
PORT MAP
(
in_a => REG_OUT_array(0),
in_b => Bi(0),
mult_out => DIN_mult
);
DIN_mult_extension_0: IF (Nbadder <= Nbmult) GENERATE
mult_ext <= DIN_mult((DIN_mult'LENGTH - (Nbmult - Nbadder) -1) DOWNTO (DIN_mult'LENGTH)-1-(Nbmult-1));
END GENERATE;
DIN_mult_extension_1: IF (Nbadder > Nbmult) GENERATE
mult_ext(Nbmult-1 DOWNTO 0)<= DIN_mult((DIN_mult'LENGTH -1) DOWNTO ((DIN_mult'LENGTH)-1-(Nbmult-1)) );
mult_ext(Nbadder-1 DOWNTO Nbmult) <= (OTHERS => mult_ext(Nbmult-1));
END GENERATE;
SUM_OUT_array(0) <= mult_ext;
-------------------------------------------------------------
------------------------ Matrix of Cells --------------------
Cells_gen: FOR j IN 0 to Ord-1 GENERATE
Single_cell: Cell PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN_delay_line(1),
DIN => REG_OUT_array(j),
SUM_IN => SUM_OUT_array(j),
Bi => Bi(j+1),
REG_OUT => REG_OUT_array(j+1),
ADD_OUT => SUM_OUT_array(j+1)
);
END GENERATE;
-----------------------------------------------------------
----------------------- Output Buffers --------------------
Out_buffers_1: IF IO_buffers GENERATE
data_out_reg: Reg_n GENERIC MAP (Nb => Nb)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => VIN_delay_line(1),
DIN => SUM_OUT_array(Ord)(Nb-1 DOWNTO 0),
DOUT => DOUT
);
VIN_out_reg: Reg_n GENERIC MAP (Nb => 1)
PORT MAP
(
CLK => CLK,
RST_n => RST_n,
EN => '1',
DIN => VIN_delay_line(1 DOWNTO 1),
DOUT => VIN_delay_line(2 DOWNTO 2)
);
VOUT <= VIN_delay_line(2);
END GENERATE;
Out_buffers_0: IF NOT(IO_buffers) GENERATE
DOUT <= SUM_OUT_array(Ord)(Nb-1 DOWNTO 0);
VOUT <= VIN;
END GENERATE;
END beh_fir;
|
--**********************************************************************************************
-- Resynchronizer (for n-bit vector)
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_vect;
architecture rtl of rsnc_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
inverted_first_stg:if (inv_f_stgs/=0) generate
seq_f_fe_prc:process(clk)
begin
if(clk='0' and clk'event) then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
norm_first_stg:if (inv_f_stgs=0) generate
seq_f_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
|
--**********************************************************************************************
-- Resynchronizer (for n-bit vector)
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_vect;
architecture rtl of rsnc_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
inverted_first_stg:if (inv_f_stgs/=0) generate
seq_f_fe_prc:process(clk)
begin
if(clk='0' and clk'event) then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
norm_first_stg:if (inv_f_stgs=0) generate
seq_f_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
|
--**********************************************************************************************
-- Resynchronizer (for n-bit vector)
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_vect;
architecture rtl of rsnc_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
inverted_first_stg:if (inv_f_stgs/=0) generate
seq_f_fe_prc:process(clk)
begin
if(clk='0' and clk'event) then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
norm_first_stg:if (inv_f_stgs=0) generate
seq_f_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
|
--**********************************************************************************************
-- Resynchronizer (for n-bit vector)
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_vect is generic(
width : integer := 8;
add_stgs_num : integer := 0;
inv_f_stgs : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_vect;
architecture rtl of rsnc_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
inverted_first_stg:if (inv_f_stgs/=0) generate
seq_f_fe_prc:process(clk)
begin
if(clk='0' and clk'event) then -- Clock (falling edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
norm_first_stg:if (inv_f_stgs=0) generate
seq_f_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
end generate;
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
|
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
----------------------------------------------------------------------
--top level design unit
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY booth_multiplier IS
--GENERIC(k : POSITIVE := 7); --input number word length less one
GENERIC(k : POSITIVE := 3); --input number word length less one
PORT(multiplicand, multiplier : IN BIT_VECTOR(k DOWNTO 0);
clock : IN BIT; product : INOUT BIT_VECTOR((2 * k + 1) DOWNTO 0));
END booth_multiplier;
ARCHITECTURE structural OF booth_multiplier IS
SIGNAL mdreg, adderout, carries, augend, tcbuffout : BIT_VECTOR(k DOWNTO 0);
SIGNAL mrreg : BIT_VECTOR((k + 1) DOWNTO 0);
SIGNAL adder_ovfl : BIT;
SIGNAL comp ,clr_mr ,load_mr ,shift_mr ,clr_md ,load_md ,clr_pp ,load_pp ,shift_pp : BIT;
SIGNAL boostate : NATURAL RANGE 0 TO 2*(k + 1);
BEGIN
PROCESS --main clocked process containing all sequential elements
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
--register to hold multiplicand during multiplication
IF clr_md = '1' THEN
mdreg <= (OTHERS => '0'); -- clean multiplicand
ELSIF load_md = '1' THEN
mdreg <= multiplicand; -- assign multiplicand to mdreg register
ELSE
mdreg <= mdreg; -- nothing, dut to correspond "if else end if" annoying syntax.
END IF;
--register/shifter to product pair of bits used to control adder
IF clr_mr = '1' THEN
mrreg <= (OTHERS => '0'); -- clean multiplier
ELSIF load_mr = '1' THEN
mrreg((k + 1) DOWNTO 1) <= multiplier; -- assign multiplier to mrreg register
mrreg(0) <= '0';
ELSIF shift_mr = '1' THEN
mrreg <= mrreg SRL 1;
ELSE
mrreg <= mrreg; -- nothing, dut to correspond "if else end if" annoying syntax.
END IF;
--register/shifter accumulates partial product values
IF clr_pp = '1' THEN
product <= (OTHERS => '0');
ELSIF load_pp = '1' THEN
product(( 2 * k + 1 ) DOWNTO( k + 1 ) ) <= adderout; --add to top half
product(k DOWNTO 0) <= product(k DOWNTO 0); --refresh bootm half
ELSIF shift_pp = '1' THEN
product <= product SRA 1; --shift right with sign extend( arithmetic right shift )
ELSE
product <= product;
END IF;
END PROCESS;
--full adder adds/subtracts partial product to multiplicand
augend <= product( ( 2 * k + 1 ) DOWNTO( k + 1 ) ); -- high half of partial product
addgen : FOR i IN adderout'RANGE GENERATE
lsadder : IF i = 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR comp; -- sum
carries(i) <= (tcbuffout(i) AND augend(i)) OR -- carry
(tcbuffout(i) AND comp) OR
(comp AND augend(i));
END GENERATE;
otheradder : IF i /= 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR carries(i-1);-- sum
carries(i) <= (tcbuffout(i) AND augend(i)) OR -- carry
(tcbuffout(i) AND carries(i-1)) OR
(carries(i-1) AND augend(i));
END GENERATE;
END GENERATE;
--twos comp overflow bit
adder_ovfl <= carries(k-1) XOR carries(k);
--true/complement buffer to generate two's comp of mdreg
tcbuffout <= NOT mdreg WHEN (comp = '1') ELSE mdreg;
--booth multiplier state counter
PROCESS
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
IF boostate < 2*(k + 1) THEN
boostate <= boostate + 1;
ELSE
boostate <= 0;
END IF;
END PROCESS;
--assign control signal values based on state
PROCESS(boostate)
BEGIN
--assign defaults, all registers refresh
comp <= '0';
clr_mr <= '0'; -- multiplier
load_mr <= '0';
shift_mr <= '0';
clr_md <= '0'; -- multiplicand
load_md <= '0';
clr_pp <= '0'; -- partial product
load_pp <= '0';
shift_pp <= '0';
IF boostate = 0 THEN
load_mr <= '1';
load_md <= '1';
clr_pp <= '1';
ELSIF boostate MOD 2 = 0 THEN --boostate = 2,4,6,8 .... even number
shift_mr <= '1'; -- shift multiplier
shift_pp <= '1'; -- shift partial product
ELSE --boostate = 1,3,5,7...... odd number
IF mrreg(0) = mrreg(1) THEN
NULL; --refresh partial product
ELSE
load_pp <= '1'; --update product
END IF;
comp <= mrreg(1); --subract if mrreg(1 DOWNTO 0) ="10"
END IF;
END PROCESS;
END structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 03:30:43 04/10/2009
-- Design Name:
-- Module Name: Subsys_Adder - Behavioral
-- Project Name: 3-Bit Adder
-- Target Devices:
-- Tool versions:
-- Description: A system that is able to store two 3-bit numbers, add them, and display their result in hexadecimal
-- on a 7-segment display
--
-- Dependencies: Comp_4bitRegister.vhd, Comp_FullAdder.vhd, Comp_7segDecoder.vhd, Comp_Dflipflop.vhd,
-- Gate_Nand.vhd, Gate_And.vhd Gate_Or.vhd, Gate_Xor.vhd, Gate_Inv.vhd, Gate_Buf.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Subsys_Adder is
Port ( N1 : in STD_LOGIC_VECTOR (3 downto 0);
N2 : in STD_LOGIC_VECTOR (3 downto 0);
CLK1 : in STD_LOGIC;
CLK2 : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (6 downto 0);
ano : out STD_LOGIC_VECTOR (3 downto 0));
end Subsys_Adder;
architecture Behavioral of Subsys_Adder is
component Comp_4bitRegister is
Port ( D1 : in STD_LOGIC;
D2 : in STD_LOGIC;
D3 : in STD_LOGIC;
D4 : in STD_LOGIC;
CLK : in STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC;
Q4 : out STD_LOGIC);
end component;
component Comp_FullAdder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
component Comp_7segDecoder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal S1 : STD_LOGIC;
signal S2 : STD_LOGIC;
signal S3 : STD_LOGIC;
signal S4 : STD_LOGIC;
signal S5 : STD_LOGIC;
signal S6 : STD_LOGIC;
signal S7 : STD_LOGIC;
signal S8 : STD_LOGIC;
signal S9 : STD_LOGIC;
signal S10 : STD_LOGIC;
signal S11 : STD_LOGIC;
signal S12 : STD_LOGIC;
signal S13 : STD_LOGIC_VECTOR (3 downto 0);
signal S14 : STD_LOGIC;
signal S15 : STD_LOGIC;
signal S16 : STD_LOGIC;
signal S17 : STD_LOGIC;
begin
S13(0) <= S14;
S13(1) <= S15;
S13(2) <= S16;
S13(3) <= S17;
G1: Comp_4bitRegister port map (N1(0), N1(1), N1(2), N1(3), CLK1, S1, S2, S3);
G2: Comp_4bitRegister port map (N2(0), N2(1), N2(2), N2(3), CLK1, S4, S5, S6);
G3: Comp_FullAdder port map (S1, S4, '0', S9, S7);
G4: Comp_FullAdder port map (S2, S5, S7, S10, S8);
G5: Comp_FullAdder port map (S3, S6, S8, S11, S12);
G6: Comp_4bitRegister port map (S9, S10, S11, S12, CLK2, S14, S15, S16, S17);
G7: Comp_7segDecoder port map (S13, seg);
ano <= "1110";
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity exceptions is
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
int_mul: in std_logic_vector(31 downto 0);
enable: in std_logic;
m_in47:in std_logic;
exp_out: out std_logic_vector(31 downto 0)
);
end exceptions;
architecture arch_exceptions of exceptions is
signal expa :std_logic_vector (8 downto 0);
signal expb :std_logic_vector (8 downto 0);
signal summ :std_logic_vector (8 downto 0);
signal m :std_logic_vector (8 downto 0) ;
begin
expa<='0' & in1(30 downto 23);
expb<='0' & in2(30 downto 23);
m<="00000000" & m_in47;
summ<=std_logic_vector(unsigned(expa)+unsigned(expb)+unsigned(m));
process (enable,in1,in2,int_mul,summ)
begin
if(enable='1')then
-- not anumber
if (in1(30 downto 23)="11111111" and in1(22 downto 0 )/= "00000000000000000000000") then
exp_out<="11111111111111111111111111111111"; -- NaN
elsif (in2(30 downto 23)="11111111" and in2(22 downto 0 )/="00000000000000000000000") then
exp_out<="11111111111111111111111111111111"; -- NaN
elsif(in1=x"00000000")then
-- zero by infinity or negative infinity = NaN
if(in2(30 downto 0)="1111111100000000000000000000000")then
exp_out<="11111111111111111111111111111111"; --NaN
-- zero by any number = 0
else
exp_out<=(others=>'0');
end if;
elsif(in2=x"00000000")then
if(in1(30 downto 0)="1111111100000000000000000000000")then
exp_out<="11111111111111111111111111111111"; -- NaN
else
exp_out<=(others=>'0');
end if;
elsif(in1(30 downto 0)="1111111100000000000000000000000") then
exp_out<=int_mul(31)&in1(30 downto 0 );
elsif(in2(30 downto 0)="1111111100000000000000000000000") then
exp_out<=int_mul(31)&in2(30 downto 0 );
---overflow detector \\\ ----
elsif (summ>="111111100") then
exp_out<=int_mul(31)&"1111111100000000000000000000000";
-- underflow detector
elsif (summ<="001111111") then
exp_out<="00000000000000000000000000000000";
else
exp_out<=int_mul;
end if ;
end if;
end process;
end arch_exceptions;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report "Hello World";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report "Hello World";
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report "Hello World";
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity new_tx_frame_buffer is
port(
DOA : out std_logic_vector(3 downto 0); -- Port A 4-bit Data Output
DOB : out std_logic_vector(7 downto 0); -- Port B 8-bit Data Output
DOPB : out std_logic_vector(0 downto 0); -- Port B 1-bit Parity Output
ADDRA : in std_logic_vector(11 downto 0); -- Port A 12-bit Address Input
ADDRB : in std_logic_vector(10 downto 0); -- Port B 11-bit Address Input
CLKA : in std_logic; -- Port A Clock
CLKB : in std_logic; -- Port B Clock
DIA : in std_logic_vector(3 downto 0); -- Port A 4-bit Data Input
DIB : in std_logic_vector(7 downto 0); -- Port B 8-bit Data Input
DIPB : in std_logic_vector(0 downto 0); -- Port-B 1-bit parity Input
ENA : in std_logic; -- Port A RAM Enable Input
ENB : in std_logic; -- PortB RAM Enable Input
SSRA : in std_logic; -- Port A Synchronous Set/Reset Input
SSRB : in std_logic; -- Port B Synchronous Set/Reset Input
WEA : in std_logic; -- Port A Write Enable Input
WEB : in std_logic -- Port B Write Enable Input
);
end new_tx_frame_buffer;
architecture Behavioral of new_tx_frame_buffer is
begin
RAMB16_S4_S9_inst : RAMB16_S4_S9
generic map (
INIT_A => X"0", -- Value of output RAM registers on Port A at startup
INIT_B => X"000", -- Value of output RAM registers on Port B at startup
SRVAL_A => X"0", -- Port A output value upon SSR assertion
SRVAL_B => X"000", -- Port B output value upon SSR assertion
WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
-- The following INIT_xx declarations specify the initial contents of the RAM
-- Port A Address 0 to 1023, Port B Address 0 to 511
INIT_00 => X"00084500111111110000e200004040003093fc20e7ff11115555555d55555555",
INIT_01 => X"0000edde00000000fddedeeddeed45bf00000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"000000000000000000000000000000000000000000000000da8315e000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 1024 to 2047, Port B Address 512 to 1023
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 2048 to 3071, Port B Address 1024 to 1535
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port A Address 3072 to 4095, Port B Address 1536 to 2047
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Port B Address 0 to 511
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port B Address 512 to 1023
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port B Address 1024 to 1535
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Port B Address 1536 to 2047
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => DOA, -- Port A 4-bit Data Output
DOB => DOB, -- Port B 8-bit Data Output
DOPB => DOPB, -- Port B 1-bit Parity Output
ADDRA => ADDRA, -- Port A 12-bit Address Input
ADDRB => ADDRB, -- Port B 11-bit Address Input
CLKA => CLKA, -- Port A Clock
CLKB => CLKB, -- Port B Clock
DIA => DIA, -- Port A 4-bit Data Input
DIB => DIB, -- Port B 8-bit Data Input
DIPB => DIPB, -- Port-B 1-bit parity Input
ENA => ENA, -- Port A RAM Enable Input
ENB => ENB, -- PortB RAM Enable Input
SSRA => SSRA, -- Port A Synchronous Set/Reset Input
SSRB => SSRB, -- Port B Synchronous Set/Reset Input
WEA => WEA, -- Port A Write Enable Input
WEB => WEB -- Port B Write Enable Input
);
end Behavioral; |
--Alert
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALERT IS
PORT( DATA_RANGE :IN STD_LOGIC;
CARRY_LABEL :IN STD_LOGIC;
D1_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D4_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
BEEP :OUT STD_LOGIC;
RANGE_DISP :OUT STD_LOGIC);
END ENTITY ALERT;
ARCHITECTURE ART1 OF ALERT IS
BEGIN
PROCESS(DATA_RANGE,D1_IN,D2_IN,D3_IN)
BEGIN
IF (DATA_RANGE='0') THEN
IF (D4_IN /= "0000")THEN
D1_OUT <= "0000";
D2_OUT <= "0000";
D3_OUT <= "0000";
RANGE_DISP <= '0';
BEEP <= '1';
ELSE
D1_OUT <= D1_IN;
D2_OUT <= D2_IN;
D3_OUT <= D3_IN;
RANGE_DISP <= '0';
BEEP <= '0';
END IF;
ELSE
IF (CARRY_LABEL = '1') THEN
D1_OUT <= "0000";
D2_OUT <= "0000";
D3_OUT <= "0000";
RANGE_DISP <= '1';
BEEP <= '1';
ELSE
D1_OUT <= D2_IN;
D2_OUT <= D3_IN;
D3_OUT <= D4_IN;
RANGE_DISP <= '1';
BEEP <= '0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library stack;
use stack.OneHotStack.all;
entity DPATH is
port(
EN: in std_logic;
-- synchronization
CLK: in std_logic;
-- operation type
OT: in operation;
-- operand
OP: in operand;
-- result
RES: out operand;
-- zero flag
ZF: out std_logic;
-- stop - the processing is finished
Stop: out std_logic
);
end DPATH;
architecture Beh_Stack of DPATH is
component LIFO
generic(
-- address bus
m: integer := 2;
-- data bus
n: integer := 2
);
port (
EN: in std_logic;
-- synchronization
CLK: in std_logic;
-- write/read operation type
WR: in std_logic;
-- read data bus
RB: out std_logic_vector(n-1 downto 0);
-- write data bus
WB: in std_logic_vector(n-1 downto 0)
);
end component;
type states is (I, IPOP1, IPOP2, A, SB, SH, IPUSH, MOVERES, MOVERESOP, H);
-- I - Idle - the initial state for operations
-- IPOP1 - POP 1 - pop the value and put it into the first internal operand i_op1
-- IPOP2 - POP 2 - pop the value and put it into the second internal operand i_op2
-- A - res_op = i_op1 + i_op2
-- SB - res_op = i_op1 - i_op2
-- IPUSH - PUSH - push the value of res_op to the stack
-- MOVERES - i_res = i_op1 - used in external POP operation
-- MOVERESOP - res_op = i_op - used in external push operation
-- H - Halt - indicates that the processing has been completed
signal nxt_state, cur_state: states;
-- operation result
signal res_op: operand;
-- internal input operand value
signal i_op: operand;
-- internal first operand value
signal i_op1: operand;
-- internal second operand value
signal i_op2: operand;
-- the result of the data path
signal i_res: operand;
signal s_en: std_logic;
signal s_wr: std_logic;
signal s_res: operand;
signal s_data: operand;
signal t_zf: std_logic;
Begin
USTACK: LIFO
generic map(
m => 5,
n => 16
)
port map(
CLK => CLK,
EN => s_en,
WR => s_wr,
RB => s_res,
WB => s_data
);
i_op <= OP;
FSM: process(CLK, nxt_state)
begin
if rising_edge(CLK) then
cur_state <= nxt_state;
end if;
end process;
-- Next state
COMB: process(cur_state, EN, OT)
begin
case cur_state is
when I =>
if (EN = '1') then
case OT is
when ADD | SUBT | SHIFT | POP | POPIN => nxt_state <= IPOP1;
when others => nxt_state <= MOVERESOP;
end case;
else
nxt_state <= I;
end if;
when IPOP1 =>
if (OT = POP or OT = POPIN) then
nxt_state <= MOVERES;
elsif (OT = SHIFT) then
nxt_state <= SH;
else
nxt_state <= IPOP2;
end if;
when IPOP2 =>
if (OT = ADD) then
nxt_state <= A;
else
nxt_state <= SB;
end if;
when A | SB | SH | MOVERESOP => nxt_state <= IPUSH;
when MOVERES => nxt_state <= H;
when IPUSH => nxt_state <= H;
when H => nxt_state <= I;
when others => nxt_state <= I;
end case;
end process;
-- stop signal handler
PSTOP: process (cur_state)
begin
if (cur_state = H) then
stop <= '1';
else
stop <= '0';
end if;
end process;
STACKCTRL: process (cur_state, nxt_state)
begin
if (nxt_state = IPOP1 or nxt_state = IPOP2) then
s_wr <= '1';
s_en <= '1';
elsif (cur_state = IPUSH) then
s_wr <= '0';
s_en <= '1';
else
s_wr <= '1';
s_en <= '0';
end if;
end process;
OP1CTRL: process (cur_state, s_res)
begin
if (cur_state = IPOP1) then
i_op1 <= s_res;
end if;
end process;
OP2CTRL: process (cur_state, s_res)
begin
if (cur_state = IPOP2) then
i_op2 <= s_res;
end if;
end process;
OPRESULTCTRL: process (cur_state, i_op1, i_op2, i_op)
begin
if (cur_state = A) then
res_op <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(i_op1) + CONV_INTEGER(i_op2), 16);
elsif (cur_state = SB) then
res_op <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(i_op1) - CONV_INTEGER(i_op2), 16);
elsif (cur_state = SH) then
for i in 0 to 14 loop
res_op(i) <= i_op1(i) xor i_op1(i+1);
end loop;
res_op(15) <= i_op1(15);
elsif (cur_state = MOVERESOP) then
res_op <= i_op;
end if;
end process;
IRESCTRL: process (cur_state, i_op1)
begin
if (cur_state = MOVERES) then
i_res <= i_op1;
end if;
end process;
FLAGS: process(res_op)
begin
if res_op = (res_op'range => '0') then
t_zf <= '1';
else
t_zf <= '0';
end if;
end process;
s_data <= res_op;
RES <= i_res;
ZF <= t_zf;
End Beh_Stack; |
--! @file tb_LinearRegression.vhd
--!
--! @authors Salvatore Barone <salvator.barone@gmail.com> <br>
--! Alfonso Di Martino <alfonsodimartino160989@gmail.com> <br>
--! Sossio Fiorillo <fsossio@gmail.com> <br>
--! Pietro Liguori <pie.liguori@gmail.com> <br>
--!
--! @date 03 07 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <salvator.barone@gmail.com> <br>
--! Alfonso Di Martino <alfonsodimartino160989@gmail.com> <br>
--! Sossio Fiorillo <fsossio@gmail.com> <br>
--! Pietro Liguori <pie.liguori@gmail.com> <br>
--!
--!
--! This file is part of Linear-Regression.
--!
--! Linear-Regression is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Linear-Regression is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_LinearRegression is
end tb_LinearRegression;
architecture Behavioral of tb_LinearRegression is
component LinearRegression
Port ( clk : in std_logic;
load : in std_logic;
reset_n : in std_logic;
prim : in STD_LOGIC_VECTOR (5 downto 0);
Sum2 : in STD_LOGIC_VECTOR (23 downto 0);
B : in STD_LOGIC_VECTOR (23 downto 0);
Sum1 : in STD_LOGIC_VECTOR (23 downto 0);
C : in STD_LOGIC_VECTOR (23 downto 0);
A : in STD_LOGIC_VECTOR (23 downto 0);
m : out STD_LOGIC_VECTOR (23 downto 0);
q : out STD_LOGIC_VECTOR (23 downto 0));
end component;
constant clock_period : time := 10ns;
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal reset_n : std_logic := '0';
signal prim : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
signal Sum2 : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal B : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal Sum1 : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal C : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal A : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal m : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
signal q : STD_LOGIC_VECTOR (23 downto 0):= (others => '0');
begin
clock_process : process
begin
clk <= not clk;
wait for clock_period / 2;
end process clock_process;
uut: LinearRegression
Port map ( clk => clk,
load => load,
reset_n => reset_n,
prim => prim,
Sum2 => Sum2,
B => B,
Sum1 => Sum1,
C => C,
A => A,
m => m,
q => q);
stim_proc: process
begin
wait for 10*clock_period;
reset_n <= '1';
load <= '1';
-- Test 1
prim <= b"011001"; -- 25
Sum2 <= b"001101011110110111001111"; -- 1.685279688780849
Sum1 <= b"001101000111011100011001"; -- 1.049304719064735e+02
B <= b"010011001100110011001100"; -- 0.3
C <= b"010100000100100000010110"; -- 0.0049
A <= b"011110110001001110110001"; -- 30.769230769230795
-- m 327.779907226562 -- 3.277800199255130e+02
-- q 0.263859272003174 -- 0.263858637152785
wait;
end process;
end Behavioral;
|
--Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tracking_camera_system_switch is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal in_port : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- outputs:
signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end entity tracking_camera_system_switch;
architecture europa of tracking_camera_system_switch is
signal clk_en : STD_LOGIC;
signal data_in : STD_LOGIC;
signal read_mux_out : STD_LOGIC;
begin
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))) AND data_in;
process (clk, reset_n)
begin
if reset_n = '0' then
readdata <= std_logic_vector'("00000000000000000000000000000000");
elsif clk'event and clk = '1' then
if std_logic'(clk_en) = '1' then
readdata <= std_logic_vector'("00000000000000000000000000000000") OR (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_mux_out)));
end if;
end if;
end process;
data_in <= in_port;
end europa;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.