content stringlengths 1 1.04M ⌀ |
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----------------------------------------------------------------------------------------------------
--
-- FileName: Clock_Div_5.vhd
-- Description: Clock Divide by 5.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
ENTITY Clock_Div_5 IS
PORT
(
nReset : IN STD_LOGIC; -- Reset
ClkIn : IN STD_LOGIC; -- Incoming Clock
ClkOut : OUT STD_LOGIC -- Outgoing Clock
);
END Clock_Div_5;
ARCHITECTURE Behavioral OF Clock_Div_5 IS
SIGNAL Div_1 : STD_LOGIC;
SIGNAL Div_2 : STD_LOGIC;
SIGNAL Counter_1 : UNSIGNED(2 DOWNTO 0);
SIGNAL Counter_2 : UNSIGNED(2 DOWNTO 0);
BEGIN
PROCESS(ClkIn, nReset)
BEGIN
IF (nReset = '0') THEN
Div_1 <= '0';
Counter_1 <= "000";
ELSIF RISING_EDGE(ClkIn) THEN
IF Counter_1 = 5 THEN
Counter_1 <= "001";
Div_1 <= '1';
ELSIF Counter_1 >= 2 THEN
Div_1 <= '0';
Counter_1 <= Counter_1 + 1;
ELSE
Div_1 <= '1';
Counter_1 <= Counter_1 + 1;
END IF;
END IF;
END PROCESS;
PROCESS(ClkIn, nReset)
BEGIN
IF (nReset = '0') THEN
Div_2 <= '0';
Counter_2 <= "000";
ELSIF FALLING_EDGE(ClkIn) THEN
IF Counter_2 = 5 THEN
Counter_2 <= "001";
Div_2 <= '1';
ELSIF Counter_2 >= 2 THEN
Div_2 <= '0';
Counter_2 <= Counter_2 + 1;
ELSE
Div_2 <= '1';
Counter_2 <= Counter_2 + 1;
END IF;
END IF;
END PROCESS;
ClkOut <= Div_1 OR Div_2;
END Behavioral; |
entity stop1 is
end entity;
library std;
use std.env.all;
architecture test of stop1 is
begin
process is
begin
stop(0);
report "should not print this" severity failure;
wait;
end process;
end architecture;
|
-- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
|
-- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
|
-- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
|
-- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
|
-- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
|
-- NEED RESULT: ARCH00272: Configuration item in block configuration may be block or component configuration passed
-- NEED RESULT: ARCH00272: Block specification may be architecture name or block label passed
-- NEED RESULT: ARCH00272: Several configuration item may appear in a block configuration and block configurations may be nested to an arbitrary depth passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00272
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.3.1 (3)
-- 1.3.1 (4)
-- 1.3.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00272(ARCH00272)
-- ENT00272_1(ARCH00272_1)
-- CONF00272
-- ENT00272_Test_Bench(ARCH00272_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
entity ENT00272 is
generic ( g10, g11, g12 : integer ) ;
port ( s10, s11, s12 : out integer ) ;
end ENT00272 ;
architecture ARCH00272 of ENT00272 is
component COMP1
end component ;
begin
C1 : COMP1;
B1_1 :
block
begin
B2_2 :
block
component COMP1
end component ;
begin
CIS1 : COMP1;
end block B2_2 ;
B2_3 :
block
begin
B3_4 :
block
component COMP1
end component ;
begin
CIS1 : COMP1;
end block B3_4 ;
end block B2_3 ;
end block B1_1 ;
end ARCH00272 ;
entity ENT00272_1 is
generic ( g1 : integer ) ;
port ( s1 : out integer ) ;
begin
end ENT00272_1 ;
architecture ARCH00272_1 of ENT00272_1 is
begin
s1 <= g1 ;
end ARCH00272_1 ;
configuration CONF00272 of WORK.ENT00272 is
for ARCH00272
for C1 : COMP1
use entity WORK.ENT00272_1 ( ARCH00272_1 )
generic map ( g10 )
port map ( s10 ) ;
end for ;
for B1_1
for B2_2
for CIS1 : COMP1
use entity WORK.ENT00272_1 ( ARCH00272_1 )
generic map ( g11 )
port map ( s11 ) ;
end for ;
end for ; -- B2_2 component
for B2_3
for B3_4
for CIS1 : COMP1 -- 3 deep
use entity WORK.ENT00272_1 ( ARCH00272_1 )
generic map ( g12 )
port map ( s12 ) ;
end for ;
end for ; -- B3_4
end for ; -- B2_3
end for ; -- B1_1
end for ;
end CONF00272 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00272_Test_Bench is
end ENT00272_Test_Bench ;
architecture ARCH00272_Test_Bench of ENT00272_Test_Bench is
begin
L1:
block
constant c1 : integer := 1 ;
constant c2 : integer := 2 ;
constant c3 : integer := 3 ;
signal s1, s2, s3 : integer ;
component UUT
end component ;
for CIS1 : UUT use configuration WORK.CONF00272
generic map ( c1, c2, c3 )
port map ( s1, s2, s3 ) ;
begin
CIS1 : UUT ;
P00272 :
process ( s1, s2, s3 )
begin
if s1 = c1 and s2 = c2 and s3 = c3 then
test_report ( "ARCH00272" ,
"Configuration item in block configuration may"
& " be block or component configuration" ,
true ) ;
test_report ( "ARCH00272" ,
"Block specification may be architecture name"
& " or block label" ,
true ) ;
test_report ( "ARCH00272" ,
"Several configuration item may appear in a block"
& " configuration and block configurations may be"
& " nested to an arbitrary depth" ,
true ) ;
end if ;
end process P00272 ;
end block L1 ;
end ARCH00272_Test_Bench ;
|
-------------------------------------------------------------------------------
-- Synthesis test for the floating point math package
-- This test is designed to be synthesizable and exercise much of the package.
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:50:32-04 $
-- Version $Id: float_synth.vhdl,v 1.1 2006-06-08 10:50:32-04 l435385 Exp $
-------------------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
use ieee.math_real.all;
entity float_synth is
port (
in1, in2 : in std_logic_vector (31 downto 0); -- inputs
out1 : out std_logic_vector (31 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end entity float_synth;
architecture rtl of float_synth is
subtype fp16 is float (6 downto -9); -- 16 bit
type cmd_type is array (1 to 15) of std_ulogic_vector (cmd'range); -- cmd
signal cmdarray : cmd_type; -- command pipeline
type cry_type is array (0 to 15) of float32; -- arrays
signal outx : cry_type;
signal in1reg3, in2reg3 : float32; -- register stages
begin -- architecture rtl
-- purpose: "0000" test the "+" operator
cmd0reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(0) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(0) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 + in2reg3;
end if;
end process cmd0reg;
-- purpose: "0001" test the "-" operator
cmd1reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(1) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(1) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 - in2reg3;
end if;
end process cmd1reg;
-- purpose: "0010" test the "*" operator
cmd2reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(2) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(2) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 * in2reg3;
end if;
end process cmd2reg;
-- purpose: "0011" performs test the "/" operator
cmd3reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(3) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(3) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
if (cmdarray(4) = "0011") then
outarray(0) := in1reg3 / in2reg3;
else
outarray(0) := (others => '0');
end if;
end if;
end process cmd3reg;
-- purpose: "0100" test the "resize" function
cmd4reg: process (clk, rst_n) is
variable tmpfp161, tmpfp162 : fp16; -- 16 bit fp number
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(4) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(4) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_zero);
when "001" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "010" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "011" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_inf);
when "100" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_neginf);
when "101" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
check_error => false,
round_style => round_zero);
when "110" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low);
when "111" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low
-- size_res => tmpfp161
);
when others => null;
end case;
outarray(0)(-8 downto -23) := tmpfp161;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(6 downto -7) := (others => '0');
end if;
end process cmd4reg;
-- purpose: "0101" Conversion function test
cmd5reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(5) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(5) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := to_unsigned (in1reg3, uns'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "001" =>
uns := to_unsigned (in1reg3, uns);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "010" =>
s := to_signed (in1reg3, s'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "011" =>
s := to_signed (in1reg3, s);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "100" =>
uf := to_ufixed (in1reg3, uf'high, uf'low);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "101" =>
uf := to_ufixed (in1reg3, uf);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "110" =>
sf := to_sfixed (in1reg3, sf'high, sf'low);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when "111" =>
sf := to_sfixed (in1reg3, sf);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when others => null;
end case;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(5 downto -7) := (others => '0');
end if;
end process cmd5reg;
-- purpose: "0110" to_float()
cmd6reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(6) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(6) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, 8, 23);
when "001" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, in1reg3);
when "010" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, 8, 23);
when "011" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, in1reg3);
when "100" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf'high, uf'low);
outarray(0) := to_float(uf, 8, 23);
when "101" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf);
outarray(0) := to_float(uf, in1reg3);
when "110" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf'high, sf'low);
outarray(0) := to_float(sf, 8, 23);
when "111" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf);
outarray(0) := to_float(sf, in1reg3);
when others => null;
end case;
end if;
end process cmd6reg;
-- purpose: "0111" mod function
cmd7reg: process (clk, rst_n) is
variable tmpuns : unsigned (31 downto 0); -- unsigned number
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(7) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(7) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 mod in2reg3;
end if;
end process cmd7reg;
-- purpose: "1000" rem function
cmd8reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(8) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(8) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 rem in2reg3;
end if;
end process cmd8reg;
-- purpose: "1001" to_float (constants) test
cmd9reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(9) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(9) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := to_float(0, 8, 23);
when "001" =>
outarray(0) := to_float(0.0, 8, 23);
when "010" =>
outarray(0) := to_float(8, in1reg3);
when "011" =>
outarray(0) := to_float(8.0, in1reg3);
when "100" =>
outarray(0) := to_float(-8, 8, 23);
when "101" =>
outarray(0) := to_float(-8.0, 8, 23);
when "110" =>
outarray(0) := to_float(27000, in2reg3);
when "111" =>
-- outarray(0) := "01000000010010010000111111011011";
outarray(0) := to_float(MATH_PI, in2reg3);
when others => null;
end case;
end if;
end process cmd9reg;
-- purpose: "1010" data manipulation (+, -, scalb, etc)
cmd10reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable s : SIGNED (7 downto 0); -- signed number
variable outarray : cry_type; -- array for output
constant posinf : float32 := "01111111100000000000000000000000"; -- +inf
constant neginf : float32 := "11111111100000000000000000000000"; -- +inf
constant onept5 : float32 := "00111111110000000000000000000000"; -- 1.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(10) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(10) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := - in1reg3;
when "001" =>
outarray(0) := abs( in1reg3);
when "010" =>
if (cmdarray(4) = "1010") then
s := resize (SIGNED (to_slv (in2reg3(8 downto 5))), s'length);
outarray(0) := Scalb (in1reg3, s);
else
outarray(0) := (others => '0');
end if;
when "011" =>
if (cmdarray(4) = "1010") then
s := logb (in1reg3);
outarray(0) := (others => '0');
outarray(0)(-16 downto -23) := float(std_logic_vector(s));
else
outarray(0) := (others => '0');
end if;
when "100" =>
outarray(0) := Nextafter ( in1reg3, onept5);
when "101" =>
outarray(0) := Nextafter ( in1reg3, -onept5);
when "110" =>
outarray(0) := Nextafter ( x => in1reg3, y => posinf,
check_error => false,
denormalize => false);
when "111" =>
outarray(0) := Nextafter (x => in1reg3, y => neginf,
check_error => false,
denormalize => false);
when others => null;
end case;
end if;
end process cmd10reg;
-- purpose "1011" copysign
cmd11reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(11) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(11) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := Copysign (in1reg3, in2reg3);
end if;
end process cmd11reg;
-- purpose "1100" compare test
cmd12reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
constant fifteenpt5 : float32 := "01000001011110000000000000000000";-- 15.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(12) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(12) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := (others => '0');
if (in1reg3 = in2reg3) then
outarray(0)(outarray(0)'high) := '1';
else
outarray(0)(outarray(0)'high) := '0';
end if;
if (in1reg3 /= in2reg3) then
outarray(0)(outarray(0)'high-1) := '1';
else
outarray(0)(outarray(0)'high-1) := '0';
end if;
if (in1reg3 > in2reg3) then
outarray(0)(outarray(0)'high-2) := '1';
else
outarray(0)(outarray(0)'high-2) := '0';
end if;
if (in1reg3 < in2reg3) then
outarray(0)(outarray(0)'high-3) := '1';
else
outarray(0)(outarray(0)'high-3) := '0';
end if;
if (in1reg3 >= in2reg3) then
outarray(0)(outarray(0)'high-4) := '1';
else
outarray(0)(outarray(0)'high-4) := '0';
end if;
if (in1reg3 <= in2reg3) then
outarray(0)(outarray(0)'high-5) := '1';
else
outarray(0)(outarray(0)'high-5) := '0';
end if;
outarray(0)(outarray(0)'high-6) := \?=\ (in1reg3, 15);
outarray(0)(outarray(0)'high-7) := \?=\ (in1reg3, 15.5);
if (Unordered (in1reg3, in2reg3)) then
outarray(0)(outarray(0)'high-8) := '1';
else
outarray(0)(outarray(0)'high-8) := '0';
end if;
if (Finite (in1reg3)) then
outarray(0)(outarray(0)'high-9) := '1';
else
outarray(0)(outarray(0)'high-9) := '0';
end if;
if (Isnan (in1reg3)) then
outarray(0)(outarray(0)'high-10) := '1';
else
outarray(0)(outarray(0)'high-10) := '0';
end if;
end if;
end process cmd12reg;
-- purpose "1101" boolean test
cmd13reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(13) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(13) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := not (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3;
when "010" =>
outarray(0) := in1reg3 or in2reg3;
when "011" =>
outarray(0) := in1reg3 nand in2reg3;
when "100" =>
outarray(0) := in1reg3 nor in2reg3;
when "101" =>
outarray(0) := in1reg3 xor in2reg3;
when "110" =>
outarray(0) := in1reg3 xnor in2reg3;
when "111" =>
outarray(0) := in1reg3 xor '1';
when others => null;
end case;
end if;
end process cmd13reg;
-- purpose "1110" reduce and vector test
cmd14reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(14) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(14) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := (others => '0');
outarray(0)(outarray(0)'high) := and_reduce (in1reg3);
outarray(0)(outarray(0)'high-1) := nand_reduce (in1reg3);
outarray(0)(outarray(0)'high-2) := or_reduce (in1reg3);
outarray(0)(outarray(0)'high-3) := nor_reduce (in1reg3);
outarray(0)(outarray(0)'high-4) := xor_reduce (in1reg3);
outarray(0)(outarray(0)'high-5) := xnor_reduce (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3(in2reg3'high);
when "010" =>
outarray(0) := in1reg3 or in2reg3(in2reg3'high);
when "011" =>
outarray(0) := in1reg3 nand in2reg3(in2reg3'high);
when "100" =>
outarray(0) := in1reg3 nor in2reg3(in2reg3'high);
when "101" =>
outarray(0) := in2reg3(in2reg3'high) xor in1reg3;
when "110" =>
outarray(0) := in2reg3(in2reg3'high) xnor in1reg3;
when "111" =>
outarray(0) := in2reg3(in2reg3'high) and in1reg3;
when others => null;
end case;
end if;
end process cmd14reg;
-- purpose "1111" + constant
cmd15reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(15) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(15) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := in1reg3 + 1;
when "001" =>
outarray(0) := 1 + in1reg3;
when "010" =>
outarray(0) := in1reg3 + 1.0;
when "011" =>
outarray(0) := 1.0 + in1reg3;
when "100" =>
outarray(0) := in1reg3 * 1;
when "101" =>
outarray(0) := 1 * in1reg3;
when "110" =>
outarray(0) := in1reg3 * 1.0;
when "111" =>
outarray(0) := 1.0 * in1reg3;
when others => null;
end case;
end if;
end process cmd15reg;
-- purpose: multiply floating point
-- type : sequential
-- inputs : clk, rst_n, in1, in2
-- outputs: out1
cmdreg: process (clk, rst_n) is
variable outreg : float32; -- register stages
variable in1reg, in2reg : float32; -- register stages
variable in1reg2, in2reg2 : float32; -- register stages
begin -- process mulreg
if rst_n = '0' then -- asynchronous reset (active low)
in1reg := ( others => '0');
in2reg := ( others => '0');
in1reg2 := ( others => '0');
in2reg2 := ( others => '0');
in1reg3 <= ( others => '0');
in2reg3 <= ( others => '0');
out1 <= ( others => '0');
outreg := (others => '0');
rcloop: for i in 1 to 15 loop
cmdarray (i) <= (others => '0');
end loop rcloop;
elsif rising_edge(clk) then -- rising clock edge
out1 <= to_slv (outreg);
outregc: case cmdarray (13) is
when "0000" => outreg := outx (0);
when "0001" => outreg := outx (1);
when "0010" => outreg := outx (2);
when "0011" => outreg := outx (3);
when "0100" => outreg := outx (4);
when "0101" => outreg := outx (5);
when "0110" => outreg := outx (6);
when "0111" => outreg := outx (7);
when "1000" => outreg := outx (8);
when "1001" => outreg := outx (9);
when "1010" => outreg := outx (10);
when "1011" => outreg := outx (11);
when "1100" => outreg := outx (12);
when "1101" => outreg := outx (13);
when "1110" => outreg := outx (14);
when "1111" => outreg := outx (15);
when others => null;
end case outregc;
cmdpipe: for i in 15 downto 3 loop
cmdarray (i) <= cmdarray (i-1);
end loop cmdpipe;
cmdarray (2) <= std_ulogic_vector(cmd);
in1reg3 <= in1reg2;
in2reg3 <= in2reg2;
in1reg2 := in1reg;
in2reg2 := in2reg;
in1reg := to_float (in1, in1reg);
in2reg := to_float (in2, in2reg);
end if;
end process cmdreg;
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Synthesis test for the floating point math package
-- This test is designed to be synthesizable and exercise much of the package.
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
-- --------------------------------------------------------------------
-- modification history : Last Modified $Date: 2006-06-08 10:50:32-04 $
-- Version $Id: float_synth.vhdl,v 1.1 2006-06-08 10:50:32-04 l435385 Exp $
-------------------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
use ieee.math_real.all;
entity float_synth is
port (
in1, in2 : in std_logic_vector (31 downto 0); -- inputs
out1 : out std_logic_vector (31 downto 0); -- output
cmd : in std_logic_vector (3 downto 0);
clk, rst_n : in std_ulogic); -- clk and reset
end entity float_synth;
architecture rtl of float_synth is
subtype fp16 is float (6 downto -9); -- 16 bit
type cmd_type is array (1 to 15) of std_ulogic_vector (cmd'range); -- cmd
signal cmdarray : cmd_type; -- command pipeline
type cry_type is array (0 to 15) of float32; -- arrays
signal outx : cry_type;
signal in1reg3, in2reg3 : float32; -- register stages
begin -- architecture rtl
-- purpose: "0000" test the "+" operator
cmd0reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd0reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(0) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(0) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 + in2reg3;
end if;
end process cmd0reg;
-- purpose: "0001" test the "-" operator
cmd1reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(1) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(1) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 - in2reg3;
end if;
end process cmd1reg;
-- purpose: "0010" test the "*" operator
cmd2reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(2) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(2) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 * in2reg3;
end if;
end process cmd2reg;
-- purpose: "0011" performs test the "/" operator
cmd3reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(3) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(3) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
if (cmdarray(4) = "0011") then
outarray(0) := in1reg3 / in2reg3;
else
outarray(0) := (others => '0');
end if;
end if;
end process cmd3reg;
-- purpose: "0100" test the "resize" function
cmd4reg: process (clk, rst_n) is
variable tmpfp161, tmpfp162 : fp16; -- 16 bit fp number
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(4) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(4) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_zero);
when "001" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "010" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => false,
denormalize => false);
when "011" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_inf);
when "100" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
round_style => round_neginf);
when "101" =>
tmpfp161 := resize ( arg => in1reg3,
-- size_res => tmpfp161,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low,
denormalize_in => true,
denormalize => false,
check_error => false,
round_style => round_zero);
when "110" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low);
when "111" =>
tmpfp161 := resize ( arg => in1reg3,
exponent_width => tmpfp161'high,
fraction_width => -tmpfp161'low
-- size_res => tmpfp161
);
when others => null;
end case;
outarray(0)(-8 downto -23) := tmpfp161;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(6 downto -7) := (others => '0');
end if;
end process cmd4reg;
-- purpose: "0101" Conversion function test
cmd5reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(5) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(5) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := to_unsigned (in1reg3, uns'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "001" =>
uns := to_unsigned (in1reg3, uns);
outarray(0)(-8 downto -23) := float(std_logic_vector(uns));
when "010" =>
s := to_signed (in1reg3, s'length);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "011" =>
s := to_signed (in1reg3, s);
outarray(0)(-8 downto -23) := float(std_logic_vector(s));
when "100" =>
uf := to_ufixed (in1reg3, uf'high, uf'low);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "101" =>
uf := to_ufixed (in1reg3, uf);
outarray(0)(-8 downto -23) := float(to_slv(uf));
when "110" =>
sf := to_sfixed (in1reg3, sf'high, sf'low);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when "111" =>
sf := to_sfixed (in1reg3, sf);
outarray(0)(-8 downto -23) := float(to_slv(sf));
when others => null;
end case;
outarray(0)(8 downto 6) := float(tmpcmd);
outarray(0)(5 downto -7) := (others => '0');
end if;
end process cmd5reg;
-- purpose: "0110" to_float()
cmd6reg: process (clk, rst_n) is
variable uns : unsigned (15 downto 0); -- unsigned number
variable s : signed (15 downto 0); -- signed number
variable uf : ufixed (8 downto -7); -- unsigned fixed
variable sf : sfixed (8 downto -7); -- signed fixed point
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(6) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(6) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, 8, 23);
when "001" =>
uns := UNSIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(uns, in1reg3);
when "010" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, 8, 23);
when "011" =>
s := SIGNED (to_slv (in1reg3(-8 downto -23)));
outarray(0) := to_float(s, in1reg3);
when "100" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf'high, uf'low);
outarray(0) := to_float(uf, 8, 23);
when "101" =>
uf := to_ufixed (to_slv (in1reg3(-8 downto -23)), uf);
outarray(0) := to_float(uf, in1reg3);
when "110" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf'high, sf'low);
outarray(0) := to_float(sf, 8, 23);
when "111" =>
sf := to_sfixed (to_slv (in1reg3(-8 downto -23)), sf);
outarray(0) := to_float(sf, in1reg3);
when others => null;
end case;
end if;
end process cmd6reg;
-- purpose: "0111" mod function
cmd7reg: process (clk, rst_n) is
variable tmpuns : unsigned (31 downto 0); -- unsigned number
variable outarray : cry_type; -- array for output
begin -- process cmd1reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(7) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(7) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 mod in2reg3;
end if;
end process cmd7reg;
-- purpose: "1000" rem function
cmd8reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(8) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(8) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := in1reg3 rem in2reg3;
end if;
end process cmd8reg;
-- purpose: "1001" to_float (constants) test
cmd9reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(9) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(9) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := to_float(0, 8, 23);
when "001" =>
outarray(0) := to_float(0.0, 8, 23);
when "010" =>
outarray(0) := to_float(8, in1reg3);
when "011" =>
outarray(0) := to_float(8.0, in1reg3);
when "100" =>
outarray(0) := to_float(-8, 8, 23);
when "101" =>
outarray(0) := to_float(-8.0, 8, 23);
when "110" =>
outarray(0) := to_float(27000, in2reg3);
when "111" =>
-- outarray(0) := "01000000010010010000111111011011";
outarray(0) := to_float(MATH_PI, in2reg3);
when others => null;
end case;
end if;
end process cmd9reg;
-- purpose: "1010" data manipulation (+, -, scalb, etc)
cmd10reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable s : SIGNED (7 downto 0); -- signed number
variable outarray : cry_type; -- array for output
constant posinf : float32 := "01111111100000000000000000000000"; -- +inf
constant neginf : float32 := "11111111100000000000000000000000"; -- +inf
constant onept5 : float32 := "00111111110000000000000000000000"; -- 1.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(10) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(10) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := - in1reg3;
when "001" =>
outarray(0) := abs( in1reg3);
when "010" =>
if (cmdarray(4) = "1010") then
s := resize (SIGNED (to_slv (in2reg3(8 downto 5))), s'length);
outarray(0) := Scalb (in1reg3, s);
else
outarray(0) := (others => '0');
end if;
when "011" =>
if (cmdarray(4) = "1010") then
s := logb (in1reg3);
outarray(0) := (others => '0');
outarray(0)(-16 downto -23) := float(std_logic_vector(s));
else
outarray(0) := (others => '0');
end if;
when "100" =>
outarray(0) := Nextafter ( in1reg3, onept5);
when "101" =>
outarray(0) := Nextafter ( in1reg3, -onept5);
when "110" =>
outarray(0) := Nextafter ( x => in1reg3, y => posinf,
check_error => false,
denormalize => false);
when "111" =>
outarray(0) := Nextafter (x => in1reg3, y => neginf,
check_error => false,
denormalize => false);
when others => null;
end case;
end if;
end process cmd10reg;
-- purpose "1011" copysign
cmd11reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(11) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(11) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := Copysign (in1reg3, in2reg3);
end if;
end process cmd11reg;
-- purpose "1100" compare test
cmd12reg: process (clk, rst_n) is
variable outarray : cry_type; -- array for output
constant fifteenpt5 : float32 := "01000001011110000000000000000000";-- 15.5
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(12) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(12) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
outarray(0) := (others => '0');
if (in1reg3 = in2reg3) then
outarray(0)(outarray(0)'high) := '1';
else
outarray(0)(outarray(0)'high) := '0';
end if;
if (in1reg3 /= in2reg3) then
outarray(0)(outarray(0)'high-1) := '1';
else
outarray(0)(outarray(0)'high-1) := '0';
end if;
if (in1reg3 > in2reg3) then
outarray(0)(outarray(0)'high-2) := '1';
else
outarray(0)(outarray(0)'high-2) := '0';
end if;
if (in1reg3 < in2reg3) then
outarray(0)(outarray(0)'high-3) := '1';
else
outarray(0)(outarray(0)'high-3) := '0';
end if;
if (in1reg3 >= in2reg3) then
outarray(0)(outarray(0)'high-4) := '1';
else
outarray(0)(outarray(0)'high-4) := '0';
end if;
if (in1reg3 <= in2reg3) then
outarray(0)(outarray(0)'high-5) := '1';
else
outarray(0)(outarray(0)'high-5) := '0';
end if;
outarray(0)(outarray(0)'high-6) := \?=\ (in1reg3, 15);
outarray(0)(outarray(0)'high-7) := \?=\ (in1reg3, 15.5);
if (Unordered (in1reg3, in2reg3)) then
outarray(0)(outarray(0)'high-8) := '1';
else
outarray(0)(outarray(0)'high-8) := '0';
end if;
if (Finite (in1reg3)) then
outarray(0)(outarray(0)'high-9) := '1';
else
outarray(0)(outarray(0)'high-9) := '0';
end if;
if (Isnan (in1reg3)) then
outarray(0)(outarray(0)'high-10) := '1';
else
outarray(0)(outarray(0)'high-10) := '0';
end if;
end if;
end process cmd12reg;
-- purpose "1101" boolean test
cmd13reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(13) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(13) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := not (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3;
when "010" =>
outarray(0) := in1reg3 or in2reg3;
when "011" =>
outarray(0) := in1reg3 nand in2reg3;
when "100" =>
outarray(0) := in1reg3 nor in2reg3;
when "101" =>
outarray(0) := in1reg3 xor in2reg3;
when "110" =>
outarray(0) := in1reg3 xnor in2reg3;
when "111" =>
outarray(0) := in1reg3 xor '1';
when others => null;
end case;
end if;
end process cmd13reg;
-- purpose "1110" reduce and vector test
cmd14reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(14) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(14) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := (others => '0');
outarray(0)(outarray(0)'high) := and_reduce (in1reg3);
outarray(0)(outarray(0)'high-1) := nand_reduce (in1reg3);
outarray(0)(outarray(0)'high-2) := or_reduce (in1reg3);
outarray(0)(outarray(0)'high-3) := nor_reduce (in1reg3);
outarray(0)(outarray(0)'high-4) := xor_reduce (in1reg3);
outarray(0)(outarray(0)'high-5) := xnor_reduce (in1reg3);
when "001" =>
outarray(0) := in1reg3 and in2reg3(in2reg3'high);
when "010" =>
outarray(0) := in1reg3 or in2reg3(in2reg3'high);
when "011" =>
outarray(0) := in1reg3 nand in2reg3(in2reg3'high);
when "100" =>
outarray(0) := in1reg3 nor in2reg3(in2reg3'high);
when "101" =>
outarray(0) := in2reg3(in2reg3'high) xor in1reg3;
when "110" =>
outarray(0) := in2reg3(in2reg3'high) xnor in1reg3;
when "111" =>
outarray(0) := in2reg3(in2reg3'high) and in1reg3;
when others => null;
end case;
end if;
end process cmd14reg;
-- purpose "1111" + constant
cmd15reg: process (clk, rst_n) is
variable tmpcmd : STD_LOGIC_VECTOR (2 downto 0);
variable outarray : cry_type; -- array for output
begin -- process cmd2reg
if rst_n = '0' then -- asynchronous reset (active low)
outx(15) <= ( others => '0');
jrloop: for j in 0 to 7 loop
outarray (j) := (others => '0');
end loop jrloop;
elsif rising_edge(clk) then -- rising clock edge
outx(15) <= outarray(7);
jcloop: for j in 7 downto 1 loop
outarray (j) := outarray(j-1);
end loop jcloop;
tmpcmd := to_slv (in2reg3 (in2reg3'low+2 downto in2reg3'low));
case tmpcmd is
when "000" =>
outarray(0) := in1reg3 + 1;
when "001" =>
outarray(0) := 1 + in1reg3;
when "010" =>
outarray(0) := in1reg3 + 1.0;
when "011" =>
outarray(0) := 1.0 + in1reg3;
when "100" =>
outarray(0) := in1reg3 * 1;
when "101" =>
outarray(0) := 1 * in1reg3;
when "110" =>
outarray(0) := in1reg3 * 1.0;
when "111" =>
outarray(0) := 1.0 * in1reg3;
when others => null;
end case;
end if;
end process cmd15reg;
-- purpose: multiply floating point
-- type : sequential
-- inputs : clk, rst_n, in1, in2
-- outputs: out1
cmdreg: process (clk, rst_n) is
variable outreg : float32; -- register stages
variable in1reg, in2reg : float32; -- register stages
variable in1reg2, in2reg2 : float32; -- register stages
begin -- process mulreg
if rst_n = '0' then -- asynchronous reset (active low)
in1reg := ( others => '0');
in2reg := ( others => '0');
in1reg2 := ( others => '0');
in2reg2 := ( others => '0');
in1reg3 <= ( others => '0');
in2reg3 <= ( others => '0');
out1 <= ( others => '0');
outreg := (others => '0');
rcloop: for i in 1 to 15 loop
cmdarray (i) <= (others => '0');
end loop rcloop;
elsif rising_edge(clk) then -- rising clock edge
out1 <= to_slv (outreg);
outregc: case cmdarray (13) is
when "0000" => outreg := outx (0);
when "0001" => outreg := outx (1);
when "0010" => outreg := outx (2);
when "0011" => outreg := outx (3);
when "0100" => outreg := outx (4);
when "0101" => outreg := outx (5);
when "0110" => outreg := outx (6);
when "0111" => outreg := outx (7);
when "1000" => outreg := outx (8);
when "1001" => outreg := outx (9);
when "1010" => outreg := outx (10);
when "1011" => outreg := outx (11);
when "1100" => outreg := outx (12);
when "1101" => outreg := outx (13);
when "1110" => outreg := outx (14);
when "1111" => outreg := outx (15);
when others => null;
end case outregc;
cmdpipe: for i in 15 downto 3 loop
cmdarray (i) <= cmdarray (i-1);
end loop cmdpipe;
cmdarray (2) <= std_ulogic_vector(cmd);
in1reg3 <= in1reg2;
in2reg3 <= in2reg2;
in1reg2 := in1reg;
in2reg2 := in2reg;
in1reg := to_float (in1, in1reg);
in2reg := to_float (in2, in2reg);
end if;
end process cmdreg;
end architecture rtl;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY dll_img_ram IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END dll_img_ram;
ARCHITECTURE dll_img_ram_arch OF dll_img_ram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dll_img_ram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dll_img_ram_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dll_img_ram_arch : ARCHITECTURE IS "dll_img_ram,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dll_img_ram_arch: ARCHITECTURE IS "dll_img_ram,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=dll_img_ram.mif,C_INIT_FILE=dll_img_ram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=65536,C_READ_DEPTH_A=65536,C_ADDRA_WIDTH=16,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=65536,C_READ_DEPTH_B=65536,C_ADDRB_WIDTH=16,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=NONE,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=1,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=1,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.114201 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 0,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "dll_img_ram.mif",
C_INIT_FILE => "dll_img_ram.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 65536,
C_READ_DEPTH_A => 65536,
C_ADDRA_WIDTH => 16,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 65536,
C_READ_DEPTH_B => 65536,
C_ADDRB_WIDTH => 16,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "NONE",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 1,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 1,
C_COUNT_36K_BRAM => "16",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.114201 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END dll_img_ram_arch;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_19 is
port (
clock : in std_logic;
token_in : in std_logic_vector(18 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc_19;
architecture Gideon of token_crc_19 is
-- CRC-5 = x5 + x2 + 1
constant polynom : std_logic_vector(4 downto 0) := "00101";
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
L1: for i in token_in'reverse_range loop -- LSB first!
d := token_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & '0';
if d = '1' then
tmp := tmp xor polynom;
end if;
tmp(0) := d;
end loop;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_19 is
port (
clock : in std_logic;
token_in : in std_logic_vector(18 downto 0);
crc : out std_logic_vector(4 downto 0) );
end token_crc_19;
architecture Gideon of token_crc_19 is
-- CRC-5 = x5 + x2 + 1
constant polynom : std_logic_vector(4 downto 0) := "00101";
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
tmp := (others => '1');
L1: for i in token_in'reverse_range loop -- LSB first!
d := token_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & '0';
if d = '1' then
tmp := tmp xor polynom;
end if;
tmp(0) := d;
end loop;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
|
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: Zoltan Pekic (zpekic@hotmail.com)
--
-- Create Date: 15:42:44 02/20/2016
-- Design Name:
-- Module Name: fourdigitsevensegled - Behavioral
-- Project Name: Alarm Clock
-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
-- Tool versions: Xilinx ISE 14.7 (nt64)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fourdigitsevensegled is
Port ( -- inputs
data : in STD_LOGIC_VECTOR (15 downto 0);
digsel : in STD_LOGIC_VECTOR (1 downto 0);
showdigit : in STD_LOGIC_VECTOR (3 downto 0);
showdot : in STD_LOGIC_VECTOR (3 downto 0);
showsegments : in STD_LOGIC;
-- outputs
anode : out STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (7 downto 0)
);
end fourdigitsevensegled;
architecture structural of fourdigitsevensegled is
component nibble2sevenseg is
Port ( nibble : in STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
component mux16to4
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c : in STD_LOGIC_VECTOR (3 downto 0);
d : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
nEnable : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal internalsegment: std_logic_vector(7 downto 0); -- 7th is the dot!
signal internalsel: std_logic_vector(3 downto 0);
signal digit: std_logic_vector(3 downto 0);
begin
-- decode position
internalsel(3) <= digsel(1) and digsel(0);
internalsel(2) <= digsel(1) and (not digsel(0));
internalsel(1) <= (not digsel(1)) and digsel(0);
internalsel(0) <= (not digsel(1)) and (not digsel(0));
-- select 1 digit out of 4 incoming
digitmux: mux16to4 port map (
a => data(3 downto 0),
b => data(7 downto 4),
c => data(11 downto 8),
d => data(15 downto 12),
nEnable => '0',
sel => digsel,
y => digit
);
-- set the anodes with digit blanking
anode(3) <= not (internalsel(3) and showdigit(3));
anode(2) <= not (internalsel(2) and showdigit(2));
anode(1) <= not (internalsel(1) and showdigit(1));
anode(0) <= not (internalsel(0) and showdigit(0));
-- hook up the cathodes
sevensegdriver: nibble2sevenseg port map (
nibble => digit,
segment => internalsegment(6 downto 0)
);
-- set cathodes with blanking (seg7 == dot)
segment(7) <= (not showsegments) or ((internalsel(3) and not showdot(3)) or (internalsel(2) and not showdot(2)) or (internalsel(1) and not showdot(1)) or (internalsel(0) and not showdot(0)));
segs: for i in 6 downto 0 generate
segment(i) <= (not showsegments) or internalsegment(i);
end generate;
end structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC_Mux is
Port ( clk : in STD_LOGIC;
PcSource : in STD_LOGIC_VECTOR (1 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
Pc : in STD_LOGIC_VECTOR (31 downto 0);
Pc_Disp22 : in STD_LOGIC_VECTOR (31 downto 0);
Pc_Disp30 : in STD_LOGIC_VECTOR (31 downto 0);
nPC_Source : out STD_LOGIC_VECTOR (31 downto 0));
end PC_Mux;
architecture Behavioral of PC_Mux is
begin
process(clk)
begin
if rising_edge(clk)then
case PcSource is
when "00" =>
nPC_Source <= Pc;
when "01" =>
nPC_Source <= Pc_Disp22;
when "10" =>
nPC_Source <= Pc_Disp30;
when "11" =>
nPC_Source <= AluResult;
when others =>
nPC_Source <= Pc;
end case;
end if;
end process;
end Behavioral; |
configuration TESTBENCH_FOR_var5 of var5_tb is
for TB_ARCHITECTURE
for UUT : var5
use entity work.var5(behavior);
end for;
for UUT2 : var5
use entity work.var5(structual);
end for;
end for;
end TESTBENCH_FOR_var5; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Bresenhamer is
Port ( WriteEnable : out STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0);
Y : out STD_LOGIC_VECTOR (8 downto 0);
X1 : in STD_LOGIC_VECTOR (9 downto 0);
Y1 : in STD_LOGIC_VECTOR (8 downto 0);
X2 : in STD_LOGIC_VECTOR (9 downto 0);
Y2 : in STD_LOGIC_VECTOR (8 downto 0);
SS : out STD_LOGIC_VECTOR (3 downto 0);
Clk : in STD_LOGIC;
StartDraw : in STD_LOGIC;
dbg : out STD_LOGIC_VECTOR (11 downto 0);
Reset : in STD_LOGIC);
end Bresenhamer;
architecture Behavioral of Bresenhamer is
signal myX1,myX2 : STD_LOGIC_VECTOR (11 downto 0);
signal myY1,myY2 : STD_LOGIC_VECTOR (11 downto 0);
signal p,p0_1,p0_2,p0_3,p0_4,p0_5,p0_6,p0_7,p0_8 : STD_LOGIC_VECTOR (11 downto 0);
signal p_1,p_2,p_3,p_4,p_5,p_6,p_7,p_8 : STD_LOGIC_VECTOR (11 downto 0);
signal ndx,ndy : STD_LOGIC_VECTOR (11 downto 0);
signal dx,dy,t_2dx,t_2dy,neg_dx,neg_dy,t_2neg_dx,t_2neg_dy : STD_LOGIC_VECTOR (11 downto 0);
signal dx_minus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal minus_dx_minus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal minus_dx_plus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal dx_plus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal State : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal condX1X2,condY1Y2 : STD_LOGIC;
signal ccounter : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000000";
constant IDLE : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant INIT : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant CASE1 : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant CASE2 : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant CASE3 : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant CASE4 : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant CASE5 : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant CASE6 : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant CASE7 : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant CASE8 : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant CLEAR : STD_LOGIC_VECTOR(3 downto 0) := "1010";
begin
ndx <= ("00" & X2)-("00" & X1);
ndy <= ("000" & Y2)-("000" & Y1);
neg_dx <= 0-dx;
neg_dy <= 0-dy;
dbg <= p;
dx_minus_dy <= dx+neg_dy;
minus_dx_minus_dy <= neg_dx+neg_dy;
minus_dx_plus_dy <= neg_dx+dy;
dx_plus_dy <= dx+dy;
t_2dy <= dy(10 downto 0) & '0';
t_2dx <= dx(10 downto 0) & '0';
t_2neg_dy <= neg_dy(10 downto 0) & '0';
t_2neg_dx <= neg_dx(10 downto 0) & '0';
p0_1 <= t_2dy+neg_dx;
p0_2 <= t_2dx+neg_dy;
p0_3 <= t_2neg_dx+dy;
p0_4 <= t_2dy+neg_dx;
p0_5 <= t_2neg_dy+dx;
p0_6 <= t_2neg_dx+dy;
p0_7 <= t_2dx+neg_dy;
p0_8 <= t_2neg_dy+dx;
p_1 <= p+t_2dy when p(11)='1' else p+t_2dy+t_2neg_dx;
p_2 <= p+t_2dx when p(11)='1' else p+t_2dx+t_2neg_dy;
p_3 <= p+t_2neg_dx when p(11)='1' else p+t_2neg_dx+t_2neg_dy;
p_4 <= p+t_2dy when p(11)='1' else p+t_2dy+t_2dx;
p_5 <= p+t_2neg_dy when p(11)='1' else p+t_2neg_dy+t_2dx;
p_6 <= p+t_2neg_dx when p(11)='1' else p+t_2neg_dx+t_2dy;
p_7 <= p+t_2dx when p(11)='1' else p+t_2dx+t_2dy;
p_8 <= p+t_2neg_dy when p(11)='1' else p+t_2neg_dy+t_2neg_dx;
X <= ccounter(9 downto 0) when State = CLEAR else myX1(9 downto 0);
Y <= ccounter(18 downto 10) when State = CLEAR else myY1(8 downto 0);
SS <= State;
WriteEnable <= '0' when State = IDLE or State = INIT else '1';
process (Clk) begin
if (rising_edge(Clk)) then
if (State = IDLE) then
if (Reset = '1') then
State <= CLEAR;
ccounter <= (others=>'0');
elsif (StartDraw = '1') then
myX1(9 downto 0) <= X1;
myX1(11 downto 10) <= "00";
myY1(8 downto 0) <= Y1;
myY1(11 downto 9) <= "000";
myX2(9 downto 0) <= X2;
myX2(11 downto 10) <= "00";
myY2(8 downto 0) <= Y2;
myY2(11 downto 9) <= "000";
dx <= ndx;
dy <= ndy;
State <= INIT;
end if;
elsif (State = INIT) then
if (dx(11) = '0' and dy(11) = '0' and dx_minus_dy(11) = '0') then
State <= CASE1;
p <= p0_1;
elsif (dx(11) = '0' and dy(11) = '0' and dx_minus_dy(11) = '1') then
State <= CASE2;
p <= p0_2;
elsif (dx(11) = '1' and dy(11) = '0' and minus_dx_minus_dy(11) = '1') then
State <= CASE3;
p <= p0_3;
elsif (dx(11) = '1' and dy(11) = '0' and minus_dx_minus_dy(11) = '0') then
State <= CASE4;
p <= p0_4;
elsif (dx(11) = '1' and dy(11) = '1' and minus_dx_plus_dy(11) = '0') then
State <= CASE5;
p <= p0_5;
elsif (dx(11) = '1' and dy(11) = '1' and minus_dx_plus_dy(11) = '1') then
State <= CASE6;
p <= p0_6;
elsif (dx(11) = '0' and dy(11) = '1' and dx_plus_dy(11) = '1') then
State <= CASE7;
p <= p0_7;
else
State <= CASE8;
p <= p0_8;
end if;
elsif (State = CASE1) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 + 1;
p <= p_1;
if (P(11) = '0') then
myY1 <= myY1 + 1;
end if;
end if;
elsif (State = CASE2) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 + 1;
p <= p_2;
if (P(11) = '0') then
myX1 <= myX1 + 1;
end if;
end if;
elsif (State = CASE3) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 + 1;
p <= p_3;
if (P(11) = '0') then
myX1 <= myX1 - 1;
end if;
end if;
elsif (State = CASE4) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 - 1;
p <= p_4;
if (P(11) = '0') then
myY1 <= myY1 + 1;
end if;
end if;
elsif (State = CASE5) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 - 1;
p <= p_5;
if (P(11) = '0') then
myY1 <= myY1 - 1;
end if;
end if;
elsif (State = CASE6) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 - 1;
p <= p_6;
if (P(11) = '0') then
myX1 <= myX1 - 1;
end if;
end if;
elsif (State = CASE7) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 - 1;
p <= p_7;
if (P(11) = '0') then
myX1 <= myX1 + 1;
end if;
end if;
elsif (State = CASE8) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 + 1;
p <= p_8;
if (P(11) = '0') then
myY1 <= myY1 - 1;
end if;
end if;
elsif (State = CLEAR) then
ccounter <= ccounter + 1;
if (ccounter = "1111111111111111111") then
State <= IDLE;
end if;
end if;
end if;
end process;
end Behavioral;
|
component finalproject is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
keycode_export : out std_logic_vector(7 downto 0); -- export
usb_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_RD_N : out std_logic; -- RD_N
usb_WR_N : out std_logic; -- WR_N
usb_CS_N : out std_logic; -- CS_N
usb_RST_N : out std_logic; -- RST_N
usb_INT : in std_logic := 'X'; -- INT
sdram_out_clk_clk : out std_logic; -- clk
usb_out_clk_clk : out std_logic -- clk
);
end component finalproject;
u0 : component finalproject
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
keycode_export => CONNECTED_TO_keycode_export, -- keycode.export
usb_DATA => CONNECTED_TO_usb_DATA, -- usb.DATA
usb_ADDR => CONNECTED_TO_usb_ADDR, -- .ADDR
usb_RD_N => CONNECTED_TO_usb_RD_N, -- .RD_N
usb_WR_N => CONNECTED_TO_usb_WR_N, -- .WR_N
usb_CS_N => CONNECTED_TO_usb_CS_N, -- .CS_N
usb_RST_N => CONNECTED_TO_usb_RST_N, -- .RST_N
usb_INT => CONNECTED_TO_usb_INT, -- .INT
sdram_out_clk_clk => CONNECTED_TO_sdram_out_clk_clk, -- sdram_out_clk.clk
usb_out_clk_clk => CONNECTED_TO_usb_out_clk_clk -- usb_out_clk.clk
);
|
-------------------------------------------------------------------------------
--! @file registerFileRtl.vhd
--
--! @brief Register table file implementation
--
--! @details This implementation is a simple dual ported memory implemented in
--! using register resources.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity registerFile is
generic (
gRegCount : natural := 8
);
port (
iClk : in std_logic;
iRst : in std_logic;
iWriteA : in std_logic;
iWriteB : in std_logic;
iByteenableA: in std_logic_vector;
iByteenableB: in std_logic_vector;
iAddrA : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iAddrB : in std_logic_vector(LogDualis(gRegCount)-1 downto 0);
iWritedataA : in std_logic_vector;
oReaddataA : out std_logic_vector;
iWritedataB : in std_logic_vector;
oReaddataB : out std_logic_vector
);
end registerFile;
architecture Rtl of registerFile is
constant cByte : natural := 8;
type tRegSet is
array (natural range <>) of std_logic_vector(iWritedataA'range);
signal regFile, regFile_next : tRegSet(gRegCount-1 downto 0);
begin
--register set
reg : process(iClk)
begin
if rising_edge(iClk) then
if iRst = cActivated then
--clear register file
regFile <= (others => (others => '0'));
else
regFile <= regFile_next;
end if;
end if;
end process;
--write data into Register File with respect to address
--note: a overrules b
regFileWrite : process(
iWriteA, iWriteB, iAddrA, iAddrB,
iByteenableA, iByteenableB,
iWritedataA, iWritedataB, regFile)
variable vWritedata : std_logic_vector(iWritedataA'range);
begin
--default
regFile_next <= regFile;
vWritedata := (others => cInactivated);
if iWriteB = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrB)));
--then consider byteenable
for i in iWritedataB'range loop
if iByteenableB(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataB(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrB))) <= vWritedata;
end if;
if iWriteA = cActivated then
--read out register content first
vWritedata := regFile(to_integer(unsigned(iAddrA)));
--then consider byteenable
for i in iWritedataA'range loop
if iByteenableA(i/cByte) = cActivated then
--if byte is enabled assign it
vWritedata(i) := iWritedataA(i);
end if;
end loop;
--write to address the masked writedata
regFile_next(to_integer(unsigned(iAddrA))) <= vWritedata;
end if;
end process;
--read data from Register File with respect to iAddrRead
regFileRead : process(iAddrA, iAddrB, regFile)
begin
--read from address
oReaddataA <= regFile(to_integer(unsigned(iAddrA)));
oReaddataB <= regFile(to_integer(unsigned(iAddrB)));
end process;
end Rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle_tb is
end single_cycle_tb;
architecture behv of single_cycle_tb is
component single_cycle
port (
clk : in std_logic;
program_counter : out std_logic_vector(31 downto 0);
instruction : out std_logic_vector(31 downto 0);
ALUsrc_out : out std_logic;
RegDst_out : out std_logic;
RegWrite_out : out std_logic;
pc_rst : in std_logic;
shdir_out : out std_logic;
shamt_out : out std_logic_vector(4 downto 0);
ALUOp_out : out std_logic_vector(2 downto 0);
ALUControl_out : out std_logic_vector(3 downto 0);
RW_out : out std_logic_vector(4 downto 0);
RD1_out : out std_logic_vector(4 downto 0);
RD0_out : out std_logic_vector(4 downto 0);
RegFileOut1 : out std_logic_vector(31 downto 0);
RegFileOut0 : out std_logic_vector(31 downto 0);
Extend_out : out std_logic_vector(31 downto 0);
ALU_Result_out : out std_logic_vector(31 downto 0);
MemWrite_out : out std_logic;
C : out std_logic;
S : out std_logic;
V : out std_logic;
Z : out std_logic;
ExtOp_out : out std_logic
);
end component;
signal clk : std_logic := '0';
signal program_counter : std_logic_vector(31 downto 0);
signal instruction : std_logic_vector(31 downto 0);
signal ALUsrc_out : std_logic;
signal RegDst_out : std_logic;
signal RegWrite_out : std_logic;
signal MemWrite_out : std_logic;
signal pc_rst : std_logic;
signal shdir_out : std_logic;
signal shamt_out : std_logic_vector(4 downto 0);
signal ALUOp_out : std_logic_vector(2 downto 0);
signal ALUControl_out : std_logic_vector(3 downto 0);
signal RW_out : std_logic_vector(4 downto 0);
signal RD1_out : std_logic_vector(4 downto 0);
signal RD0_out : std_logic_vector(4 downto 0);
signal RegFileOut1 : std_logic_vector(31 downto 0);
signal RegFileOut0 : std_logic_vector(31 downto 0);
signal Extend_out : std_logic_vector(31 downto 0);
signal ALU_Result_out : std_logic_vector(31 downto 0);
signal C : std_logic;
signal S : std_logic;
signal V : std_logic;
signal Z : std_logic;
signal ExtOp_out : std_logic;
begin
single_cycle1: single_cycle
port map (
clk => clk,
program_counter => program_counter,
instruction => instruction,
ALUsrc_out => ALUsrc_out,
RegDst_out => RegDst_out,
RegWrite_out => RegWrite_out,
pc_rst => pc_rst,
shdir_out => shdir_out,
shamt_out => shamt_out,
ALUOp_out => ALUOp_out,
ALUControl_out => ALUControl_out,
RW_out => RW_out,
RD1_out => RD1_out,
RD0_out => RD0_out,
RegFileOut1 => RegFileOut1,
RegFileOut0 => RegFileOut0,
Extend_out => Extend_out,
ALU_Result_out => ALU_Result_out,
MemWrite_out => MemWrite_out,
C => C,
S => S,
V => V,
Z => Z,
Extop_out => ExtOp_out
);
clk <= not clk after 10 ns;
process
begin
pc_rst <= '1';
wait for 5 ns;
pc_rst <= '0';
wait;
end process;
end behv;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <johannes@wltr.io>
--
-- Description:
-- Triplicate data on write.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mem_data_triplicator_wr is
generic (
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- Memory interface
mem_wr_en_o : out std_ulogic;
mem_data_o : out std_ulogic_vector(width_g - 1 downto 0);
mem_done_i : in std_ulogic);
end entity mem_data_triplicator_wr;
architecture rtl of mem_data_triplicator_wr is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- FSM states
type state_t is (IDLE, A_WRITTEN, B_WRITTEN, C_WRITTEN);
-- FSM registers
type reg_t is record
state : state_t;
mem_wr_en : std_ulogic;
mem_data : std_ulogic_vector(width_g - 1 downto 0);
busy : std_ulogic;
done : std_ulogic;
end record reg_t;
-- FSM initial state
constant init_c : reg_t := (
state => IDLE,
mem_wr_en => '0',
mem_data => (others => '0'),
busy => '0',
done => '0');
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal reg : reg_t;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= reg.busy;
done_o <= reg.done;
mem_wr_en_o <= reg.mem_wr_en;
mem_data_o <= reg.mem_data;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- FSM registering
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
-- FSM combinatorics
comb : process(reg, wr_en_i, data_i, mem_done_i) is
begin -- process comb
-- Defaults
next_reg <= reg;
next_reg.mem_wr_en <= init_c.mem_wr_en;
next_reg.done <= init_c.done;
case reg.state is
when IDLE =>
if wr_en_i = '1' then
next_reg.mem_data <= data_i;
next_reg.mem_wr_en <= '1';
next_reg.busy <= '1';
next_reg.state <= A_WRITTEN;
end if;
when A_WRITTEN =>
if mem_done_i = '1' then
next_reg.mem_wr_en <= '1';
next_reg.state <= B_WRITTEN;
end if;
when B_WRITTEN =>
if mem_done_i = '1' then
next_reg.mem_wr_en <= '1';
next_reg.state <= C_WRITTEN;
end if;
when C_WRITTEN =>
if mem_done_i = '1' then
next_reg <= init_c;
next_reg.done <= '1';
end if;
end case;
end process comb;
end architecture rtl;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Trellis parameter calculations (e.g., transitions, init values).
--! @author Markus Fehrenz
--! @date 2011/07/27
--!
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
package pkg_trellis is
type t_prev_base is array (1 downto 0) of std_logic_vector(BW_TRELLIS_STATES - 1 downto 0);
type t_previous_states is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_prev_base;
type t_trans_base is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0);
type t_transitions is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base;
type t_trans_base_signed is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS downto 0);
type t_transitions_signed is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base_signed;
--
-- This function calculates the previous states of each state.
-- The values are used to connect the ACS units.
--
function calc_previous_states return t_previous_states;
--
-- This function calculates corresponding transitions to a trellis sate.
-- The values are used to connect branch units to ACS units.
--
function calc_transitions return t_transitions;
--
-- This function calculates the initialization values for trellis metrics.
-- The values are used as a constant and written to the ACS unit, every time a new block arrives.
--
function calc_initialize return t_node_s;
constant PREVIOUS_STATES : t_previous_states;
constant TRANSITIONS : t_transitions;
constant INITIALIZE_TRELLIS : t_node_s;
end package pkg_trellis;
package body pkg_trellis is
function calc_previous_states return t_previous_states is
variable v_prev_states : t_previous_states := (others=>(others=>(others => '0')));
variable v_state0, v_state1 : std_logic_vector(BW_TRELLIS_STATES - 1 downto 0);
begin
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
v_state0 := std_logic_vector(to_unsigned(i,BW_TRELLIS_STATES));
v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '0';
v_prev_states(i)(0) := v_state1;
v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '1';
v_prev_states(i)(1) := v_state1;
end loop;
return v_prev_states;
end function calc_previous_states;
function calc_transitions return t_transitions is
variable v_transitions : t_transitions_signed := (others => (others => (others => '0')));
variable v_transitions_out : t_transitions := (others => (others => (others => '0')));
variable v_one_transition : std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0);
variable v_next_state : unsigned(ENCODER_MEMORY_DEPTH - 1 downto 0) := (others => '0');
variable v_state, v_states : unsigned(ENCODER_MEMORY_DEPTH downto 0);
variable v_bit : std_logic := '0';
begin
--
-- It is possible to reduce code size at this stage, if feedback is handled differently,
-- but the complexity will increase.
--
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
--
-- for input : 0
-- determine correct input with feedback
--
v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH);
for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop
v_bit := v_bit xor v_next_state(k);
end loop;
v_state(ENCODER_MEMORY_DEPTH) := v_bit;
v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH);
v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1);
v_bit := '0';
-- determine paritybits
for j in NUMBER_PARITY_BITS - 1 downto 0 loop
v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1);
for k in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_states(k);
end loop;
v_one_transition(j) := v_bit;
v_bit := '0';
end loop;
-- decide where to save the parity result
if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1';
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
else
v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
end if;
--
-- for input: 1
-- determine correct input with feedback
--
v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH);
for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop
v_bit := v_bit xor v_next_state(k);
end loop;
v_state(ENCODER_MEMORY_DEPTH) := '1' xor v_bit;
v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH);
v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1);
v_bit := '0';
-- determine paritybits
for j in NUMBER_PARITY_BITS - 1 downto 0 loop
v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1);
for k in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_states(k);
end loop;
v_one_transition(j) := v_bit;
v_bit := '0';
end loop;
-- decide where to save parity result
if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1';
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
else
v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
end if;
end loop;
-- truncate, the bit, used to decide where to save parity result
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
v_transitions_out(i)(1) := v_transitions(i)(1)(NUMBER_PARITY_BITS - 1 downto 0);
v_transitions_out(i)(0) := v_transitions(i)(0)(NUMBER_PARITY_BITS - 1 downto 0);
end loop;
return v_transitions_out;
end function calc_transitions;
function calc_initialize return t_node_s is
variable v_initialize : t_node_s;
begin
v_initialize(0) := to_signed(0, BW_MAX_PROBABILITY);
for i in NUMBER_TRELLIS_STATES - 1 downto 1 loop
v_initialize(i) := to_signed(- 2 ** (BW_MAX_PROBABILITY - 2), BW_MAX_PROBABILITY);
end loop;
return v_initialize;
end function calc_initialize;
constant PREVIOUS_STATES : t_previous_states := calc_previous_states;
constant TRANSITIONS : t_transitions := calc_transitions;
constant INITIALIZE_TRELLIS : t_node_s := calc_initialize;
end package body pkg_trellis;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Trellis parameter calculations (e.g., transitions, init values).
--! @author Markus Fehrenz
--! @date 2011/07/27
--!
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
package pkg_trellis is
type t_prev_base is array (1 downto 0) of std_logic_vector(BW_TRELLIS_STATES - 1 downto 0);
type t_previous_states is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_prev_base;
type t_trans_base is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0);
type t_transitions is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base;
type t_trans_base_signed is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS downto 0);
type t_transitions_signed is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base_signed;
--
-- This function calculates the previous states of each state.
-- The values are used to connect the ACS units.
--
function calc_previous_states return t_previous_states;
--
-- This function calculates corresponding transitions to a trellis sate.
-- The values are used to connect branch units to ACS units.
--
function calc_transitions return t_transitions;
--
-- This function calculates the initialization values for trellis metrics.
-- The values are used as a constant and written to the ACS unit, every time a new block arrives.
--
function calc_initialize return t_node_s;
constant PREVIOUS_STATES : t_previous_states;
constant TRANSITIONS : t_transitions;
constant INITIALIZE_TRELLIS : t_node_s;
end package pkg_trellis;
package body pkg_trellis is
function calc_previous_states return t_previous_states is
variable v_prev_states : t_previous_states := (others=>(others=>(others => '0')));
variable v_state0, v_state1 : std_logic_vector(BW_TRELLIS_STATES - 1 downto 0);
begin
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
v_state0 := std_logic_vector(to_unsigned(i,BW_TRELLIS_STATES));
v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '0';
v_prev_states(i)(0) := v_state1;
v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '1';
v_prev_states(i)(1) := v_state1;
end loop;
return v_prev_states;
end function calc_previous_states;
function calc_transitions return t_transitions is
variable v_transitions : t_transitions_signed := (others => (others => (others => '0')));
variable v_transitions_out : t_transitions := (others => (others => (others => '0')));
variable v_one_transition : std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0);
variable v_next_state : unsigned(ENCODER_MEMORY_DEPTH - 1 downto 0) := (others => '0');
variable v_state, v_states : unsigned(ENCODER_MEMORY_DEPTH downto 0);
variable v_bit : std_logic := '0';
begin
--
-- It is possible to reduce code size at this stage, if feedback is handled differently,
-- but the complexity will increase.
--
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
--
-- for input : 0
-- determine correct input with feedback
--
v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH);
for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop
v_bit := v_bit xor v_next_state(k);
end loop;
v_state(ENCODER_MEMORY_DEPTH) := v_bit;
v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH);
v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1);
v_bit := '0';
-- determine paritybits
for j in NUMBER_PARITY_BITS - 1 downto 0 loop
v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1);
for k in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_states(k);
end loop;
v_one_transition(j) := v_bit;
v_bit := '0';
end loop;
-- decide where to save the parity result
if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1';
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
else
v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
end if;
--
-- for input: 1
-- determine correct input with feedback
--
v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH);
for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop
v_bit := v_bit xor v_next_state(k);
end loop;
v_state(ENCODER_MEMORY_DEPTH) := '1' xor v_bit;
v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH);
v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1);
v_bit := '0';
-- determine paritybits
for j in NUMBER_PARITY_BITS - 1 downto 0 loop
v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1);
for k in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_states(k);
end loop;
v_one_transition(j) := v_bit;
v_bit := '0';
end loop;
-- decide where to save parity result
if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1';
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
else
v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
end if;
end loop;
-- truncate, the bit, used to decide where to save parity result
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
v_transitions_out(i)(1) := v_transitions(i)(1)(NUMBER_PARITY_BITS - 1 downto 0);
v_transitions_out(i)(0) := v_transitions(i)(0)(NUMBER_PARITY_BITS - 1 downto 0);
end loop;
return v_transitions_out;
end function calc_transitions;
function calc_initialize return t_node_s is
variable v_initialize : t_node_s;
begin
v_initialize(0) := to_signed(0, BW_MAX_PROBABILITY);
for i in NUMBER_TRELLIS_STATES - 1 downto 1 loop
v_initialize(i) := to_signed(- 2 ** (BW_MAX_PROBABILITY - 2), BW_MAX_PROBABILITY);
end loop;
return v_initialize;
end function calc_initialize;
constant PREVIOUS_STATES : t_previous_states := calc_previous_states;
constant TRANSITIONS : t_transitions := calc_transitions;
constant INITIALIZE_TRELLIS : t_node_s := calc_initialize;
end package body pkg_trellis;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af_ram is
type mem_array is array (mem_size-1 downto 0) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array;
attribute ram_style : string;
attribute ram_style of mem : signal is mem_style;
begin
p_memory_read: process (clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(CONV_INTEGER(w_addr)) <= din;
end if;
dout <= mem(CONV_INTEGER(r_addr));
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af is
component nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end component;
signal mInPtr, mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal mInPtr_next, mOutPtr_next : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_raddr, ram_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_din, ram_dout : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff_valid : STD_LOGIC;
signal ram_we : STD_LOGIC;
signal wordUsed : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal internal_empty_n, internal_full_n: STD_LOGIC;
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
ram_din <= if_din;
process (wordUsed, conflict_buff_valid, conflict_buff, ram_dout)
begin
if ( wordUsed = 1 and conflict_buff_valid = '1' ) then
if_dout <= conflict_buff;
else
if_dout <= ram_dout;
end if;
end process;
process (mOutPtr)
begin
if ( mOutPtr < DEPTH -1 ) then
mOutPtr_next <= mOutPtr + 1;
else
mOutPtr_next <= (others => '0');
end if;
end process;
process (mInPtr)
begin
if ( mInPtr < DEPTH -1 ) then
mInPtr_next <= mInPtr + 1;
else
mInPtr_next <= (others => '0');
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
wordUsed <= (others => '0');
internal_empty_n <= '0';
internal_full_n <= '1';
conflict_buff <= (others => '0');
conflict_buff_valid <= '0';
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr_next;
end if;
if (if_write = '1') then
mInPtr <= mInPtr_next;
end if;
if (if_read = '1' and internal_empty_n = '1' and if_write = '0') then
wordUsed <= wordUsed -1;
if (wordUsed = 1) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif (if_read = '0' or internal_empty_n = '0') and
(if_write = '1') then
wordUsed <= wordUsed +1;
internal_empty_n <= '1';
if (wordUsed + ALMOST_FULL_MARGIN = DEPTH -1) then
internal_full_n <= '0';
end if;
end if;
conflict_buff <= if_din;
conflict_buff_valid <= if_write and internal_full_n;
end if;
end if;
end process;
ram_waddr <= mInPtr;
ram_raddr <= mOutPtr_next when if_read = '1' and internal_empty_n = '1' else mOutPtr;
-- if a read occur on the following clock edge, prepare next read data in advance
ram_we <= if_write; -- caller should check almost_full signal
U_nfa_forward_buckets_if_ap_fifo_af_ram : nfa_forward_buckets_if_ap_fifo_af_ram
generic map (
mem_style => MEM_STYLE,
dwidth => DATA_WIDTH,
awidth => ADDR_WIDTH,
mem_size => DEPTH)
port map (
clk => clk,
din => ram_din,
w_addr => ram_waddr,
we => ram_we,
r_addr => ram_raddr,
dout => ram_dout);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af_ram is
type mem_array is array (mem_size-1 downto 0) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array;
attribute ram_style : string;
attribute ram_style of mem : signal is mem_style;
begin
p_memory_read: process (clk)
begin
if (clk = '1' and clk'event) then
if (we = '1') then
mem(CONV_INTEGER(w_addr)) <= din;
end if;
dout <= mem(CONV_INTEGER(r_addr));
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_forward_buckets_if_ap_fifo_af is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of nfa_forward_buckets_if_ap_fifo_af is
component nfa_forward_buckets_if_ap_fifo_af_ram is
generic(
mem_style : string := "block";
dwidth : integer := 64;
awidth : integer := 6;
mem_size : integer := 64
);
port (
clk : in std_logic;
din : in std_logic_vector(dwidth-1 downto 0);
w_addr : in std_logic_vector(awidth-1 downto 0);
we : in std_logic;
r_addr : in std_logic_vector(awidth-1 downto 0);
dout : out std_logic_vector(dwidth-1 downto 0)
);
end component;
signal mInPtr, mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal mInPtr_next, mOutPtr_next : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_raddr, ram_waddr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal ram_din, ram_dout : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal conflict_buff_valid : STD_LOGIC;
signal ram_we : STD_LOGIC;
signal wordUsed : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
signal internal_empty_n, internal_full_n: STD_LOGIC;
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
ram_din <= if_din;
process (wordUsed, conflict_buff_valid, conflict_buff, ram_dout)
begin
if ( wordUsed = 1 and conflict_buff_valid = '1' ) then
if_dout <= conflict_buff;
else
if_dout <= ram_dout;
end if;
end process;
process (mOutPtr)
begin
if ( mOutPtr < DEPTH -1 ) then
mOutPtr_next <= mOutPtr + 1;
else
mOutPtr_next <= (others => '0');
end if;
end process;
process (mInPtr)
begin
if ( mInPtr < DEPTH -1 ) then
mInPtr_next <= mInPtr + 1;
else
mInPtr_next <= (others => '0');
end if;
end process;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
wordUsed <= (others => '0');
internal_empty_n <= '0';
internal_full_n <= '1';
conflict_buff <= (others => '0');
conflict_buff_valid <= '0';
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr_next;
end if;
if (if_write = '1') then
mInPtr <= mInPtr_next;
end if;
if (if_read = '1' and internal_empty_n = '1' and if_write = '0') then
wordUsed <= wordUsed -1;
if (wordUsed = 1) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif (if_read = '0' or internal_empty_n = '0') and
(if_write = '1') then
wordUsed <= wordUsed +1;
internal_empty_n <= '1';
if (wordUsed + ALMOST_FULL_MARGIN = DEPTH -1) then
internal_full_n <= '0';
end if;
end if;
conflict_buff <= if_din;
conflict_buff_valid <= if_write and internal_full_n;
end if;
end if;
end process;
ram_waddr <= mInPtr;
ram_raddr <= mOutPtr_next when if_read = '1' and internal_empty_n = '1' else mOutPtr;
-- if a read occur on the following clock edge, prepare next read data in advance
ram_we <= if_write; -- caller should check almost_full signal
U_nfa_forward_buckets_if_ap_fifo_af_ram : nfa_forward_buckets_if_ap_fifo_af_ram
generic map (
mem_style => MEM_STYLE,
dwidth => DATA_WIDTH,
awidth => ADDR_WIDTH,
mem_size => DEPTH)
port map (
clk => clk,
din => ram_din,
w_addr => ram_waddr,
we => ram_we,
r_addr => ram_raddr,
dout => ram_dout);
end rtl;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity tute0 is port(
clk_clk, clk_reset_n: in std_ulogic;
xx: in u8; -- reg
yy: in u8; -- reg
someUnused: in u8; -- WIRE
sum: out u8; -- reg
totalSum: out u8; -- reg
outXorWire: out u8; -- WIRE
outLatch: out u8 -- Latch
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- tute0 ------------------------------------
architecture rtl of tute0 is
signal dg_o_sum: u8; -- reg
signal dg_o_totalSum: u8; -- reg
signal dg_o_outXorWire: u8; -- WIRE
signal dg_o_outLatch: u8; -- LATCH!!!
signal counter: u4; -- reg
begin
dg_comb_proc1_comb: process (all)
begin
dg_o_outLatch <= dg_o_outLatch; -- latch preload
if (dg_boolToBit(xx = X"55") = '1') then
dg_o_outLatch <= yy;
end if;
end process;
MyProcess_comb: process (all)
variable varSum: u8;
begin
dg_o_outXorWire <= X"00"; -- wire pre-zero-init
varSum := X"00"; -- local-var zero-init
varSum := (xx + yy);
dg_o_outXorWire <= (xx xor yy);
end process;
MyProcess: process
variable varSum: u8;
begin
wait until rising_edge(clk_clk)
varSum := X"00"; -- local-var zero-init
varSum := (xx + yy);
dg_o_sum <= varSum;
dg_o_totalSum <= (dg_o_totalSum + varSum);
if (dg_boolToBit(counter = X"5") = '1') then
dg_o_totalSum <= varSum;
end if;
counter <= counter + X"1";
if clk_reset_n = '0' then
dg_o_totalSum <= X"00";
counter <= X"0";
end if;
end process;
------[ output registers/wires/latches ] --------------
sum <= dg_o_sum;
totalSum <= dg_o_totalSum;
outXorWire <= dg_o_outXorWire;
outLatch <= dg_o_outLatch;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench_pw_string is
end testbench_pw_string;
architecture testbench_arch_pw_string of testbench_pw_string is
signal clk : std_logic;
signal enable : std_logic;
signal push_pop : std_logic;
signal char : character;
signal pwd : string (1 to 5);
component pw_string
port (
char : in character;
pwd : out string;
enable: in std_logic;
push_pop : in std_logic;
clk : in std_logic
);
end component;
begin
final_string : pw_string port map (
char => char,
pwd => pwd,
enable => enable,
push_pop => push_pop,
clk => clk
);
process
begin
-- --------------------
clk <= transport '0';
push_pop <= transport '1';
enable <= transport '1';
char <= transport 'a';
-- --------------------
WAIT FOR 110 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
assert pwd(1) = 'a';
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(2) = 'a';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'b';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(3) = 'b';
enable <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'c';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(3) = 'b';
assert pwd(4) = nul;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'd';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
enable <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(4) = 'd' ;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'e';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(5) = 'e' ;
push_pop <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'f';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(5) = nul ;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'g';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
char <= transport 'h';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
char <= transport 'i';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(1) = nul ;
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
push_pop <= transport '1';
char <= transport 'j';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
assert pwd(1) = 'j' ;
char <= transport 'k';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
char <= transport 'l';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
char <= transport 'm';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '1';
-- --------------------
WAIT FOR 10 ns;
clk <= transport '0';
-- --------------------
WAIT;
end process;
end testbench_arch_pw_string;
|
-- this test program aborts during analysis
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
signal host_write : bit;
begin
process
procedure host_write is
begin
end host_write;
begin
host_write <= '1';
end process;
end behav;
|
-- this test program aborts during analysis
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
signal host_write : bit;
begin
process
procedure host_write is
begin
end host_write;
begin
host_write <= '1';
end process;
end behav;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: police_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY police_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE police_synth_ARCH OF police_synth IS
COMPONENT police_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: police_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--This should pass
context c1 is
end context c1;
context c1 is
end context;
--This should fail
context c1 is
end context;
context c1 is
end context
;
-- Split declaration across lines
context
c1
is
end
context
;
|
-- NEED RESULT: ARCH00275: Don't need to completely specify configuration items in block configurations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00275
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.3.1 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00275_1(ARCH00275_1)
-- ENT00275(ARCH00275)
-- CONF00275
-- ENT00275_Test_Bench(ARCH00275_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
entity ENT00275_1 is
generic ( g1 : integer ) ;
port ( s1 : out integer ) ;
begin
end ENT00275_1 ;
architecture ARCH00275_1 of ENT00275_1 is
begin
s1 <= g1 ;
end ARCH00275_1 ;
entity ENT00275 is
generic ( g10, g11, g12, g13 : integer ) ;
port ( s10, s11, s12, s13 : out integer ) ;
end ENT00275 ;
architecture ARCH00275 of ENT00275 is
component COMP1
end component ;
for C1 : COMP1 use entity WORK.ENT00275_1 ( ARCH00275_1 )
generic map ( g10 )
port map ( s10 ) ;
for CIS1 : COMP1 use entity WORK.ENT00275_1 ( ARCH00275_1 )
generic map ( g13 )
port map ( s13 ) ;
begin
C1 : COMP1;
B1_1 :
block
begin
B2_2 :
block
for CIS1 : COMP1 use entity WORK.ENT00275_1 ( ARCH00275_1 )
generic map ( g11 )
port map ( s11 ) ;
begin
CIS1 : COMP1;
end block B2_2 ;
B2_3 :
block
begin
B3_4 :
block
begin
CIS1 : COMP1;
end block B3_4 ;
end block B2_3 ;
end block B1_1 ;
CIS1 : COMP1;
end ARCH00275 ;
configuration CONF00275 of WORK.ENT00275 is
for ARCH00275
for C1 : COMP1
end for ;
for B1_1
for B2_3
for B3_4
for CIS1 : COMP1 -- 3 deep
use entity WORK.ENT00275_1 ( ARCH00275_1 )
generic map ( g12 )
port map ( s12 ) ;
end for ; -- B3_4 component
end for ; -- B3_4
end for ; -- B2_3
end for ; -- B1_1
end for ;
end CONF00275 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00275_Test_Bench is
end ENT00275_Test_Bench ;
architecture ARCH00275_Test_Bench of ENT00275_Test_Bench is
begin
L1:
block
constant c1 : integer := 1 ;
constant c2 : integer := 2 ;
constant c3 : integer := 3 ;
constant c4 : integer := 4 ;
signal s1, s2, s3, s4 : integer ;
component UUT
generic ( g10, g11, g12, g13 : integer ) ;
port ( s10, s11, s12, s13 : out integer ) ;
end component ;
for CIS1 : UUT use configuration WORK.CONF00275 ;
begin
CIS1 : UUT
generic map ( c1, c2, c3, c4 )
port map ( s1, s2, s3, s4 ) ;
P00275 :
process ( s1, s2, s3, s4 )
begin
if s1 = c1 and s2 = c2 and s3 = c3 and s4 = c4 then
test_report ( "ARCH00275" ,
"Don't need to completely specify configuration items"
& " in block configurations" ,
true ) ;
end if ;
end process P00275 ;
end block L1 ;
end ARCH00275_Test_Bench ;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic
) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic
) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic
) is
begin
end procedure proc_name;
begin
end architecture RTL;
|
-- Clock_manual(button 0) = PIN_R22
-- CLock_27 = PIN_D12
-- Top Level Structural Model for MIPS Processor Core
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MIPS IS
PORT(
reset, clock_27,clock_manual : IN STD_LOGIC;
switch : IN STD_LOGIC_VECTOR(9 downto 0);
Branch_out, Zero_out, LessThanZeroOut, BranchLessThanZeroOut : OUT STD_LOGIC;
flush_out,flushP_out : OUT STD_LOGIC;
resetOut, clockOut : OUT STD_LOGIC;
sevenSegmentVector4Out : OUT std_logic_vector(27 downto 0));
END MIPS;
ARCHITECTURE structure OF MIPS IS
COMPONENT Ifetch
PORT(
Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_plus_4_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
PC_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
correct : OUT STD_LOGIC_VECTOR( 15 downto 0);
wrong : OUT STD_LOGIC_VECTOR( 15 downto 0);
--Branch Signals
Branch : IN STD_LOGIC;
Zero : IN STD_LOGIC;
BranchLessThanZero: IN STD_LOGIC;
LessThanZero : IN STD_LOGIC;
Add_result : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
clock,reset : IN STD_LOGIC );
END COMPONENT;
--------------------------------------------------------
COMPONENT Idecode
PORT( read_data_1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Sign_extend : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
-----Registers output-------------------------------
registerT0 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT3 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT4 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT5 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT6 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT7 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT8 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
registerT9 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
------------------------------------------------------
write_register_addressToMemory : OUT STD_LOGIC_VECTOR(4 downto 0);
flushP : IN STD_LOGIC;
----------------
alu_result0 : IN STD_LOGIC_vector(31 downto 0);
RegWrite0 : IN STD_LOGIC;
write_register_addressFromMemory0: IN STD_LOGIC_VECTOR(4 downto 0);
MemToReg0 : IN STD_LOGIC;
stall : OUT STD_LOGIC;
---------------
write_register_addressFromMemory: IN STD_LOGIC_VECTOR(4 downto 0);
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
RegWrite : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
clock, reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT control
PORT(
ALUSrc : OUT STD_LOGIC;
ALUop : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
MemtoReg : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC;
RegDst : OUT STD_LOGIC;
--Branch Signals
Branch : OUT STD_LOGIC;
BranchLessThanZero: OUT STD_LOGIC;
--flush
flush : OUT STD_LOGIC;
flushP : IN STD_LOGIC;
Zero : IN STD_LOGIC;
LessThanZero : IN STD_LOGIC;
Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT Execute
PORT( --Branch Signals
Zero : OUT STD_LOGIC;
LessThanZero : OUT STD_LOGIC;
ALU_Result : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Add_result : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Read_data_1 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Read_data_2 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Sign_Extend : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Function_opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
ALUOp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 );
ALUSrc : IN STD_LOGIC;
flushP : IN STD_LOGIC;
PC_plus_4 : IN STD_LOGIC_VECTOR( 9 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END COMPONENT;
--------------------------------------------------------
COMPONENT dmemory
PORT( read_data : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
alu_result : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
MemRead, Memwrite,MemToReg : IN STD_LOGIC;
Clock,reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT sevenSegment4
PORT( numberDesired4 : in std_logic_vector(15 downto 0);
sevenSegmentVector4 : out std_logic_vector(27 downto 0);
clock, reset : in std_logic);
END COMPONENT;
---------------- declare signals used to connect VHDL components---------------------
--Clock
SIGNAL clock : STD_LOGIC;
--IFE
SIGNAL PC : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
--IFE to IDE
SIGNAL Instruction : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--IFE to EXE
SIGNAL PC_plus_4 : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
--IDE
SIGNAL registerT0 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT2 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT3 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT4 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT5 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT6 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT7 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT8 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL registerT9 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--IDE to EXE
SIGNAL read_data_1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL Sign_extend : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--EXE to IFE
SIGNAL Add_result : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Zero : STD_LOGIC;
SIGNAL LessThanZero : STD_LOGIC;
--EXE to (IDE and DMEM)
SIGNAL ALU_result : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--(IDE) to (EXE and DMEM)
SIGNAL read_data_2 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--DMEM to IDE
SIGNAL read_data : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
--CONTROL to IFE
SIGNAL Branch : STD_LOGIC;
SIGNAL BranchLessThanZero:STD_LOGIC;
--CONTROL to IDE
SIGNAL RegDst : STD_LOGIC;
SIGNAL RegWrite : STD_LOGIC;
SIGNAL MemtoReg : STD_LOGIC;
--CONTROL to EXE
SIGNAL ALUSrc : STD_LOGIC;
SIGNAL ALUop : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
--CONTROL to DMEM
SIGNAL MemWrite : STD_LOGIC;
SIGNAL MemRead : STD_LOGIC;
--sevenSegment4
SIGNAL sevenSegmentVector4:STD_LOGIC_VECTOR( 27 DOWNTO 0 );
--Our pipe: IF / ID-EX / DMEM / WB
--Pipe between IFE and (IDE-EXE)
SIGNAL branchP : STD_LOGIC;
SIGNAL ZeroP : STD_LOGIC;
SIGNAL BranchLessThanZeroP : STD_LOGIC;
SIGNAL LessThanZeroP : STD_LOGIC;
SIGNAL Add_resultP : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL InstructionP : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL PC_plus_4_outP : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
--Pipe between (IDE-EXE-CONTROL) and (DMEM)
SIGNAL ALU_resultP : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL read_data_2P : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL MemWriteP : STD_LOGIC;
SIGNAL MemReadP : STD_LOGIC;
SIGNAL MemToRegP : STD_LOGIC;
SIGNAL RegWriteP : STD_LOGIC;
SIGNAL write_register_addressP: STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_register_address : STD_LOGIC_VECTOR(4 downto 0);
--Pipe between (DMEM) and (WB)
SIGNAL read_dataP : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL RegWritePP : STD_LOGIC;
SIGNAL write_register_addressPP : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
--flush
SIGNAL flush : STD_LOGIC;
SIGNAL flushP : STD_LOGIC;
--stall
SIGNAL stall : STD_LOGIC;
--Branch Prediction Accuracy (static always not-taken)
SIGNAL correct : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL wrong : STD_LOGIC_VECTOR(15 downto 0);
--End of Our pipe: IF / ID-EX / DMEM / WB
--Number to display on the 7-segment display
SIGNAL numberDesiredToDisplay : STD_LOGIC_VECTOR(15 downto 0);
BEGIN
process
BEGIN
WAIT UNTIL falling_edge(clock);--clock'EVENT AND clock = '0';
--if(reset='1') then
if(reset='0') then
branchP <= '0';
ZeroP <= '0';
BranchLessThanZeroP <= '0';
LessThanZeroP <= '0';
Add_resultP <= "00000000";
InstructionP <= "00000000000000000000000000000000";
PC_plus_4_outP <= "0000000000";
--------------
ALU_resultP <= "00000000000000000000000000000000";
read_data_2P <= "00000000000000000000000000000000";
MemWriteP <= '0';
MemReadP <= '0';
MemToRegP <= '0';
RegWriteP <= '0';
write_register_addressP <= "00000";
--------------
read_dataP <= "00000000000000000000000000000000";
RegWritePP <= '0';
write_register_addressPP <= "00000";
--------------
flushP <= '0';
elsif (stall='1') then
branchP <= '1';
ZeroP <= '1';
BranchLessThanZeroP <= '0';
LessThanZeroP <= '0';
Add_resultP <= PC(9 downto 2);
--InstructionP <= "00000000000000000000000000000000";
--PC_plus_4_outP <= "0000000000";
--------------------
----------------------
read_dataP <= read_data;
RegWritePP <= RegWriteP;
write_register_addressPP <= write_register_addressP;
----------------------
--------------------
ALU_resultP <= "00000000000000000000000000000000";
read_data_2P <= "00000000000000000000000000000000";
MemWriteP <= '0';
MemReadP <= '0';
MemToRegP <= '0';
RegWriteP <= '0';
write_register_addressP <= "00000";
flushP <= '0';
else
branchP <= branch;
ZeroP <= Zero;
BranchLessThanZeroP <= BranchLessThanZero;
LessThanZeroP <= LessThanZero;
Add_resultP <= Add_result;
InstructionP <= Instruction;
PC_plus_4_outP <= PC_plus_4;
--------------------
----------------------
read_dataP <= read_data;
RegWritePP <= RegWriteP;
write_register_addressPP <= write_register_addressP;
----------------------
--------------------
ALU_resultP <= ALU_result;
read_data_2P <= read_data_2;
MemWriteP <= MemWrite;
MemReadP <= MemRead;
MemToRegP <= MemToReg;
RegWriteP <= RegWrite;
write_register_addressP <= write_register_address;
flushP <= flush;
end if;
end process;
process (clock_27,clock_manual,switch,registerT0,registerT1,registerT2,registerT3,registerT4,registerT5,registerT6,registerT7,registerT8,registerT9,PC,Alu_Result,correct,wrong)
begin
if(switch(8)='1') then
clock <= clock_manual;
else
clock <= clock_27;
end if;
if(switch(9)='1') then
if(switch(7 downto 0)=X"00") then
numberDesiredToDisplay <= registerT0(15 downto 0);
elsif (switch(7 downto 0)=X"01") then
numberDesiredToDisplay <= registerT1(15 downto 0);
elsif (switch(7 downto 0)=X"02") then
numberDesiredToDisplay <= registerT2(15 downto 0);
elsif (switch(7 downto 0)=X"03") then
numberDesiredToDisplay <= registerT3(15 downto 0);
elsif (switch(7 downto 0)=X"04") then
numberDesiredToDisplay <= registerT4(15 downto 0);
elsif (switch(7 downto 0)=X"05") then
numberDesiredToDisplay <= registerT5(15 downto 0);
elsif (switch(7 downto 0)=X"06") then
numberDesiredToDisplay <= registerT6(15 downto 0);
elsif (switch(7 downto 0)=X"07") then
numberDesiredToDisplay <= registerT7(15 downto 0);
elsif (switch(7 downto 0)=X"08") then
numberDesiredToDisplay <= registerT8(15 downto 0);
elsif (switch(7 downto 0)=X"09") then
numberDesiredToDisplay <= registerT9(15 downto 0);
elsif (switch(7 downto 0)=X"50") then
numberDesiredToDisplay <= "000000" & PC;
elsif (switch(7 downto 0)=X"40") then
numberDesiredToDisplay <= Alu_Result(15 downto 0);
elsif (switch(7 downto 0)=X"20") then
numberDesiredToDisplay <= correct(15 downto 0);
elsif (switch(7 downto 0)=X"30") then
numberDesiredToDisplay <= wrong(15 downto 0);
else
numberDesiredToDisplay <= X"0000";
end if;
else
numberDesiredToDisplay <= (registerT0(7 downto 0) & registerT1(7 downto 0));
end if;
end process;
-- copy important signals to output pins for easy display in Simulator
Branch_out <= Branch;
BranchLessThanZeroOut <= BranchLessThanZero;
Zero_out <= Zero;
LessThanZeroOut <= LessThanZero;
ResetOut <= Reset;
clockOut <= clock;
sevenSegmentVector4Out <= sevenSegmentVector4;
flush_out <= flush;
flushP_out <= flushP;
-- connect the 5 MIPS components
IFE : Ifetch
PORT MAP ( Instruction => Instruction,
PC_plus_4_out => PC_plus_4,
Add_result => Add_resultP,
--Branch Signals
Branch => branchP,
Zero => ZeroP,
BranchLessThanZero=> BranchLessThanZeroP,
LessThanZero => LessThanZeroP,
correct => correct,
wrong => wrong,
PC_out => PC,
clock => clock,
reset => not reset );
ID : Idecode
PORT MAP (
read_data_1 => read_data_1,
read_data_2 => read_data_2,
Instruction => InstructionP,
read_data => read_dataP,
flushP => flushP,
RegWrite => RegWritePP,
RegDst => RegDst,
Sign_extend => Sign_extend,
registerT0 => registerT0,
registerT1 => registerT1,
registerT2 => registerT2,
registerT3 => registerT3,
registerT4 => registerT4,
registerT5 => registerT5,
registerT6 => registerT6,
registerT7 => registerT7,
registerT8 => registerT8,
registerT9 => registerT9,
write_register_addressToMemory => write_register_address,
write_register_addressFromMemory => write_register_addressPP,
------------------Forward DMEM to ID
alu_result0 => Alu_resultP,
RegWrite0 => RegWriteP,
write_register_addressFromMemory0 => write_register_addressP,
MemToReg0 => MemToRegP,
stall => stall,
------------------
clock =>clock,
reset => not reset );
CTL: control
PORT MAP ( Opcode => InstructionP( 31 DOWNTO 26 ),
RegDst => RegDst,
ALUSrc => ALUSrc,
MemToReg => MemToReg,
RegWrite => RegWrite,
MemRead => MemRead,
MemWrite => MemWrite,
--Branch Signals
Branch => Branch,
BranchLessThanZero=> BranchLessThanZero,
--flush
flush => flush,
flushP => flushP,
Zero => Zero,
LessThanZero => LessThanZero,
ALUop => ALUop,
clock => clock,
reset => not reset );
EXE: Execute
PORT MAP ( Read_data_1 => read_data_1,
read_data_2 => read_data_2,
Sign_extend => Sign_extend,
Function_opcode => InstructionP( 5 DOWNTO 0 ),
ALUOp => ALUop,
ALUSrc => ALUSrc,
--Branch Signals
Zero => Zero,
LessThanZero => LessThanZero,
flushP => flushP,
ALU_result => ALU_result,
Add_result => Add_result,
PC_plus_4 => PC_plus_4_outP,
clock => clock,
Reset => not reset );
MEM: dmemory
PORT MAP ( read_data => read_data,
address => ALU_resultP (7 DOWNTO 0),
alu_result => ALU_resultP,
write_data => read_data_2P,
MemRead => MemReadP,
Memwrite => MemWriteP,
MemToReg => MemToRegP,
clock => clock,
reset => not reset );
SEV4: sevenSegment4
PORT MAP (
numberDesired4 => numberDesiredToDisplay,
sevenSegmentVector4 => sevenSegmentVector4,
clock => clock,
reset => reset );
END structure;
|
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
----------------------------RSA_Top_Module-----------------------------
--
-----------------------------------------------------------------------
Entity RSA_Controller is
Generic( i : integer;
Mem_addr_width : integer;
e_val : STD_LOGIC_VECTOR;
N_val : STD_LOGIC_VECTOR);--length of crypto in bits
Port(clk : in STD_LOGIC;
resetN : in STD_LOGIC;
done : out STD_LOGIC;
mem_we : out STD_LOGIC;
input_addr: in STD_LOGIC_VECTOR (mem_addr_width downto 0);
mem_addr : out STD_LOGIC_VECTOR(mem_addr_width downto 0) := (others => '0');
mem_data : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end RSA_Controller;
architecture Behavioral of RSA_Controller is
function CounterSize (X : integer)
return integer is
variable POWER : integer := 1;
variable RET : integer := 0;
begin
while (POWER < X) loop
POWER := POWER * 2;
RET := RET + 1;
end loop;
return RET;
end CounterSize;
type CMD is (GET_MSG, CTxCT, CTxMSG, WRITE_ENCRYPTED, COMPLETE);
signal state : CMD := COMPLETE;
signal mult_operator1, mult_operator2, ct, res, msg : STD_LOGIC_VECTOR( i-1 downto 0);
signal do_mult, reset, mult_done, first, second, third : STD_LOGIC;
signal mem_addr_saved : unsigned(5 downto 0) := (others => '0');
signal counter : unsigned (4 downto 0) := (others => '0');
signal itteration : unsigned (CounterSize(i)-1 downto 0) := (others => '0');
constant e : STD_LOGIC_VECTOR(i-1 downto 0) := e_val;
constant i_byte : integer := i/8;
signal resetN_s : STD_LOGIC;
component modmult is
Generic (MPWID : integer := i);
Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
mplier : in std_logic_vector(MPWID-1 downto 0);
modulus : in std_logic_vector(MPWID-1 downto 0);
product : out std_logic_vector(MPWID-1 downto 0);
clk : in std_logic;
ds : in std_logic;
reset : in std_logic;
ready : out std_logic);
end component;
begin
Mod_Multiplier: modmult Port map (
clk => clk,
mpand => mult_operator1,
mplier => mult_operator2,
modulus => N_val,
product => res,
ds => do_mult,
reset => resetN_s,
ready => mult_done
);
resetN_s <= NOT resetN;
rsa:process(clk)
begin
if(rising_edge(clk)) then
if(resetN = '0') then
--Reset all the operators to initial values
mult_operator1 <= (others => '0');
mult_operator2 <= (others => '0');
ct <= (others => '0');
ct(0) <= '1';
counter <= (others => '0');
itteration <= (others => '0');
msg <= (others => '0');
--Reset all flags to inital value
do_mult <= '0';
done <= '0';
mem_we <= '0';
first <= '0';
second <= '0';
third <= '0';
state <= GET_MSG;
--reset memory_pointers
mem_addr_saved <= unsigned(input_addr);
mem_addr <= (others => '0');
else
case state is
when GET_MSG =>
reset <= '0';
counter <= counter + 1;
mem_addr <= STD_LOGIC_VECTOR(mem_addr_saved + counter + 1);
if counter > 0 then
msg((to_integer(counter*8 - 1)) downto (to_integer(counter*8 - 8))) <= mem_data;
if(counter = i_byte) then
state <= CTxCT;
itteration <= (others => '1');
counter <= (others => '0');
mem_addr <= STD_LOGIC_VECTOR(mem_addr_saved);
end if;
end if;
when CTxCT =>
if first = '0' then
do_mult <= '1';
first <= '1';
itteration <= itteration + 1;
else
do_mult <= '0';
second <= '1';
end if;
if first = '0' then
mult_operator1 <= ct;
mult_operator2 <= ct;
--reset <= '0';
elsif mult_done = '1' and second = '1' and third = '1' then
first <= '0';
do_mult <= '0';
second <= '0';
third <= '0';
ct <= res;
--e <= e srl 1;
if e(to_integer(i-1-itteration)) = '0' then
state <= CTxCT;
if itteration = i-1 then
state <= WRITE_ENCRYPTED;
end if;
else
state <= CTxMSG;
end if;
elsif mult_done = '1' and second = '1' and third = '0' then
third <= '1';
do_mult <= '0';
end if;
when CTxMSG =>
if first = '0' then
do_mult <= '1';
first <= '1';
else
second <= '1';
do_mult <= '0';
end if;
if first = '0' then
mult_operator1 <= ct;
mult_operator2 <= msg;
--reset <= '0';
elsif mult_done = '1' and second = '1' and third = '1' then
first <= '0';
second <= '0';
third <= '0';
counter <= (others => '0');
do_mult <= '0';
ct <= res;
if itteration = i-1 then
state <= WRITE_ENCRYPTED;
counter <= (others => '0');
else
state <= CTxCT;
end if;
elsif mult_done = '1' and second = '1' and third = '0' then
third <= '1';
do_mult <= '0';
end if;
when WRITE_ENCRYPTED =>
if first = '0' then
ct <= res;
first <= '1';
mem_we <= '1';
else
counter <= counter + 1;
data_out <= ct(to_integer(counter)*8 + 7 downto to_integer(counter)*8);
mem_addr <= STD_LOGIC_VECTOR(mem_addr_saved + counter + 1);
if(counter = i_byte-1) then
state <= COMPLETE;
end if;
end if;
when others =>
done <= '1';
mem_we <= '0';
end case;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:43 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_processing_system7_0_2/gcd_block_design_processing_system7_0_2_stub.vhdl
-- Design : gcd_block_design_processing_system7_0_2
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gcd_block_design_processing_system7_0_2 is
Port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end gcd_block_design_processing_system7_0_2;
architecture stub of gcd_block_design_processing_system7_0_2 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
begin
end;
|
-- Entity name: montgomery_multiplier_tb
-- Author: Stephen Carter, Jacob Barnett, Luis Gallet
-- Contact: stephen.carter@mail.mcgill.ca, jacob.barnett@mail.mcgill.ca, luis.galletzambrano@mail.mcgill.ca
-- Date: April 09, 2016
-- Description:
-- Testbench used to test the Montgomery Multiplier
-- Tests autogenerated from a python script
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity montgomery_comparison_tb is
end entity;
architecture test of montgomery_comparison_tb is
Component montgomery_comparison is
Generic(
WIDTH_IN : integer := 32
);
Port( A : in unsigned(WIDTH_IN-1 downto 0);
B : in unsigned(WIDTH_IN-1 downto 0);
N : in unsigned(WIDTH_IN-1 downto 0);
latch : in std_logic;
clk : in std_logic;
reset : in std_logic;
M : out unsigned(WIDTH_IN-1 downto 0)
);
end component;
CONSTANT WIDTH_IN : integer := 32;
CONSTANT clk_period : time := 1 ns;
Signal N_in : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal A_in : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal B_in : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Signal clk_in : std_logic := '0';
Signal reset_t : std_logic := '0';
Signal latch_in : std_logic := '0';
Signal M_out : unsigned(WIDTH_IN-1 downto 0) := (others => '0');
Begin
-- device under test
dut: montgomery_comparison PORT MAP( A => A_in,
B => B_in,
N => N_in,
latch => latch_in,
clk => clk_in,
reset => reset_t,
M => M_out);
-- process for clock
clk_process : Process
Begin
clk_in <= '0';
wait for clk_period/2;
clk_in <= '1';
wait for clk_period/2;
end process;
stim_process: process
Begin
reset_t <= '1';
wait for 1 * clk_period;
reset_t <= '0';
wait for 1 * clk_period;
-- REPORT "Testing (2x2) mod 8";
-- A_in <= "0010";
-- B_in <= "1000";
-- N_in <= "0111";
-- latch_in <= '1';
-- wait for 2 * clk_period;
-- latch_in <= '0';
-- wait for 50 * clk_period;
-- ASSERT(M_out = "0010") REPORT "test failed" SEVERITY ERROR;
-- REPORT "Begin test case for a=156365830663300194168978100302534101760 (A=257185102598108501772724158230196362510), b=156365830663300194168978100302534101760 (B=257185102598108501772724158230196362510), N=260260176362337473672688341065763873521";
-- REPORT "Expected output is 4039137314870681147884186032237193553, 00000011000010011110100011011000010010111101110010000101011111011100011110001101110101100111000101001010111010000010100101010001";
-- A_in <= "11000001011111000000110010001101100001001011100010101000111010110100100011101011000010110011100110101100101101111001110100001110";
-- B_in <= "11000001011111000000110010001101100001001011100010101000111010110100100011101011000010110011100110101100101101111001110100001110";
-- N_in <= "11000011110011000100100101100101000101110011110101010011010011101001111010110001110100110010001000100010010010110110001011110001";
-- latch_in <= '1';
-- wait for 2 * clk_period;
-- latch_in <= '0';
-- wait for 129 * clk_period;
-- ASSERT(M_out = "00000011000010011110100011011000010010111101110010000101011111011100011110001101110101100111000101001010111010000010100101010001") REPORT "test failed" SEVERITY ERROR;
REPORT "Begin test case for a=1328668589 (A=611933216), b=1328668589 (B=611933216), N=2157374201";
REPORT "Expected output is 1602110260, 01011111011111100100001100110100";
A_in <= "00100100011110010101110000100000";
B_in <= "00100100011110010101110000100000";
N_in <= "10000000100101101110101011111001";
latch_in <= '1';
wait for 2 * clk_period;
latch_in <= '0';
wait for 33 * clk_period;
ASSERT(M_out = "01011111011111100100001100110100") REPORT "test failed" SEVERITY ERROR;
wait;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity IRegister is
port(
IR_in : in vl_logic_vector(31 downto 0);
IR_out : out vl_logic_vector(31 downto 0);
Clk : in vl_logic;
IR_write_en : in vl_logic
);
end IRegister;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.psl.all;
use work.functions.all;
use work.frame_package.all;
entity afu is
port (
ah_cvalid : out std_logic;
ah_ctag : out std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ah_ctagpar : out std_logic;
ah_com : out std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0);
ah_compar : out std_logic;
ah_cabt : out std_logic_vector(PSL_ABT_WIDTH - 1 downto 0);
ah_cea : out std_logic_vector(PSL_ADDRESS_WIDTH - 1 downto 0);
ah_ceapar : out std_logic;
ah_cch : out std_logic_vector(PSL_CH_WIDTH - 1 downto 0);
ah_csize : out std_logic_vector(PSL_SIZE_WIDTH - 1 downto 0);
ha_croom : in std_logic_vector(PSL_ROOM_WIDTH - 1 downto 0);
ha_brvalid : in std_logic;
ha_brtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_brtagpar : in std_logic;
ha_brad : in std_logic_vector(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
ah_brlat : out std_logic_vector(PSL_LATENCY_WIDTH - 1 downto 0);
ah_brdata : out std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
ah_brpar : out std_logic_vector((PSL_DATA_WIDTH - 1) / PSL_DOUBLE_WORD_WIDTH downto 0);
ha_bwvalid : in std_logic;
ha_bwtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_bwtagpar : in std_logic;
ha_bwad : in std_logic_vector(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
ha_bwdata : in std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
ha_bwpar : in std_logic_vector((PSL_DATA_WIDTH - 1) / PSL_DOUBLE_WORD_WIDTH downto 0);
ha_rvalid : in std_logic;
ha_rtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_rtagpar : in std_logic;
ha_response : in std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0);
ha_rcredits : in std_logic_vector(PSL_CREDITS_WIDTH - 1 downto 0);
ha_rcachestate : in std_logic_vector(PSL_CACHESTATE_WIDTH - 1 downto 0);
ha_rcachepos : in std_logic_vector(PSL_CACHEPOS_WIDTH - 1 downto 0);
ha_mmval : in std_logic;
ha_mmcfg : in std_logic;
ha_mmrnw : in std_logic;
ha_mmdw : in std_logic;
ha_mmad : in std_logic_vector(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0);
ha_mmadpar : in std_logic;
ha_mmdata : in std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
ha_mmdatapar : in std_logic;
ah_mmack : out std_logic;
ah_mmdata : out std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
ah_mmdatapar : out std_logic;
ha_jval : in std_logic;
ha_jcom : in std_logic_vector(PSL_JOB_COMMAND_WIDTH - 1 downto 0);
ha_jcompar : in std_logic;
ha_jea : in std_logic_vector(PSL_ADDRESS_WIDTH - 1 downto 0);
ha_jeapar : in std_logic;
ah_jrunning : out std_logic;
ah_jdone : out std_logic;
ah_jcack : out std_logic;
ah_jerror : out std_logic_vector(PSL_ERROR_WIDTH - 1 downto 0);
ah_jyield : out std_logic;
ah_tbreq : out std_logic;
ah_paren : out std_logic;
ha_pclock : in std_logic
);
end entity afu;
architecture logic of afu is
signal ha : frame_in;
signal ah : frame_out;
begin
----------------------------------------------------------------------------------------------------------------------- inputs
--ha.c.room <= ha_croom;
ha.b.rvalid <= ha_brvalid;
ha.b.rtag <= u(ha_brtag);
--ha.b.rtagpar <= ha_brtagpar;
ha.b.rad <= u(ha_brad);
ha.b.wvalid <= ha_bwvalid;
ha.b.wtag <= u(ha_bwtag);
--ha.b.wtagpar <= ha_bwtagpar;
ha.b.wad <= u(ha_bwad);
ha.b.wdata <= ha_bwdata;
--ha.b.wpar <= ha_bwpar;
ha.r.valid <= ha_rvalid;
ha.r.tag <= u(ha_rtag);
--ha.r.tagpar <= ha_rtagpar;
ha.r.response <= ha_response;
--ha.r.credits <= ha_rcredits;
--ha.r.cachestate <= ha_rcachestate;
--ha.r.cachepos <= ha_rcachepos;
ha.mm.val <= ha_mmval;
ha.mm.cfg <= ha_mmcfg;
ha.mm.rnw <= ha_mmrnw;
ha.mm.dw <= ha_mmdw;
ha.mm.ad <= u(ha_mmad);
--ha.mm.adpar <= ha_mmadpar;
ha.mm.data <= ha_mmdata;
--ha.mm.datapar <= ha_mmdatapar;
ha.j.com <= ha_jcom;
ha.j.val <= ha_jval;
--ha.j.compar <= ha_jcompar;
ha.j.ea <= u(ha_jea);
--ha.j.eapar <= ha_jeapar;
ha.j.pclock <= ha_pclock;
----------------------------------------------------------------------------------------------------------------------- outputs
ah_cvalid <= ah.c.valid;
ah_ctag <= slv(ah.c.tag);
ah_ctagpar <= '0'; --ah.c.tagpar;
ah_com <= ah.c.com;
ah_compar <= '0'; --ah.c.compar;
ah_cabt <= PTOB_PAGE; --ah.c.abt;
ah_cea <= slv(ah.c.ea);
ah_ceapar <= '0'; --ah.c.eapar;
ah_cch <= (others => '0'); --ah.c.ch;
ah_csize <= slv(ah.c.size);
ah_brlat <= slv(1, PSL_LATENCY_WIDTH); --ah.b.rlat;
ah_brdata <= ah.b.rdata;
ah_brpar <= (others => '0'); --ah.b.rpar;
ah_mmack <= ah.mm.ack;
ah_mmdata <= ah.mm.data;
ah_mmdatapar <= '0'; --ah.mm.datapar;
ah_jrunning <= ah.j.running;
ah_jdone <= ah.j.done;
ah_jcack <= '0'; --ah.j.ack;
ah_jerror <= (others => '0'); --ah.j.error;
ah_jyield <= '0'; --ah.j.yield;
ah_tbreq <= '0'; --ah.j.tbreq;
ah_paren <= '0'; --ah.j.paren;
f0 : entity work.frame port map (ha, ah);
end architecture logic;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (9 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(9 DOWNTO 0):= hex_to_std_logic_vector("0",10);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (42999 downto 0) of std_logic_vector(9 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(9 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"blk_mem_gen_v7_3.mif",
DEFAULT_DATA,
10,
43000);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>43000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 43000 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_proc_sys_reset_0_0;
ARCHITECTURE design_1_proc_sys_reset_0_0_arch OF design_1_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_proc_sys_reset_0_0_arch : ARCHITECTURE IS "design_1_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_proc_sys_reset_0_0_arch: ARCHITECTURE IS "design_1_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_proc_sys_reset_0_0_arch;
|
--
-- File Name: MemoryPkg.vhd
-- Design Unit Name: MemoryPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: jim@synthworks.com
-- Contributor(s):
-- Jim Lewis email: jim@synthworks.com
--
-- Description
-- Package defines a protected type, MemoryPType, and methods
-- for efficiently implementing memory data structures
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated NewID with ReportMode, Search, PrintParent. Supports searching for Memory models.
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Refinement to MemRead to return value, X (if X), U (if not initialized)
-- 01/2016 2016.01 Update for buf.all(buf'left)
-- 06/2015 2015.06 Updated for Alerts, ...
-- ... ... Numerous revisions for VHDL Testbenches and Verification
-- 05/2005 0.1 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.numeric_std.all ;
use IEEE.numeric_std_unsigned.all ;
use IEEE.math_real.all ;
use work.TextUtilPkg.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package MemoryPkg is
type MemoryIDType is record
ID : integer_max ;
end record MemoryIDType ;
type MemoryIDArrayType is array (integer range <>) of MemoryIDType ;
constant OSVVM_MEMORY_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
------------------------------------------------------------
impure function NewID (
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return MemoryIDType ;
------------------------------------------------------------
procedure MemWrite (
ID : MemoryIDType ;
Addr : std_logic_vector ;
Data : std_logic_vector
) ;
procedure MemRead (
ID : in MemoryIDType ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead (
ID : MemoryIDType ;
Addr : std_logic_vector
) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase (ID : in MemoryIDType);
------------------------------------------------------------
impure function GetAlertLogID (ID : in MemoryIDType) return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string
) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string
) ;
type MemoryPType is protected
------------------------------------------------------------
impure function NewID (
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return integer ;
------------------------------------------------------------
procedure MemWrite (
ID : integer ;
Addr : std_logic_vector ;
Data : std_logic_vector
) ;
procedure MemRead (
ID : in integer ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead (
ID : integer ;
Addr : std_logic_vector
) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase (ID : integer) ;
impure function GetAlertLogID (ID : integer) return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadH (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadB (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
-- Destroys the entire data structure
-- Usage: At the end of the simulation to remove all
-- memory used by data structure.
-- Note, a normal simulator does this for you.
-- You only need this if the simulator is broken.
procedure deallocate ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Historical Interface
-- In the new implementation, these use index 1.
-- These are for backward compatibility support
--
-- /////////////////////////////////////////
------------------------------------------------------------
procedure MemInit ( AddrWidth, DataWidth : in integer ) ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) ;
------------------------------------------------------------
procedure MemRead (
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) ;
procedure SetAlertLogID (Name : string ; ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadH (FileName : string) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadB (FileName : string) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteH (FileName : string) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteB (FileName : string) ;
end protected MemoryPType ;
end MemoryPkg ;
package body MemoryPkg is
constant BLOCK_WIDTH : integer := 10 ;
type MemoryPType is protected body
type MemBlockType is array (integer range <>) of integer ;
type MemBlockPtrType is access MemBlockType ;
type MemArrayType is array (integer range <>) of MemBlockPtrType ;
type MemArrayPtrType is access MemArrayType ;
type FileFormatType is (BINARY, HEX) ;
type MemStructType is record
MemArrayPtr : MemArrayPtrType ;
AddrWidth : integer ;
DataWidth : natural ;
BlockWidth : natural ;
AlertLogID : AlertLogIDType ;
--! removed Name : Line ; -- only in NameStorePType
end record MemStructType ;
-- New Structure
type ItemArrayType is array (integer range <>) of MemStructType ;
type ItemArrayPtrType is access ItemArrayType ;
variable Template : ItemArrayType(1 to 1) := (1 => (NULL, -1, 1, 0, OSVVM_MEMORY_ALERTLOG_ID)) ; -- Work around for QS 2020.04 and 2021.02
constant MEM_STRUCT_PTR_LEFT : integer := Template'left ;
variable MemStructPtr : ItemArrayPtrType := new ItemArrayType'(Template) ;
variable NumItems : integer := 0 ;
-- constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable ItemArrayPtr : InOut ItemArrayPtrType ;
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
-- constant NewNumItems : in integer ;
-- constant CurNumItems : in integer ;
constant MinNumItems : in integer
) is
variable oldItemArrayPtr : ItemArrayPtrType ;
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
-- Array Allocated in declaration to have a single item, but no items (historical mode)
-- if ItemArrayPtr = NULL then
-- ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
-- elsif NewNumItems > ItemArrayPtr'length then
if NewNumItems > ItemArrayPtr'length then
oldItemArrayPtr := ItemArrayPtr ;
ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
ItemArrayPtr.all(1 to NumItems) := oldItemArrayPtr.all(1 to NumItems) ;
deallocate(oldItemArrayPtr) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- PT Local
procedure MemInit (ID : integer ; AddrWidth, DataWidth : integer ) is
------------------------------------------------------------
constant ADJ_BLOCK_WIDTH : integer := minimum(BLOCK_WIDTH, AddrWidth) ;
begin
if AddrWidth <= 0 then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemInit/NewID. AddrWidth = " & to_string(AddrWidth) & " must be > 0.", FAILURE) ;
return ;
end if ;
if DataWidth <= 0 or DataWidth > 31 then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemInit/NewID. DataWidth = " & to_string(DataWidth) & " must be > 0 and <= 31.", FAILURE) ;
return ;
end if ;
MemStructPtr(ID).AddrWidth := AddrWidth ;
MemStructPtr(ID).DataWidth := DataWidth ;
MemStructPtr(ID).BlockWidth := ADJ_BLOCK_WIDTH ;
MemStructPtr(ID).MemArrayPtr := new MemArrayType(0 to 2**(AddrWidth-ADJ_BLOCK_WIDTH)-1) ;
end procedure MemInit ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return integer is
variable NameID : integer ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_MEMORY_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_MEMORY_ALERTLOG_ID, PrintParent) ;
NameID := LocalNameStore.find(Name, ParentID, ResolvedSearch) ;
-- Share the memory if they match
if NameID /= ID_NOT_FOUND.ID then
if MemStructPtr(NumItems).MemArrayPtr /= NULL then
-- Found ID and structure exists, does structure match?
AlertIf(MemStructPtr(NumItems).AlertLogID, AddrWidth /= MemStructPtr(NameID).AddrWidth,
"NewID: AddrWidth: " & to_string(AddrWidth) & " /= Existing AddrWidth: " & to_string(MemStructPtr(NameID).AddrWidth), FAILURE);
AlertIf(MemStructPtr(NumItems).AlertLogID, DataWidth /= MemStructPtr(NameID).DataWidth,
"NewID: DataWidth: " & to_string(DataWidth) & " /= Existing DataWidth: " & to_string(MemStructPtr(NameID).DataWidth), FAILURE);
-- NameStore IDs are issued sequentially and match MemoryID
else
-- Found ID and structure does not exist, Reconstruct Memory
MemInit(NameID, AddrWidth, DataWidth) ;
end if ;
return NameID ;
else
-- Add New Memory to Structure
GrowNumberItems(MemStructPtr, NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
MemStructPtr(NumItems).AlertLogID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
-- Construct Memory, Reports agains AlertLogID
MemInit(NumItems, AddrWidth, DataWidth) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, ResolvedSearch) ;
-- Check NameStore Index vs MemoryIndex
AlertIfNotEqual(MemStructPtr(NumItems).AlertLogID, NameID, NumItems, "MemoryStore, Check Index of LocalNameStore matches MemoryID") ;
return NumItems ;
end if ;
end function NewID ;
------------------------------------------------------------
-- PT Local
impure function IdOutOfRange(
------------------------------------------------------------
constant ID : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_MEMORY_ALERTLOG_ID, ID < MemStructPtr'Low or ID > MemStructPtr'High,
"MemoryPkg." & Name & " ID: " & to_string(ID) &
"is not in the range (" & to_string(MemStructPtr'Low) &
" to " & to_string(MemStructPtr'High) & ")",
FAILURE ) ;
end function IdOutOfRange ;
------------------------------------------------------------
procedure MemWrite (
------------------------------------------------------------
ID : integer ;
Addr : std_logic_vector ;
Data : std_logic_vector
) is
variable BlockWidth : integer ;
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
if IdOutOfRange(ID, "MemWrite") then
return ;
end if ;
BlockWidth := MemStructPtr(ID).BlockWidth ;
-- Check Bounds of Address and if memory is initialized
if Addr'length /= MemStructPtr(ID).AddrWidth then
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Memory not initialized, Write Ignored.", FAILURE) ;
else
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(MemStructPtr(ID).AddrWidth), FAILURE) ;
end if ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= MemStructPtr(ID).DataWidth then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(MemStructPtr(ID).DataWidth), FAILURE) ;
return ;
end if ;
if is_X( Addr ) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Address X, Write Ignored.") ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockWidth then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockWidth)) ;
else
BlockAddr := 0 ;
end if ;
-- If empty, allocate a memory block
if (MemStructPtr(ID).MemArrayPtr(BlockAddr) = NULL) then
MemStructPtr(ID).MemArrayPtr(BlockAddr) := new MemBlockType(0 to 2**BlockWidth-1) ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockWidth -1 downto 0)) ;
-- Write to BlockAddr, WordAddr
if (Is_X(Data)) then
MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) := -1 ;
else
MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) := to_integer( Data ) ;
end if ;
end procedure MemWrite ;
------------------------------------------------------------
procedure MemRead (
------------------------------------------------------------
ID : in integer ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) is
variable BlockWidth : integer ;
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
if IdOutOfRange(ID, "MemRead") then
return ;
end if ;
BlockWidth := MemStructPtr(ID).BlockWidth ;
-- Check Bounds of Address and if memory is initialized
if Addr'length /= MemStructPtr(ID).AddrWidth then
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemRead: Memory not initialized. Returning U", FAILURE) ;
else
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemRead: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(MemStructPtr(ID).AddrWidth), FAILURE) ;
end if ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= MemStructPtr(ID).DataWidth then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemRead: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(MemStructPtr(ID).DataWidth), FAILURE) ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- If Addr X, data = X
if is_X( aAddr ) then
Data := (Data'range => 'X') ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockWidth then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockWidth)) ;
else
BlockAddr := 0 ;
end if ;
-- Empty Block, return all U
if (MemStructPtr(ID).MemArrayPtr(BlockAddr) = NULL) then
Data := (Data'range => 'U') ;
return ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockWidth -1 downto 0)) ;
if MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) >= 0 then
-- Get the Word from the Array
Data := to_slv(MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr), Data'length) ;
elsif MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) = -1 then
-- X in Word, return all X
Data := (Data'range => 'X') ;
else
-- Location Uninitialized, return all X
Data := (Data'range => 'U') ;
end if ;
end procedure MemRead ;
------------------------------------------------------------
impure function MemRead (
ID : integer ;
Addr : std_logic_vector
) return std_logic_vector is
------------------------------------------------------------
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "MemRead function") ;
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
--!!Cadence variable Data : std_logic_vector(MemStructPtr(ID).DataWidth-1 downto 0) ;
constant DATA_WIDTH : integer := MemStructPtr(ID).DataWidth ;
variable Data : std_logic_vector(DATA_WIDTH-1 downto 0) ;
begin
MemRead(ID, Addr, Data) ;
return Data ;
end function MemRead ;
------------------------------------------------------------
procedure MemErase(ID : integer) is
-- Erase the memory, but not the array of pointers
------------------------------------------------------------
begin
if IdOutOfRange(ID, "MemErase") then
return ;
end if ;
for BlockAddr in MemStructPtr(ID).MemArrayPtr'range loop
if (MemStructPtr(ID).MemArrayPtr(BlockAddr) /= NULL) then
deallocate (MemStructPtr(ID).MemArrayPtr(BlockAddr)) ;
end if ;
end loop ;
end procedure ;
------------------------------------------------------------
impure function GetAlertLogID (ID : integer) return AlertLogIDType is
------------------------------------------------------------
begin
if IdOutOfRange(ID, "MemErase") then
return ALERTLOG_ID_NOT_FOUND ;
else
return MemStructPtr(ID).AlertLogID ;
end if ;
end function GetAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure FileReadX (
-- Hexadecimal or Binary File Read
------------------------------------------------------------
ID : integer ;
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant DATA_WIDTH : integer := MemStructPtr(ID).DataWidth ;
-- constant TemplateRange : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '0') ;
-- Format:
-- @hh..h -- Address in hex
-- hhh_XX_ZZ -- data values in hex - space delimited
-- "--" or "//" -- comments
file MemFile : text open READ_MODE is FileName ;
variable Addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable SmallAddr : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable BigAddr : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable Data : std_logic_vector(DATA_WIDTH - 1 downto 0) ;
variable LineNum : natural ;
variable ItemNum : natural ;
variable AddrInc : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable buf : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean ;
variable NextChar : character ;
variable StrLen : integer ;
begin
MultiLineComment := FALSE ;
if StartAddr'length /= ADDR_WIDTH and EndAddr'length /= ADDR_WIDTH then
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(ADDR_WIDTH), FAILURE) ;
end if ;
return ;
end if ;
Addr := StartAddr ;
LineNum := 0 ;
if StartAddr <= EndAddr then
SmallAddr := StartAddr ;
BigAddr := EndAddr ;
AddrInc := (ADDR_WIDTH -1 downto 0 => '0') + 1 ;
else
SmallAddr := EndAddr ;
BigAddr := StartAddr ;
AddrInc := (others => '1') ; -- -1
end if;
ReadLineLoop : while not EndFile(MemFile) loop
ReadLine(MemFile, buf) ;
LineNum := LineNum + 1 ;
ItemNum := 0 ;
ItemLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ItemLoop when Empty ;
ItemNum := ItemNum + 1 ;
NextChar := buf.all(buf'left) ;
if (NextChar = '@') then
-- Get Address
read(buf, NextChar) ;
ReadHexToken(buf, Addr, StrLen) ;
exit ReadLineLoop when AlertIf(MemStructPtr(ID).AlertLogID, StrLen = 0, "MemoryPkg.FileReadX: Address length 0 on line: " & to_string(LineNum), FAILURE) ;
exit ItemLoop when AlertIf(MemStructPtr(ID).AlertLogID, Addr < SmallAddr,
"MemoryPkg.FileReadX: Address in file: " & to_hxstring(Addr) &
" < StartAddr: " & to_hxstring(StartAddr) & " on line: " & to_string(LineNum)) ;
exit ItemLoop when AlertIf(MemStructPtr(ID).AlertLogID, Addr > BigAddr,
"MemoryPkg.FileReadX: Address in file: " & to_hxstring(Addr) &
" > EndAddr: " & to_hxstring(BigAddr) & " on line: " & to_string(LineNum)) ;
elsif DataFormat = HEX and ishex(NextChar) then
-- Get Hex Data
ReadHexToken(buf, data, StrLen) ;
exit ReadLineLoop when AlertIfNot(MemStructPtr(ID).AlertLogID, StrLen > 0,
"MemoryPkg.FileReadH: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: MemWrite(Addr => " & to_hxstring(Addr) & ", Data => " & to_hxstring(Data) & ")", DEBUG) ;
MemWrite(ID, Addr, data) ;
Addr := Addr + AddrInc ;
elsif DataFormat = BINARY and isstd_logic(NextChar) then
-- Get Binary Data
-- read(buf, data, ReadValid) ;
ReadBinaryToken(buf, data, StrLen) ;
-- exit ReadLineLoop when AlertIfNot(MemStructPtr(ID).AlertLogID, ReadValid,
exit ReadLineLoop when AlertIfNot(MemStructPtr(ID).AlertLogID, StrLen > 0,
"MemoryPkg.FileReadB: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: MemWrite(Addr => " & to_hxstring(Addr) & ", Data => " & to_string(Data) & ")", DEBUG) ;
MemWrite(ID, Addr, data) ;
Addr := Addr + AddrInc ;
else
if NextChar = LF or NextChar = CR then
-- If LF or CR, silently skip the character (DOS file in Unix)
read(buf, NextChar) ;
else
-- invalid Text, issue warning and skip rest of line
Alert(MemStructPtr(ID).AlertLogID,
"MemoryPkg.FileReadX: Invalid text on line: " & to_string(LineNum) &
" Item: " & to_string(ItemNum) & ". Skipping text: " & buf.all) ;
exit ItemLoop ;
end if ;
end if ;
end loop ItemLoop ;
end loop ReadLineLoop ;
-- -- must read EndAddr-StartAddr number of words if both start and end specified
-- if (StartAddr /= 0 or (not EndAddr) /= 0) and (Addr /= EndAddr) then
-- Alert("MemoryPkg.FileReadH: insufficient data values", WARNING) ;
-- end if ;
file_close(MemFile) ;
end FileReadX ;
------------------------------------------------------------
procedure FileReadH (
-- Hexadecimal File Read
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadH") ;
begin
FileReadX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
-- Hexadecimal File Read
procedure FileReadH (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
-- Hexadecimal File Read
procedure FileReadH (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
-- Binary File Read
procedure FileReadB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadB") ;
begin
FileReadX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- Binary File Read
procedure FileReadB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- Binary File Read
procedure FileReadB (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- PT Local
-- Hexadecimal or Binary File Write
procedure FileWriteX (
------------------------------------------------------------
ID : integer ;
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant DATA_WIDTH : integer := MemStructPtr(ID).DataWidth ;
constant BLOCK_WIDTH : integer := MemStructPtr(ID).BlockWidth ;
-- Format:
-- @hh..h -- Address in hex
-- hhhhh -- data one per line in either hex or binary as specified
file MemFile : text open WRITE_MODE is FileName ;
alias normStartAddr : std_logic_vector(StartAddr'length-1 downto 0) is StartAddr ;
alias normEndAddr : std_logic_vector(EndAddr'length-1 downto 0) is EndAddr ;
variable StartBlockAddr : natural ;
variable EndBlockAddr : natural ;
variable StartWordAddr : natural ;
variable EndWordAddr : natural ;
variable Data : std_logic_vector(DATA_WIDTH-1 downto 0) ;
variable FoundData : boolean ;
variable buf : line ;
begin
if StartAddr'length /= ADDR_WIDTH and EndAddr'length /= ADDR_WIDTH then
-- Check StartAddr and EndAddr Widths and Memory not initialized
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileWriteX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
AlertIf(MemStructPtr(ID).AlertLogID, StartAddr'length /= ADDR_WIDTH, "MemoryPkg.FileWriteX: StartAddr'length: "
& to_string(StartAddr'length) &
" /= Memory Address Width: " & to_string(ADDR_WIDTH), FAILURE) ;
AlertIf(MemStructPtr(ID).AlertLogID, EndAddr'length /= ADDR_WIDTH, "MemoryPkg.FileWriteX: EndAddr'length: "
& to_string(EndAddr'length) &
" /= Memory Address Width: " & to_string(ADDR_WIDTH), FAILURE) ;
end if ;
return ;
end if ;
if StartAddr > EndAddr then
-- Only support ascending addresses
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileWriteX: StartAddr: " & to_hxstring(StartAddr) &
" > EndAddr: " & to_hxstring(EndAddr), FAILURE) ;
return ;
end if ;
-- Slice out upper address to form block address
if ADDR_WIDTH >= BLOCK_WIDTH then
StartBlockAddr := to_integer(normStartAddr(ADDR_WIDTH-1 downto BLOCK_WIDTH)) ;
EndBlockAddr := to_integer( normEndAddr(ADDR_WIDTH-1 downto BLOCK_WIDTH)) ;
else
StartBlockAddr := 0 ;
EndBlockAddr := 0 ;
end if ;
BlockAddrLoop : for BlockAddr in StartBlockAddr to EndBlockAddr loop
next BlockAddrLoop when MemStructPtr(ID).MemArrayPtr(BlockAddr) = NULL ;
if BlockAddr = StartBlockAddr then
StartWordAddr := to_integer(normStartAddr(BLOCK_WIDTH-1 downto 0)) ;
else
StartWordAddr := 0 ;
end if ;
if BlockAddr = EndBlockAddr then
EndWordAddr := to_integer(normEndAddr(BLOCK_WIDTH-1 downto 0)) ;
else
EndWordAddr := 2**BLOCK_WIDTH-1 ;
end if ;
FoundData := FALSE ;
WordAddrLoop : for WordAddr in StartWordAddr to EndWordAddr loop
if (MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) < 0) then
-- X in Word, return all X
Data := (Data'range => 'X') ;
FoundData := FALSE ;
else
-- Get the Word from the Array
Data := to_slv(MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr), Data'length) ;
if not FoundData then
-- Write Address
write(buf, '@') ;
hwrite(buf, to_slv(BlockAddr, ADDR_WIDTH-BLOCK_WIDTH) & to_slv(WordAddr, BLOCK_WIDTH)) ;
writeline(MemFile, buf) ;
end if ;
FoundData := TRUE ;
end if ;
if FoundData then -- Write Data
if DataFormat = HEX then
hwrite(buf, Data) ;
writeline(MemFile, buf) ;
else
write(buf, Data) ;
writeline(MemFile, buf) ;
end if;
end if ;
end loop WordAddrLoop ;
end loop BlockAddrLoop ;
file_close(MemFile) ;
end FileWriteX ;
------------------------------------------------------------
-- Hexadecimal File Write
procedure FileWriteH (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteH") ;
begin
FileWriteX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
-- Hexadecimal File Write
procedure FileWriteH (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
begin
FileWriteX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
-- Hexadecimal File Write
procedure FileWriteH (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
-- fails constant StartAddr : std_logic_vector(MemStructPtr(ID).AddrWidth - 1 downto 0) := (others => '0') ;
-- fails constant EndAddr : std_logic_vector(MemStructPtr(ID).AddrWidth - 1 downto 0) := (others => '1') ;
begin
FileWriteX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
-- Binary File Write
procedure FileWriteB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteB") ;
begin
FileWriteX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
-- Binary File Write
procedure FileWriteB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
begin
FileWriteX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
-- Binary File Write
procedure FileWriteB (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
begin
FileWriteX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Structure Wide Methods
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
-- Erase the memory
-- Used between independent pieces of a test
-- to erase the all memory model contents, but
-- keeps the memory size and infrastructure
procedure MemErase is
------------------------------------------------------------
begin
for ID in MemStructPtr'range loop
MemErase(ID) ;
end loop ;
end procedure ;
------------------------------------------------------------
-- Destroys the entire data structure
-- Usage: At the end of the simulation to remove all
-- memory used by data structure.
-- Note, a normal simulator does this for you.
-- You only need this if the simulator is broken.
------------------------------------------------------------
-- PT Local
procedure deallocate (ID : integer) is
------------------------------------------------------------
begin
MemErase(ID) ;
deallocate(MemStructPtr(ID).MemArrayPtr) ;
MemStructPtr(ID).AddrWidth := -1 ;
MemStructPtr(ID).DataWidth := 1 ;
MemStructPtr(ID).BlockWidth := 0 ;
--! removed -- deallocate(MemStructPtr(ID).Name) ;
end procedure ;
procedure deallocate is
begin
for ID in MemStructPtr'range loop
deallocate(ID) ;
end loop ;
--! Deallocate not able to be called on MemoryStore - no accessor procedure
--! if make directly visible, then do this, but otherwise no.
-- deallocate(MemStructPtr) ;
-- NumItems := 0 ;
end procedure deallocate ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Compatibility Methods
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
procedure MemInit ( AddrWidth, DataWidth : in integer ) is
------------------------------------------------------------
begin
MemInit(MEM_STRUCT_PTR_LEFT, AddrWidth, DataWidth) ;
end procedure MemInit ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) is
------------------------------------------------------------
begin
MemWrite(MEM_STRUCT_PTR_LEFT, Addr, Data) ;
end procedure MemWrite ;
------------------------------------------------------------
procedure MemRead (
------------------------------------------------------------
Addr : In std_logic_vector ;
Data : Out std_logic_vector
) is
begin
MemRead(MEM_STRUCT_PTR_LEFT, Addr, Data) ;
end procedure MemRead ;
------------------------------------------------------------
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector is
------------------------------------------------------------
constant DATA_WIDTH : integer := MemStructPtr(MEM_STRUCT_PTR_LEFT).DataWidth ;
variable Data : std_logic_vector(DATA_WIDTH-1 downto 0) ;
begin
MemRead(MEM_STRUCT_PTR_LEFT, Addr, Data) ;
return Data ;
end function MemRead ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
MemStructPtr(MEM_STRUCT_PTR_LEFT).AlertLogID := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
MemStructPtr(MEM_STRUCT_PTR_LEFT).AlertLogID := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return MemStructPtr(MEM_STRUCT_PTR_LEFT).AlertLogID ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure FileReadH (
-- Hexadecimal File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Read
------------------------------------------------------------
begin
FileReadH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string) is
-- Hexadecimal File Read
------------------------------------------------------------
begin
FileReadH(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadB (
-- Binary File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Read
------------------------------------------------------------
begin
FileReadB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string) is
-- Binary File Read
------------------------------------------------------------
begin
FileReadB(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileReadB ;
------------------------------------------------------------
procedure FileWriteH (
-- Hexadecimal File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Write
------------------------------------------------------------
begin
FileWriteH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string) is
-- Hexadecimal File Write
------------------------------------------------------------
begin
FileWriteH(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteB (
-- Binary File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Write
------------------------------------------------------------
begin
FileWriteB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string) is
-- Binary File Write
------------------------------------------------------------
begin
FileWriteB(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileWriteB ;
end protected body MemoryPType ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Singleton Data Structure
-- /////////////////////////////////////////
-- /////////////////////////////////////////
shared variable MemoryStore : MemoryPType ;
------------------------------------------------------------
impure function NewID (
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return MemoryIDType is
variable Result : MemoryIDType ;
begin
Result.ID := MemoryStore.NewID(Name, AddrWidth, DataWidth, ParentID, ReportMode, Search, PrintParent) ;
return Result ;
end function NewID ;
------------------------------------------------------------
procedure MemWrite (
ID : MemoryIDType ;
Addr : std_logic_vector ;
Data : std_logic_vector
) is
begin
MemoryStore.MemWrite(ID.ID, Addr, Data) ;
end procedure MemWrite ;
procedure MemRead (
ID : in MemoryIDType ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) is
begin
MemoryStore.MemRead(ID.ID, Addr, Data) ;
end procedure MemRead ;
impure function MemRead (
ID : MemoryIDType ;
Addr : std_logic_vector
) return std_logic_vector is
begin
return MemoryStore.MemRead(ID.ID, Addr) ;
end function MemRead ;
------------------------------------------------------------
procedure MemErase (ID : in MemoryIDType) is
begin
MemoryStore.MemErase(ID.ID) ;
end procedure MemErase ;
------------------------------------------------------------
impure function GetAlertLogID (
ID : in MemoryIDType
) return AlertLogIDType is
begin
return MemoryStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileReadH(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileReadH ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileReadH(ID.ID, FileName, StartAddr) ;
end procedure FileReadH ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileReadH(ID.ID, FileName) ;
end procedure FileReadH ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileReadB(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileReadB ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileReadB(ID.ID, FileName, StartAddr) ;
end procedure FileReadB ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileReadB(ID.ID, FileName) ;
end procedure FileReadB ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteH(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileWriteH ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteH(ID.ID, FileName, StartAddr) ;
end procedure FileWriteH ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileWriteH(ID.ID, FileName) ;
end procedure FileWriteH ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteB(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileWriteB ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteB(ID.ID, FileName, StartAddr) ;
end procedure FileWriteB ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileWriteB(ID.ID, FileName) ;
end procedure FileWriteB ;
end MemoryPkg ; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.std_logic_unsigned."+";
USE IEEE.std_logic_unsigned."-";
USE IEEE.std_logic_unsigned."=";
USE IEEE.std_logic_unsigned."<";
USE IEEE.std_logic_unsigned.">";
USE IEEE.std_logic_unsigned."<=";
USE IEEE.std_logic_unsigned.">=";
ENTITY KCVIDEO_INTERFACE IS PORT
(
CLK : IN STD_LOGIC; -- master clock input 108 MHz
KC_CLK : IN STD_LOGIC; -- external video clock 7.09 MHz
R : IN STD_LOGIC; -- red pixel color
G : IN STD_LOGIC; -- green pixel color
B : IN STD_LOGIC; -- blue pixel color
EZ : IN STD_LOGIC; -- foreground/background bit
EX : IN STD_LOGIC; -- intensity bit
HSYNC : IN STD_LOGIC; -- horizontal sync input
VSYNC : IN STD_LOGIC; -- vertical sync input
nRESET : IN STD_LOGIC; -- reset input
FIFO_WR : OUT STD_LOGIC; -- SRAM FIFO write output
FIFO_FULL : IN STD_LOGIC; -- SRAM FIFO full input
FRAMESYNC : IN STD_LOGIC; -- start of frame from VGA module for screensaver
DATA_OUT : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); -- SRAM pixel data
SRAM_ADDR : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address
SRAM_ADDR_WR : OUT STD_LOGIC
);
END KCVIDEO_INTERFACE;
ARCHITECTURE Behavioral OF KCVIDEO_INTERFACE IS
SIGNAL counter : INTEGER RANGE 0 TO 320;
SIGNAL prescaler : INTEGER RANGE 0 TO 1;
SIGNAL FRAMESYNC_EDGE_DETECTOR : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
DATA_OUT <= "11010";
PROCESS (CLK, nRESET)
BEGIN
IF nRESET = '0' THEN
FRAMESYNC_EDGE_DETECTOR <= (OTHERS => '0');
FIFO_WR <= '0';
prescaler <= 0;
-- elsif rising_edge(CLK) then
-- SRAM_ADDR_WR <= '0';
--
-- if counter > 0 then
-- if prescaler = 0 then
-- FIFO_WR <= '1';
-- prescaler <= 1;
-- else
-- prescaler <= 0;
-- FIFO_WR <= '0';
-- counter <= counter - 1;
-- end if;
-- end if;
--
-- if FRAMESYNC_EDGE_DETECTOR = "01" then
-- SRAM_ADDR <= (others => '0');
-- SRAM_ADDR_WR <= '1';
-- counter <= 3;
-- end if;
--
-- FRAMESYNC_EDGE_DETECTOR <= FRAMESYNC_EDGE_DETECTOR(0) & FRAMESYNC;
END IF;
END PROCESS;
END Behavioral;
---- screensaver position after reset
--constant LOGO_X : integer := 0;
--constant LOGO_Y : integer := 42;
--
---- screensaver dimensions
--constant LOGO_W : integer := 128;
--constant LOGO_H : integer := 128;
--
---- X and Y position of incoming pixel data
--signal X : STD_LOGIC_VECTOR(10 downto 0) := (others => '0');
--signal Y : STD_LOGIC_VECTOR(10 downto 0) := (others => '0');
--
---- current SRAM address
--signal A : STD_LOGIC_VECTOR(16 downto 0);
--
---- edge detectors and filters for clock, HSYNC, VSYNC
--signal KC_CLK_edge_detector : STD_LOGIC_VECTOR(2 downto 0);
--signal KC_CLK_glitch_filter : STD_LOGIC_VECTOR(3 downto 0);
--signal HSYNC_edge_detector : STD_LOGIC_VECTOR(2 downto 0);
--signal HSYNC_glitch_filter : STD_LOGIC_VECTOR(7 downto 0);
--signal VSYNC_edge_detector : STD_LOGIC_VECTOR(2 downto 0);
--signal VSYNC_glitch_filter : STD_LOGIC_VECTOR(7 downto 0);
--
---- internal frame start flag, gets set on falling edge of VSYNC
--signal FRAME_START : STD_LOGIC;
--
---- current screensaver data address
--signal SCREENSAVER_ROM_ADDRESS: STD_LOGIC_VECTOR(13 downto 0);
--
---- screensaver position and movement
--signal LOGO_POSITION_X : STD_LOGIC_VECTOR(8 downto 0);
--signal LOGO_POSITION_Y : STD_LOGIC_VECTOR(7 downto 0);
--signal LOGO_DIRECTION_X : STD_LOGIC;
--signal LOGO_DIRECTION_Y : STD_LOGIC;
--
---- gets set after screensaver has been completely written to SRAM
--signal SCREENSAVER_DONE : STD_LOGIC;
--
---- counter for screensaver activation
--signal TIMEOUT : STD_LOGIC_VECTOR(27 downto 0) := (others => '0');
--
--signal SCREENSAVER_ROM_DATA: STD_LOGIC;
--
--type INTERFACE_STATE is (STATE1, STATE2, STATE3, STATE4);
--signal current_state: INTERFACE_STATE := STATE1;
--signal PIXEL: STD_LOGIC_VECTOR(4 downto 0);
--signal blink: STD_LOGIC;
-- i_SCREENSAVER_ROM: entity SCREENSAVER_ROM port map(
-- CLK => CLK,
-- ADDR => SCREENSAVER_ROM_ADDRESS,
-- DATA => SCREENSAVER_ROM_DATA
-- );
-- SRAM_ADDR <= A;
-- SRAM_ADDR_WR <= '1';
-- A <= A + 107;
-- PIXEL <= PIXEL + 1;
-- counter <= 0;
-- if counter < 320 then
---- if counter = 0 then
---- SRAM_ADDR <= A;
---- SRAM_ADDR_WR <= '1';
---- end if;
--
-- if current_state = STATE1 then
-- if counter = 0 then
-- DATA_OUT <= "11010";
-- else
-- DATA_OUT <= "00000";
-- end if;
---- DATA_OUT <= PIXEL;
-- FIFO_WR <= '1';
-- current_state <= STATE2;
-- elsif current_state = STATE2 then
-- FIFO_WR <= '0';
-- current_state <= STATE1;
-- counter <= counter + 1;
-- end if;
--
---- TIMEOUT <= TIMEOUT + 1;
---- if TIMEOUT = 54000000 then
---- TIMEOUT <= (others => '0');
---- if blink = '0' then
---- blink <= '1';
---- PIXEL <= "11010";
---- else
---- blink <= '0';
---- PIXEL <= (others => '0');
---- end if;
---- end if;
--
-- end if;
-- process(CLK, nRESET, R, G, B, EZ, EX)
-- variable color : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
-- variable KC_CLK_filtered : STD_LOGIC;
-- variable HSYNC_filtered : STD_LOGIC;
-- variable VSYNC_filtered : STD_LOGIC;
-- begin
-- -- assign video inputs to color variable for easier access
-- color(0) := not(B);
-- color(1) := not(R);
-- color(2) := not(G);
-- color(3) := not(EX); -- intensity
-- color(4) := EZ; -- foreground/background
--
-- if nRESET = '0' then
-- LOGO_POSITION_X <= STD_LOGIC_VECTOR(to_unsigned(LOGO_X, 9));
-- LOGO_POSITION_Y <= STD_LOGIC_VECTOR(to_unsigned(LOGO_Y, 8));
-- KC_CLK_edge_detector <= (others => '0');
-- HSYNC_edge_detector <= (others => '0');
-- VSYNC_edge_detector <= (others => '0');
-- SCREENSAVER_ROM_ADDRESS <= (others => '0');
-- A <= (others => '1');
-- TIMEOUT <= (others => '0');
-- prescaler <= '0';
--
-- elsif rising_edge(CLK) then
-- FIFO_WR <= '0';
--
-- -------------------------------------------------------------------
-- -- screensaver timeout and movement
-- -------------------------------------------------------------------
-- -- only execute screensaver if no input data was available for more
-- -- than 216 000 000 cycles (2 seconds)
-- if not(TIMEOUT = 216000000) then
-- TIMEOUT <= TIMEOUT + 1;
-- else
-- -- move logo on every VGA frame start
-- if FRAMESYNC = '1' then
-- SCREENSAVER_DONE <= '0';
-- if LOGO_DIRECTION_X = '1' then
-- -- move in positive X direction
-- if LOGO_POSITION_X + LOGO_W < 319 then
-- LOGO_POSITION_X <= LOGO_POSITION_X + 1;
-- else
-- LOGO_DIRECTION_X <= '0';
-- end if;
-- else
-- -- move in negative X direction
-- if LOGO_POSITION_X > 0 then
-- LOGO_POSITION_X <= LOGO_POSITION_X - 1;
-- else
-- LOGO_DIRECTION_X <= '1';
-- end if;
-- end if;
--
-- if LOGO_DIRECTION_Y = '1' then
-- -- move in positive Y direction
-- if LOGO_POSITION_Y + LOGO_H < 255 then
-- LOGO_POSITION_Y <= LOGO_POSITION_Y + 1;
-- else
-- LOGO_DIRECTION_Y <= '0';
-- end if;
-- else
-- -- move in negative Y direction
-- if LOGO_POSITION_Y > 0 then
-- LOGO_POSITION_Y <= LOGO_POSITION_Y - 1;
-- else
-- LOGO_DIRECTION_Y <= '1';
-- end if;
-- end if;
-- end if;
--
-- -- prescaler: only execute every second cycle because ROM needs
-- -- one additional cycle to deliver next pixel
-- prescaler <= not(prescaler);
--
-- -- write screen saver pixels to RAM
-- if SCREENSAVER_DONE = '0' and FIFO_FULL = '0' and prescaler = '1' then
--
-- -- insert logo at position LOGO_POSITION_X, LOGO_POSITION_Y
-- if X >= LOGO_POSITION_X and X < LOGO_POSITION_X+STD_LOGIC_VECTOR(to_unsigned(LOGO_W, 9))
-- and Y >= LOGO_POSITION_Y and Y < LOGO_POSITION_Y+STD_LOGIC_VECTOR(to_unsigned(LOGO_H, 8)) then
-- if SCREENSAVER_ROM_DATA = '1' then
-- color := "11111";
-- else
-- color := "00001";
-- end if;
--
-- -- increment internal ROM address
-- SCREENSAVER_ROM_ADDRESS <= SCREENSAVER_ROM_ADDRESS + 1;
-- else
---- color := LOGO_BG;
-- color := "00000";
-- end if;
--
-- -- stuff current pixel into dataword
-- if pixel = pixel1 then
-- DATA_OUT(4 downto 0) <= color;
-- pixel <= pixel2;
-- elsif pixel = pixel2 then
-- DATA_OUT(9 downto 5) <= color;
-- pixel <= pixel3;
-- else
-- DATA_OUT(14 downto 10) <= color;
-- -- current dataword is now complete
-- -- -> set address bits in upper 16 bits
-- DATA_OUT(31 downto 15) <= A;
-- -- write to FIFO
-- FIFO_WR <= '1';
-- A <= A + 1;
-- pixel <= pixel1;
-- end if;
--
-- -- update X and Y counters
-- -- write 321 pixels per line because 321 is divisible by
-- -- 3 and we need to fill the last dataword completely
-- -- -> use one dummy pixel
-- if not(X = 320) then
-- X <= X + 1;
-- else
-- X <= (others => '0');
-- pixel <= pixel1;
-- if not(Y = 255) then
-- Y <= Y + 1;
-- else
-- Y <= (others => '0');
-- A <= (others => '0');
-- SCREENSAVER_ROM_ADDRESS <= (others => '0');
-- SCREENSAVER_DONE <= '1';
-- end if;
-- end if;
-- end if;
-- end if;
--
-- -------------------------------------------------------------------
-- -- external video sampling
-- -------------------------------------------------------------------
-- -- check for falling edge on KC_CLK
-- -- Normally, the data in the target device is valid on
-- -- the _rising_ clock edge. Since we have inserted a small
-- -- shift register for synchronization and edge detection,
-- -- data is now valid on the first _falling_ edge after
-- -- falling HSYNC.
-- if KC_CLK_edge_detector(2 downto 1) = "10" then
-- -- write 321 pixels per line because 321 is divisible by 3 and
-- -- we need to fill the last dataword completely
-- -- -> use one dummy pixel
-- if X < 321 and Y < 256
-- then
-- -- stuff current pixel into dataword
-- if pixel = pixel1 then
-- DATA_OUT(4 downto 0) <= color;
-- pixel <= pixel2;
-- elsif pixel = pixel2 then
-- DATA_OUT(9 downto 5) <= color;
-- pixel <= pixel3;
-- else
-- DATA_OUT(14 downto 10) <= color;
-- -- current dataword is now complete
-- -- -> set address bits in upper 16 bits
-- DATA_OUT(31 downto 15) <= A;
--
-- -- write to FIFO
-- -- skip dataword if FIFO is full (can't happen if
-- -- SRAM_INTERFACE and VGA_OUTPUT is behaving correctly)
-- if FIFO_FULL = '0' then
-- FIFO_WR <= '1';
-- end if;
-- pixel <= pixel1;
-- A <= A + 1;
-- end if;
-- X <= X + 1;
-- end if;
-- end if;
--
-- -- check for falling edge on HSYNC
-- if HSYNC_edge_detector(2 downto 1) = "10" then
-- if FRAME_START = '1' then
-- Y <= (others => '0');
-- A <= (others => '0');
-- SCREENSAVER_ROM_ADDRESS <= (others => '0');
-- FRAME_START <= '0';
-- else
-- Y <= Y + 1;
-- end if;
-- X <= (others => '0');
-- pixel <= pixel1;
-- end if;
--
-- -- check for falling edge on VSYNC
-- if VSYNC_edge_detector(2 downto 1) = "10" then
-- FRAME_START <= '1';
-- TIMEOUT <= (others => '0');
-- end if;
--
-- -- glitch filter, necessary due to capacitive coupling of some
-- -- signal lines
-- -- (does not delay falling edge, only delays rising edge)
-- -- only accepts H level if it persists for more than 4 or 8 clock cycles
-- KC_CLK_glitch_filter <= KC_CLK_glitch_filter(2 downto 0) & KC_CLK;
-- HSYNC_glitch_filter <= HSYNC_glitch_filter(6 downto 0) & HSYNC;
-- VSYNC_glitch_filter <= VSYNC_glitch_filter(6 downto 0) & VSYNC;
-- if KC_CLK_glitch_filter = "1111" then
-- KC_CLK_filtered := '1';
-- else
-- KC_CLK_filtered := '0';
-- end if;
-- if HSYNC_glitch_filter = "11111111" then
-- HSYNC_filtered := '1';
-- else
-- HSYNC_filtered := '0';
-- end if;
-- if VSYNC_glitch_filter = "11111111" then
-- VSYNC_filtered := '1';
-- else
-- VSYNC_filtered := '0';
-- end if;
--
-- -- shift left edge detectors, concatenate filtered input
-- -- signals on LSB side
-- KC_CLK_edge_detector <= KC_CLK_edge_detector(1 downto 0) & KC_CLK_filtered;
-- HSYNC_edge_detector <= HSYNC_edge_detector(1 downto 0) & HSYNC_filtered;
-- VSYNC_edge_detector <= VSYNC_edge_detector(1 downto 0) & VSYNC_filtered;
--
-- end if;
-- end process;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ppuseq is
Port (CLK : in STD_LOGIC;
SE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : in STD_LOGIC_VECTOR (15 downto 0);
PPU_HSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_VSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC := '0';
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC := '0';
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC := '0';
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC := '0';
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4Read : out STD_LOGIC := '0';
VRAM4Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM4Data : in STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : in STD_LOGIC;
SprWR : in STD_LOGIC;
SprAddr : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : in STD_LOGIC;
PalWR : in STD_LOGIC;
PalAddr : in STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
Color : out STD_LOGIC_VECTOR ( 5 downto 0) := "000000");
end ppuseq;
architecture Dataflow of ppuseq is
signal phase : integer := 0;
signal counter : integer := 0;
signal PatAddr1 : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatAddr2 : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatAddr : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatRead : STD_LOGIC := '0';
signal PatData : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
-- sprites
type sprites_t is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
signal sprites : sprites_t := (others => x"00");
signal sprindex : integer := 0;
signal sprdata : STD_LOGIC_VECTOR (7 downto 0) := x"00";
type sprcache_t is array (0 to 7) of STD_LOGIC_VECTOR (31 downto 0);
signal sprcache : sprcache_t := (others => x"00000000");
signal lastSprRD : STD_LOGIC := '0';
signal lastSprWR : STD_LOGIC := '0';
-- palette
type palette_t is array (0 to 15) of STD_LOGIC_VECTOR (5 downto 0);
signal PatPal : palette_t := (others => "000000"); -- pattern palette
signal SprPal : palette_t := (others => "000000"); -- sprite palette
signal lastPalRD : STD_LOGIC := '0';
signal lastPalWR : STD_LOGIC := '0';
attribute ram_style: string;
attribute ram_style of sprites : signal is "block";
-- attribute ram_style of sprcache : signal is "block";
begin
PatAddr <= PatAddr1 when phase = 2 else PatAddr2;
VRAM0Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM1Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM2Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM3Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM0Read <= (NOT PatAddr(12));
VRAM1Read <= (NOT PatAddr(12));
VRAM2Read <= ( PatAddr(12));
VRAM3Read <= ( PatAddr(12));
PatData( 7 downto 0) <= VRAM0Data or VRAM2Data;
PatData(15 downto 8) <= VRAM1Data or VRAM3Data;
process (CLK)
variable tcolor : STD_LOGIC_VECTOR ( 3 downto 0) := "0000";
variable scolor : STD_LOGIC_VECTOR ( 3 downto 0) := "0000";
variable ashift : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
variable bshift : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
variable n : integer := 0;
variable m : integer := 0;
variable sstate : integer := 0;
variable cur_y : integer := 0;
variable spr_y : integer := 0;
variable max_y : integer := 0;
variable row : integer := 0;
variable cur_x : integer := 0;
variable spr0x : integer := 0;
variable spr1x : integer := 0;
variable spr2x : integer := 0;
variable spr3x : integer := 0;
variable spr4x : integer := 0;
variable spr5x : integer := 0;
variable spr6x : integer := 0;
variable spr7x : integer := 0;
variable offset : integer := 0;
variable sprindx : integer := 0;
variable V : STD_LOGIC := '0'; -- vert. nametable
variable H : STD_LOGIC := '0'; -- hori. nametable
variable VT : STD_LOGIC_VECTOR ( 4 downto 0); -- vert. tile index
variable HT : STD_LOGIC_VECTOR ( 4 downto 0); -- hori. tile index
variable FV : STD_LOGIC_VECTOR ( 2 downto 0); -- vert. pixel index
variable FH : STD_LOGIC_VECTOR ( 2 downto 0); -- hori. pixel index
begin
if (CLK = '1' and CLK'event ) then
-- sprite processing
if (SE = '0' or phase = 0 or phase = 4) then
-- make use of hblank time by loading
if (n < 64 and m < 8) then
if (sstate = 0) then
-- current sprite in range?
spr_y := conv_integer(unsigned(sprdata))+1;
if (PPU_CTRL(5) = '0') then
max_y := spr_y + 8;
else
max_y := spr_y + 16;
end if;
if (cur_y >= spr_y and cur_y < max_y) then
-- in range
row := cur_y-spr_y;
sstate := 1;
sprindex <= sprindex + 2;
else
-- skip
n := n + 1;
sprindex <= sprindex + 4;
end if;
elsif (sstate = 1) then
-- store sprite attributes
sprcache(m)(15 downto 8) <= sprdata;
if (sprdata(7) = '1') then
if (PPU_CTRL(5) = '0') then
row := 7 - row;
else
row := 15 - row;
end if;
end if;
sprindex <= sprindex + 1;
sstate := 2;
elsif (sstate = 2) then
-- store sprite X
if (m = 0) then
spr0x:=conv_integer(unsigned(sprdata));
elsif (m = 1) then
spr1x:=conv_integer(unsigned(sprdata));
elsif (m = 2) then
spr2x:=conv_integer(unsigned(sprdata));
elsif (m = 3) then
spr3x:=conv_integer(unsigned(sprdata));
elsif (m = 4) then
spr4x:=conv_integer(unsigned(sprdata));
elsif (m = 5) then
spr5x:=conv_integer(unsigned(sprdata));
elsif (m = 6) then
spr6x:=conv_integer(unsigned(sprdata));
elsif (m = 7) then
spr7x:=conv_integer(unsigned(sprdata));
end if;
sprcache(m)(7 downto 0) <= sprdata;
sprindex <= sprindex - 2;
sstate := 3;
elsif (sstate = 3) then
--load color bit 0
if (PPU_CTRL(5) = '0') then
PatAddr2 <= PPU_CTRL(3) &
sprdata &
"0" &
conv_std_logic_vector(row,3);
elsif (row < 8) then
PatAddr2 <= sprdata(0) &
sprdata(7 downto 1) & "0" &
"0" &
conv_std_logic_vector(row,3);
else
PatAddr2 <= sprdata(0) &
sprdata(7 downto 1) & "1" &
"0" &
conv_std_logic_vector(row-8,3);
end if;
PatRead <= '1';
sprindex <= sprindex + 1;
sstate := 4;
elsif (sstate = 4) then
sstate := 5;
elsif (sstate = 5) then
-- read color bit 0
if (sprdata(6) = '0') then
sprcache(m)(16) <= PatData(7);
sprcache(m)(17) <= PatData(6);
sprcache(m)(18) <= PatData(5);
sprcache(m)(19) <= PatData(4);
sprcache(m)(20) <= PatData(3);
sprcache(m)(21) <= PatData(2);
sprcache(m)(22) <= PatData(1);
sprcache(m)(23) <= PatData(0);
sprcache(m)(24) <= PatData(15);
sprcache(m)(25) <= PatData(14);
sprcache(m)(26) <= PatData(13);
sprcache(m)(27) <= PatData(12);
sprcache(m)(28) <= PatData(11);
sprcache(m)(29) <= PatData(10);
sprcache(m)(30) <= PatData(9);
sprcache(m)(31) <= PatData(8);
else
sprcache(m)(31 downto 16) <= PatData;
end if;
-- next sprite
m := m + 1;
n := n + 1;
sprindex <= sprindex + 2;
sstate := 0;
end if;
end if;
end if;
-- rendering
if (SE = '0') then
-- reset state machine counters
phase <= 0;
counter <= 0;
-- reset color
if (phase /= 0) then
color <= "111111";
else
color <= "000000";
end if;
else
if (phase = 0) then
-- here we introduce little delay so that next line
-- is drawn in the middle of screen.
color <= "111111";
if (counter < 64) then
counter <= counter + 1;
else
counter <= 0;
phase <= 1;
-- beginning of a new row. Is this the first scanline?
if (Y = x"0000") then
-- first line on screen, reset vertical
V := PPU_CTRL(1);
VT := PPU_VSCR(7 downto 3);
FV := PPU_VSCR(2 downto 0);
elsif (Y(0) = '0') then
if (FV /= "111") then
-- next pixel inside the tile
FV := conv_std_logic_vector(
conv_integer(unsigned(FV))+1,3);
else
-- next tile
FV := "000";
if (VT /= "11101") then
-- next tile inside window
VT := conv_std_logic_vector(
conv_integer(unsigned(VT))+1,5);
else
-- next window
VT := "00000";
V := NOT V;
end if;
end if;
end if;
-- reset horizontal counters
H := PPU_CTRL(0);
HT := PPU_HSCR(7 downto 3);
FH := PPU_HSCR(2 downto 0);
-- pipelining, read patIndex of first pixel
VRAM4Read <= '1';
PatRead <= '1';
VRAM4Addr <= H & VT & HT;
end if;
elsif (phase = 1) then
-- load lowest 2 bits of color
PatAddr1 <= PPU_CTRL(4) & VRAM4Data(7 downto 0) & "0" & FV;
-- load associated attribute
VRAM4Addr <= H & "1111" & VT(4 downto 2) & HT(4 downto 2);
-- early calculation for shifts
bshift := FH;
ashift := VT(1)&HT(1)&"0";
-- prepare next column:
if (FH /= "111") then
-- next pixel inside the tile
FH := conv_std_logic_vector(
conv_integer(unsigned(FH))+1,3);
else
-- next tile
FH := "000";
if (HT /= "11111") then
-- next tile inside window
HT := conv_std_logic_vector(
conv_integer(unsigned(HT))+1,5);
else
-- next window
HT := "00000";
H := NOT H;
end if;
end if;
-- find matching sprite, if any
if (counter >= spr0x and counter < (spr0x+8)) then
sprindx := 0;
elsif (counter >= spr1x and counter < (spr1x+8)) then
sprindx := 1;
elsif (counter >= spr2x and counter < (spr2x+8)) then
sprindx := 2;
elsif (counter >= spr3x and counter < (spr3x+8)) then
sprindx := 3;
elsif (counter >= spr4x and counter < (spr4x+8)) then
sprindx := 4;
elsif (counter >= spr5x and counter < (spr5x+8)) then
sprindx := 5;
elsif (counter >= spr6x and counter < (spr6x+8)) then
sprindx := 6;
elsif (counter >= spr7x and counter < (spr7x+8)) then
sprindx := 7;
else
sprindx := 8;
end if;
-- go to next step
phase <= 2;
elsif (phase = 2) then
-- read tile color
tcolor(0) := PatData( 7-conv_integer(unsigned(bshift)));
tcolor(1) := PatData(15-conv_integer(unsigned(bshift)));
tcolor(2) := VRAM4Data(conv_integer(unsigned(ashift))+0);
tcolor(3) := VRAM4Data(conv_integer(unsigned(ashift))+1);
-- continue sprite evaluation
if (sprindx < 8) then
offset := counter -
conv_integer(unsigned(sprcache(sprindx)(7 downto 0)));
scolor(0) := sprcache(sprindx)(16+offset);
scolor(1) := sprcache(sprindx)(24+offset);
scolor(2) := sprcache(sprindx)(8);
scolor(3) := sprcache(sprindx)(9);
else
scolor := "0000";
end if;
-- output color
if (scolor(0) = '1' or scolor(1) = '1') then
-- sprite
color <= SprPal(conv_integer(unsigned(scolor)));
elsif (tcolor(1) = '0' and tcolor(0) = '0') then
-- background color
color <= PatPal(0);
else
color <= PatPal(conv_integer(unsigned(tcolor)));
end if;
-- load next pat index
VRAM4Addr <= H & VT & HT;
-- move to next state
if (counter < 255) then
counter <= counter + 1;
phase <= 1;
else
phase <= 3;
end if;
elsif (phase = 3) then
phase <= 4;
-- reset sprite cache
n := 0;
m := 0;
sstate := 0;
cur_y := conv_integer(unsigned(Y(9 downto 1)));
spr0x := 255;
spr1x := 255;
spr2x := 255;
spr3x := 255;
spr4x := 255;
spr5x := 255;
spr6x := 255;
spr7x := 255;
sprindex <= 0;
else
VRAM4Read <= '0';
PatRead <= '0';
color <= "111111";
end if;
end if;
end if;
end process;
-- sprite access
process (CLK)
begin
if (CLK = '0' and CLK'event ) then
if (lastSprRD /= SprRD and SprRD='1') then
-- read
SprDataOut <= sprites(conv_integer(unsigned(SprAddr)));
end if;
sprdata <= sprites(sprindex);
if (lastSprWR /= SprWR and SprWR='1') then
-- write
sprites(conv_integer(unsigned(SprAddr))) <= SprDataIn;
end if;
lastSprRD <= SprRD;
lastSprWR <= SprWR;
end if;
end process;
-- palette access
process (CLK)
begin
if (CLK = '0' and CLK'event ) then
if (lastPalRD /= PalRD and PalRD='1') then
-- read
if (PalAddr(4) = '0') then
PalDataOut(5 downto 0) <= PatPal(
conv_integer(unsigned(PalAddr(3 downto 0))));
else
PalDataOut(5 downto 0) <= SprPal(
conv_integer(unsigned(PalAddr(3 downto 0))));
end if;
end if;
if (lastPalWR /= PalWR and PalWR='1') then
-- write
if (PalAddr(4) = '0') then
PatPal(conv_integer(unsigned(PalAddr(3 downto 0))))
<= PalDataIn(5 downto 0);
else
SprPal(conv_integer(unsigned(PalAddr(3 downto 0))))
<= PalDataIn(5 downto 0);
end if;
end if;
lastPalRD <= PalRD;
lastPalWR <= PalWR;
end if;
end process;
end Dataflow;
|
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity mult is
generic (k : integer := 4);
port( carryin : in std_logic ;
A, B : in std_logic_vector (k-1 downto 0);
S : out std_logic_vector (k-1 downto 0);
carryout : out std_logic);
end entity mult;
architecture Behave of mult is
signal Sum : std_logic_vector (k downto 0);
begin
Sum <= ( '0' & A) - ( '0' & B) - carryin ;
S <= Sum (k-1 downto 0);
carryout <= Sum(k) ;
end Behave;
|
------------------------------------------------------------------------------
---- ----
---- Testbench for the ZPU Small connection to the FPGA ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a testbench to simulate the ZPU_Small1 core as used in the ----
---- *_small1.vhdl ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Small1_TB(Behave) (Entity and architecture) ----
---- File name: small1_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- zpu.txt_util ----
---- work.zpu_memory ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
use zpu.txt_util.all;
library work;
use work.zpu_memory.all;
entity Small1_TB is
end entity Small1_TB;
architecture Behave of Small1_TB is
constant WORD_SIZE : natural:=32; -- 32 bits data path
constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB
constant D_CARE_VAL : std_logic:='0'; -- Fill value
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant BRATE : positive:=115200;
component ZPU_Small1 is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='0'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=115200; -- RS232 baudrate
ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end component ZPU_Small1;
signal clk : std_logic;
signal reset : std_logic:='1';
signal break : std_logic;
signal dbg : zpu_dbgo_t; -- Debug info
signal rs232_tx : std_logic;
signal rs232_rx : std_logic;
begin
zpu : ZPU_Small1
generic map(
WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
BRAM_W => BRAM_W)
port map(
clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
gpio_in => (others => '0'));
trace_mod : Trace
generic map(
ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
LOG_FILE => "small1_trace.log")
port map(
clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_reset:
process
begin
wait until rising_edge(clk);
reset <= '0';
end process do_reset;
end architecture Behave; -- Entity: Small1_TB
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);
|
----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity decode is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_SUPPORT_SPR: boolean := true;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end decode;
architecture arch of decode is
type decode_reg_type is record
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
immediate : std_logic_vector(15 downto 0);
is_immediate : std_logic;
interrupt : std_logic;
delay_interrupt : std_logic;
block_interrupt : std_logic;
end record;
signal r, rin : decode_out_type;
signal reg, regin : decode_reg_type;
signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wrb <= r.ctrl_wrb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_o.int_ack <= r.int_ack;
decode_comb: process(decode_i,decode_i.ctrl_wrb,
decode_i.ctrl_mem_wrb,
decode_i.instruction,
decode_i.inst_valid,
decode_i.ctrl_mem_wrb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wrb,
r.ctrl_wrb.reg_d,
r.fwd_dec,reg)
variable v : decode_out_type;
variable v_reg : decode_reg_type;
variable opcode : std_logic_vector(5 downto 0);
variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
v.int_ack := '0';
-- Default register values (NOP)
v_reg.immediate := (others => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
if decode_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
else
mem_result := decode_i.alu_result;
end if;
wb_dat_d <= mem_result;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '0';
end if;
if CFG_REG_FWD_WRB = true then
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wrb;
else
v.fwd_dec_result := (others => '0');
v.fwd_dec.reg_d := (others => '0');
v.fwd_dec.reg_write := '0';
end if;
if decode_i.inst_valid = '0' then
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
-- not a hazard, just a nop
elsif (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif r.hazard = '1' then
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
else
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
end if;
v.program_counter := program_counter;
opcode := instruction(31 downto 26);
v.ctrl_wrb.reg_d := instruction(25 downto 21);
v.reg_a := instruction(20 downto 16);
v.reg_b := instruction(15 downto 11);
-- SET IMM value
if reg.is_immediate = '1' then
v.imm := reg.immediate & instruction(15 downto 0);
else
v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
end if;
-- Register if an interrupt occurs
if G_INTERRUPT = true then
if decode_i.interrupt_enable = '1' and decode_i.interrupt = '1' and reg.block_interrupt = '0' then
v_reg.interrupt := '1';
end if;
if decode_i.interrupt_enable = '0' then
v_reg.block_interrupt := '0';
end if;
end if;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := "00";
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_ex.msr_op := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
if G_INTERRUPT = true and (reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.interrupt := '0';
v_reg.block_interrupt := '1'; -- because interrupt enable is cleared in exec, we block here any new interrupts until MSR_I bit is cleared.
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.int_ack := '1';
v.imm := X"00000010";
v.ctrl_wrb.reg_d := "01110"; -- link register is r14
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.msr_op := MSR_CLR_I;
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA; -- will read 0 because reg_a = 0
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif (decode_i.flush_id or v.hazard) = '1' then
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
if G_DEBUG = true then
v.program_counter := (others => '0');
v.ctrl_wrb.reg_d := (others => '0');
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := (others => '0');
end if;
elsif is_zero(opcode(5 downto 4)) = '1' then
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
if opcode(0) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
else
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
end if;
-- Source operand B
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Pass modifier for CMP and CMPU
if (compare(opcode, "000101") = '1') then
v.ctrl_ex.operation := instruction(1 downto 0);
end if;
-- Carry
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ONE;
when others => v.ctrl_ex.carry := CARRY_ALU;
end case;
-- Carry keep
if opcode(2) = '1' then
v.ctrl_ex.carry_keep := CARRY_KEEP;
else
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then
-- OR, AND, XOR, ANDN
-- ORI, ANDI, XORI, ANDNI
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
elsif opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode, "101100") = '1' then
-- IMM instruction
v_reg.immediate := instruction(15 downto 0);
v_reg.is_immediate := '1';
elsif compare(opcode, "100100") = '1' then
-- SHIFT, SIGN EXTEND
if compare(instruction(6 downto 5), "11") = '1' then
if instruction(0) = '1' then
v.ctrl_ex.alu_op:= ALU_SEXT16;
else
v.ctrl_ex.alu_op:= ALU_SEXT8;
end if;
else
v.ctrl_ex.alu_op:= ALU_SHIFT;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
case instruction(6 downto 5) is
when "10" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ALU;
when others => v.ctrl_ex.carry := CARRY_ARITH;
end case;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.delay := instruction(20);
-- Link: WRITE THE CURRENT PC TO REGISTER D. In the MEM stage, a multiplexer decides that PC is being written in case of a branch.
if instruction(18) = '1' then
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
end if;
if instruction(19) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.reg_a := (others => '0'); -- select register 0 to emulate 0.
else
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
end if;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
case v.ctrl_wrb.reg_d(2 downto 0) is
when "000" => v.ctrl_ex.branch_cond := BEQ;
when "001" => v.ctrl_ex.branch_cond := BNE;
when "010" => v.ctrl_ex.branch_cond := BLT;
when "011" => v.ctrl_ex.branch_cond := BLE;
when "100" => v.ctrl_ex.branch_cond := BGT;
when others => v.ctrl_ex.branch_cond := BGE;
end case;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
elsif compare(opcode, "101101") = '1' then
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
if G_INTERRUPT = true then
if v.ctrl_wrb.reg_d(0) = '1' then
v.ctrl_ex.msr_op := MSR_SET_I;
end if;
v_reg.delay_interrupt := '1';
end if;
elsif compare(opcode(5 downto 4), "11") = '1' then
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.carry := CARRY_ZERO;
if opcode(2) = '1' then
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
else
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wrb.reg_write := '1';
end if;
case opcode(1 downto 0) is
when "00" => v.ctrl_mem.transfer_size := BYTE;
when "01" => v.ctrl_mem.transfer_size := HALFWORD;
when others => v.ctrl_mem.transfer_size := WORD;
end case;
v.ctrl_ex.delay := '0';
elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
v.ctrl_ex.alu_op := ALU_MUL;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
v.ctrl_ex.alu_op := ALU_BS;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_SUPPORT_SPR and opcode = "100101" then
if instruction(15 downto 14) = "11" then -- MTS, SPR[Sd] := Ra
v.ctrl_ex.msr_op := LOAD_MSR; -- Ra will be written to the status bits
elsif instruction(15 downto 14) = "10" then -- MFS, Rd := SPR[Sd]
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
else -- 00 (MSRSET/MSRCLR) and 01 -> illegal
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
v.ctrl_wrb.reg_write := '1';
if instruction(16)='0' then -- SET
v.ctrl_ex.msr_op := MSR_SET;
else -- CLR
v.ctrl_ex.msr_op := MSR_CLR;
end if;
end if;
else
-- UNKNOWN OPCODE
null;
end if;
rin <= v;
regin <= v_reg;
end process;
decode_seq: process(clk_i)
procedure proc_reset_decode is
begin
r.reg_a <= (others => '0');
r.reg_b <= (others => '0');
r.imm <= (others => '0');
r.program_counter <= (others => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= "00";
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.fwd_dec_result <= (others => '0');
r.fwd_dec.reg_d <= (others => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (others => '0');
reg.program_counter <= (others => '0');
reg.immediate <= (others => '0');
reg.is_immediate <= '0';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
reg.block_interrupt <= '0';
end procedure proc_reset_decode;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_reset_decode;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
gprf0 : gprf port map
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
end arch;
|
--------------------------------------------------------------------------------
-- FILE: Consts
-- DESC: Define all constants.
--
-- Author:
-- Create: 2015-05-20
-- Update: 2015-09-20
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package Consts is
constant C_SYS_DATA_SIZE : integer := 32; -- Data size
constant C_SYS_ISTR_SIZE : integer := 32; -- Instruction size
constant C_SYS_ADDR_SIZE : integer := 32; -- Address size
constant C_SYS_CWRD_SIZE : integer := 20; -- Control Word size
constant C_SYS_OPCD_SIZE : integer := 6; -- Operation code size
constant C_SYS_FUNC_SIZE : integer := 11; -- Function code size
constant C_SYS_IMME_SIZE : integer := 16; -- Immediate value size
constant C_CTR_CALU_SIZE : integer := 5; -- ALU Operation Code size
constant C_CTR_DRCW_SIZE : integer := 4; -- Data Memory Control word size
constant C_ADD_SPARSITY : integer := 4; -- Sparsity of Adder carray generator
constant C_MUL_STAGE : integer := 10; -- Stage of multiply operation
constant C_DIV_STAGE : integer := 34; -- Stage of division operation
constant C_SQRT_STAGE : integer := 18; -- Stage of square root operation
constant C_REG_NUM : integer := 32; -- Number of Register in Register File
constant C_REG_GLOBAL_NUM : integer := 8; -- Number of Global register in register file
constant C_REG_GENERAL_NUM : integer := 8; -- Number of General registers (I/L/O) in register file
constant C_REG_WINDOW_NUM : integer := 8; -- Number of Windows in register file
constant C_RAM_IRAM_SIZE : integer := 10240; -- IRAM size
constant C_RAM_DRAM_SIZE : integer := 1024; -- DRAM size
constant C_BPU_ADDR_SIZE : integer := 5; -- BPU ADDR SIZE
-- ALU Operations
constant OP_ADD : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00000"; --0x00
constant OP_AND : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00001"; --0x01
constant OP_OR : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00010"; --0x02
constant OP_XOR : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00011"; --0x03
constant OP_SLL : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00100"; --0x04
constant OP_SRL : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00101"; --0x05
constant OP_SRA : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "00111"; --0x07
constant OP_MULTU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01000"; --0x08 -- unsigned
constant OP_MULT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01001"; --0x09 -- signed
constant OP_DIVU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01010"; --0x0a -- unsigned
constant OP_DIV : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01011"; --0x0b -- signed
constant OP_SQRT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "01100"; --0x0c -- SQRT unsigned
constant OP_SUB : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10000"; --0x10
constant OP_SGT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10001"; --0x11
constant OP_SGE : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10010"; --0x12
constant OP_SLT : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10011"; --0x13
constant OP_SLE : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10100"; --0x14
constant OP_SGTU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10101"; --0x15
constant OP_SGEU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10110"; --0x16
constant OP_SLTU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "10111"; --0x17
constant OP_SLEU : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "11000"; --0x18
constant OP_SEQ : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "11001"; --0x19
constant OP_SNE : std_logic_vector(C_CTR_CALU_SIZE-1 downto 0) := "11010"; --0x1a
-- Control Word
constant CW_S1_LATCH : integer := 0;
constant CW_S2_JUMP : integer := 1; -- JUMP HAPPENS ?
constant CW_S2_SEL_JA_0 : integer := 2; -- ADDR0 = NPC + EXT_I or ADDR = NPC + EXT_J ?
constant CW_S2_SEL_JA_1 : integer := 3; -- ADDR1 = ADDR0 or ADD1 = REG_A ?
constant CW_S2_LINK : integer := 4;
constant CW_S2_EXT_S : integer := 5;
constant CW_S2_LATCH : integer := 6;
constant CW_S3_SEL_B : integer := 7;
constant CW_S3_LD_FLAG : integer := 8;
constant CW_S3_WB_FLAG : integer := 9;
constant CW_S3_LATCH : integer := 10;
constant CW_S4_DRAM_T_0 : integer := 11;
constant CW_S4_DRAM_T_1 : integer := 12;
constant CW_S4_DRAM_T_2 : integer := 13;
constant CW_S4_DRAM_WR : integer := 14;
constant CW_S4_SEL_WB : integer := 15;
constant CW_S4_LD_FLAG : integer := 16;
constant CW_S4_WB_FLAG : integer := 17;
constant CW_S4_LATCH : integer := 18;
constant CW_S5_EN_WB : integer := 19;
-- Instructions -- OpCode
constant OPCD_R : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000000"; --0x00
constant OPCD_F : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000001"; --0x01
constant OPCD_J : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000010"; --0x02
constant OPCD_JAL : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000011"; --0x03
constant OPCD_BEQZ : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000100"; --0x04
constant OPCD_BNEZ : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "000101"; --0x05
constant OPCD_ADDI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001000"; --0x08
constant OPCD_ADDUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001001"; --0x09
constant OPCD_SUBI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001010"; --0x0a
constant OPCD_SUBUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001011"; --0x0b
constant OPCD_ANDI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001100"; --0x0c
constant OPCD_ORI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001101"; --0x0d
constant OPCD_XORI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001110"; --0x0e
constant OPCD_LHI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "001111"; --0x0f
constant OPCD_JR : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010010"; --0x12
constant OPCD_JALR : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010011"; --0x13
constant OPCD_SLLI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010100"; --0x14
constant OPCD_NOP : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010101"; --0x15
constant OPCD_SRLI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010110"; --0x16
constant OPCD_SRAI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "010111"; --0x17
constant OPCD_SEQI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011000"; --0x18
constant OPCD_SNEI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011001"; --0x19
constant OPCD_SLTI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011010"; --0x1a
constant OPCD_SGTI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011011"; --0x1b
constant OPCD_SLEI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011100"; --0x1c
constant OPCD_SGEI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "011101"; --0x1d
constant OPCD_LB : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100000"; --0x20
constant OPCD_LH : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100001"; --0x21
constant OPCD_LW : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100011"; --0x23
constant OPCD_LBU : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100100"; --0x24
constant OPCD_LHU : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "100101"; --0x25
constant OPCD_SB : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "101000"; --0x28
constant OPCD_SH : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "101001"; --0x29
constant OPCD_SW : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "101011"; --0x2b
constant OPCD_SLTUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111010"; --0x3a
constant OPCD_SGTUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111011"; --0x3b
constant OPCD_SLEUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111100"; --0x3c
constant OPCD_SGEUI : std_logic_vector(C_SYS_OPCD_SIZE-1 downto 0) := "111101"; --0x3d
-- Instructions --FUNC
-- R TYPE
constant FUNC_SLL : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000000100"; --0x04
constant FUNC_SRL : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000000110"; --0x06
constant FUNC_SRA : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000000111"; --0x07
constant FUNC_ADD : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100000"; --0x20
constant FUNC_ADDU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100001"; --0x21
constant FUNC_SUB : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100010"; --0x22
constant FUNC_SUBU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100011"; --0x23
constant FUNC_AND : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100100"; --0x24
constant FUNC_OR : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100101"; --0x25
constant FUNC_XOR : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100110"; --0x26
constant FUNC_SEQ : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101000"; --0x28
constant FUNC_SNE : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101001"; --0x29
constant FUNC_SLT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101010"; --0x2a
constant FUNC_SGT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101011"; --0x2b
constant FUNC_SLE : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101100"; --0x2c
constant FUNC_SGE : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000101101"; --0x2d
constant FUNC_SLTU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111010"; --0x3a
constant FUNC_SGTU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111011"; --0x3b
constant FUNC_SLEU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111100"; --0x3c
constant FUNC_SGEU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000111101"; --0x3d
-- F TYPE
constant FUNC_MULT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000001110"; --0x0e
constant FUNC_DIV : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000001111"; --0x0f
constant FUNC_MULTU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000010110"; --0x16
constant FUNC_DIVU : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000010111"; --0x17
constant FUNC_SQRT : std_logic_vector(C_SYS_FUNC_SIZE-1 downto 0) := "00000100000"; --0x20
-- STALL GENERATOR STATES
constant SG_ST0 : integer := 0;
constant SG_ST1 : integer := 1;
constant SG_ST2 : integer := 2;
constant SG_ST3 : integer := 3;
constant SG_ST4 : integer := 4;
constant SG_ST5 : integer := 5;
constant SG_ST6 : integer := 6;
constant SG_ST7 : integer := 7;
constant SG_ST8 : integer := 8;
constant SG_ST9 : integer := 9;
constant SG_ST10 : integer := 10;
constant SG_ST11 : integer := 11;
constant SG_ST12 : integer := 12;
constant SG_ST13 : integer := 13;
constant SG_ST14 : integer := 14;
constant SG_ST15 : integer := 15;
constant SG_ST16 : integer := 16;
constant SG_ST17 : integer := 17;
constant SG_ST18 : integer := 18;
constant SG_ST19 : integer := 19;
constant SG_ST20 : integer := 20;
constant SG_ST21 : integer := 21;
constant SG_ST22 : integer := 22;
constant SG_ST23 : integer := 23;
end package Consts;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2016 Cobham Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
USE_MIG_INTERFACE_MODEL : boolean := false;
clkperiod : integer := 10 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
-- MIG Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
signal sysclk : std_ulogic := '0';
-- LEDs
signal led : std_logic_vector(7 downto 0);
-- Buttons
signal btnc : std_ulogic;
signal btnd : std_ulogic;
signal btnl : std_ulogic;
signal btnr : std_ulogic;
signal cpu_resetn : std_ulogic;
-- Switches
signal sw : std_logic_vector(7 downto 0);
-- USB-RS232 interface
signal uart_tx_in : std_logic;
signal uart_rx_out : std_logic;
-- DDR3
signal ddr3_dq : std_logic_vector(15 downto 0);
signal ddr3_dqs_p : std_logic_vector(1 downto 0);
signal ddr3_dqs_n : std_logic_vector(1 downto 0);
signal ddr3_addr : std_logic_vector(14 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(1 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- Fan PWM
signal fan_pwm : std_ulogic;
-- SPI
signal qspi_cs : std_logic;
signal qspi_dq : std_logic_vector(3 downto 0);
signal scl : std_ulogic;
signal gnd : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
begin
gnd <= '0';
-- clock and reset
sysclk <= not sysclk after ct * 1 ns;
cpu_resetn <= '0', '1' after 100 ns;
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow,
SIM_BYPASS_INIT_CAL, SIMULATION, USE_MIG_INTERFACE_MODEL)
port map (
sysclk => sysclk, led => led,
btnc => btnc, btnd => btnd, btnl => btnl, btnr => btnr,
cpu_resetn => cpu_resetn,
sw => sw,
uart_tx_in => uart_tx_in, uart_rx_out => uart_rx_out,
ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n, ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt,
fan_pwm => fan_pwm,
qspi_cs => qspi_cs, qspi_dq => qspi_dq, scl => scl,
phy_txclk => phy_gtxclk,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
phy_rxd => phy_rxd(3 downto 0)'delayed(0 ns),
phy_rxctl_rxdv => phy_rxctl_rxdv'delayed(0 ns),
phy_rxclk => phy_rxclk'delayed(0 ns),
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
phy_int => '0'
);
ddr3mem0 : ddr3ram
generic map(
width => 16, abits => 15, colbits => 10, rowbits => 13,
implbanks => 8, fname => sdramfile, speedbin=>1, density => 3, lddelay => (0 ns))
-- swap => CFG_MIG_7SERIES)
port map (ck => ddr3_ck_p(0), ckn => ddr3_ck_n(0), cke => ddr3_cke(0), csn => gnd,
odt => ddr3_odt(0), rasn => ddr3_ras_n, casn => ddr3_cas_n, wen => ddr3_we_n,
dm => ddr3_dm, ba => ddr3_ba, a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq(15 downto 0),
dqs => ddr3_dqs_p, dqsn => ddr3_dqs_n, doload => led(4));
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT)
port map (scl, qspi_dq(0), qspi_dq(1), qspi_cs);
end generate spimem0;
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 10 us;
assert (to_X01(led(3)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3167.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03167ent IS
END c14s01b00x00p17n01i03167ent;
ARCHITECTURE c14s01b00x00p17n01i03167arch OF c14s01b00x00p17n01i03167ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'right = 15 and
roufbit'right = 0 )
report "***PASSED TEST: c14s01b00x00p17n01i03167"
severity NOTE;
assert ( fourbit'right = 15 and
roufbit'right = 0 )
report "***FAILED TEST: c14s01b00x00p17n01i03167 - Predefined attribute RIGHT for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03167arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3167.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03167ent IS
END c14s01b00x00p17n01i03167ent;
ARCHITECTURE c14s01b00x00p17n01i03167arch OF c14s01b00x00p17n01i03167ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'right = 15 and
roufbit'right = 0 )
report "***PASSED TEST: c14s01b00x00p17n01i03167"
severity NOTE;
assert ( fourbit'right = 15 and
roufbit'right = 0 )
report "***FAILED TEST: c14s01b00x00p17n01i03167 - Predefined attribute RIGHT for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03167arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3167.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03167ent IS
END c14s01b00x00p17n01i03167ent;
ARCHITECTURE c14s01b00x00p17n01i03167arch OF c14s01b00x00p17n01i03167ent IS
subtype fourbit is integer range 0 to 15;
subtype roufbit is integer range 15 downto 0;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( fourbit'right = 15 and
roufbit'right = 0 )
report "***PASSED TEST: c14s01b00x00p17n01i03167"
severity NOTE;
assert ( fourbit'right = 15 and
roufbit'right = 0 )
report "***FAILED TEST: c14s01b00x00p17n01i03167 - Predefined attribute RIGHT for integer subtype test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03167arch;
|
library ieee;
use ieee.std_logic_1164.all;
package slv is
generic(
N: integer
);
subtype slv_t is std_logic_vector(N-1 downto 0);
end package;
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafaf2708000c4034241400ac373c343c343c373c00100010",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f000cafafafafafafafafafafafafafafafaf",
INIT_02 => X"008faf03afaf270003278f0303af2740034034278f8f8f8f8f8f8f8f8f8f8f8f",
INIT_03 => X"08000caf24008faf240008af2400080010008f240010008f24af008f000caf24",
INIT_04 => X"008f8f0008af00008f8f00080010008f240010008f24af008faf24af03af2700",
INIT_05 => X"00000000000000000000000000000000000000000000000003278f0324af0000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"aaa9a8a7a6a5a4a3a2a1bd000000880884608580bd1da50584049c1c00000000",
INIT_01 => X"aeadacabaaa9a8a7a6a5a4a3a2a10000bfb9b8b7b6b5b4b3b2b1b0afaeadacab",
INIT_02 => X"00c2c0a0bebfbd00e0bdbec0a0bebd9a601b1abdbfb9b8b7b6b5b4b3b2b1b0af",
INIT_03 => X"000000824200828202000082020000006200c302006200c302c2008200008242",
INIT_04 => X"00c3c20000824300c3820000006200c302006200c302c200c2c202c4a0bebd00",
INIT_05 => X"000000000000000000000000000000000000000000000000e0bdbec002820043",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000ff000000600000ff18001f0018001800180000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"000000f00000ff00000000e8f000ff6000700000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"00000000000010000000000000000000000000000000000000000000f000ff00",
INIT_05 => X"000000000000000000000000000000000000000000000000000000e8ff001000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"2c2824201c181410040090140059000104fd2a00f80004000000000000120003",
INIT_01 => X"3c3a34302c2824201c181410040000516c6864605c5854504c4844403c3a3430",
INIT_02 => X"001010212024d80008100c21210cf000080001706c6864605c5854504c484440",
INIT_03 => X"7f00810002000000050079000100790007001803000800180218000000810001",
INIT_04 => X"00180000a3002100000000a3000a00080200080008010800180001182114e800",
INIT_05 => X"00000000000000000000000000000000000000000000000008181421ff001218",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafaf2708000c4034241400ac373c343c343c373c00100010",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f000cafafafafafafafafafafafafafafafaf",
INIT_02 => X"008faf03afaf270003278f0303af2740034034278f8f8f8f8f8f8f8f8f8f8f8f",
INIT_03 => X"08000caf24008faf240008af2400080010008f240010008f24af008f000caf24",
INIT_04 => X"008f8f0008af00008f8f00080010008f240010008f24af008faf24af03af2700",
INIT_05 => X"00000000000000000000000000000000000000000000000003278f0324af0000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"aaa9a8a7a6a5a4a3a2a1bd000000880884608580bd1da50584049c1c00000000",
INIT_01 => X"aeadacabaaa9a8a7a6a5a4a3a2a10000bfb9b8b7b6b5b4b3b2b1b0afaeadacab",
INIT_02 => X"00c2c0a0bebfbd00e0bdbec0a0bebd9a601b1abdbfb9b8b7b6b5b4b3b2b1b0af",
INIT_03 => X"000000824200828202000082020000006200c302006200c302c2008200008242",
INIT_04 => X"00c3c20000824300c3820000006200c302006200c302c200c2c202c4a0bebd00",
INIT_05 => X"000000000000000000000000000000000000000000000000e0bdbec002820043",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000ff000000600000ff18001f0018001800180000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"000000f00000ff00000000e8f000ff6000700000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"00000000000010000000000000000000000000000000000000000000f000ff00",
INIT_05 => X"000000000000000000000000000000000000000000000000000000e8ff001000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"2c2824201c181410040090140059000104fd2a00f80004000000000000120003",
INIT_01 => X"3c3a34302c2824201c181410040000516c6864605c5854504c4844403c3a3430",
INIT_02 => X"001010212024d80008100c21210cf000080001706c6864605c5854504c484440",
INIT_03 => X"7f00810002000000050079000100790007001803000800180218000000810001",
INIT_04 => X"00180000a3002100000000a3000a00080200080008010800180001182114e800",
INIT_05 => X"00000000000000000000000000000000000000000000000008181421ff001218",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:37:33 05/14/2015
-- Design Name:
-- Module Name: module_IR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_IR is
port (
clk_IR: in std_logic;
nreset: in std_logic;
LD_IR1, LD_IR2, LD_IR3: in std_logic; -- ¿ØÖÆÐźÅ
nARen: in std_logic; -- ramµØÖ·¿ØÖÆÐźÅ
datai: in std_logic_vector(7 downto 0);
IR: out std_logic_vector(7 downto 0); -- IRÖ¸Áî±àÂë
PC: out std_logic_vector(11 downto 0); -- PCеØÖ·
ARo: out std_logic_vector(6 downto 0); -- RAM¶ÁдµØÖ·
ao: out std_logic;
RS, RD: out std_logic); -- Ô´¼Ä´æÆ÷ºÍÄ¿µÄ¼Ä´æÆ÷
end module_IR;
architecture Behavioral of module_IR is
signal thePC2AR: std_logic_vector(6 downto 0);
begin
process(nreset, clk_IR)
begin
if nreset = '0' then
thePC2AR <= (others => '0');
elsif rising_edge(clk_IR) then
if LD_IR1 = '1' then
IR <= datai;
RS <= datai(0);
RD <= datai(1);
ARo <= (others => 'Z');
ao <= '0';
elsif LD_IR2 = '1' then
PC(11 downto 8) <= datai(3 downto 0);
ARo <= (others => 'Z');
ao <= '0';
elsif LD_IR3 = '1' then
PC(7 downto 0) <= datai(7 downto 0);
thePC2AR <= datai(6 downto 0);
ARo <= (others => 'Z');
ao <= '0';
elsif nARen = '0' then
ARo <= thePC2AR;
ao <= '1';
else
ARo <= (others => 'Z');
ao <= '0';
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--! @file dpRamSplx-e.vhd
--
--! @brief Simplex Dual Port Ram Entity
--
--! @details This is the Simplex DPRAM entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRamSplx is
generic (
--! Word width port A [bit]
gWordWidthA : natural := 16;
--! Byteenable width port A [bit]
gByteenableWidthA : natural := 2;
--! Number of words (reference is port A)
gNumberOfWordsA : natural := 1024;
--! Word width port B [bit]
gWordWidthB : natural := 32;
--! Number of words (reference is port B)
gNumberOfWordsB : natural := 512;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWordsA)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gByteenableWidthA-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidthA-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWordsB)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidthB-1 downto 0)
);
end dpRamSplx;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_SUBB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Subtract ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_subb;
ARCHITECTURE rtl OF dp_subb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal bbinv : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
gia: FOR k IN 1 TO width GENERATE
bbinv(k) <= NOT(bb(k));
END GENERATE;
-- lpm_add_sub subs 1's complement of bb
ccnode <= aa + bbinv + (zerovec & borrowin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity issue is
end issue;
architecture beh of issue is
procedure foo is
variable cnt : integer;
begin
cnt := cnt - 1;
end procedure;
begin
foo;
end architecture beh;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_pwm_interface_pkg IS
CONSTANT c_max_number_of_PWMs : INTEGER := 16; --Depens off the address with and the number of registers per pwm
CONSTANT c_pwm_interface_address_width : INTEGER := 6;
COMPONENT avalon_pwm_interface IS
GENERIC (
number_of_pwms: INTEGER RANGE 0 TO c_max_number_of_PWMs := 1;
base_clk: INTEGER := 125000000;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_pwm_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_pwm : OUT STD_LOGIC_VECTOR(number_of_pwms-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT c_pwm_subtype_id : INTEGER := 0;
CONSTANT c_pwm_interface_version : INTEGER := 0;
END PACKAGE avalon_pwm_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.adjustable_pwm_pkg.ALL;
USE work.avalon_pwm_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY avalon_pwm_interface IS
GENERIC (
number_of_pwms: INTEGER RANGE 0 TO c_max_number_of_PWMs := 1;
base_clk: INTEGER := 125000000;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_pwm_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_pwm : OUT STD_LOGIC_VECTOR(number_of_pwms-1 DOWNTO 0)
);
CONSTANT c_usig_base_clk_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers, c_pwm_interface_address_width);
CONSTANT c_usig_frequency_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := c_usig_base_clk_address + 1;
CONSTANT c_usig_ratio_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := c_usig_frequency_address + number_of_pwms;
CONSTANT c_usig_max_address : UNSIGNED(c_pwm_interface_address_width-1 DOWNTO 0) := c_usig_ratio_address + number_of_pwms;
END ENTITY avalon_pwm_interface;
ARCHITECTURE rtl OF avalon_pwm_interface IS
Type t_pwm_regs IS ARRAY(number_of_pwms-1 DOWNTO 0) OF UNSIGNED(c_fLink_avs_data_width-1 DOWNTO 0);
TYPE t_internal_register IS RECORD
frequency_regs : t_pwm_regs;
ratio_regs : t_pwm_regs;
conf_reg : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
END RECORD;
SIGNAL pwm_reset_n : STD_LOGIC;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
gen_pwm:
FOR i IN 0 TO number_of_pwms-1 GENERATE
my_adjustable_pwm : adjustable_pwm
GENERIC MAP (frequency_resolution =>c_fLink_avs_data_width)
PORT MAP (isl_clk,pwm_reset_n,ri.frequency_regs(i),ri.ratio_regs(i),oslv_pwm(i));
END GENERATE gen_pwm;
-- combinatorial process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,islv_avs_byteenable)
VARIABLE vi : t_internal_register;
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
pwm_reset_n <= '1';
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF UNSIGNED(islv_avs_address) = to_unsigned(c_fLink_configuration_address,c_pwm_interface_address_width) THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.conf_reg((i + 1) * 8 - 1 DOWNTO i * 8) := islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8);
END IF;
END LOOP;
ELSIF UNSIGNED(islv_avs_address)>= c_usig_frequency_address AND UNSIGNED(islv_avs_address)< c_usig_ratio_address THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.frequency_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_frequency_address))((i + 1) * 8 - 1 DOWNTO i * 8) := UNSIGNED(islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8));
END IF;
END LOOP;
ELSIF UNSIGNED(islv_avs_address)>= c_usig_ratio_address AND UNSIGNED(islv_avs_address)< c_usig_max_address THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.ratio_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_ratio_address))((i + 1) * 8 - 1 DOWNTO i * 8) := UNSIGNED(islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8));
END IF;
END LOOP;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE UNSIGNED(islv_avs_address) IS
WHEN to_unsigned(c_fLink_typdef_address,c_pwm_interface_address_width) =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_pwm_out_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(c_pwm_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(c_pwm_interface_version,c_fLink_interface_version_length));
WHEN to_unsigned(c_fLink_mem_size_address,c_pwm_interface_address_width) =>
oslv_avs_read_data(c_pwm_interface_address_width+2) <= '1';
WHEN to_unsigned(c_fLink_number_of_channels_address,c_pwm_interface_address_width) =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(number_of_pwms,c_fLink_avs_data_width));
WHEN to_unsigned(c_fLink_configuration_address,c_pwm_interface_address_width) =>
oslv_avs_read_data <= vi.conf_reg;
WHEN to_unsigned(c_fLink_unique_id_address,c_pwm_interface_address_width) =>
oslv_avs_read_data <= unique_id;
WHEN c_usig_base_clk_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(base_clk,c_fLink_avs_data_width));
WHEN OTHERS =>
IF UNSIGNED(islv_avs_address)>= c_usig_frequency_address AND UNSIGNED(islv_avs_address)< c_usig_ratio_address THEN
oslv_avs_read_data <= STD_LOGIC_VECTOR(vi.frequency_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_frequency_address)));
ELSIF UNSIGNED(islv_avs_address)>= c_usig_ratio_address AND UNSIGNED(islv_avs_address)< c_usig_max_address THEN
oslv_avs_read_data <= STD_LOGIC_VECTOR(vi.ratio_regs(to_integer(UNSIGNED(islv_avs_address)-c_usig_ratio_address)));
ELSE
oslv_avs_read_data <= (OTHERS => '0');
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.conf_reg(c_fLink_reset_bit_num) = '1' THEN
vi.conf_reg := (OTHERS =>'0');
pwm_reset_n <= '0';
FOR i IN 0 TO number_of_pwms-1 LOOP
vi.frequency_regs(i) := (OTHERS => '0');
vi.ratio_regs(i) := (OTHERS => '1');
END LOOP;
END IF;
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: top entity
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.comppack.all;
use work.fpupack.all;
entity fpu is
port (
clk_i : in std_logic;
-- Input Operands A & B
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0); -- Default: FP_WIDTH=32
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
-- fpu operations (fpu_op_i):
-- ========================
-- 000 = add,
-- 001 = substract,
-- 010 = multiply,
-- 011 = divide,
-- 100 = square root
-- 101 = unused
-- 110 = unused
-- 111 = unused
fpu_op_i : in std_logic_vector(2 downto 0);
-- Rounding Mode:
-- ==============
-- 00 = round to nearest even(default),
-- 01 = round to zero,
-- 10 = round up,
-- 11 = round down
rmode_i : in std_logic_vector(1 downto 0);
-- Output port
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
-- Control signals
start_i : in std_logic; -- is also restart signal
ready_o : out std_logic;
-- Exceptions
ine_o : out std_logic; -- inexact
overflow_o : out std_logic; -- overflow
underflow_o : out std_logic; -- underflow
div_zero_o : out std_logic; -- divide by zero
inf_o : out std_logic; -- infinity
zero_o : out std_logic; -- zero
qnan_o : out std_logic; -- queit Not-a-Number
snan_o : out std_logic -- signaling Not-a-Number
);
end fpu;
architecture rtl of fpu is
constant MUL_SERIAL: integer range 0 to 1 := 0; -- 0 for parallel multiplier, 1 for serial
constant MUL_COUNT: integer:= 10; --10 for parallel multiplier, 33 for serial
-- Input/output registers
signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_fpu_op_i : std_logic_vector(2 downto 0);
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o, s_overflow_o, s_underflow_o, s_div_zero_o, s_inf_o, s_zero_o, s_qnan_o, s_snan_o : std_logic;
type t_state is (waiting,busy);
signal s_state : t_state;
signal s_start_i : std_logic;
signal s_count : integer;
signal s_output1 : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_infa, s_infb : std_logic;
-- ***Add/Substract units signals***
signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(27 downto 0);
signal prenorm_addsub_exp_o : std_logic_vector(7 downto 0);
signal addsub_fract_o : std_logic_vector(27 downto 0);
signal addsub_sign_o : std_logic;
signal postnorm_addsub_output_o : std_logic_vector(31 downto 0);
signal postnorm_addsub_ine_o : std_logic;
-- ***Multiply units signals***
signal pre_norm_mul_exp_10 : std_logic_vector(9 downto 0);
signal pre_norm_mul_fracta_24 : std_logic_vector(23 downto 0);
signal pre_norm_mul_fractb_24 : std_logic_vector(23 downto 0);
signal mul_24_fract_48 : std_logic_vector(47 downto 0);
signal mul_24_sign : std_logic;
signal serial_mul_fract_48 : std_logic_vector(47 downto 0);
signal serial_mul_sign : std_logic;
signal mul_fract_48: std_logic_vector(47 downto 0);
signal mul_sign: std_logic;
signal post_norm_mul_output : std_logic_vector(31 downto 0);
signal post_norm_mul_ine : std_logic;
-- ***Division units signals***
signal pre_norm_div_dvdnd : std_logic_vector(49 downto 0);
signal pre_norm_div_dvsor : std_logic_vector(26 downto 0);
signal pre_norm_div_exp : std_logic_vector(EXP_WIDTH+1 downto 0);
signal serial_div_qutnt : std_logic_vector(26 downto 0);
signal serial_div_rmndr : std_logic_vector(26 downto 0);
signal serial_div_sign : std_logic;
signal serial_div_div_zero : std_logic;
signal post_norm_div_output : std_logic_vector(31 downto 0);
signal post_norm_div_ine : std_logic;
-- ***Square units***
signal pre_norm_sqrt_fracta_o : std_logic_vector(51 downto 0);
signal pre_norm_sqrt_exp_o : std_logic_vector(7 downto 0);
signal sqrt_sqr_o : std_logic_vector(25 downto 0);
signal sqrt_ine_o : std_logic;
signal post_norm_sqrt_output : std_logic_vector(31 downto 0);
signal post_norm_sqrt_ine_o : std_logic;
begin
--***Add/Substract units***
i_prenorm_addsub: pre_norm_addsub
port map (
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
fracta_28_o => prenorm_addsub_fracta_28_o,
fractb_28_o => prenorm_addsub_fractb_28_o,
exp_o=> prenorm_addsub_exp_o);
i_addsub: addsub_28
port map(
clk_i => clk_i,
fpu_op_i => s_fpu_op_i(0),
fracta_i => prenorm_addsub_fracta_28_o,
fractb_i => prenorm_addsub_fractb_28_o,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
fract_o => addsub_fract_o,
sign_o => addsub_sign_o);
i_postnorm_addsub: post_norm_addsub
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
fract_28_i => addsub_fract_o,
exp_i => prenorm_addsub_exp_o,
sign_i => addsub_sign_o,
fpu_op_i => s_fpu_op_i(0),
rmode_i => s_rmode_i,
output_o => postnorm_addsub_output_o,
ine_o => postnorm_addsub_ine_o
);
--***Multiply units***
i_pre_norm_mul: pre_norm_mul
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_o => pre_norm_mul_exp_10,
fracta_24_o => pre_norm_mul_fracta_24,
fractb_24_o => pre_norm_mul_fractb_24);
i_mul_24 : mul_24
port map(
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
start_i => start_i,
fract_o => mul_24_fract_48,
sign_o => mul_24_sign,
ready_o => open);
i_serial_mul : serial_mul
port map(
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
start_i => s_start_i,
fract_o => serial_mul_fract_48,
sign_o => serial_mul_sign,
ready_o => open);
-- serial or parallel multiplier will be choosed depending on constant MUL_SERIAL
mul_fract_48 <= mul_24_fract_48 when MUL_SERIAL=0 else serial_mul_fract_48;
mul_sign <= mul_24_sign when MUL_SERIAL=0 else serial_mul_sign;
i_post_norm_mul : post_norm_mul
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_i => pre_norm_mul_exp_10,
fract_48_i => mul_fract_48,
sign_i => mul_24_sign,
rmode_i => s_rmode_i,
output_o => post_norm_mul_output,
ine_o => post_norm_mul_ine
);
--***Division units***
i_pre_norm_div : pre_norm_div
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_o => pre_norm_div_exp,
dvdnd_50_o => pre_norm_div_dvdnd,
dvsor_27_o => pre_norm_div_dvsor);
i_serial_div : serial_div
port map(
clk_i=> clk_i,
dvdnd_i => pre_norm_div_dvdnd,
dvsor_i => pre_norm_div_dvsor,
sign_dvd_i => s_opa_i(31),
sign_div_i => s_opb_i(31),
start_i => s_start_i,
ready_o => open,
qutnt_o => serial_div_qutnt,
rmndr_o => serial_div_rmndr,
sign_o => serial_div_sign,
div_zero_o => serial_div_div_zero);
i_post_norm_div : post_norm_div
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
qutnt_i => serial_div_qutnt,
rmndr_i => serial_div_rmndr,
exp_10_i => pre_norm_div_exp,
sign_i => serial_div_sign,
rmode_i => s_rmode_i,
output_o => post_norm_div_output,
ine_o => post_norm_div_ine);
--***Square units***
i_pre_norm_sqrt : pre_norm_sqrt
port map(
clk_i => clk_i,
opa_i => s_opa_i,
fracta_52_o => pre_norm_sqrt_fracta_o,
exp_o => pre_norm_sqrt_exp_o);
i_sqrt: sqrt
generic map(RD_WIDTH=>52, SQ_WIDTH=>26)
port map(
clk_i => clk_i,
rad_i => pre_norm_sqrt_fracta_o,
start_i => s_start_i,
ready_o => open,
sqr_o => sqrt_sqr_o,
ine_o => sqrt_ine_o);
i_post_norm_sqrt : post_norm_sqrt
port map(
clk_i => clk_i,
opa_i => s_opa_i,
fract_26_i => sqrt_sqr_o,
exp_i => pre_norm_sqrt_exp_o,
ine_i => sqrt_ine_o,
rmode_i => s_rmode_i,
output_o => post_norm_sqrt_output,
ine_o => post_norm_sqrt_ine_o);
-----------------------------------------------------------------
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_opb_i <= opb_i;
s_fpu_op_i <= fpu_op_i;
s_rmode_i <= rmode_i;
s_start_i <= start_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
overflow_o <= s_overflow_o;
underflow_o <= s_underflow_o;
div_zero_o <= s_div_zero_o;
inf_o <= s_inf_o;
zero_o <= s_zero_o;
qnan_o <= s_qnan_o;
snan_o <= s_snan_o;
end if;
end process;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
s_count <= 0;
elsif s_count=5 and ((fpu_op_i="000") or (fpu_op_i="001")) then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=MUL_COUNT and fpu_op_i="010" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=33 and fpu_op_i="011" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=33 and fpu_op_i="100" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_state=busy then
s_count <= s_count + 1;
else
s_state <= waiting;
ready_o <= '0';
end if;
end if;
end process;
-- Output Multiplexer
process(clk_i)
begin
if rising_edge(clk_i) then
if fpu_op_i="000" or fpu_op_i="001" then
s_output1 <= postnorm_addsub_output_o;
s_ine_o <= postnorm_addsub_ine_o;
elsif fpu_op_i="010" then
s_output1 <= post_norm_mul_output;
s_ine_o <= post_norm_mul_ine;
elsif fpu_op_i="011" then
s_output1 <= post_norm_div_output;
s_ine_o <= post_norm_div_ine;
elsif fpu_op_i="100" then
s_output1 <= post_norm_sqrt_output;
s_ine_o <= post_norm_sqrt_ine_o;
else
s_output1 <= (others => '0');
s_ine_o <= '0';
end if;
end if;
end process;
s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
--In round down: the subtraction of two equal numbers other than zero are always -0!!!
process(s_output1, s_rmode_i, s_div_zero_o, s_infa, s_infb, s_qnan_o, s_snan_o, s_zero_o, s_fpu_op_i, s_opa_i, s_opb_i )
begin
if s_rmode_i="00" or (s_div_zero_o or (s_infa or s_infb) or s_qnan_o or s_snan_o)='1' then --round-to-nearest-even
s_output_o <= s_output1;
elsif s_rmode_i="01" and s_output1(30 downto 23)="11111111" then
--In round-to-zero: the sum of two non-infinity operands is never infinity,even if an overflow occures
s_output_o <= s_output1(31) & "1111111011111111111111111111111";
elsif s_rmode_i="10" and s_output1(31 downto 23)="111111111" then
--In round-up: the sum of two non-infinity operands is never negative infinity,even if an overflow occures
s_output_o <= "11111111011111111111111111111111";
elsif s_rmode_i="11" then
--In round-down: a-a= -0
if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(31) or (s_fpu_op_i(0) xor s_opb_i(31)))='1' then
s_output_o <= "1" & s_output1(30 downto 0);
--In round-down: the sum of two non-infinity operands is never postive infinity,even if an overflow occures
elsif s_output1(31 downto 23)="011111111" then
s_output_o <= "01111111011111111111111111111111";
else
s_output_o <= s_output1;
end if;
else
s_output_o <= s_output1;
end if;
end process;
-- Generate Exceptions
s_underflow_o <= '1' when s_output1(30 downto 23)="00000000" and s_ine_o='1' else '0';
s_overflow_o <= '1' when s_output1(30 downto 23)="11111111" and s_ine_o='1' else '0';
s_div_zero_o <= serial_div_div_zero when fpu_op_i="011" else '0';
s_inf_o <= '1' when s_output1(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0';
s_zero_o <= '1' when or_reduce(s_output1(30 downto 0))='0' else '0';
s_qnan_o <= '1' when s_output1(30 downto 0)=QNAN else '0';
s_snan_o <= '1' when s_opa_i(30 downto 0)=SNAN or s_opb_i(30 downto 0)=SNAN else '0';
end rtl; |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: top entity
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.comppack.all;
use work.fpupack.all;
entity fpu is
port (
clk_i : in std_logic;
-- Input Operands A & B
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0); -- Default: FP_WIDTH=32
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
-- fpu operations (fpu_op_i):
-- ========================
-- 000 = add,
-- 001 = substract,
-- 010 = multiply,
-- 011 = divide,
-- 100 = square root
-- 101 = unused
-- 110 = unused
-- 111 = unused
fpu_op_i : in std_logic_vector(2 downto 0);
-- Rounding Mode:
-- ==============
-- 00 = round to nearest even(default),
-- 01 = round to zero,
-- 10 = round up,
-- 11 = round down
rmode_i : in std_logic_vector(1 downto 0);
-- Output port
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
-- Control signals
start_i : in std_logic; -- is also restart signal
ready_o : out std_logic;
-- Exceptions
ine_o : out std_logic; -- inexact
overflow_o : out std_logic; -- overflow
underflow_o : out std_logic; -- underflow
div_zero_o : out std_logic; -- divide by zero
inf_o : out std_logic; -- infinity
zero_o : out std_logic; -- zero
qnan_o : out std_logic; -- queit Not-a-Number
snan_o : out std_logic -- signaling Not-a-Number
);
end fpu;
architecture rtl of fpu is
constant MUL_SERIAL: integer range 0 to 1 := 0; -- 0 for parallel multiplier, 1 for serial
constant MUL_COUNT: integer:= 10; --10 for parallel multiplier, 33 for serial
-- Input/output registers
signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_fpu_op_i : std_logic_vector(2 downto 0);
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o, s_overflow_o, s_underflow_o, s_div_zero_o, s_inf_o, s_zero_o, s_qnan_o, s_snan_o : std_logic;
type t_state is (waiting,busy);
signal s_state : t_state;
signal s_start_i : std_logic;
signal s_count : integer;
signal s_output1 : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_infa, s_infb : std_logic;
-- ***Add/Substract units signals***
signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(27 downto 0);
signal prenorm_addsub_exp_o : std_logic_vector(7 downto 0);
signal addsub_fract_o : std_logic_vector(27 downto 0);
signal addsub_sign_o : std_logic;
signal postnorm_addsub_output_o : std_logic_vector(31 downto 0);
signal postnorm_addsub_ine_o : std_logic;
-- ***Multiply units signals***
signal pre_norm_mul_exp_10 : std_logic_vector(9 downto 0);
signal pre_norm_mul_fracta_24 : std_logic_vector(23 downto 0);
signal pre_norm_mul_fractb_24 : std_logic_vector(23 downto 0);
signal mul_24_fract_48 : std_logic_vector(47 downto 0);
signal mul_24_sign : std_logic;
signal serial_mul_fract_48 : std_logic_vector(47 downto 0);
signal serial_mul_sign : std_logic;
signal mul_fract_48: std_logic_vector(47 downto 0);
signal mul_sign: std_logic;
signal post_norm_mul_output : std_logic_vector(31 downto 0);
signal post_norm_mul_ine : std_logic;
-- ***Division units signals***
signal pre_norm_div_dvdnd : std_logic_vector(49 downto 0);
signal pre_norm_div_dvsor : std_logic_vector(26 downto 0);
signal pre_norm_div_exp : std_logic_vector(EXP_WIDTH+1 downto 0);
signal serial_div_qutnt : std_logic_vector(26 downto 0);
signal serial_div_rmndr : std_logic_vector(26 downto 0);
signal serial_div_sign : std_logic;
signal serial_div_div_zero : std_logic;
signal post_norm_div_output : std_logic_vector(31 downto 0);
signal post_norm_div_ine : std_logic;
-- ***Square units***
signal pre_norm_sqrt_fracta_o : std_logic_vector(51 downto 0);
signal pre_norm_sqrt_exp_o : std_logic_vector(7 downto 0);
signal sqrt_sqr_o : std_logic_vector(25 downto 0);
signal sqrt_ine_o : std_logic;
signal post_norm_sqrt_output : std_logic_vector(31 downto 0);
signal post_norm_sqrt_ine_o : std_logic;
begin
--***Add/Substract units***
i_prenorm_addsub: pre_norm_addsub
port map (
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
fracta_28_o => prenorm_addsub_fracta_28_o,
fractb_28_o => prenorm_addsub_fractb_28_o,
exp_o=> prenorm_addsub_exp_o);
i_addsub: addsub_28
port map(
clk_i => clk_i,
fpu_op_i => s_fpu_op_i(0),
fracta_i => prenorm_addsub_fracta_28_o,
fractb_i => prenorm_addsub_fractb_28_o,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
fract_o => addsub_fract_o,
sign_o => addsub_sign_o);
i_postnorm_addsub: post_norm_addsub
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
fract_28_i => addsub_fract_o,
exp_i => prenorm_addsub_exp_o,
sign_i => addsub_sign_o,
fpu_op_i => s_fpu_op_i(0),
rmode_i => s_rmode_i,
output_o => postnorm_addsub_output_o,
ine_o => postnorm_addsub_ine_o
);
--***Multiply units***
i_pre_norm_mul: pre_norm_mul
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_o => pre_norm_mul_exp_10,
fracta_24_o => pre_norm_mul_fracta_24,
fractb_24_o => pre_norm_mul_fractb_24);
i_mul_24 : mul_24
port map(
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
start_i => start_i,
fract_o => mul_24_fract_48,
sign_o => mul_24_sign,
ready_o => open);
i_serial_mul : serial_mul
port map(
clk_i => clk_i,
fracta_i => pre_norm_mul_fracta_24,
fractb_i => pre_norm_mul_fractb_24,
signa_i => s_opa_i(31),
signb_i => s_opb_i(31),
start_i => s_start_i,
fract_o => serial_mul_fract_48,
sign_o => serial_mul_sign,
ready_o => open);
-- serial or parallel multiplier will be choosed depending on constant MUL_SERIAL
mul_fract_48 <= mul_24_fract_48 when MUL_SERIAL=0 else serial_mul_fract_48;
mul_sign <= mul_24_sign when MUL_SERIAL=0 else serial_mul_sign;
i_post_norm_mul : post_norm_mul
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_i => pre_norm_mul_exp_10,
fract_48_i => mul_fract_48,
sign_i => mul_24_sign,
rmode_i => s_rmode_i,
output_o => post_norm_mul_output,
ine_o => post_norm_mul_ine
);
--***Division units***
i_pre_norm_div : pre_norm_div
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
exp_10_o => pre_norm_div_exp,
dvdnd_50_o => pre_norm_div_dvdnd,
dvsor_27_o => pre_norm_div_dvsor);
i_serial_div : serial_div
port map(
clk_i=> clk_i,
dvdnd_i => pre_norm_div_dvdnd,
dvsor_i => pre_norm_div_dvsor,
sign_dvd_i => s_opa_i(31),
sign_div_i => s_opb_i(31),
start_i => s_start_i,
ready_o => open,
qutnt_o => serial_div_qutnt,
rmndr_o => serial_div_rmndr,
sign_o => serial_div_sign,
div_zero_o => serial_div_div_zero);
i_post_norm_div : post_norm_div
port map(
clk_i => clk_i,
opa_i => s_opa_i,
opb_i => s_opb_i,
qutnt_i => serial_div_qutnt,
rmndr_i => serial_div_rmndr,
exp_10_i => pre_norm_div_exp,
sign_i => serial_div_sign,
rmode_i => s_rmode_i,
output_o => post_norm_div_output,
ine_o => post_norm_div_ine);
--***Square units***
i_pre_norm_sqrt : pre_norm_sqrt
port map(
clk_i => clk_i,
opa_i => s_opa_i,
fracta_52_o => pre_norm_sqrt_fracta_o,
exp_o => pre_norm_sqrt_exp_o);
i_sqrt: sqrt
generic map(RD_WIDTH=>52, SQ_WIDTH=>26)
port map(
clk_i => clk_i,
rad_i => pre_norm_sqrt_fracta_o,
start_i => s_start_i,
ready_o => open,
sqr_o => sqrt_sqr_o,
ine_o => sqrt_ine_o);
i_post_norm_sqrt : post_norm_sqrt
port map(
clk_i => clk_i,
opa_i => s_opa_i,
fract_26_i => sqrt_sqr_o,
exp_i => pre_norm_sqrt_exp_o,
ine_i => sqrt_ine_o,
rmode_i => s_rmode_i,
output_o => post_norm_sqrt_output,
ine_o => post_norm_sqrt_ine_o);
-----------------------------------------------------------------
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_opb_i <= opb_i;
s_fpu_op_i <= fpu_op_i;
s_rmode_i <= rmode_i;
s_start_i <= start_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
overflow_o <= s_overflow_o;
underflow_o <= s_underflow_o;
div_zero_o <= s_div_zero_o;
inf_o <= s_inf_o;
zero_o <= s_zero_o;
qnan_o <= s_qnan_o;
snan_o <= s_snan_o;
end if;
end process;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
s_count <= 0;
elsif s_count=5 and ((fpu_op_i="000") or (fpu_op_i="001")) then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=MUL_COUNT and fpu_op_i="010" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=33 and fpu_op_i="011" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_count=33 and fpu_op_i="100" then
s_state <= waiting;
ready_o <= '1';
s_count <=0;
elsif s_state=busy then
s_count <= s_count + 1;
else
s_state <= waiting;
ready_o <= '0';
end if;
end if;
end process;
-- Output Multiplexer
process(clk_i)
begin
if rising_edge(clk_i) then
if fpu_op_i="000" or fpu_op_i="001" then
s_output1 <= postnorm_addsub_output_o;
s_ine_o <= postnorm_addsub_ine_o;
elsif fpu_op_i="010" then
s_output1 <= post_norm_mul_output;
s_ine_o <= post_norm_mul_ine;
elsif fpu_op_i="011" then
s_output1 <= post_norm_div_output;
s_ine_o <= post_norm_div_ine;
elsif fpu_op_i="100" then
s_output1 <= post_norm_sqrt_output;
s_ine_o <= post_norm_sqrt_ine_o;
else
s_output1 <= (others => '0');
s_ine_o <= '0';
end if;
end if;
end process;
s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
--In round down: the subtraction of two equal numbers other than zero are always -0!!!
process(s_output1, s_rmode_i, s_div_zero_o, s_infa, s_infb, s_qnan_o, s_snan_o, s_zero_o, s_fpu_op_i, s_opa_i, s_opb_i )
begin
if s_rmode_i="00" or (s_div_zero_o or (s_infa or s_infb) or s_qnan_o or s_snan_o)='1' then --round-to-nearest-even
s_output_o <= s_output1;
elsif s_rmode_i="01" and s_output1(30 downto 23)="11111111" then
--In round-to-zero: the sum of two non-infinity operands is never infinity,even if an overflow occures
s_output_o <= s_output1(31) & "1111111011111111111111111111111";
elsif s_rmode_i="10" and s_output1(31 downto 23)="111111111" then
--In round-up: the sum of two non-infinity operands is never negative infinity,even if an overflow occures
s_output_o <= "11111111011111111111111111111111";
elsif s_rmode_i="11" then
--In round-down: a-a= -0
if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(31) or (s_fpu_op_i(0) xor s_opb_i(31)))='1' then
s_output_o <= "1" & s_output1(30 downto 0);
--In round-down: the sum of two non-infinity operands is never postive infinity,even if an overflow occures
elsif s_output1(31 downto 23)="011111111" then
s_output_o <= "01111111011111111111111111111111";
else
s_output_o <= s_output1;
end if;
else
s_output_o <= s_output1;
end if;
end process;
-- Generate Exceptions
s_underflow_o <= '1' when s_output1(30 downto 23)="00000000" and s_ine_o='1' else '0';
s_overflow_o <= '1' when s_output1(30 downto 23)="11111111" and s_ine_o='1' else '0';
s_div_zero_o <= serial_div_div_zero when fpu_op_i="011" else '0';
s_inf_o <= '1' when s_output1(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0';
s_zero_o <= '1' when or_reduce(s_output1(30 downto 0))='0' else '0';
s_qnan_o <= '1' when s_output1(30 downto 0)=QNAN else '0';
s_snan_o <= '1' when s_opa_i(30 downto 0)=SNAN or s_opb_i(30 downto 0)=SNAN else '0';
end rtl; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0_15;
USE axi_uartlite_v2_0_15.axi_uartlite;
ENTITY system_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END system_axi_uartlite_0_0;
ARCHITECTURE system_axi_uartlite_0_0_arch OF system_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_uartlite_0_0_arch : ARCHITECTURE IS "system_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "system_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=9600,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END system_axi_uartlite_0_0_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
entity e is
end entity;
architecture a of e is
begin
process is
begin
assert false; -- OK
assert 1 > 2 report "false"; -- OK
assert 4 < 7 report "true" severity failure; -- OK
report "boo" severity note;
end process;
process is
begin
assert 1; -- Not BOOLEAN
end process;
process is
begin
report 53; -- Not STRING
end process;
process is
begin
report "boo" severity 1; -- Not SEVERITY_LEVEL
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
begin
assert false; -- OK
assert 1 > 2 report "false"; -- OK
assert 4 < 7 report "true" severity failure; -- OK
report "boo" severity note;
end process;
process is
begin
assert 1; -- Not BOOLEAN
end process;
process is
begin
report 53; -- Not STRING
end process;
process is
begin
report "boo" severity 1; -- Not SEVERITY_LEVEL
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
begin
assert false; -- OK
assert 1 > 2 report "false"; -- OK
assert 4 < 7 report "true" severity failure; -- OK
report "boo" severity note;
end process;
process is
begin
assert 1; -- Not BOOLEAN
end process;
process is
begin
report 53; -- Not STRING
end process;
process is
begin
report "boo" severity 1; -- Not SEVERITY_LEVEL
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
begin
assert false; -- OK
assert 1 > 2 report "false"; -- OK
assert 4 < 7 report "true" severity failure; -- OK
report "boo" severity note;
end process;
process is
begin
assert 1; -- Not BOOLEAN
end process;
process is
begin
report 53; -- Not STRING
end process;
process is
begin
report "boo" severity 1; -- Not SEVERITY_LEVEL
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
begin
process is
begin
assert false; -- OK
assert 1 > 2 report "false"; -- OK
assert 4 < 7 report "true" severity failure; -- OK
report "boo" severity note;
end process;
process is
begin
assert 1; -- Not BOOLEAN
end process;
process is
begin
report 53; -- Not STRING
end process;
process is
begin
report "boo" severity 1; -- Not SEVERITY_LEVEL
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc477.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00477ent IS
END c03s02b01x01p19n01i00477ent;
ARCHITECTURE c03s02b01x01p19n01i00477arch OF c03s02b01x01p19n01i00477ent IS
function resolution3(i:in bit_vector) return bit is
variable temp : bit := '1';
begin
return temp;
end resolution3;
subtype bit_state is resolution3 bit;
constant C66 : bit_state := '1';
function complex_scalar(s : bit_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return bit_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : bit_state;
signal S2 : bit_state;
signal S3 : bit_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00477"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00477 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00477arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc477.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00477ent IS
END c03s02b01x01p19n01i00477ent;
ARCHITECTURE c03s02b01x01p19n01i00477arch OF c03s02b01x01p19n01i00477ent IS
function resolution3(i:in bit_vector) return bit is
variable temp : bit := '1';
begin
return temp;
end resolution3;
subtype bit_state is resolution3 bit;
constant C66 : bit_state := '1';
function complex_scalar(s : bit_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return bit_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : bit_state;
signal S2 : bit_state;
signal S3 : bit_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00477"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00477 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00477arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc477.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00477ent IS
END c03s02b01x01p19n01i00477ent;
ARCHITECTURE c03s02b01x01p19n01i00477arch OF c03s02b01x01p19n01i00477ent IS
function resolution3(i:in bit_vector) return bit is
variable temp : bit := '1';
begin
return temp;
end resolution3;
subtype bit_state is resolution3 bit;
constant C66 : bit_state := '1';
function complex_scalar(s : bit_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return bit_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : bit_state;
signal S2 : bit_state;
signal S3 : bit_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00477"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00477 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00477arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2688.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p02n01i02688ent IS
constant n: real := 45.3 E+11; -- failure_here
END c13s04b01x00p02n01i02688ent;
ARCHITECTURE c13s04b01x00p02n01i02688arch OF c13s04b01x00p02n01i02688ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p02n01i02688 - No space is allowed in literals."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p02n01i02688arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2688.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p02n01i02688ent IS
constant n: real := 45.3 E+11; -- failure_here
END c13s04b01x00p02n01i02688ent;
ARCHITECTURE c13s04b01x00p02n01i02688arch OF c13s04b01x00p02n01i02688ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p02n01i02688 - No space is allowed in literals."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p02n01i02688arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2688.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p02n01i02688ent IS
constant n: real := 45.3 E+11; -- failure_here
END c13s04b01x00p02n01i02688ent;
ARCHITECTURE c13s04b01x00p02n01i02688arch OF c13s04b01x00p02n01i02688ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s04b01x00p02n01i02688 - No space is allowed in literals."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p02n01i02688arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.arith namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package arith is
component arith_firstone is
generic (
N : positive -- Length of Token Chain
);
port (
tin : in std_logic := '1'; -- Enable: Fed Token
rqst : in std_logic_vector(N-1 downto 0); -- Request: Token Requests
grnt : out std_logic_vector(N-1 downto 0); -- Grant: Token Output
tout : out std_logic; -- Inactive: Unused Token
bin : out std_logic_vector(log2ceil(N)-1 downto 0) -- Binary Grant Index
);
end component;
component arith_counter_bcd is
generic (
DIGITS : positive);
port (
clk : in std_logic;
rst : in std_logic;
inc : in std_logic;
val : out T_BCD_VECTOR(DIGITS-1 downto 0));
end component;
component arith_counter_gray is
generic (
BITS : positive; -- Bit width of the counter
INIT : natural := 0 -- Initial/reset counter value
);
port (
clk : in std_logic;
rst : in std_logic; -- Reset to INIT value
inc : in std_logic; -- Increment
dec : in std_logic := '0'; -- Decrement
val : out std_logic_vector(BITS-1 downto 0); -- Value output
cry : out std_logic -- Carry output
);
end component;
component arith_div
generic (
N : positive;
RAPOW : positive;
REGISTERED : boolean);
port (
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
rdy : out std_logic;
arg1, arg2 : in std_logic_vector(N-1 downto 0);
res : out std_logic_vector(N-1 downto 0));
end component;
component arith_div_pipelined
generic (
DIVIDEND_BITS : POSITIVE;
DIVISOR_BITS : POSITIVE;
RADIX : POSITIVE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Enable : in STD_LOGIC;
Dividend : in STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
Divisor : in STD_LOGIC_VECTOR(DIVISOR_BITS - 1 downto 0);
Quotient : out STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
Valid : out STD_LOGIC
);
end component;
component arith_prng
generic (
BITS : positive;
SEED : natural := 0
);
port (
clk : in std_logic;
rst : in std_logic;
got : in std_logic;
val : out std_logic_vector(BITS-1 downto 0));
end component;
component arith_muls_wide
generic (
NA : integer range 2 to 18;
NB : integer range 19 to 36;
SPLIT : positive);
port (
a : in signed(NA-1 downto 0);
b : in signed(NB-1 downto 0);
p : out signed(NA+NB-1 downto 0));
end component;
component arith_sqrt
generic (
N : positive);
port (
rst : in std_logic;
clk : in std_logic;
arg : in std_logic_vector(N-1 downto 0);
start : in std_logic;
sqrt : out std_logic_vector((N-1)/2 downto 0);
rdy : out std_logic);
end component;
type tArch is (AAM, CAI, CCA, PAI);
type tBlocking is (DFLT, FIX, ASC, DESC);
type tSkipping is (PLAIN, CCC, PPN_KS, PPN_BK);
component arith_addw is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := AAM; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end component;
end package;
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