content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
use work.isp_hal.all;
-- Add your library and packages declaration here ...
entity hal_tb is
end hal_tb;
architecture TB_ARCHITECTURE of hal_tb is
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
sig... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
---------------------------------------------------------------------------------
-- sp0256 by Dar (darfpga@aol.fr) (14/04/2018)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Ma... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Ma... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity fetch_block is
generic (
SIZE : integer := 32
);
port (
branch_target_i : in std_logic_vector(SIZE - 1 downto 0);
sum_addr_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downt... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity fetch_block is
generic (
SIZE : integer := 32
);
port (
branch_target_i : in std_logic_vector(SIZE - 1 downto 0);
sum_addr_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downt... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- NEED RESULT: ARCH00629: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00629.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00629: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00629: One transport transaction occurred on a concurrent signal asg passed
-- NEE... |
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_ve... |
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_ve... |
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_ve... |
library verilog;
use verilog.vl_types.all;
entity full_adder_vlg_check_tst is
port(
c1 : in vl_logic;
c2 : in vl_logic;
cout : in vl_logic;
s1 : in vl_logic;
sum : in vl_logic;
sampler_r... |
--! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-... |
--------------------------------------------------------------------------------------------------
-- Interpolator
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
---------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity test_aludec is
end entity;
architecture arq_test_aludec of test_aludec is
component aludec
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
package pkg_FileIO is
-------------------------------
-- Define some basic data types
-------------------------------
subtype t_BYTE is integer range 0 to 2**8 - 1;
---------------------------------------
-- And arrays of those basic data types
-------------------------------------... |
package pkg_FileIO is
-------------------------------
-- Define some basic data types
-------------------------------
subtype t_BYTE is integer range 0 to 2**8 - 1;
---------------------------------------
-- And arrays of those basic data types
-------------------------------------... |
-- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate2.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- **... |
-------------------------------------------------------------------------------
-- Last update : Fri Jun 14 13:31:50 2019
-- Project : VHDL Mode for Sublime Text
-------------------------------------------------------------------------------
-- Description: This VHDL file is intended as a test of scope and beau... |
package ffaccel_toplevel_params is
constant fu_DATA_LSU_addrw_g : integer := 12;
constant fu_PARAM_LSU_addrw_g : integer := 32;
constant fu_SP_LSU_addrw_g : integer := 10;
end ffaccel_toplevel_params;
|
package ffaccel_toplevel_params is
constant fu_DATA_LSU_addrw_g : integer := 12;
constant fu_PARAM_LSU_addrw_g : integer := 32;
constant fu_SP_LSU_addrw_g : integer := 10;
end ffaccel_toplevel_params;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ForLoop is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_lo... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hex_lcd_driver is
port(
CLK: in std_logic;
DIG0: in std_logic_vector(3 downto 0);
DIG1: in std_logic_vector(3 downto 0);
DIG2: in std_logic_vector(3 downto 0);
DIG3: in std_logic_vector(3 downto 0);
SEV... |
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
library work ;
use work.nco_p.all ;
entity fsk_modulator is
port (
clock : in std_logic ;
reset : in std_logic ;
symbol : in std_logic ;
... |
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variab... |
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variab... |
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variab... |
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variab... |
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variab... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test3 is
port(
clk : in std_logic;
write_data : in std_ulogic;
arst : std_ulogic
);
end;
architecture rtl of test3 is
begin
test_1: process(clk, arst)
begin
if arst = '1' then
null;
... |
entity bb is
end entity;
architecture aa of bb is
signal x, y, z : integer;
signal w : bit_vector(1 to 3);
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wa... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 12-02-2016
-- Module Name: mux.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;... |
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-29-10
-- Platform : FPGA-gene... |
--!
--! Copyright (C) 2010 - 2012 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Generic single port RAM with a single read/write port
--! @author Matthias Alles
--! @date 2010/09/28... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and coun... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcdctl is
Port ( clk,reset : in STD_LOGIC;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ud : out STD_LOGIC;
rl : out STD_LOGIC;
enab : out ST... |
/*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be... |
--!
--! @file: example9_4.vhd
--! @brief: procedure min_max in a package
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_components.all;
--------------------------------------
... |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_sha256
-- sha256_pl.vhd is part of DS_sha256.
-- DS_sha256 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General ... |
library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_dif... |
library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_dif... |
library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_dif... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
package testbench is
constant zero: std_logic_vector(3 downto 0) := x"0";
constant one: std_logic_vector(3 downto 0) := x"1";
constant two: std_logic_vector(3 downto 0) := x"2";
constant three: std_logic_vector(3 downto 0) := x"3";
constant four: std_log... |
library ieee;
use ieee.std_logic_1164.all;
package testbench is
constant zero: std_logic_vector(3 downto 0) := x"0";
constant one: std_logic_vector(3 downto 0) := x"1";
constant two: std_logic_vector(3 downto 0) := x"2";
constant three: std_logic_vector(3 downto 0) := x"3";
constant four: std_log... |
library ieee;
use ieee.std_logic_1164.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
architecture behavior of c_co... |
library ieee;
use ieee.std_logic_1164.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
architecture behavior of c_co... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Fri May 9 13:48:22 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
entity test_lfsr is
end test_lfsr;
architecture behave of test_lfsr is
constant num_rng : integer := 4;
constant width : integer := 8;
type state_array_t is array(1 to num_rng) of
st... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------
-- _ __ __ __ ____ __ = --
-- | | / // / / // __ \ / / = --
-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ --
-- | |/ // __ // /_/ // /___ = /___) | ... |
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All right... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_unit is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_received_in : in STD_LOGIC;
interrupt : in STD_LOGIC;
crc... |
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_mux_2x1 IS END tb_mux_2x1;
ARCHITECTURE test OF tb_mux_2x1 IS
COMPONENT mux_2x1 IS
PORT(a, b, ctrl: ... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library PoC;
--use PoC.utils.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
package SoFPGA_sim is
type T_PB_FUNCTIONS is (
UNKNOWN, p0_ERROR_BLOCK, p0__push_arg0, p0__pop_arg0, p0__push_arg1, p0__pop_arg1, p0__push_arg2, p0__pop_ar... |
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- Microprocessor Systems Project
-- December, 6th 2018
--
-- Design: Testbench for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
-- controlled using Xilinx Picoblaze processor and whose output is displayed on seven segment
-- displa... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemen... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
-------------------------------------
-- ?g word 32 bit SRAM --
-- PORT MAPPING --
-- DATA: 32 bit input value --
-- ADDR: ceil(log2(?g)) bit address--
-- WE : 1 bit write enable --
-- EN : 1 bit enable --
-- CLK : 1 bit RAM clock --
----------------... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LatchSR_AB is
Port ( Sn : in STD_LOGIC;
Rn : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end LatchSR_AB;
architecture Behavioral of LatchSR_AB is
signal Q_aux : std_logic := '0';
signal Qn_aux : std_logic := '0';
be... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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