content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1315.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n03i01315ent IS
generic (GEN : in INTEGER);
END c08s04b00x00p07n03i01315ent;
ARCHITECTURE c08s04b00x00p07n03i01315arch OF c08s04b00x00p07n03i01315ent IS
subtype CH2 is STRING( 1 to 2 );
BEGIN
TESTING: PROCESS
variable STRV : CH2 := "bb";
variable C1, C2 : CHARACTER;
BEGIN
-- Assign to a non-signal. ERROR:
( C1,C2 ) <= STRV after 20 ns;
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p07n03i01315 - The expression in the element association is not locally static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n03i01315arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1315.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n03i01315ent IS
generic (GEN : in INTEGER);
END c08s04b00x00p07n03i01315ent;
ARCHITECTURE c08s04b00x00p07n03i01315arch OF c08s04b00x00p07n03i01315ent IS
subtype CH2 is STRING( 1 to 2 );
BEGIN
TESTING: PROCESS
variable STRV : CH2 := "bb";
variable C1, C2 : CHARACTER;
BEGIN
-- Assign to a non-signal. ERROR:
( C1,C2 ) <= STRV after 20 ns;
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p07n03i01315 - The expression in the element association is not locally static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n03i01315arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1315.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p07n03i01315ent IS
generic (GEN : in INTEGER);
END c08s04b00x00p07n03i01315ent;
ARCHITECTURE c08s04b00x00p07n03i01315arch OF c08s04b00x00p07n03i01315ent IS
subtype CH2 is STRING( 1 to 2 );
BEGIN
TESTING: PROCESS
variable STRV : CH2 := "bb";
variable C1, C2 : CHARACTER;
BEGIN
-- Assign to a non-signal. ERROR:
( C1,C2 ) <= STRV after 20 ns;
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c08s04b00x00p07n03i01315 - The expression in the element association is not locally static."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n03i01315arch;
|
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
use work.isp_hal.all;
-- Add your library and packages declaration here ...
entity hal_tb is
end hal_tb;
architecture TB_ARCHITECTURE of hal_tb is
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal d : isp_hal_in_t;
signal otg_data : STD_LOGIC_VECTOR(15 downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal q : isp_hal_out_t;
--local signals
signal slowclk_en : bit := '1';
signal write_sense :std_logic;
signal write_end_sense : std_logic;
--------------------------------------------------------------
-- clock cycle
constant period : time := 20 ns;
--------------------------------------------------------------
begin
-- Unit Under Test port map
UUT : hal
generic map(3)
port map (
clk => clk,
reset => reset,
otg_data => otg_data,
d => d,
q => q
);
--d.int <= '1'; -- not used in this tb
----------------------------------------------------
-- clock
process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process;
--produces 25MHz clock enable for OTG
p_slowclk_en: process
begin
wait until rising_edge(clk);
slowclk_en <= not(slowclk_en);
end process;
d.slowclk_en <= slowclk_en;
----------------------------------------------------
-- resets
process
begin
reset <= '1';
wait for period;
reset <= '0';
wait;
end process;
----------------------------------------------------
-- read emulation
----------------------------------------------------
process
begin
otg_data <= (others => 'Z');
wait until falling_edge(q.rd_n);
wait for 22 ns;
otg_data <= x"BEAD";
wait until rising_edge(q.cs_n);
wait for 3 ns;
end process;
----------------------------------------------------
-- write emulation
----------------------------------------------------
write_sense <= to_stdulogic(d.drv.cmd(1));
write_end_sense <= to_stdulogic(q.drv.rdy);
process
begin
wait for period;
if (write_sense = '1') then
d.drv.data <= x"FACE";
else
d.drv.data <= x"0000";
end if;
wait until rising_edge(write_end_sense);
wait until rising_edge(clk);
d.drv.data <= x"0000";
wait for period * 4;
end process;
--choose what to do
d.drv.cmd <= otg_rd; -- otg_wr; -- otg_wr_cmd;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_hal of hal_tb is
for TB_ARCHITECTURE
for UUT : hal
use entity work.hal(handler);
end for;
end for;
end TESTBENCH_FOR_hal;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.net.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package ethernet_mac is
type eth_tx_in_type is record
start : std_ulogic;
valid : std_ulogic;
data : std_logic_vector(31 downto 0);
full_duplex : std_ulogic;
length : std_logic_vector(10 downto 0);
col : std_ulogic;
crs : std_ulogic;
read_ack : std_ulogic;
end record;
type eth_tx_out_type is record
status : std_logic_vector(1 downto 0);
done : std_ulogic;
restart : std_ulogic;
read : std_ulogic;
tx_er : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
end record;
type eth_rx_in_type is record
writeok : std_ulogic;
rxen : std_ulogic;
rx_dv : std_ulogic;
rx_er : std_ulogic;
rxd : std_logic_vector(3 downto 0);
done_ack : std_ulogic;
write_ack : std_ulogic;
end record;
type eth_rx_out_type is record
write : std_ulogic;
data : std_logic_vector(31 downto 0);
done : std_ulogic;
length : std_logic_vector(10 downto 0);
status : std_logic_vector(2 downto 0);
start : std_ulogic;
end record;
type eth_mdio_in_type is record
mdioi : std_ulogic;
write : std_ulogic;
read : std_ulogic;
mdiostart : std_ulogic;
regadr : std_logic_vector(4 downto 0);
phyadr : std_logic_vector(4 downto 0);
data : std_logic_vector(15 downto 0);
end record;
type eth_mdio_out_type is record
mdc : std_ulogic;
mdioo : std_ulogic;
mdioen : std_ulogic;
data : std_logic_vector(15 downto 0);
done : std_ulogic;
error : std_ulogic;
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
component eth_ahb_mst is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
generic(
hindex : integer := 0;
revision : integer := 0;
irq : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
end package;
|
---------------------------------------------------------------------------------
-- sp0256 by Dar (darfpga@aol.fr) (14/04/2018)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
--
-- SP0256-al2 prom decoding scheme and speech synthesis algorithm are from :
--
-- Copyright Joseph Zbiciak, all rights reserved.
-- Copyright tim lindner, all rights reserved.
--
-- See C source code and license in sp0256.c from MAME source
--
-- VHDL code is by Dar.
--
---------------------------------------------------------------------------------
--
-- One allophone is made of N parts (called here after lines), each part has a
-- 16 bytes descriptor. One descriptor (for one part) contains one repeat value
-- one amplitude value, one period value and 2x6 filtering coefficients.
--
-- for line_cnt from 0 to nb_line-1 (part)
-- for line_rpt from 0 to line_rpt-1 (repeat)
-- for per_cnt from 0 to line_per-1 (period)
-- produce 1 sample
--
-- One sample is the output of the 6 stages filter. Each filter stage is fed by
-- the output of the previous stage, the first stage is fed by the source sample
--
-- when line_per != 0 source sample is set to amplitude value only once at the
-- begin of each repeat (per_cnt==0) then source sample is set to 0
--
-- when line_per == 0 source sample is set to amplitude value only at the begin
-- of each repeat (per_cnt==0) then source sample sign is toggled (+/-) when then
-- random noise generator lsb equal 1. In that case actual line_per is set to 64
--
--
-- Sound sample frequency is 10kHz. I make a 25 stages linear state machine
-- running at 250kHz that produce one sound sample per cycle.
--
-- As long as one allophones is available the state machine runs permanently and
-- there is zero latency between allophones.
--
-- During one (each) cycle the state machine:
--
-- - fetch new allophone or go on with current one if not finished
-- - get allophone first line descriptor address from rom entry table
-- - get allophone nb_line from rom entry table and jump to first line address
-- - get allophone line_rpt from rom current line descriptor
-- - get allophone amplitude from rom current line descriptor
-- manage source amplitude, reset filter if needed
-- - get allophone line_per from rom current line descriptor
-- - address filter coefficients F/B within rom current line descriptor,
-- feed filter input, update filter state with computation output
-- - rescale last filter stage output to audio output
-- - manage per_cnt, rpt_cnt, line_cnt and random noise generator
--
-- Filter computation:
--
-- Filter coefficients F or B index is get from rom current line descriptor
-- (address managed by state machine), value is converted thru coeff_array
-- table. Coefficient index has a sign bit to be managed:
--
-- if index sign bit = 0, filter coefficient <= -coeff_array(index)
-- if index sign bit = 1, filter coefficient <= coeff_array(-index)
--
-- During one state machine cycle each filter is updated once.
-- One filter update require two state machine steps:
--
-- step 1
-- sum_in1 <= filter input
-- sum_in2 <= filter coefficient F * filter state z1 / 256
-- sum_out <= sum_in1 + sum_in2
-- step 2
-- sum_in1 <= sum_out
-- sum_in2 <= filter coefficient B * filter state z2 / 512
-- sum_out <= sum_in1 + sum_in2
-- filter state z1 <= sum_in1 + sum_in2
-- filter state z2 <= filter state z1
--
-- (sum_out will be limited to -32768/+32767)
--
-- Audio output scaling to 10bits unsigned:
--
-- what :
-- Last filter output is limited to -8192/+8191
-- Then divided by 16 => -512/+511
-- Then offset by 512 => 0/1023
--
-- how:
-- if X > 8191, Y <= 1023
-- elsif X < -8192, Y <= 0
-- else Y <= (X/16)+512
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity sp0256 is
port
(
clock : in std_logic;
clock_250k_en : in std_logic;
reset : in std_logic;
input_rdy : out std_logic;
allophone : in std_logic_vector(5 downto 0);
trig_allophone : in std_logic;
audio_out : out std_logic_vector(9 downto 0)
);
end sp0256;
architecture syn of sp0256 is
signal clock_n : std_logic;
signal rom_addr : std_logic_vector(11 downto 0);
signal rom_do : std_logic_vector( 7 downto 0);
signal stage : integer range 0 to 24; -- stage counter 0-24;
signal allophone_latch : std_logic_vector(5 downto 0);
signal allo_entry : std_logic_vector(7 downto 0);
signal allo_addr_lsb, allo_addr_msb : std_logic_vector(7 downto 0);
signal allo_nb_line : std_logic_vector(7 downto 0);
signal line_rpt, line_per : std_logic_vector(7 downto 0);
signal line_amp_lsb, line_amp_msb : std_logic_vector(7 downto 0);
signal amp, filter, coeff : signed(15 downto 0);
signal sum_in2 : signed(31 downto 0);
signal sum_in1,sum_out_ul : signed(15 downto 0);
signal sum_out : signed(15 downto 0);
signal divider : std_logic;
signal audio : signed(15 downto 0);
signal is_noise : std_logic;
signal noise_rng : std_logic_vector(15 downto 0) := X"0001";
signal f0_z1,f0_z2 : signed(15 downto 0);
signal f1_z1,f1_z2 : signed(15 downto 0);
signal f2_z1,f2_z2 : signed(15 downto 0);
signal f3_z1,f3_z2 : signed(15 downto 0);
signal f4_z1,f4_z2 : signed(15 downto 0);
signal f5_z1,f5_z2 : signed(15 downto 0);
signal input_rdy_in : std_logic;
signal sound_on : std_logic := '0';
signal trig_allophone_r : std_logic;
signal line_cnt, rpt_cnt, per_cnt : std_logic_vector(7 downto 0);
signal coeff_idx : std_logic_vector(6 downto 0);
type coeff_array_t is array(0 to 127) of integer range 0 to 511;
signal coeff_array : coeff_array_t := (
0, 9, 17, 25, 33, 41, 49, 57,
65, 73, 81, 89, 97, 105, 113, 121,
129, 137, 145, 153, 161, 169, 177, 185,
193, 201, 209, 217, 225, 233, 241, 249,
257, 265, 273, 281, 289, 297, 301, 305,
309, 313, 317, 321, 325, 329, 333, 337,
341, 345, 349, 353, 357, 361, 365, 369,
373, 377, 381, 385, 389, 393, 397, 401,
405, 409, 413, 417, 421, 425, 427, 429,
431, 433, 435, 437, 439, 441, 443, 445,
447, 449, 451, 453, 455, 457, 459, 461,
463, 465, 467, 469, 471, 473, 475, 477,
479, 481, 482, 483, 484, 485, 486, 487,
488, 489, 490, 491, 492, 493, 494, 495,
496, 497, 498, 499, 500, 501, 502, 503,
504, 505, 506, 507, 508, 509, 510, 511);
begin
input_rdy <= input_rdy_in;
-- stage counter : Fs=250k/25 = 10kHz
process (clock, reset)
begin
if reset='1' then
stage <= 0;
elsif rising_edge(clock) then
if clock_250k_en = '1' then
if stage >= 24 then
stage <= 0;
else
stage <= stage + 1;
end if;
end if;
end if;
end process;
process (clock, reset)
begin
if reset='1' then
input_rdy_in <= '1';
sound_on <= '0';
noise_rng <= X"0001";
elsif rising_edge(clock) then
trig_allophone_r <= trig_allophone;
if trig_allophone = '1' and trig_allophone_r = '0' then
input_rdy_in <= '0';
allophone_latch <= allophone;
end if;
if clock_250k_en = '1' then
if sound_on = '0' then
if stage = 0 and input_rdy_in = '0' then
allo_entry <= allophone_latch*"11";
rom_addr <= X"0"&(allophone_latch*"11");
line_cnt <= (others => '0');
rpt_cnt <= (others => '0');
per_cnt <= (others => '0');
sound_on <= '1';
input_rdy_in <= '1';
end if;
else -- sound is on
case stage is
when 0 =>
rom_addr <= X"0"&allo_entry;
when 1 =>
allo_addr_msb <= rom_do;
rom_addr <= rom_addr + '1';
when 2 =>
allo_addr_lsb <= rom_do;
rom_addr <= rom_addr + '1';
when 3 =>
allo_nb_line <= rom_do - '1';
rom_addr <= (allo_addr_lsb +line_cnt) & X"0";
when 4 =>
line_rpt <= rom_do - '1';
rom_addr <= rom_addr + '1';
when 5 =>
line_amp_msb <= rom_do;
rom_addr <= rom_addr + '1';
when 6 =>
if per_cnt = X"00" then
amp <= signed(line_amp_msb & rom_do);
else
if is_noise = '1' then
if noise_rng(0) = '1' then
amp <= -amp;
end if;
else
amp <= (others => '0');
end if;
end if;
if per_cnt = X"00"then
f0_z1 <= (others => '0'); f0_z2 <= (others => '0');
f1_z1 <= (others => '0'); f1_z2 <= (others => '0');
f2_z1 <= (others => '0'); f2_z2 <= (others => '0');
f3_z1 <= (others => '0'); f3_z2 <= (others => '0');
f4_z1 <= (others => '0'); f4_z2 <= (others => '0');
f5_z1 <= (others => '0'); f5_z2 <= (others => '0');
end if;
rom_addr <= rom_addr + '1';
when 7 =>
if rom_do = X"00" then
line_per <= X"40";
is_noise <= '1';
else
line_per <= rom_do - '1';
is_noise <= '0';
end if;
sum_in1 <= amp;
filter <= f0_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 8 =>
sum_in1 <= sum_out;
filter <= f0_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 9 =>
f0_z1 <= sum_out;
f0_z2 <= f0_z1;
sum_in1 <= sum_out;
filter <= f1_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 10 =>
sum_in1 <= sum_out;
filter <= f1_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 11 =>
f1_z1 <= sum_out;
f1_z2 <= f1_z1;
sum_in1 <= sum_out;
filter <= f2_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 12 =>
sum_in1 <= sum_out;
filter <= f2_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 13 =>
f2_z1 <= sum_out;
f2_z2 <= f2_z1;
sum_in1 <= sum_out;
filter <= f3_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 14 =>
sum_in1 <= sum_out;
filter <= f3_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 15 =>
f3_z1 <= sum_out;
f3_z2 <= f3_z1;
sum_in1 <= sum_out;
filter <= f4_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 16 =>
sum_in1 <= sum_out;
filter <= f4_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 17 =>
f4_z1 <= sum_out;
f4_z2 <= f4_z1;
sum_in1 <= sum_out;
filter <= f5_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 18 =>
sum_in1 <= sum_out;
filter <= f5_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 19 =>
f5_z1 <= sum_out;
f5_z2 <= f5_z1;
if sum_out > 510*16 then
audio <= to_signed(1023,16);
elsif sum_out < -510*16 then
audio <= to_signed(0,16);
else
audio <= (sum_out/16)+X"0200";
end if;
when 20 =>
if per_cnt >= line_per then
per_cnt <= (others => '0');
if rpt_cnt >= line_rpt then
rpt_cnt <= (others => '0');
if line_cnt >= allo_nb_line then
line_cnt <= (others => '0');
sound_on <= '0';
else
line_cnt <= line_cnt + '1';
end if;
is_noise <= '0';
else
rpt_cnt <= rpt_cnt + '1';
end if;
else
per_cnt <= per_cnt + '1';
end if;
if noise_rng(0) = '1' then
noise_rng <= ('0' & noise_rng(15 downto 1) ) xor X"4001";
else
noise_rng <= '0' & noise_rng(15 downto 1);
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
audio_out <= std_logic_vector(unsigned(audio(9 downto 0)));
-- filter computation
coeff_idx <= rom_do(6 downto 0) when rom_do(7)='0' else
not(rom_do(6 downto 0)) + '1';
coeff <= -to_signed(coeff_array(to_integer(unsigned(coeff_idx))),16) when rom_do(7)='0' else
to_signed(coeff_array(to_integer(unsigned(coeff_idx))),16);
sum_in2 <= (filter * coeff) / 256 when divider = '0' else
(filter * coeff) / 512 ;
sum_out_ul <= sum_in1 + sum_in2(15 downto 0);
sum_out <= to_signed( 32767,16) when sum_out_ul > 32767 else
to_signed(-32768,16) when sum_out_ul < -32768 else
sum_out_ul;
-- sp0256-al2 prom (decoded)
sp0256_al2_decoded : entity work.sp0256_al2_decoded
port map(
clk => clock,
addr => rom_addr,
data => rom_do
);
end syn;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Module: FIFO, Common Clock (cc), Pipelined Interface
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- DATA_REG (=true) is a hint, that distributed memory or registers should be
-- used as data storage. The actual memory type depends on the device
-- architecture. See implementation for details.
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
use poc.utils.all;
use poc.ocram.all;
entity fifo_cc_got is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0)
);
end fifo_cc_got;
architecture rtl of fifo_cc_got is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
OP0 <= (others => '0');
else
-- Update Input Pointer upon Write
if we = '1' then
IP0 <= IP1;
end if;
-- Update Output Pointer upon Read
if re = '1' then
OP0 <= OP1;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(IP0, OP0, fulli)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
estate_wr <= (others => 'X');
fstate_rd <= (others => 'X');
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
-- Fix assignment to outputs
if ESTATE_WR_BITS > 0 then
-- one's complement is pessimistically low by one but
-- benefits optimization by synthesis
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
end if;
if FSTATE_RD_BITS > 0 then
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
-- Cheapest implementation using a direction flag DF to determine
-- full or empty condition on equal input and output pointers.
-- Both conditions are derived combinationally involving a comparison
-- of the two pointers.
genStateCmb: if not STATE_REG generate
signal DF : std_logic := '0'; -- Direction Flag
signal Peq : std_logic; -- Pointer Comparison
begin
-- Direction Flag remembering the last Operation
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
DF <= '0'; -- get => empty
elsif we /= re then
DF <= we;
end if;
end if;
end process;
-- Fill Conditions
Peq <= '1' when IP0 = OP0 else '0';
fulli <= Peq and DF;
empti <= Peq and not DF;
end generate genStateCmb;
-- Implementation investing another comparator so as to provide both full and
-- empty indications from registers.
genStateReg: if STATE_REG generate
signal Ful : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Avl <= '0';
elsif we /= re then
-- Update Full Indicator
if we = '0' or IP1 /= OP0 then
Ful <= '0';
else
Ful <= '1';
end if;
-- Update Empty Indicator
if re = '0' or OP1 /= IP0 then
Avl <= '1';
else
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end generate genStateReg;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Module: FIFO, Common Clock (cc), Pipelined Interface
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- DATA_REG (=true) is a hint, that distributed memory or registers should be
-- used as data storage. The actual memory type depends on the device
-- architecture. See implementation for details.
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
use poc.utils.all;
use poc.ocram.all;
entity fifo_cc_got is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0)
);
end fifo_cc_got;
architecture rtl of fifo_cc_got is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
OP0 <= (others => '0');
else
-- Update Input Pointer upon Write
if we = '1' then
IP0 <= IP1;
end if;
-- Update Output Pointer upon Read
if re = '1' then
OP0 <= OP1;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(IP0, OP0, fulli)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
estate_wr <= (others => 'X');
fstate_rd <= (others => 'X');
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
-- Fix assignment to outputs
if ESTATE_WR_BITS > 0 then
-- one's complement is pessimistically low by one but
-- benefits optimization by synthesis
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
end if;
if FSTATE_RD_BITS > 0 then
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
-- Cheapest implementation using a direction flag DF to determine
-- full or empty condition on equal input and output pointers.
-- Both conditions are derived combinationally involving a comparison
-- of the two pointers.
genStateCmb: if not STATE_REG generate
signal DF : std_logic := '0'; -- Direction Flag
signal Peq : std_logic; -- Pointer Comparison
begin
-- Direction Flag remembering the last Operation
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
DF <= '0'; -- get => empty
elsif we /= re then
DF <= we;
end if;
end if;
end process;
-- Fill Conditions
Peq <= '1' when IP0 = OP0 else '0';
fulli <= Peq and DF;
empti <= Peq and not DF;
end generate genStateCmb;
-- Implementation investing another comparator so as to provide both full and
-- empty indications from registers.
genStateReg: if STATE_REG generate
signal Ful : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Avl <= '0';
elsif we /= re then
-- Update Full Indicator
if we = '0' or IP1 /= OP0 then
Ful <= '0';
else
Ful <= '1';
end if;
-- Update Empty Indicator
if re = '0' or OP1 /= IP0 then
Avl <= '1';
else
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end generate genStateReg;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2426.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02426ent IS
END c07s03b02x01p01n03i02426ent;
ARCHITECTURE c07s03b02x01p01n03i02426arch OF c07s03b02x01p01n03i02426ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
variable p :rec := (ele_1 => 4, others => true); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02426 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02426arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2426.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02426ent IS
END c07s03b02x01p01n03i02426ent;
ARCHITECTURE c07s03b02x01p01n03i02426arch OF c07s03b02x01p01n03i02426ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
variable p :rec := (ele_1 => 4, others => true); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02426 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02426arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2426.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n03i02426ent IS
END c07s03b02x01p01n03i02426ent;
ARCHITECTURE c07s03b02x01p01n03i02426arch OF c07s03b02x01p01n03i02426ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
end record;
variable p :rec := (ele_1 => 4, others => true); -- Failure_here
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n03i02426 - Element association with others choice should be used to represent elements of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n03i02426arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc973.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00973ent IS
END c06s03b00x00p05n01i00973ent;
ARCHITECTURE c06s03b00x00p05n01i00973arch OF c06s03b00x00p05n01i00973ent IS
TYPE simple_record_2_type IS
RECORD
a2 : integer;
b2 : integer;
END RECORD;
TYPE array_of_records_type IS
ARRAY (20 TO 30) OF simple_record_2_type;
SIGNAL sr : array_of_records_type;
BEGIN
TESTING: PROCESS
VARIABLE ar,br : array_of_records_type;
FUNCTION convert (ain : array_of_records_type) RETURN integer IS
BEGIN
RETURN (ain(25).b2);
END;
BEGIN
wait for 1 ns;
br(20).b2 := 8;
ar(30).b2 := br(20).b2;
ar(30).b2 := 8;
ar(20).a2 := ar(30).b2;
sr(30).b2 <= 8;
wait for 1 ns;
sr(20).a2 <= sr(30).b2;
wait for 1 ns;
ar(25).b2 := 3;
sr(25).b2 <= 3;
wait for 1 ns;
assert NOT((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***PASSED TEST: c06s03b00x00p05n01i00973"
severity NOTE;
assert ((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***FAILED TEST: c06s03b00x00p05n01i00973 - The prefix fo the selected names can be an array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00973arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc973.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00973ent IS
END c06s03b00x00p05n01i00973ent;
ARCHITECTURE c06s03b00x00p05n01i00973arch OF c06s03b00x00p05n01i00973ent IS
TYPE simple_record_2_type IS
RECORD
a2 : integer;
b2 : integer;
END RECORD;
TYPE array_of_records_type IS
ARRAY (20 TO 30) OF simple_record_2_type;
SIGNAL sr : array_of_records_type;
BEGIN
TESTING: PROCESS
VARIABLE ar,br : array_of_records_type;
FUNCTION convert (ain : array_of_records_type) RETURN integer IS
BEGIN
RETURN (ain(25).b2);
END;
BEGIN
wait for 1 ns;
br(20).b2 := 8;
ar(30).b2 := br(20).b2;
ar(30).b2 := 8;
ar(20).a2 := ar(30).b2;
sr(30).b2 <= 8;
wait for 1 ns;
sr(20).a2 <= sr(30).b2;
wait for 1 ns;
ar(25).b2 := 3;
sr(25).b2 <= 3;
wait for 1 ns;
assert NOT((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***PASSED TEST: c06s03b00x00p05n01i00973"
severity NOTE;
assert ((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***FAILED TEST: c06s03b00x00p05n01i00973 - The prefix fo the selected names can be an array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00973arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc973.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00973ent IS
END c06s03b00x00p05n01i00973ent;
ARCHITECTURE c06s03b00x00p05n01i00973arch OF c06s03b00x00p05n01i00973ent IS
TYPE simple_record_2_type IS
RECORD
a2 : integer;
b2 : integer;
END RECORD;
TYPE array_of_records_type IS
ARRAY (20 TO 30) OF simple_record_2_type;
SIGNAL sr : array_of_records_type;
BEGIN
TESTING: PROCESS
VARIABLE ar,br : array_of_records_type;
FUNCTION convert (ain : array_of_records_type) RETURN integer IS
BEGIN
RETURN (ain(25).b2);
END;
BEGIN
wait for 1 ns;
br(20).b2 := 8;
ar(30).b2 := br(20).b2;
ar(30).b2 := 8;
ar(20).a2 := ar(30).b2;
sr(30).b2 <= 8;
wait for 1 ns;
sr(20).a2 <= sr(30).b2;
wait for 1 ns;
ar(25).b2 := 3;
sr(25).b2 <= 3;
wait for 1 ns;
assert NOT((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***PASSED TEST: c06s03b00x00p05n01i00973"
severity NOTE;
assert ((ar(30).b2 = 8) AND
(ar(20).a2 = 8) AND
(sr(20).a2 = 8) AND
(convert(ar) = 3) AND
(convert(sr) = 3))
report "***FAILED TEST: c06s03b00x00p05n01i00973 - The prefix fo the selected names can be an array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00973arch;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the entire universal frequency or period counter.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Globals.all;
entity UniversalCounter_Tester is
end entity;
architecture stdarch of UniversalCounter_Tester is
--------------------
-- Constants
--------------------
-- We use a counter width of 4 here to make tests easier.
constant counter_width: natural := 4;
-- Set the system clock period and a gate signal of clock/10, i.e. 100ns.
constant clk_period: time := 10ns;
constant gate_period: time := 10 * clk_period;
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal update_output: std_logic := '0';
signal external_signal: std_logic := '0';
--------------------
-- Outputs
--------------------
signal value: unsigned(counter_width-1 downto 0);
signal overflow: std_logic;
signal ready: std_logic;
--------------------
-- Internals
--------------------
signal external_signal_period: time := 10ns;
signal value_assumed_as_stable: boolean := false; -- for waveform diagram
signal run_test: boolean := true;
-------------------------------------------------------------------------
-- Measures the external signal repeatedly and checks whether the counter
-- works properly including overflow detection.
-------------------------------------------------------------------------
procedure verify_counter(signal_period: time;
expected_value_1: integer;
expected_value_2: integer;
some_must_overflow: boolean := false;
all_must_overflow: boolean := false)
is
variable overflow_cnt: integer;
begin
-- Change the external signal´s period and ensure that the counter
-- value becomes stable and correct before verifying it.
-- Set the new signal period and wait until it gets active.
external_signal_period <= signal_period;
wait until external_signal'event;
-- Wait for the counter to settle down.
value_assumed_as_stable <= false;
wait for 2 * gate_period + 4 * signal_period;
value_assumed_as_stable <= true;
-- Read and verify the counter´s value several times.
overflow_cnt := 0;
for i in 0 to 9 loop
-- Get and verify the counter value once per gate period.
wait for gate_period;
-- Verify the (propably overflown) counter value.
assert (value = expected_value_1 or value = expected_value_2)
report "Counter value incorrect, was " &
integer'image(to_integer(value)) & " instead of " &
integer'image(expected_value_1) & " or " &
integer'image(expected_value_2) & "."
severity error;
if (overflow = '1') then
overflow_cnt := overflow_cnt + 1;
end if;
if (all_must_overflow) then
assert (overflow = '1') report "Overflow not indicated." severity error;
end if;
if (not some_must_overflow and not all_must_overflow) then
assert (overflow = '0') report "Overflow indicated unexpectedly." severity error;
end if;
end loop;
-- Check the number of overflows happened (there should be some but not all for occasional
-- overflows).
if (some_must_overflow and not all_must_overflow) then
assert (overflow_cnt > 0 and overflow_cnt < 10)
report "Overflow for no or all measurements indicated unexpectedly." severity error;
end if;
end procedure;
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
uut: entity work.UniversalCounter
generic map
(
counter_width => counter_width,
clock_divider_test_mode => true
)
port map
(
clk => clk,
update_output => update_output,
external_signal => external_signal,
measure_period => '0',
clk_division_mode => "0000", -- this is ignored in test mode
value => value,
overflow => overflow,
ready => ready
);
--------------------------------------------------------------------------------
-- Generate the system clock and other freely running periodic signals.
--------------------------------------------------------------------------------
clk <= not clk after clk_period/2 when run_test;
external_signal <= not external_signal after external_signal_period/2 when run_test;
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
variable iteration: integer := 0;
begin
-- Activate the output.
update_output <= '1';
-- Test using some signals that fit exactly into a gate period.
verify_counter(100ns, 1, 1, false, false);
verify_counter(25ns, 4, 4, false, false);
verify_counter(12.5ns, 8, 8, false, false);
-- Test using some signals that don´t fit exactly into a gate period.
verify_counter(30ns, 3, 4, false, false);
-- Test using signals that cause all measurements to overflow.
verify_counter(6.25ns, 0, 0, true, true); -- 16
-- Test using signals that cause some measurements to overflow, but not all.
verify_counter(6.5ns, 15, 0, true, false); -- 15..16
-- Test the update output mechanism.
update_output <= '1';
verify_counter(100ns, 1, 1, false, false);
update_output <= '0';
verify_counter(25ns, 1, 1, false, false); -- Counter not affected by changed signal.
update_output <= '1';
verify_counter(25ns, 4, 4, false, false);
-- Repeat the test once to verify proper continuous operation, then
-- terminate the test.
if (iteration = 0) then
iteration := iteration + 1;
else
run_test <= false;
wait;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity fetch_block is
generic (
SIZE : integer := 32
);
port (
branch_target_i : in std_logic_vector(SIZE - 1 downto 0);
sum_addr_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
NPC4_i : in std_logic_vector(SIZE - 1 downto 0);
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
PC_o : out std_logic_vector(SIZE - 1 downto 0);
PC4_o : out std_logic_vector(SIZE - 1 downto 0);
PC_BUS_pre_BTB : out std_logic_vector(SIZE - 1 downto 0);
stall_i : in std_logic;
take_prediction_i : in std_logic;
mispredict_i : in std_logic;
predicted_PC : in std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end fetch_block;
architecture Struct of fetch_block is
component add4
port(
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end component;
component ff32_en
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component mux41
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
IN3 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
signal PC_help : std_logic_vector(SIZE - 1 downto 0);
signal PC_BUS : std_logic_vector(SIZE - 1 downto 0);
signal TARGET_PC : std_logic_vector(SIZE - 1 downto 0);
signal help_ctrl : std_logic_vector(1 downto 0);
signal PC4_o_uns : unsigned(SIZE - 1 downto 0);
signal en_IR : std_logic;
begin
en_IR <= not stall_i;
PC: ff32_en port map(
D => PC_BUS,
Q => PC_help,
en => en_IR,
clk => clk,
rst => rst);
PCADD: add4 port map(
IN1 => unsigned(PC_help),
OUT1 => PC4_o_uns);
MUXTARGET: mux41 port map(
IN0 => NPC4_i,
IN1 => A_i,
IN2 => sum_addr_i,
IN3 => branch_target_i,
CTRL => S_MUX_PC_BUS_i,
OUT1 => TARGET_PC);
MUXPREDICTION: mux41 port map(
IN0 => std_logic_vector(PC4_o_uns),
IN1 => predicted_PC,
IN2 => TARGET_PC,
IN3 => TARGET_PC,
CTRL => help_ctrl,
OUT1 => PC_BUS);
help_ctrl <= mispredict_i&take_prediction_i;
PC4_o <= std_logic_vector(PC4_o_uns);
PC_o <= PC_help;
PC_BUS_pre_BTB <= TARGET_PC;
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity fetch_block is
generic (
SIZE : integer := 32
);
port (
branch_target_i : in std_logic_vector(SIZE - 1 downto 0);
sum_addr_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
NPC4_i : in std_logic_vector(SIZE - 1 downto 0);
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
PC_o : out std_logic_vector(SIZE - 1 downto 0);
PC4_o : out std_logic_vector(SIZE - 1 downto 0);
PC_BUS_pre_BTB : out std_logic_vector(SIZE - 1 downto 0);
stall_i : in std_logic;
take_prediction_i : in std_logic;
mispredict_i : in std_logic;
predicted_PC : in std_logic_vector(SIZE - 1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end fetch_block;
architecture Struct of fetch_block is
component add4
port(
IN1 : in unsigned(SIZE - 1 downto 0);
OUT1 : out unsigned(SIZE - 1 downto 0)
);
end component;
component ff32_en
port(
D : in std_logic_vector(SIZE - 1 downto 0);
Q : out std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component mux41
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
IN3 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
signal PC_help : std_logic_vector(SIZE - 1 downto 0);
signal PC_BUS : std_logic_vector(SIZE - 1 downto 0);
signal TARGET_PC : std_logic_vector(SIZE - 1 downto 0);
signal help_ctrl : std_logic_vector(1 downto 0);
signal PC4_o_uns : unsigned(SIZE - 1 downto 0);
signal en_IR : std_logic;
begin
en_IR <= not stall_i;
PC: ff32_en port map(
D => PC_BUS,
Q => PC_help,
en => en_IR,
clk => clk,
rst => rst);
PCADD: add4 port map(
IN1 => unsigned(PC_help),
OUT1 => PC4_o_uns);
MUXTARGET: mux41 port map(
IN0 => NPC4_i,
IN1 => A_i,
IN2 => sum_addr_i,
IN3 => branch_target_i,
CTRL => S_MUX_PC_BUS_i,
OUT1 => TARGET_PC);
MUXPREDICTION: mux41 port map(
IN0 => std_logic_vector(PC4_o_uns),
IN1 => predicted_PC,
IN2 => TARGET_PC,
IN3 => TARGET_PC,
CTRL => help_ctrl,
OUT1 => PC_BUS);
help_ctrl <= mispredict_i&take_prediction_i;
PC4_o <= std_logic_vector(PC4_o_uns);
PC_o <= PC_help;
PC_BUS_pre_BTB <= TARGET_PC;
end struct;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity DRAM_controller is
port ( rd, wr, mem : in bit;
ras, cas, we, ready : out bit );
end entity DRAM_controller;
-- end of code from book
----------------------------------------------------------------
architecture fpld of DRAM_controller is
begin
end architecture fpld;
----------------------------------------------------------------
entity ch_05_18 is
end entity ch_05_18;
----------------------------------------------------------------
architecture test of ch_05_18 is
begin
block_05_4_a : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy );
-- end of code from book
end block block_05_4_a;
----------------
block_05_4_b : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( rd => cpu_rd, wr => cpu_wr,
mem => cpu_mem, ready => cpu_rdy,
ras => mem_ras, cas => mem_cas, we => mem_we );
-- end of code from book
end block block_05_4_b;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity DRAM_controller is
port ( rd, wr, mem : in bit;
ras, cas, we, ready : out bit );
end entity DRAM_controller;
-- end of code from book
----------------------------------------------------------------
architecture fpld of DRAM_controller is
begin
end architecture fpld;
----------------------------------------------------------------
entity ch_05_18 is
end entity ch_05_18;
----------------------------------------------------------------
architecture test of ch_05_18 is
begin
block_05_4_a : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy );
-- end of code from book
end block block_05_4_a;
----------------
block_05_4_b : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( rd => cpu_rd, wr => cpu_wr,
mem => cpu_mem, ready => cpu_rdy,
ras => mem_ras, cas => mem_cas, we => mem_we );
-- end of code from book
end block block_05_4_b;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
entity DRAM_controller is
port ( rd, wr, mem : in bit;
ras, cas, we, ready : out bit );
end entity DRAM_controller;
-- end of code from book
----------------------------------------------------------------
architecture fpld of DRAM_controller is
begin
end architecture fpld;
----------------------------------------------------------------
entity ch_05_18 is
end entity ch_05_18;
----------------------------------------------------------------
architecture test of ch_05_18 is
begin
block_05_4_a : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy );
-- end of code from book
end block block_05_4_a;
----------------
block_05_4_b : block is
signal cpu_rd, cpu_wr, cpu_mem,
mem_ras, mem_cas, mem_we, cpu_rdy : bit;
begin
-- code from book:
main_mem_controller : entity work.DRAM_controller(fpld)
port map ( rd => cpu_rd, wr => cpu_wr,
mem => cpu_mem, ready => cpu_rdy,
ras => mem_ras, cas => mem_cas, we => mem_we );
-- end of code from book
end block block_05_4_b;
end architecture test;
|
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`protect end_protected
|
-- NEED RESULT: ARCH00629: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00629.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00629: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00629: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00629: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00629
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00629(ARCH00629)
-- ENT00629_Test_Bench(ARCH00629_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00629 is
end ENT00629 ;
--
--
architecture ARCH00629 of ENT00629 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
procedure P1
(signal s_st_rec3 : in st_rec3 ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00629" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00629.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00629" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00629" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00629" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00629" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec3_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_rec3 ,
st_rec3_select ,
s_st_rec3_savt ,
chk_st_rec3 ,
s_st_rec3_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f2.f2 <= transport
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when 1,
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when 2,
--
c_st_rec3_1.f2.f2 after 5 ns when 3 ;
--
end ARCH00629 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00629_Test_Bench is
end ENT00629_Test_Bench ;
--
--
architecture ARCH00629_Test_Bench of ENT00629_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00629 ( ARCH00629 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00629_Test_Bench ;
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(15 downto 0) := x"1230"; -- lower 16 bits only
signal last_wr_addr : std_logic_vector(15 downto 0) := x"1231"; -- lower 16 bits only
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
-- Debug stuff around Rd/Wr access
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= abus_address_latched(15 downto 0);
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE0" then
abus_data_out <= X"FFFF"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE2" then
abus_data_out <= X"0000"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE4" then
abus_data_out <= X"A5A5"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE6" then
abus_data_out <= X"5A5A"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE8" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEA" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEC" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEE" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
-- Debug stuff around Rd/Wr access
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' then
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= abus_address_latched(15 downto 0);
last_wr_data <= abus_data_in;
end if;
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"E0" =>
avalon_nios_readdata <= x"CA" & rd_access_cntr;
when X"E2" =>
avalon_nios_readdata <= x"FE" & wr_access_cntr;
when X"E4" =>
avalon_nios_readdata <= last_rd_addr;
when X"E6" =>
avalon_nios_readdata <= last_wr_addr;
when X"E8" =>
avalon_nios_readdata <= last_wr_data;
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(15 downto 0) := x"1230"; -- lower 16 bits only
signal last_wr_addr : std_logic_vector(15 downto 0) := x"1231"; -- lower 16 bits only
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
-- Debug stuff around Rd/Wr access
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= abus_address_latched(15 downto 0);
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE0" then
abus_data_out <= X"FFFF"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE2" then
abus_data_out <= X"0000"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE4" then
abus_data_out <= X"A5A5"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE6" then
abus_data_out <= X"5A5A"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE8" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEA" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEC" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEE" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
-- Debug stuff around Rd/Wr access
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' then
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= abus_address_latched(15 downto 0);
last_wr_data <= abus_data_in;
end if;
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"E0" =>
avalon_nios_readdata <= x"CA" & rd_access_cntr;
when X"E2" =>
avalon_nios_readdata <= x"FE" & wr_access_cntr;
when X"E4" =>
avalon_nios_readdata <= last_rd_addr;
when X"E6" =>
avalon_nios_readdata <= last_wr_addr;
when X"E8" =>
avalon_nios_readdata <= last_wr_data;
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(15 downto 0) := x"1230"; -- lower 16 bits only
signal last_wr_addr : std_logic_vector(15 downto 0) := x"1231"; -- lower 16 bits only
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
& abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
-- Debug stuff around Rd/Wr access
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= abus_address_latched(15 downto 0);
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE0" then
abus_data_out <= X"FFFF"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE2" then
abus_data_out <= X"0000"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE4" then
abus_data_out <= X"A5A5"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE6" then
abus_data_out <= X"5A5A"; -- Test for cartridge assembly
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFE8" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEA" then
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEC" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFEE" then
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
-- Debug stuff around Rd/Wr access
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' then
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= abus_address_latched(15 downto 0);
last_wr_data <= abus_data_in;
end if;
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"E0" =>
avalon_nios_readdata <= x"CA" & rd_access_cntr;
when X"E2" =>
avalon_nios_readdata <= x"FE" & wr_access_cntr;
when X"E4" =>
avalon_nios_readdata <= last_rd_addr;
when X"E6" =>
avalon_nios_readdata <= last_wr_addr;
when X"E8" =>
avalon_nios_readdata <= last_wr_data;
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
library verilog;
use verilog.vl_types.all;
entity full_adder_vlg_check_tst is
port(
c1 : in vl_logic;
c2 : in vl_logic;
cout : in vl_logic;
s1 : in vl_logic;
sum : in vl_logic;
sampler_rx : in vl_logic
);
end full_adder_vlg_check_tst;
|
--! @file dpRam-bhv-a.vhd
--
--! @brief Dual Port Ram Register Transfer Level Architecture
--
--! @details This is the DPRAM intended for synthesis on Altera platforms only.
--! Timing as follows [clk-cycles]: write=0 / read=1
--
-------------------------------------------------------------------------------
-- Architecture : rtl
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use altera_mf library
library altera_mf;
use altera_mf.altera_mf_components.all;
architecture rtl of dpRam is
begin
altsyncram_component : altsyncram
generic map (
operation_mode => "BIDIR_DUAL_PORT",
intended_device_family => "Cyclone IV",
init_file => gInitFile,
numwords_a => gNumberOfWords,
numwords_b => gNumberOfWords,
widthad_a => logDualis(gNumberOfWords),
widthad_b => logDualis(gNumberOfWords),
width_a => gWordWidth,
width_b => gWordWidth,
width_byteena_a => gWordWidth/8,
width_byteena_b => gWordWidth/8
)
port map (
clock0 => iClk_A,
clocken0 => iEnable_A,
wren_a => iWriteEnable_A,
address_a => iAddress_A,
byteena_a => iByteenable_A,
data_a => iWritedata_A,
q_a => oReaddata_A,
clock1 => iClk_B,
clocken1 => iEnable_B,
wren_b => iWriteEnable_B,
address_b => iAddress_B,
byteena_b => iByteenable_B,
data_b => iWritedata_B,
q_b => oReaddata_B
);
end architecture rtl;
|
--------------------------------------------------------------------------------------------------
-- Interpolator
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - d01matt@gmail.com
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package interpolator_pkg is
component interpolator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_low : in sig;
sig_high : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.muxer_pkg.all;
use work.multichannel_fir_filter_pkg.all;
entity interpolator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_low : in sig;
sig_high : out sig);
end interpolator;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of interpolator is
constant H0 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 1, 1);
constant H1 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 2, 1);
signal filtered1 : fir_sig;
signal filtered2 : fir_sig;
signal combined : fir_sig;
begin
--Low pass the input signal using the multichannel approach
low_pass : multichannel_fir_filter
generic map(h0 => H0,
h1 => H1,
INIT_SEL => b"10")
port map( clk => clk_low,
clk_2x => clk_high,
rst => rst,
x1 => sig_low,
x2 => sig_low,
y1 => filtered1,
y2 => filtered2);
--Mux the poly-phase filter results into one signal
--NOTE: If this design were to ever support interpolation factor > 2, the mux would need to
--select the input signals in descending order
mux_sigs : muxer
generic map(INIT_SEL => std_logic_vector(rotate_left(unsigned'(b"01"), h'length)))
port map(clk => clk_low,
clk_2x => clk_high,
rst => rst,
sig1 => std_logic_vector(filtered1),
sig2 => std_logic_vector(filtered2),
fir_sig(sigs) => combined);
sig_high <= combined(30 downto 15);
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_aludec is
end entity;
architecture arq_test_aludec of test_aludec is
component aludec
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
end component;
signal funct_1: std_logic_vector(5 downto 0);
signal aluop_1: std_logic_vector(1 downto 0);
signal alucontrol_1: std_logic_vector(2 downto 0);
begin
prueba: aludec port map (funct_1, aluop_1, alucontrol_1);
process
begin
aluop_1 <= "00";
wait for 5 ns;
aluop_1 <= "01";
wait for 5 ns;
aluop_1 <= "10";
wait for 5 ns;
aluop_1 <= "11";
wait for 5 ns;
aluop_1 <= "11";
wait for 5 ns;
aluop_1 <= "10";
wait for 5 ns;
aluop_1 <= "01";
wait for 5 ns;
aluop_1 <= "11";
wait for 5 ns;
aluop_1 <= "10";
wait for 5 ns;
end process;
process
begin
funct_1 <= "000000";
wait for 5 ns;
funct_1 <= "010101";
wait for 5 ns;
funct_1 <= "100000";
wait for 5 ns;
funct_1 <= "100100";
wait for 5 ns;
funct_1 <= "100101";
wait for 5 ns;
funct_1 <= "101010";
wait for 5 ns;
funct_1 <= "100010";
wait for 5 ns;
funct_1 <= "100101";
wait for 5 ns;
funct_1 <= "100000";
wait for 5 ns;
funct_1 <= "100010";
wait for 5 ns;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3;
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
else
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3;
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
else
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3;
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
else
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
package pkg_FileIO is
-------------------------------
-- Define some basic data types
-------------------------------
subtype t_BYTE is integer range 0 to 2**8 - 1;
---------------------------------------
-- And arrays of those basic data types
---------------------------------------
type arr_t_BYTE is array(natural range <>) of t_BYTE;
----------------------------
-- And a pointer to an array
----------------------------
type ptr_arr_t_BYTE is access arr_t_BYTE;
procedure Read_File(File_Name: in STRING; Data: out ptr_arr_t_BYTE; Length: out integer);
end pkg_FileIO;
package body pkg_FileIO is
procedure Read_File(File_Name: in STRING; Data: out ptr_arr_t_BYTE; Length: out integer) is
begin
Data := new arr_t_BYTE(0 to 10);
for i in 0 to 10 loop
Data(i) := 0; -- Comment this line out and GHDL is happy
end loop;
Length := 11;
end Read_File;
end pkg_FileIO;
|
package pkg_FileIO is
-------------------------------
-- Define some basic data types
-------------------------------
subtype t_BYTE is integer range 0 to 2**8 - 1;
---------------------------------------
-- And arrays of those basic data types
---------------------------------------
type arr_t_BYTE is array(natural range <>) of t_BYTE;
----------------------------
-- And a pointer to an array
----------------------------
type ptr_arr_t_BYTE is access arr_t_BYTE;
procedure Read_File(File_Name: in STRING; Data: out ptr_arr_t_BYTE; Length: out integer);
end pkg_FileIO;
package body pkg_FileIO is
procedure Read_File(File_Name: in STRING; Data: out ptr_arr_t_BYTE; Length: out integer) is
begin
Data := new arr_t_BYTE(0 to 10);
for i in 0 to 10 loop
Data(i) := 0; -- Comment this line out and GHDL is happy
end loop;
Length := 11;
end Read_File;
end pkg_FileIO;
|
-- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate2.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altaccumulate2 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END altaccumulate2;
ARCHITECTURE SYN OF altaccumulate2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 16,
width_out => 32
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate2_inst.vhd TRUE
|
-------------------------------------------------------------------------------
-- Last update : Fri Jun 14 13:31:50 2019
-- Project : VHDL Mode for Sublime Text
-------------------------------------------------------------------------------
-- Description: This VHDL file is intended as a test of scope and beautifier
-- functions for the VHDL Mode package. It should never be actually compiled
-- as I do several strange things to make sure various aspects of beautification
-- and syntax scoping are checked.
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- VHDL-2008 package library use.
package master_bfm is new work.avalon_bfm_pkg
generic map
(
G_DATA_WIDTH => 32,
G_ADDR_WIDTH => 10,
G_BURST_WIDTH => 4
);
use work.master_bfm.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
/*
VHDL-2008 Block Comment
test zone.
*/
--/* Invalid layered
commenting */
--/* Valid layered
-- commenting */
-------------------------------------------------------------------------------
-- ENTITY STYLE TEST
-------------------------------------------------------------------------------
---------------------------------------
-- Sloppy Comment Test
-- Basically checking that comments are
-- preserved and do not affect
-- beautification or port copying.
---------------------------------------
-- Comment above
entity my_entity is -- comments everywhere
generic( -- I mean everywhere
DATA_WIDTH : integer := 8; -- This value is 8
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4" -- This comment should align with prior
); -- Holy crap another comment -- with a comment inside the -- comment
port ( -- What about a comment here?
-- Basic ports
clk : in std_logic;
-- Another comment on a line by itself!
reset : in std_logic; -- And here's an inline comment.
--d : in std_logic; -- Oh no! I commented out an actual line
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic); -- And finally
-- A final
end entity my_entity; -- Comment
-- Comment below.
---------------------------------------
-- Blank Entity (and variations)
---------------------------------------
entity foobar is
end entity foobar;
entity entity_1 is
end entity_1;
entity entity_1 is
end entity;
package foo2 is
end package foo2;
package body foo2 is
end package body foo2;
architecture test of thing is
begin
end architecture test;
configuration MY_IDENT of thing is
end configuration MY_IDENT;
---------------------------------------
-- K&R Style Approximate. entity/end
-- form the main block which shares the
-- same indent level, and inside opening
-- parens are on the same line as the
-- keyword, closing parens are at same
-- level as keyword.
---------------------------------------
entity kr_style_entity is
generic (
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default
);
port (
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : type(3 downto 0) := X"4";
item_12345 : out type
);
end entity kr_style_entity;
---------------------------------------
-- Allman Style (C Style). Parens share
-- same indent level as associated keyword
---------------------------------------
entity allman_style_entity is
generic
(
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default
);
port
(
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : in type(3 downto 0) := X"4";
item_12345 : out type
);
end entity allman_style_entity;
---------------------------------------
-- Lisp Style: emacs vhdl-mode style
-- with the closing paren on the final
-- item line.
---------------------------------------
entity lisp_style_entity is
generic (
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default);
port (
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : in type(3 downto 0) := X"4";
item_12345 : out type);
end entity lisp_style_entity;
--------------------------------------------------------------------------------
-- EXTENDED ENTITY TEST -- Uses the passive statements, assertion, a passive
-- procedure, a passive process. VHDL-2008 inclusion of PSL Directives is
-- beyond the scope of this as I don't have a PSL syntax file.
--------------------------------------------------------------------------------
entity passive_test is
generic (
G_ADDR_WIDTH : integer := 10;
G_DATA_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(G_ADDR_WIDTH-1 downto 0);
data_in : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
we : in std_logic;
data_out : out std_logic_vector(G_DATA_WIDTH-1 downto 0)
);
begin
CHECK : assert (G_DATA_WIDTH <= 32)
report "ERROR : DATA WIDTH TOO LARGE (>32)"
severity ERROR;
TIME_CHECK : process (we) is
begin
if (we = '1') then
report "MEMORY WRITTEN AT TIME" & to_string(now);
end if;
end process TIME_CHECK;
my_passive_procedure(clk, addr, result);
end entity passive_test;
-------------------------------------------------------------------------------
-- END ENTITY TEST
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 0 HERE IF ALL TESTS PASS
-------------------------------------------------------------------------------
configuration foobar of my_entity is
use work.my_package.all;
for rtl
use lala.other_thing.all;
end for;
end configuration foobar;
architecture rtl of my_entity is
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- COMPONENT STYLE TEST. Also checking lexing of variations in optional
-- words for components.
-------------------------------------------------------------------------------
-- K&R Style
component kr_style_component is
generic (
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4"
);
port (
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic
);
end component kr_style_component;
-- Allman Style
component allman_style_component
generic
(
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4"
);
port
(
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic
);
end component allman_style_component;
-- Lisp Style
component lisp_style_component is
generic (
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4");
port (
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic);
end component;
-------------------------------------------------------------------------------
-- END COMPONENT STYLE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- SIGNALS TEST
-------------------------------------------------------------------------------
signal my_signal_1 : std_logic;
signal my_signal_2 : std_logic_vector(3 downto 0);
signal a, b, c : std_logic := '1';
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
constant C_CLOCK_PERIOD : real := 1.23e-9;
constant MY_PI : real := 3.141592654;
constant C_FOO, C_BAR : integer := 999;
constant C_OPERATOR_CHECK : std_logic_vector(31 downto 0) :=
std_logic_vector(to_unsigned(1, 8)) &
std_logic_vector(to_unsigned(2, 8)) &
std_logic_vector(to_unsigned(3, 8)) &
std_logic_vector(to_unsigned(4, 8));
alias slv is std_logic_vector;
alias 'c' is letter_c;
alias + is plus;
alias bus_rev : std_logic_vector is bus_thing;
begin
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INSTANTIATION TESTS
-------------------------------------------------------------------------------
-- Direct entity instantiation tests.
-- K&R Style
my_entity_1 : entity work.my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Allman Style
my_entity_1 : entity work.my_entity
generic map
(
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map
(
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Lisp Style
my_entity_1 : entity work.my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q);
-- Component instantiation tests
-- K&R Style
my_entity_1 : component my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Allman Style
my_entity_1 : my_entity
generic map
(
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map
(
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Lisp Style
my_entity_1 : my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q,
x(1) => z,
y(3 downto 0) => 9,
z(x'range) => zz);
i_if_cpu : if_cpu
port map (
clk => clk,
reset => reset,
a => a,
b => b
);
-------------------------------------------------------------------------------
-- END OF INSTANTIATION TESTS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MIXED CODE TESTS
-------------------------------------------------------------------------------
SEQUENTIAL_PROCESS : process (clk, reset)
variable my_variable : integer;
shared variable alpha : std_logic_vector(31 downto 0);
begin
-- If/then normal style
IF_LABEL : if (reset = '1') then
q1 <= '0';
q2_long <= '1';
q3 <= b"1010Y";
octal_test <= 12o"01234567_XY";
hex_test := 7X"0123456789--aAbBcCdDeEfF_XY"; -- Comment
bool_test := true;
elsif rising_edge(clk) then
if (ce = '1') then
q1 <= d1;
q2_long <= d2_long;
-- Some syntax number matching.
x0 <= 25_6;
x1 <= 16#1234_ABCD_EF#;
x2 <= 10#1024#E+00;
x3 <= 1_024e-9;
y0 <= 3.141_592_654;
y1 <= 1_2.5e-9;
y2 <= 2#0.1_0#;
y3 <= 10#10_24.0#E+00;
z0 <= math_pi;
a <= 3 + 4;
pt1 <= 0;
pt2 <= (0);
end if;
end if;
-- If/then Leo style (heaven help us)
if (my_condition_a = 1)
then a <= b;
elsif (my_condition_b = 2)
then c <= d;
else e <= f;
end if;
-- Extremely long conditional test
if (((a and b) and (x or y) or
((m or n) and c
or d) and
boolean)) then
g <= h;
end if;
-- Case test long form
CASE_LABEL : case my_tester is
when 1 =>
a <= b;
c <= d;
when 2 =>
e <= f;
g <= h;
when 3 =>
i <= j;
k <= l;
when 4 =>
foo <= (others => '0');
when others =>
null;
end case CASE_LABEL;
-- Case test compact form
-- The fix for the alignment of => breaks alignment here, but it's
-- probably okay. Compact is already readable.
case my_test is
when a => a <= b;
when c => c <= d;
when others => e <= f;
end case;
-- Case test for alignment of => in a case statement.
case my_alignment_test is
when a =>
long_signal_name <= (others => '0');
when b =>
another_long_name <= (others => '0');
when others =>
a_third_long_name <= (others => '0');
end case;
end process SEQUENTIAL_PROCESS;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
COMBINATORIAL_PROCESS : process (all)
begin
wait;
wait until (a > b);
wait for 10 ns;
-- Procedure calls
SUBPROGRAM_CALL_LABEL : my_subprogram_call(values);
ANOTHER_CALL : some_write(L, string'("Text"));
write(L, string'("foobar"));
std.env.stop(0);
stop(0);
-- Loop tests
MY_BASIC_LOOP : loop
end loop MY_BASIC_LOOP;
MY_LOOP : loop
MY_INNER_LOOP : loop
next;
end loop MY_INNER_LOOP;
MY_WHILE_LOOP : while (a > b) loop
a <= b;
end loop;
exit;
end loop MY_LOOP;
MY_FOR_LOOP : for index in 0 to 9 loop
if (condition) then
a := b;
counter := counter + 1;
else
next;
end if;
end loop MY_FOR_LOOP;
end process COMBINATORIAL_PROCESS;
-------------------------------------------------------------------------------
-- Process name variations
-------------------------------------------------------------------------------
process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end process;
LABEL : process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end process;
LABEL : postponed process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end postponed process LABEL;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-- Assignment statements
foo <= bar;
foo(99) <= signal_name;
foo(15 downto 0) <= other_signal_name(15 downto 0);
foo(some_signal'range) <= yet_another_name'range;
foo(other_signal'reverse_range) <= foo(15 downto 0);
foo(to_integer(my_unsigned)) <= 97;
foo(some_signal'range) <= yet_another_name'range;
foo(other_signal'reverse_range) <= foo(15 downto 0);
adder1 <= ( '0' & add_l) + ( '0' & add_m);
adder2 <= ("0" & add_r) + ('0' & add_b);
adder <= ('0' & adder1) + ('0' & adder2);
bus_rw <= '1' when (condition) else '0';
mux_output <= selection_1 when condition else
selection_2 when condition else
selection_3 when condition else
selection_4 when others;
mux_output <=
selection_1 when condition else
selection_2 when condition else
selection_3 when condition else
selection_4 when others;
with my_signal select
address <=
adc_addr when choice1,
temp_sensor_addr when choice2,
light_sense_addr when choice3,
X"0000" when others;
with my_signal select
a <= adc_addr when choice1,
temp_sensor_addr when choice2,
light_sense_addr when choice3,
X"0000" when others;
with my_signal select a <=
tiny when choice1,
bigger when choice2,
really_long when choice3,
X"0000" when others;
data_bus_miso <=
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"FFFFFFFF" when others;
assert (condition)
report "This string would \nget printed in a simulator. -- Comment Test /* Other comment test */"
severity WARNING;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
MY_GENERATOR : for x in 0 to 7 generate
signal a : std_logic;
begin
x <= a;
end generate MY_GENERATOR;
for i in foobar'range generate
end generate;
for x in std_logic_vector generate
end generate;
for index in 0 to 9 generate
end generate;
MY_THING : if (x>1) generate
else
elsif (y<0) generate
end generate;
MY_CASE_GEN : case thing generate
when choice =>
when choice =>
end generate MY_CASE_GEN;
end architecture rtl;
-------------------------------------------------------------------------------
-- Syntax testing some architecture end clause variations.
-------------------------------------------------------------------------------
architecture testing of my_entity is
begin
end architecture testing;
architecture testing of my_entity is
begin
end testing;
architecture testing of my_entity is
begin
end architecture;
architecture testing of my_entity is
begin
end;
-------------------------------------------------------------------------------
-- PACKAGE, PROCEDURE, AND FUNCTION TESTS
-------------------------------------------------------------------------------
package my_package is
-------------------------------------------------------------------------------
-- Type and constant declarations
-------------------------------------------------------------------------------
-- Fairly simple enumerated type.
type MY_STATES is (IDLE, STATE1, STATE2, STATE3);
-- Enumerated type with entries on different lines
type MY_STATES is
(
IDLE,
S1,
S2,
S3
);
-- Complex type with record
type T_MY_TYPE is record
name : type;
name : type;
name : type(3 downto 0);
name : other_type;
really_long_name : yat;
a, b, c : std_logic;
end record;
type T_MY_ARRAY_TYPE is array (3 downto 0) of integer;
type word is array (0 to 31) of bit;
type state_counts is array (idle to error) of natural;
type state_counts is array (controller_state range idle to error) of natural;
type coeff_array is array (coeff_ram_address'reverse_range) of real;
type my_range is range 0 to 31;
type bit_index is range 0 to number_of_bits-1;
type resistance is range 0 to 1e9 units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units resistance;
-- Simple constant
constant C_CLOCK_SPEED : real := 3.75e-9; -- seconds
-- Complex constant
constant C_MY_BFM_INIT : T_MY_TYPE :=
(
clk => 'z',
addr => (others => '0'),
addr_data => (others => '0'),
oe_n => 'z',
gta_n => 'z'
);
-------------------------------------------------------------------------------
-- Procedure Declarations
-------------------------------------------------------------------------------
-- K&R Style
procedure another_procedure (
signal name : inout type;
name : in type2;
variable data_out : out std_logic_vector(3 downto 0);
debug : in boolean := FALSE
);
-- Allman Style. It looks a little like the GNU style because parens are
-- indented, however it's only because these are being treated as the code
-- block. Might be able to mix it up a little with the continuation
-- clauses.
procedure my_init_procedure
(
signal name : inout type
);
-- Lisp Style
procedure another_procedure (
signal name : inout type;
name : in type2;
variable data_out : out std_logic_vector(3 downto 0);
debug : in boolean := FALSE);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- One line style
function reverse_bus (bus_in : in std_logic_vector) return std_logic_vector;
-- K&R Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : in integer
) return boolean;
-- Allman Style
function equal_with_tol
(
a : in unsigned;
b : in unsigned;
tol : in integer
) return boolean;
-- Lisp Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : in integer) return boolean;
end package my_package;
package body my_package is
-------------------------------------------------------------------------------
-- Procedure Body Tests
-------------------------------------------------------------------------------
-- K&R Style
procedure elbc_gpcm_init (
signal elbc_if_rec : inout T_ELBC_GPCM_IF
) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-- Allman Style
procedure elbc_gpcm_init
(
signal elbc_if_rec : inout T_ELBC_GPCM_IF
) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-- Lisp Style
procedure elbc_gpcm_init (
signal elbc_if_rec : inout T_ELBC_GPCM_IF) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-------------------------------------------------------------------------------
-- Function Body Tests
-------------------------------------------------------------------------------
-- Single line style.
function reverse_bus (bus_in : in slv) return slv is
variable bus_out : std_logic_vector(bus_in'range);
alias bus_in_rev : std_logic_vector(bus_in'reverse_range) is bus_in;
begin
for i in bus_in_rev'range loop
bus_out(i) := bus_in_rev(i);
end loop;
return bus_out;
end; -- function reverse_bus
-- K&$ Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : integer
) return boolean is
variable low_limit : unsigned(b'range);
variable high_limit : unsigned(b'range);
variable foo, bar : std_logic;
begin
low_limit := b - tol;
high_limit := b + tol;
if (a >= low_limit and a <= high_limit) then
return TRUE;
else
return FALSE;
end if;
end function equal_with_tol;
-- Allman Style
function equal_with_tol
(
a : in unsigned;
b : in unsigned;
tol : integer
) return boolean is
variable low_limit : unsigned(b'range);
variable high_limit : unsigned(b'range);
begin
low_limit := b - tol;
high_limit := b + tol;
if (a >= low_limit and a <= high_limit) then
return TRUE;
else
return FALSE;
end if;
end function equal_with_tol;
-- Lisp Style
function onehot_vector (
size : in integer;
index : in integer) return slv is
variable vector_out : std_logic_vector(size-1 downto 0);
begin
for i in vector_out'range loop
if (i = index) then
vector_out(i) := '1';
else
vector_out(i) := '0';
end if;
end loop;
return vector_out;
end function onehot_vector;
-- Padding function
function make_miso_word (d_in : std_logic_vector)
return std_logic_vector is
variable d_out : std_logic_vector(C_SPI_DATA_LEN-1 downto 0);
begin
end function make_miso_word;
end package body my_package;
|
package ffaccel_toplevel_params is
constant fu_DATA_LSU_addrw_g : integer := 12;
constant fu_PARAM_LSU_addrw_g : integer := 32;
constant fu_SP_LSU_addrw_g : integer := 10;
end ffaccel_toplevel_params;
|
package ffaccel_toplevel_params is
constant fu_DATA_LSU_addrw_g : integer := 12;
constant fu_PARAM_LSU_addrw_g : integer := 32;
constant fu_SP_LSU_addrw_g : integer := 10;
end ffaccel_toplevel_params;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ForLoop is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ForLoop;
architecture behaviour of ForLoop is
signal result : std_logic_vector(n downto 0);
begin
gen : for i in 1 to 2 generate
nested : for j in 1 to 1 + i * 2 generate
sum <= i + j + k;
end generate nested;
end generate gen;
reverse: for i in 2 downto 1 generate
nestedReverse : for j in 2 downto 1 generate
sum <= j + i;
end generate nestedReverse;
end generate reverse;
end behaviour;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity hex_lcd_driver is
port(
CLK: in std_logic;
DIG0: in std_logic_vector(3 downto 0);
DIG1: in std_logic_vector(3 downto 0);
DIG2: in std_logic_vector(3 downto 0);
DIG3: in std_logic_vector(3 downto 0);
SEVENSEG_SELECT: out std_logic_vector(3 downto 0);
SEVENSEG_DATA: out std_logic_vector(0 to 7)
);
end entity;
architecture beh of hex_lcd_driver is
--values in 7seg are are A, B, C, D, E, F, G, DP
begin
process(clk)
variable dignum: integer range 0 to 7 := 0;
variable currentdigit: std_logic_vector(3 downto 0);
variable clk_div: integer range 0 to 31 := 31;
begin
if rising_edge(clk) then
if clk_div = 31 then --clk_divider is required because 50MHz is too fast to drive seven segment displays.
if dignum = 7 then
dignum := 0;
else
dignum := dignum + 1;
end if;
if dignum = 0 then
SEVENSEG_SELECT <= "1110";
currentdigit := DIG0;
elsif dignum = 2 then
SEVENSEG_SELECT <= "1101";
currentdigit := DIG1;
elsif dignum = 4 then
SEVENSEG_SELECT <= "1011";
currentdigit := DIG2;
elsif dignum = 6 then
SEVENSEG_SELECT <= "0111";
currentdigit := DIG3;
else
SEVENSEG_SELECT <= "1111"; --this is required so that all digits are "off" during the crossover. Without it, we will have blur across digits
end if;
clk_div := 0;
else
clk_div := clk_div + 1;
end if;
case currentdigit is
when "0000" => SEVENSEG_DATA <= "00000011"; --on on on on on on off
when "0001" => SEVENSEG_DATA <= "10011111"; --off on on off off off off
when "0010" => SEVENSEG_DATA <= "00100101"; --on on off on on off on
when "0011" => SEVENSEG_DATA <= "00001101"; --on on on on off off on
when "0100" => SEVENSEG_DATA <= "10011001"; --off on on off off on on
when "0101" => SEVENSEG_DATA <= "01001001"; --on off on on off on on
when "0110" => SEVENSEG_DATA <= "01000001"; --on off on on on on on
when "0111" => SEVENSEG_DATA <= "00011111"; --on on on off off off off
when "1000" => SEVENSEG_DATA <= "00000001"; --on on on on on on on
when "1001" => SEVENSEG_DATA <= "00001001"; --on on on on off on on
when "1010" => SEVENSEG_DATA <= "00010001"; --on on on off on on on
when "1011" => SEVENSEG_DATA <= "11000001"; --off off on on on on on
when "1100" => SEVENSEG_DATA <= "01100011"; --on off off on on on off
when "1101" => SEVENSEG_DATA <= "10000101"; --off on on on on off on
when "1110" => SEVENSEG_DATA <= "01100001"; --on off off on on on on
when others => SEVENSEG_DATA <= "01110001"; --on off off off on on on
end case;
end if;
end process;
end architecture;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
library work ;
use work.nco_p.all ;
entity fsk_modulator is
port (
clock : in std_logic ;
reset : in std_logic ;
symbol : in std_logic ;
symbol_valid : in std_logic ;
out_real : out signed(15 downto 0) ;
out_imag : out signed(15 downto 0) ;
out_valid : out std_logic
) ;
end entity ; -- fsk_modulator
architecture arch of fsk_modulator is
-- Positive deviation for ZERO and negative deviation for ONE
constant ZERO : signed(15 downto 0) := to_signed(integer(round(4096.0/19.2)),16) ;
constant ONE : signed(15 downto 0) := -ZERO ;
signal nco_input : nco_input_t ;
signal nco_output : nco_output_t ;
begin
register_new_symbol : process(clock, reset)
-- variable dir : std_logic ;
-- variable dphase : signed(15 downto 0) ;
begin
if( reset = '1' ) then
-- dir := '1' ;
-- dphase := (others =>'0') ;
nco_input.dphase <= ZERO ;
nco_input.valid <= '0' ;
elsif( rising_edge( clock ) ) then
nco_input.valid <= '1' ;
-- if( dir = '1' ) then
-- if( dphase < 4094) then
-- dphase := dphase + 1 ;
-- else
-- dphase := dphase - 1 ;
-- dir := '0' ;
-- end if ;
-- else
-- if( dphase > -4094) then
-- dphase := dphase - 1 ;
-- else
-- dphase := dphase + 1 ;
-- dir := '1' ;
-- end if ;
-- end if ;
if( symbol_valid = '1' ) then
-- nco_input.dphase <= dphase ;
if( symbol = '0' ) then
nco_input.dphase <= ZERO ;
else
nco_input.dphase <= ONE ;
end if ;
end if ;
end if ;
end process ;
U_nco : entity work.nco
port map (
clock => clock,
reset => reset,
inputs => nco_input,
outputs => nco_output
) ;
out_real <= nco_output.re ;
out_imag <= nco_output.im ;
out_valid <= nco_output.valid ;
end architecture ; -- arch |
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
package issue164 is
end package;
package body issue164 is
procedure same_name(variable var : out integer) is
begin
end;
impure function same_name return integer is
variable var : integer;
begin
return var;
end function;
end package body;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter0 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END lpm_counter0;
ARCHITECTURE SYN OF lpm_counter0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (16 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(16 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 72000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 17
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "72000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "17"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "72000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "17"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 17 0 OUTPUT NODEFVAL "q[16..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 17 0 @q 0 0 17 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variable r : rec; l : out integer) is
begin
l := r.p.all'length; -- OK
end;
type str_ptr_ptr is access str_ptr;
type rec2 is record
pp : str_ptr_ptr;
end record;
procedure get_length3(variable r : rec2; l : out integer) is
begin
l := r.pp.all'length; -- OK
l := r.p.all.all'length; -- Error
end;
begin
end architecture;
|
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variable r : rec; l : out integer) is
begin
l := r.p.all'length; -- OK
end;
type str_ptr_ptr is access str_ptr;
type rec2 is record
pp : str_ptr_ptr;
end record;
procedure get_length3(variable r : rec2; l : out integer) is
begin
l := r.pp.all'length; -- OK
l := r.p.all.all'length; -- Error
end;
begin
end architecture;
|
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variable r : rec; l : out integer) is
begin
l := r.p.all'length; -- OK
end;
type str_ptr_ptr is access str_ptr;
type rec2 is record
pp : str_ptr_ptr;
end record;
procedure get_length3(variable r : rec2; l : out integer) is
begin
l := r.pp.all'length; -- OK
l := r.p.all.all'length; -- Error
end;
begin
end architecture;
|
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variable r : rec; l : out integer) is
begin
l := r.p.all'length; -- OK
end;
type str_ptr_ptr is access str_ptr;
type rec2 is record
pp : str_ptr_ptr;
end record;
procedure get_length3(variable r : rec2; l : out integer) is
begin
l := r.pp.all'length; -- OK
l := r.p.all.all'length; -- Error
end;
begin
end architecture;
|
entity issue88 is
end entity;
architecture test of issue88 is
type str_ptr is access string;
type rec is record
p : str_ptr;
end record;
procedure get_length(variable r : rec; l : out integer) is
begin
l := r.p'length; -- OK
end;
procedure get_length2(variable r : rec; l : out integer) is
begin
l := r.p.all'length; -- OK
end;
type str_ptr_ptr is access str_ptr;
type rec2 is record
pp : str_ptr_ptr;
end record;
procedure get_length3(variable r : rec2; l : out integer) is
begin
l := r.pp.all'length; -- OK
l := r.p.all.all'length; -- Error
end;
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test3 is
port(
clk : in std_logic;
write_data : in std_ulogic;
arst : std_ulogic
);
end;
architecture rtl of test3 is
begin
test_1: process(clk, arst)
begin
if arst = '1' then
null;
elsif rising_edge(clk) then
assert write_data = '0' report "bad" severity failure;
end if;
end process test_1;
end architecture rtl;
|
entity bb is
end entity;
architecture aa of bb is
signal x, y, z : integer;
signal w : bit_vector(1 to 3);
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
end process;
-- Blocking assignment
process is
variable a : integer;
begin
a := 2;
a := a + (a * 3);
end process;
-- Assert and report
process is
begin
assert true;
assert false severity note;
assert 1 > 2 report "oh no" severity failure;
report "hello";
report "boo" severity error;
end process;
-- Function calls
process is
variable a, b : integer;
function foo (x, y, z : integer) return integer;
begin
x := foo(1, 2, 3);
a := "abs"(b);
end process;
-- If
process is
variable x, y : integer;
begin
if true then
x := 1;
end if;
test: if true then
x := y;
end if test;
if x > 2 then
x := 5;
else
y := 2;
end if;
if x > 3 then
null;
elsif x > 5 then
null;
elsif true then
null;
else
x := 2;
end if;
end process;
-- Null
process is
begin
null;
end process;
-- Return
process is
begin
return 4 * 4;
end process;
-- While
process is
variable n : integer;
begin
while n > 0 loop
n := n - 1;
end loop;
loop
null;
end loop;
end process;
-- Delayed assignment
process is
begin
x <= 4 after 5 ns;
x <= 5 after 1 ns, 7 after 8 ns;
x <= 5, 7 after 8 ns;
x <= inertial 5;
x <= transport 4 after 2 ns;
x <= reject 4 ns inertial 6 after 10 ns;
end process;
-- For
process is
type foo is (A, B, C);
begin
for i in 0 to 10 loop
null;
end loop;
for i in foo'range loop
null;
end loop;
end process;
-- Exit
process is
begin
exit;
exit when x = 1;
end process;
-- Procedure call
process is
procedure foo (a, b, c : integer);
procedure bar;
begin
foo(x, y, 1);
bar;
foo(a => 1, b => 2, 3);
end process;
-- Case
process is
begin
case x is
when 1 =>
null;
when 2 =>
null;
when 3 | 4 =>
null;
when others =>
null;
end case;
end process;
-- Next
process is
begin
next;
next when x = 5;
end process;
-- Signal assignment to aggregate
process is
type int_vec is array (natural range <>) of integer;
constant foo : int_vec := (1, 2, 3);
begin
( x, y, z ) <= foo;
end process;
-- Case statement range bug
process is
begin
case y is
when 1 =>
for i in integer'range loop
end loop;
end case;
end process;
-- 2008: all-sensitive process
process (all) is
begin
x <= y;
end process;
-- Variable assignment with aggregate target
process is
type int_vec is array (natural range <>) of integer;
variable v : int_vec(1 to 2);
variable a, b : integer;
begin
(a, b) := v; -- OK
end process;
-- Signal assignment with null transaction
process is
begin
x <= 1, null after 2 ns; -- OK
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 12-02-2016
-- Module Name: mux.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux_2 is
port(i0, i1, sel : in std_logic;
o : out std_logic);
end entity mux_2;
architecture arch_mux_2 of mux_2 is
begin
o <= i1 when sel = '1' else i0;
end architecture arch_mux_2;
|
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-29-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: ADC Interface with FMC ADC boards.
--
-- Currently ADC data (channel) 1 and 2 are clocked on rising_edge of clk0
-- (CLK1_M2C_P and CLK1_M2C_N from the FMC Specifications) and ADC data 0 and 3
-- are clocked on rising edge of clk1 as they are IO pins capable of driving
-- regional clocks up to 3 clocks regions (MRCC), but only half of an IO bank.
-- Hence, in order to use BUFIOs to drive all ILOGIC blocks (e.g., IDDR) of all
-- ADC channels, we need to use both of the clocks
--
-- The generic parameter g_use_clocks specifies which clocks are to be used
-- for acquiring the corresponding adc data. Alternatively, one can use the new
-- generic parameter (g_map_clk_data_chains) to explicitly map which ADC clock
-- chain will clock the ADC data chain. Use with caution!
--
-- Generics:
-- g_clk_default_dly and g_data_default_dly are ignored for now, as the iodelay
-- xilinx primitive in VAR_LOADABLE mode does not consider it
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-29-10 1.0 lucas.russo Created
-- 2013-19-08 1.1 lucas.russo Refactored to enable use with other FMC ADC boards
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.dbe_wishbone_pkg.all;
use work.fmc_adc_pkg.all;
use work.fmc_adc_private_pkg.all;
entity fmc_adc_iface is
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_delay_type : string := "VARIABLE";
g_adc_clk_period_values : t_clk_values_array;
g_use_clk_chains : t_clk_use_chain := default_clk_use_chain;
g_clk_default_dly : t_default_adc_dly := default_clk_dly;
g_use_data_chains : t_data_use_chain := default_data_use_chain;
g_map_clk_data_chains : t_map_clk_data_chain := default_map_clk_data_chain;
g_data_default_dly : t_default_adc_dly := default_data_dly;
g_ref_clk : t_ref_adc_clk := default_ref_adc_clk;
g_mmcm_param : t_mmcm_param := default_mmcm_param;
g_with_bufio_clk_chains : t_clk_use_bufio_chain := default_clk_use_bufio_chain;
g_with_bufr_clk_chains : t_clk_use_bufr_chain := default_clk_use_bufr_chain;
g_with_data_sdr : boolean := false;
g_with_fn_dly_select : boolean := false;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
-- System Reset. Rgular reset, not ANDed with mmcm_adc_locked
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- External ports
-----------------------------
-- Do I need really to worry about the deassertion of async resets?
-- Generate them outside this module, as this reset is needed by
-- external logic
-- ADC clock + data differential inputs (from the top module)
adc_in_i : in t_adc_in_array(c_num_adc_channels-1 downto 0);
-- ADC clock + data single ended inputs (from the top module)
adc_in_sdr_i : in t_adc_sdr_in_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- ADC Delay signals
-----------------------------
-- ADC fine delay control
adc_fn_dly_i : in t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
adc_fn_dly_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- ADC coarse delay control (falling edge + regular delay)
adc_cs_dly_i : in t_adc_cs_dly_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- ADC output signals
-----------------------------
adc_out_o : out t_adc_out_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- General status signals
-----------------------------
-- MMCM lock signal
mmcm_adc_locked_o : out std_logic;
-- Idelay ready signal
idelay_rdy_o : out std_logic;
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end fmc_adc_iface;
architecture rtl of fmc_adc_iface is
-- Fill out the intercon vector. This vector has c_num_data_chains positions
-- and means which clock is connected for each data chain (position index): -1,
-- means not to use this data chain; 0..c_num_clock_chains, means the clock
-- driving this data chain.
constant chain_intercon : t_chain_intercon :=
f_generate_chain_intercon(g_use_clk_chains, g_use_data_chains, g_map_clk_data_chains);
constant first_used_clk : natural := f_first_used_clk(g_use_clk_chains);
-- Number of ADC input pins. This is different for SDR or DDR ADCs.
constant c_num_in_adc_pins : natural := f_num_adc_pins(g_with_data_sdr);
-- Temporary!
constant c_with_bufio : boolean := true;
constant c_with_bufr : boolean := true;
-- ADC input signals
signal adc_in_t : t_adc_sdr_in_array(c_num_adc_channels-1 downto 0);
-- Reset generation
signal sys_rst : std_logic;
-- AND mmcm signals. Use the MSB bit for the final result
signal mmcm_adc_locked_and : std_logic_vector(c_num_adc_channels downto 0);
-- ADC and Clock chains
signal adc_clk_chain_glob : t_adc_clk_chain_glob_array(c_num_adc_channels-1 downto 0);
signal adc_clk_chain_priv : t_adc_clk_chain_priv_array(c_num_adc_channels-1 downto 0);
signal adc_out_int : t_adc_out_array(c_num_adc_channels-1 downto 0);
--signal adc_data_chain_out : t_adc_int_array(c_num_adc_channels-1 downto 0);
--type t_adc_fn_dly_val_array is array (natural range <>) of std_logic_vector(4 downto 0);
-- ADC fine delay internal signal
signal adc_data_dly_sel_int : std_logic_vector(c_num_in_adc_pins-1 downto 0);
signal adc_fn_dly_clk_chain_int : t_adc_clk_fn_dly_array(c_num_adc_channels-1 downto 0);
signal adc_fn_dly_data_chain_int : t_adc_data_fn_dly_array(c_num_adc_channels-1 downto 0);
begin
sys_rst <= not (sys_rst_n_i);
gen_channels_adc_in : for i in 0 to c_num_adc_channels-1 generate
-- SDR data structure
gen_with_data_sdr : if (g_with_data_sdr) generate
adc_in_t(i).adc_data(c_num_in_adc_pins-1 downto 0)
<= adc_in_sdr_i(i).adc_data;
adc_in_t(i).adc_clk <= adc_in_sdr_i(i).adc_clk;
adc_in_t(i).adc_rst_n <= adc_in_sdr_i(i).adc_rst_n;
-- DDR data structure
gen_without_data_sdr : if (not g_with_data_sdr) generate
adc_in_t(i).adc_data(c_num_in_adc_pins-1 downto 0)
<= adc_in_i(i).adc_data;
adc_in_t(i).adc_clk <= adc_in_i(i).adc_clk;
adc_in_t(i).adc_rst_n <= adc_in_i(i).adc_rst_n;
end generate;
end generate;
end generate;
-- idelay control for var_loadable iodelay mode
cmp_idelayctrl : idelayctrl
port map(
rst => sys_rst,
refclk => sys_clk_200Mhz_i,
rdy => idelay_rdy_o
);
-- Generate clock chains
gen_clock_chains : for i in 0 to chain_intercon'length-1 generate
gen_clock_chains_check : if g_use_clk_chains(i) = '1' generate
cmp_fmc_adc_clk : fmc_adc_clk
generic map (
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device => g_fpga_device,
--g_delay_type => "VARIABLE",
g_delay_type => g_delay_type,
g_adc_clock_period => g_adc_clk_period_values(i),
g_default_adc_clk_delay => g_clk_default_dly(i),
g_with_ref_clk => f_with_ref_clk(i, g_ref_clk),
g_mmcm_param => g_mmcm_param,
g_with_fn_dly_select => g_with_fn_dly_select,
g_with_bufio => f_std_logic_to_bool(g_with_bufio_clk_chains(i)),
g_with_bufr => f_std_logic_to_bool(g_with_bufr_clk_chains(i)),
g_sim => g_sim
)
port map (
sys_clk_i => sys_clk_i,
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
sys_rst_i => sys_rst,
-----------------------------
-- External ports
-----------------------------
-- ADC clocks. One clock per ADC channel
adc_clk_i => adc_in_t(i).adc_clk,
-----------------------------
-- ADC Delay signals.
-----------------------------
adc_clk_fn_dly_i => adc_fn_dly_i(i).clk_chain,
adc_clk_fn_dly_o => adc_fn_dly_clk_chain_int(i),
-----------------------------
-- ADC output signals.
-----------------------------
adc_clk_chain_priv_o => adc_clk_chain_priv(i),
adc_clk_chain_glob_o => adc_clk_chain_glob(i)
);
end generate;
-- Default mmcm_locked signals to 1 is this chain is not used
gen_mmcm_locked_clock_chains : if (g_use_clk_chains(i) = '0') generate
adc_clk_chain_glob(i).mmcm_adc_locked <= '1';
end generate;
end generate;
mmcm_adc_locked_and(0) <= '1';
-- ANDing all clock chains mmcm_adc_locked_o
gen_mmcm_adc_locked : for i in 0 to chain_intercon'length-1 generate
mmcm_adc_locked_and(i+1) <= mmcm_adc_locked_and(i) and adc_clk_chain_glob(i).mmcm_adc_locked;
end generate;
-- Output the MSB of mmcm_adc_locked_and, as it contains the and of all the chain.
-- Note, however, that the snsthesis tool will generate an AND tree for all the
-- inputs and a single output (mmcm_adc_locked_and(c_num_clock_chains))
mmcm_adc_locked_o <= mmcm_adc_locked_and(c_num_adc_channels);
-- Generate data chains and connect it to the clock chain as specified
-- in chain_intercon
gen_adc_data_chains : for i in 0 to chain_intercon'length-1 generate
-- Check if this data chain is to be instanciated
gen_adc_data_chains_check : if chain_intercon(i) /= -1 generate
--gen_implicitly_clk_data_map : if f_explicitly_clk_data_map(g_map_clk_data_chains) = false generate
cmp_fmc_adc_data : fmc_adc_data
generic map (
g_default_adc_data_delay => g_data_default_dly(i),
--g_delay_type => "VARIABLE",
g_delay_type => g_delay_type,
g_with_data_sdr => g_with_data_sdr,
g_with_fn_dly_select => g_with_fn_dly_select,
g_sim => g_sim
)
port map (
sys_clk_i => sys_clk_i,
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
sys_rst_n_i => adc_in_t(i).adc_rst_n,--sys_rst_n_i,
-----------------------------
-- External ports
-----------------------------
-- DDR ADC data channels.
adc_data_i => adc_in_t(i).adc_data(c_num_in_adc_pins-1 downto 0),
-----------------------------
-- Input Clocks from fmc_adc_clk signals
-----------------------------
adc_clk_chain_priv_i => adc_clk_chain_priv(chain_intercon(i)),
adc_clk_chain_glob_i => adc_clk_chain_glob(g_ref_clk),
-----------------------------
-- ADC Data Delay signals.
-----------------------------
-- Fine delay
adc_data_fn_dly_i => adc_fn_dly_i(i).data_chain,
adc_data_fn_dly_o => adc_fn_dly_data_chain_int(i),
-- Coarse delay
adc_cs_dly_i => adc_cs_dly_i(i),
-----------------------------
-- ADC output signals.
-----------------------------
adc_out_o => adc_out_int(i),
fifo_debug_valid_o => fifo_debug_valid_o(i),
fifo_debug_full_o => fifo_debug_full_o(i),
fifo_debug_empty_o => fifo_debug_empty_o(i)
);
-- The clock delay information for each channel corresponds to the delay
-- in its correspondent clock chain, referenced by chain_intercon(i).
adc_fn_dly_o(i).data_chain <= adc_fn_dly_data_chain_int(i);
adc_fn_dly_o(i).clk_chain <= adc_fn_dly_clk_chain_int(chain_intercon(i));
end generate;
end generate;
-- We have the possibility that some adc data chains are clocked with
-- different source-synchronous clocks. In this case, we need to synchronize
-- all data chains to a single clock domain. Need to evaluate its real
-- necessity
cmp_fmc_adc_sync_chains : fmc_adc_sync_chains
--generic map (
--)
port map (
sys_clk_i => sys_clk_i,
--sys_rst_n_i => sys_rst_n_i,
sys_rst_n_i => adc_in_t(g_ref_clk).adc_rst_n,
-----------------------------
-- ADC Data Input signals. Each data chain is synchronous to its
-- own clock.
-----------------------------
adc_out_i => adc_out_int,
-- Reference clock for synchronization with all data chains
adc_refclk_i => adc_clk_chain_glob(g_ref_clk),
-----------------------------
-- ADC output signals. Synchronous to a single clock
-----------------------------
adc_out_o => adc_out_o
);
end rtl;
|
--!
--! Copyright (C) 2010 - 2012 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Generic single port RAM with a single read/write port
--! @author Matthias Alles
--! @date 2010/09/28
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_helper.all;
entity generic_sp_ram is
generic(
DISTR_RAM : boolean := false;
WORDS : integer := 8;
BITWIDTH : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
wen : in std_logic;
en : in std_logic;
a : in std_logic_vector(no_bits_natural(WORDS - 1) - 1 downto 0);
d : in std_logic_vector(BITWIDTH - 1 downto 0);
q : out std_logic_vector(BITWIDTH - 1 downto 0)
);
end generic_sp_ram;
architecture rtl of generic_sp_ram is
type t_ram is array(WORDS - 1 downto 0) of
std_logic_vector(BITWIDTH - 1 downto 0);
signal sp_ram : t_ram := (others => (others => '0'));
function get_ram_style_xilinx(dist_ram : in boolean) return string is
begin
if dist_ram then
return "pipe_distributed";
else
return "block";
end if;
end function;
function get_ram_style_altera(dist_ram : in boolean) return string is
begin
if dist_ram then
return "MLAB, no_rw_check";
else
return "AUTO";
end if;
end function;
attribute RAM_STYLE : string;
attribute RAM_STYLE of sp_ram : signal is get_ram_style_xilinx(DISTR_RAM);
attribute ramstyle : string;
attribute ramstyle of sp_ram : signal is get_ram_style_altera(DISTR_RAM);
begin
--
-- Do not register the address for reading, since the synthesis doesn't
-- recognize then that this is a single-port RAM.
--
pr_sp_ram_rw: process(clk)
begin
if rising_edge(clk) then
if en = '1' then
if wen = '1' then
sp_ram(to_integer(UNSIGNED(a))) <= d;
else
q <= sp_ram(to_integer(UNSIGNED(a)));
end if;
end if;
end if;
end process pr_sp_ram_rw;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity xupv5_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 51;
COUNT_CYCLES : boolean := false;
CLK_FREQ : positive := 100000000;
CLK_MUL : positive := 25;
CLK_DIV : positive := 14;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clkx : in std_logic;
rstx : in std_logic;
rx : in std_logic;
tx : out std_logic;
leds : out std_logic_vector(0 to 7)
);
end xupv5_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of xupv5_queens_uart is
-- Global Control
signal clk : std_logic;
signal rst : std_logic;
-- Solver Status
signal snap : std_logic_vector(3 downto 0);
signal avail : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clk_u : std_logic; -- Unbuffered Synthesized Clock
signal rst_s : std_logic_vector(1 downto 0) := (others => '0');
begin
DCM0 : DCM_BASE
generic map (
CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ),
CLKIN_DIVIDE_BY_2 => FALSE,
PHASE_SHIFT => 0,
CLKFX_MULTIPLY => CLK_MUL,
CLKFX_DIVIDE => CLK_DIV,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE", -- only using clkfx
DLL_FREQUENCY_MODE => "HIGH",
DFS_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
STARTUP_WAIT => TRUE -- Delay until DCM LOCK
)
port map (
CLK0 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => clk_u,
CLKFX180 => open,
LOCKED => open,
CLKFB => '0',
CLKIN => clkx,
RST => '0'
);
clk_buf : BUFG
port map (
I => clk_u,
O => clk
);
-- Reset Synchronization
process(clk)
begin
if rising_edge(clk) then
rst_s <= (not rstx) & rst_s(rst_s'left downto 1);
end if;
end process;
rst <= rst_s(0);
end block blkGlobal;
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk,
rst => rst,
rx => rx,
tx => tx,
snap => snap,
avail => avail
);
----------------------------------------------------------------------------
-- Basic Status Output
leds <= snap & std_logic_vector(to_unsigned((SOLVERS mod 7)+1, 3)) & avail;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcdctl is
Port ( clk,reset : in STD_LOGIC;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ud : out STD_LOGIC;
rl : out STD_LOGIC;
enab : out STD_LOGIC;
vsync : out STD_LOGIC;
hsync : out STD_LOGIC;
ck : out STD_LOGIC;
r : out std_logic_vector(5 downto 0);
g : out std_logic_vector(5 downto 0);
b : out std_logic_vector(5 downto 0)
);
end lcdctl;
architecture Behavioral of lcdctl is
signal clk_fast : std_logic := '0';
signal ired : std_logic_vector(5 downto 0) := "000000";
signal igreen : std_logic_vector(5 downto 0) := "000000";
signal iblue : std_logic_vector(5 downto 0) := "000000";
signal fg_r : std_logic_vector(5 downto 0) := "000000";
signal fg_g : std_logic_vector(5 downto 0) := "000000";
signal fg_b : std_logic_vector(5 downto 0) := "000000";
signal bg_r : std_logic_vector(5 downto 0) := "000000";
signal bg_g : std_logic_vector(5 downto 0) := "000000";
signal bg_b : std_logic_vector(5 downto 0) := "000000";
signal lcdvsync : STD_LOGIC;
signal lcdhsync : STD_LOGIC;
signal char_addr: std_logic_vector(6 downto 0);
signal char_attr: std_logic_vector(7 downto 0) := x"42";
signal attr_not_char: std_logic := '1';
signal rom_addr: std_logic_vector(10 downto 0);
signal row_addr: std_logic_vector(3 downto 0);
signal bit_addr: std_logic_vector(2 downto 0);
signal font_word: std_logic_vector(7 downto 0);
signal font_bit: std_logic;
signal video_on: std_logic;
signal dout: std_logic_vector(7 downto 0) := "01100010";
signal addr_read: std_logic_vector(12 downto 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal ipixel_x, ipixel_y: std_logic_vector(9 downto 0);
begin
ud <= '1';
rl <= '1';
enab <= '0';
ck <= clk_fast;
r <= ired;
g <= igreen;
b <= iblue;
hsync<=lcdhsync;
vsync<=lcdvsync;
sync0: entity work.vga_sync
port map(
clock=>clk_fast,
reset=>reset,
hsync=>lcdhsync, vsync=>lcdvsync,
video_on=>video_on,
pixel_tick=>open,
pixel_x=>pixel_x, pixel_y=>pixel_y
);
-- instantiate frame buffer
-- frame_buffer_unit: entity work.blk_mem_gen_v7_3
-- port map (
-- clka => clk,
-- wea => (others => '0'),
-- addra => (others => '0'),
-- dina => (others => '0'),
-- clkb => clk,
-- addrb => addr_read,
-- doutb => dout
-- );
vramaddr <= "000" & addr_read;
dout <= vramdata;
-- instantiate font ROM
font_unit: entity work.font_rom
port map(
clock => clk_fast,
addr => rom_addr,
data => font_word
);
-- tile RAM read
-- addr_read <= ((pixel_y(9 downto 4) & "000000") + ("00" & pixel_y(9 downto 4) & "0000") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
addr_read <= ((pixel_y(9 downto 4) * "000101") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
process(clk,clk_fast,video_on)
begin
if rising_edge(clk) then
if video_on='0' then
attr_not_char <= '0';
clk_fast <= '0';
else
if clk_fast='0' then
char_attr <= dout(7 downto 0);
attr_not_char <= '1';
else
char_addr <= dout(6 downto 0);
attr_not_char <= '0';
end if;
end if;
clk_fast <= not clk_fast;
end if;
end process;
fg_r <= (others => '1') when char_attr(0)='1' else (others => '0');
fg_g <= (others => '1') when char_attr(1)='1' else (others => '0');
fg_b <= (others => '1') when char_attr(2)='1' else (others => '0');
bg_r <= (others => '1') when char_attr(3)='1' else (others => '0');
bg_g <= (others => '1') when char_attr(4)='1' else (others => '0');
bg_b <= (others => '1') when char_attr(5)='1' else (others => '0');
-- font ROM interface
row_addr <= pixel_y(3 downto 0);
rom_addr <= char_addr & row_addr;
-- bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0)) - 1);
bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0))-2);
font_bit <= font_word(to_integer(unsigned(not bit_addr)));
-- rgb multiplexing
process(font_bit,video_on,fg_r,fg_g,fg_b,bg_r,bg_g,bg_b)
begin
if video_on='0' then
ired <= (others => '0');
igreen <= (others => '0');
iblue <= (others => '0');
elsif font_bit = '1' then
ired <= fg_r;
igreen <= fg_g;
iblue <= fg_b;
-- ired <= (others => '1');
-- igreen <= (others => '1');
-- iblue <= (others => '1');
else
ired <= bg_r;
igreen <= bg_g;
iblue <= bg_b;
-- ired <= (others => '0');
-- igreen <= (others => '0');
-- iblue <= (others => '0');
end if;
end process;
end Behavioral;
|
/*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with fpgaNES. If not, see <http://www.gnu.org/licenses/>.
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity vga is
generic
(
HFP : natural := 88;
HSYNC : natural := 44;
HBP : natural := 148;
HRES : natural := 1920;
VFP : natural := 4;
VSYNC : natural := 5;
VBP : natural := 36;
VRES : natural := 1080
);
port
(
i_data_clk : in std_logic;
i_data_clk_enable : in std_logic;
i_vga_clk : in std_logic;
i_vga_clk_enable : in std_logic;
i_reset_n : in std_logic;
i_addr : in std_logic_vector(15 downto 0);
i_data : in std_logic_vector(8 downto 0);
i_write_enable : in std_logic;
o_data_enable : out std_logic;
o_vsync : out std_logic;
o_hsync : out std_logic;
o_data : out std_logic_vector(23 downto 0)
);
end vga;
architecture behavioral of vga is
component frmmem is
port
(
data : in std_logic_vector(8 downto 0);
rdaddress : in std_logic_vector(15 downto 0);
rdclock : in std_logic;
rdclocken : in std_logic;
wraddress : in std_logic_vector(15 downto 0);
wrclock : in std_logic := '1';
wrclocken : in std_logic;
wren : in std_logic := '0';
q : out std_logic_vector(8 downto 0)
);
end component;
type color_t is array (0 to 511) of std_logic_vector(23 downto 0);
constant PALETTE : color_t := (
x"656565", x"00298a", x"1a14a8", x"3d05a1", x"5c0077", x"6c0239", x"680d00", x"512000", x"2f3600", x"0d4700", x"004f00", x"004c11", x"003d51", x"000000", x"050505", x"050505",
x"b1b1b1", x"1b5ce5", x"473eff", x"7927ff", x"a41dcb", x"bb2274", x"b5341b", x"965000", x"666f00", x"348700", x"0f9300", x"008e39", x"027a95", x"050505", x"050505", x"050505",
x"ffffff", x"67afff", x"988fff", x"ce75ff", x"fc6aff", x"ff6fc8", x"ff8368", x"eca21f", x"bac300", x"84dd06", x"59ea35", x"44e489", x"49cfec", x"4d4d4d", x"050505", x"050505",
x"ffffff", x"c5e4ff", x"dad6ff", x"f1cbff", x"ffc6ff", x"ffc8ee", x"ffd1c5", x"fddea4", x"e8ec93", x"d1f797", x"bffcae", x"b5fad4", x"b8f1fd", x"b9b9b9", x"050505", x"050505",
x"66423b", x"000f5a", x"190177", x"3b0074", x"580053", x"690022", x"680400", x"521100", x"312100", x"112d00", x"003100", x"002b00", x"001d28", x"000000", x"060000", x"060000",
x"b37f74", x"1c35a0", x"461fc8", x"7610c4", x"9f0b97", x"b61250", x"b6240a", x"963900", x"694f00", x"396000", x"156600", x"035e12", x"034a5a", x"060000", x"060000", x"060000",
x"ffc5b7", x"6976e5", x"985eff", x"cb4dff", x"f747db", x"ff4f91", x"ff6443", x"ee7a05", x"bd9300", x"8aa500", x"61ab0c", x"4ba34d", x"4b8d9b", x"4e302a", x"060000", x"060000",
x"ffc5b7", x"c7a4ca", x"db9adb", x"f193d9", x"ff90c6", x"ff93a7", x"ff9d86", x"ffa669", x"ebb059", x"d5b85b", x"c3bb6d", x"b9b78a", x"baaeab", x"bb867b", x"060000", x"060000",
x"375d2e", x"002357", x"000f6d", x"190164", x"2f003f", x"3f0010", x"3e0900", x"2e1c00", x"153100", x"004300", x"004d00", x"004700", x"00382a", x"000000", x"000200", x"000200",
x"6fa560", x"00549a", x"1d36ba", x"431fae", x"631379", x"791a35", x"782e00", x"624900", x"3d6800", x"188100", x"008f00", x"008714", x"00715b", x"000200", x"000200", x"000200",
x"aff99c", x"33a3d9", x"5783f9", x"8069ed", x"a35bb6", x"ba646d", x"b97923", x"a19800", x"7bb800", x"51d300", x"32e209", x"1dd948", x"1ec396", x"26461e", x"000200", x"000200",
x"aff99c", x"7ad5b5", x"8ac8c2", x"9cbdbd", x"aab7a7", x"b4ba89", x"b3c468", x"aad14f", x"99de43", x"88ea47", x"7af05c", x"70ec79", x"71e39a", x"75ad66", x"000200", x"000200",
x"3e3f25", x"000e49", x"04015e", x"1c0059", x"31003c", x"41000d", x"400200", x"300f00", x"181e00", x"012a00", x"003000", x"002a00", x"001c21", x"000000", x"000000", x"000000",
x"797a54", x"063387", x"241ea5", x"470e9e", x"660875", x"7c0e31", x"7c2000", x"653500", x"434b00", x"1f5d00", x"056500", x"005d09", x"00484f", x"000000", x"000000", x"000000",
x"bdbf8a", x"3f73c0", x"615cdf", x"884ad8", x"a942ad", x"c14965", x"c05e1b", x"a87500", x"838d00", x"5ca000", x"3ea800", x"29a038", x"298a85", x"2c2d17", x"000000", x"000000",
x"bdbf8a", x"87a0a0", x"9795ad", x"a78eaa", x"b58a99", x"bf8e7b", x"be975b", x"b4a044", x"a5aa39", x"94b23b", x"87b64b", x"7eb268", x"7ea988", x"7f8159", x"000000", x"000000",
x"48457d", x"001a93", x"120bb0", x"2d00a7", x"440080", x"4f0046", x"49000c", x"330a00", x"151900", x"002900", x"003300", x"003321", x"00295e", x"000000", x"00000e", x"00000e",
x"8783d5", x"1146f3", x"3930ff", x"6119ff", x"820ed8", x"910e87", x"881a34", x"6a2d00", x"3e4300", x"195c00", x"00690c", x"006953", x"005ba8", x"00000e", x"00000e", x"00000e",
x"d0cbff", x"508aff", x"7d72ff", x"a858ff", x"cb4bff", x"db4ce7", x"d2598d", x"b16f47", x"828724", x"59a12e", x"39b05f", x"2bafaf", x"33a1ff", x"343262", x"00000e", x"00000e",
x"d0cbff", x"9ab0ff", x"ada6ff", x"bf9bff", x"ce95ff", x"d495ff", x"d19bf1", x"c3a5d2", x"b0afc1", x"9ebac6", x"90c0dd", x"89c0ff", x"8dbaff", x"8e8ade", x"00000e", x"00000e",
x"46344b", x"000b60", x"10007c", x"2a0077", x"400059", x"4b002c", x"480000", x"330500", x"151400", x"002000", x"002500", x"002301", x"00192d", x"000000", x"000000", x"000000",
x"856a8c", x"0f2ea9", x"3719d0", x"5c0ac9", x"7c039f", x"8c065f", x"88121e", x"692500", x"3d3b00", x"1a4d00", x"015500", x"005120", x"004362", x"000000", x"000000", x"000000",
x"cda9d7", x"4d69f5", x"7b51ff", x"a240ff", x"c437eb", x"d53ba8", x"d04961", x"b05f1e", x"817700", x"5a8a04", x"3c9226", x"2d8e63", x"307faa", x"332438", x"000000", x"000000",
x"cda9d7", x"978ee4", x"ab84f4", x"bc7cf2", x"c979e0", x"d07ac4", x"cf80a5", x"c18a87", x"ae9477", x"9d9c7a", x"8f9f8b", x"899ea6", x"8a97c5", x"8c7093", x"000000", x"000000",
x"304144", x"00165f", x"000875", x"16006c", x"2c0047", x"37001b", x"350000", x"250900", x"0e1700", x"002800", x"003200", x"002f08", x"002536", x"000000", x"000000", x"000000",
x"637d82", x"003fa7", x"192ac6", x"3f13ba", x"5f0885", x"6f0b46", x"6b1809", x"542b00", x"334100", x"0e5a00", x"006700", x"00632b", x"00556e", x"000000", x"000000", x"000000",
x"a0c2c9", x"2e81f1", x"5069ff", x"7950ff", x"9b43cd", x"ac468a", x"a85545", x"906b11", x"6c8300", x"439d03", x"24ab2f", x"16a76c", x"1a98b4", x"202e32", x"000000", x"000000",
x"a0c2c9", x"70a7da", x"7e9de6", x"9092e1", x"9e8ccb", x"a58eaf", x"a39491", x"999e79", x"8aa86d", x"79b372", x"6bb987", x"65b7a2", x"66b1c0", x"698389", x"000000", x"000000",
x"343434", x"000b4e", x"010064", x"19005f", x"2e0041", x"390016", x"360000", x"260500", x"0f1400", x"002000", x"002500", x"002300", x"001926", x"000000", x"000000", x"000000",
x"6a6a6a", x"022e8f", x"1f19ad", x"430aa6", x"61037d", x"71063f", x"6d1202", x"572600", x"353b00", x"124d00", x"005500", x"005116", x"004356", x"000000", x"000000", x"000000",
x"a9a9a9", x"3669d0", x"5852ef", x"7f40e8", x"9f38bd", x"b03b7b", x"ac4a36", x"945f05", x"707700", x"4a8a00", x"2c9213", x"1e8f4e", x"217f94", x"242424", x"000000", x"000000",
x"a9a9a9", x"788eb9", x"8784c6", x"977cc3", x"a579b1", x"ac7a96", x"aa8178", x"a08a61", x"919455", x"819c58", x"74a068", x"6d9e83", x"6f98a0", x"707070", x"000000", x"000000"
);
-- http://www.3dexpress.de/displayconfigx/timings.html
/*
640x480 25.175 MHz Pixel Clock
HFP: natural := 16;
HBP: natural := 48;
HSYNC: natural := 96;
HRES: natural := 640;
VFP: natural := 10;
VBP: natural := 33;
VSYNC: natural := 2;
VRES: natural := 480;
*/
/*
1280x720 74.25 MHz Pixel Clock
HFP: natural := 72;
HSYNC: natural := 80;
HBP: natural := 216;
HRES: natural := 1280;
VFP: natural := 3;
VSYNC: natural := 5;
VBP: natural := 22;
VRES: natural := 720;
*/
/*
1920x1080 148.5 MHz Pixel Clock
HFP : natural := 88;
HSYNC : natural := 44;
HBP : natural := 148;
HRES : natural := 1920;
VFP : natural := 4;
VSYNC : natural := 5;
VBP : natural := 36;
VRES : natural := 1080
*/
constant HSYNC_START : natural := HFP;
constant HSYNC_STOP : natural := HFP + HSYNC;
constant VSYNC_START : natural := VFP;
constant VSYNC_STOP : natural := VFP + VSYNC;
constant HACT_START : natural := HFP + HBP + HSYNC;
constant HACT_STOP : natural := 0;
constant VACT_START : natural := VFP + VBP + VSYNC;
constant VACT_STOP : natural := 0;
constant HMAX : natural := HFP + HBP + HSYNC + HRES - 1;
constant VMAX : natural := VFP + VBP + VSYNC + VRES - 1;
signal s_red : std_logic_vector(7 downto 0) := (others => '0');
signal s_green : std_logic_vector(7 downto 0) := (others => '0');
signal s_blue : std_logic_vector(7 downto 0) := (others => '0');
signal s_addr : std_logic_vector(15 downto 0) := (others => '0');
signal s_pixel : std_logic_vector(8 downto 0);
signal s_data : std_logic_vector(23 downto 0) := (others => '0');
signal s_palette_index : integer range 0 to 63;
signal s_hpos : natural range 0 to HMAX := 0;
signal s_vpos : natural range 0 to VMAX := 0;
signal s_xpos : std_logic_vector(9 downto 0);
signal s_ypos : std_logic_vector(9 downto 0);
signal s_hsync : std_logic := '1';
signal s_vsync : std_logic := '1';
signal s_hact : std_logic := '0';
signal s_vact : std_logic := '0';
begin
framebuffer: frmmem port map
(
data => i_data,
rdaddress => s_addr,
rdclock => i_vga_clk,
rdclocken => i_vga_clk_enable,
wraddress => i_addr,
wrclock => i_data_clk,
wrclocken => i_data_clk_enable,
wren => i_write_enable,
q => s_pixel
);
-- Horizontal / Vertical Position
process (i_vga_clk)
begin
if rising_edge(i_vga_clk) then
if i_vga_clk_enable = '1' then
if i_reset_n = '0' then
s_hpos <= 0;
s_vpos <= 0;
elsif s_hpos = HMAX then
s_hpos <= 0;
if s_vpos = VMAX then
s_vpos <= 0;
else
s_vpos <= s_vpos + 1;
end if;
else
s_hpos <= s_hpos + 1;
end if;
end if;
end if;
end process;
-- Horizontal Sync
process (i_vga_clk)
begin
if rising_edge(i_vga_clk) then
if i_vga_clk_enable = '1' then
if i_reset_n = '0' then
s_hsync <= '1';
elsif s_hpos = HSYNC_START then
s_hsync <= '0';
elsif s_hpos = HSYNC_STOP then
s_hsync <= '1';
end if;
end if;
end if;
end process;
-- Vertical Sync
process (i_vga_clk)
begin
if rising_edge(i_vga_clk) then
if i_vga_clk_enable = '1' then
if i_reset_n = '0' then
s_vsync <= '1';
elsif s_vpos = VSYNC_START then
s_vsync <= '0';
elsif s_vpos = VSYNC_STOP then
s_vsync <= '1';
end if;
end if;
end if;
end process;
-- Horizontal Actual View
process (i_vga_clk)
begin
if rising_edge(i_vga_clk) then
if i_vga_clk_enable = '1' then
if i_reset_n = '0' then
s_hact <= '0';
elsif s_hpos = HACT_START then
s_hact <= '1';
elsif s_hpos = HACT_STOP then
s_hact <= '0';
end if;
end if;
end if;
end process;
-- Vertical Actual View
process (i_vga_clk)
begin
if rising_edge(i_vga_clk) then
if i_vga_clk_enable = '1' then
if i_reset_n = '0' then
s_vact <= '0';
elsif s_vpos = VACT_START then
s_vact <= '1';
elsif s_vpos = VACT_STOP then
s_vact <= '0';
end if;
end if;
end if;
end process;
-- @todo ugly, do a complete rewrite of this process
process (i_vga_clk)
begin
if rising_edge(i_vga_clk) then
if i_vga_clk_enable = '1' then
if i_reset_n = '0' then
s_xpos <= (others => '0');
s_ypos <= (others => '0');
s_data <= (others => '0');
else
if s_hpos >= HFP + HBP + HSYNC + 62 then
s_xpos <= std_logic_vector(to_unsigned(s_hpos - HFP - HBP - HSYNC - 62, 10));
else
s_xpos <= (others => '0');
end if;
if s_vpos >= VFP + VBP + VSYNC then
s_ypos <= std_logic_vector(to_unsigned(s_vpos - VFP - VBP - VSYNC, 10));
else
s_ypos <= (others => '0');
end if;
if (s_hpos >= HFP + HBP + HSYNC + 64) and (s_hpos < HMAX - 64) and (s_vpos >= VFP + VBP + VSYNC) then
s_data <= PALETTE(s_palette_index);
else
s_data <= (others => '0');
end if;
end if;
end if;
end if;
end process;
s_palette_index <= to_integer(unsigned(s_pixel));
s_addr <= s_ypos(8 downto 1) & s_xpos(8 downto 1);
o_data <= s_data;
o_data_enable <= s_hact and s_vact;
o_hsync <= s_hsync;
o_vsync <= s_vsync;
end architecture;
|
--!
--! @file: example9_4.vhd
--! @brief: procedure min_max in a package
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_components.all;
--------------------------------------
entity comparator is
--generic declarations
port (
a, b, c: in integer range -256 to 255;
min, max: out integer range -256 to 255);
end entity comparator;
--------------------------------------
architecture circuit of comparator is
--signals and declarations
begin
min_max(a, b, c, min, max);
end architecture circuit;
--------------------------------------
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_sha256
-- sha256_pl.vhd is part of DS_sha256.
-- DS_sha256 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_sha256 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all; -- std_logic
use ieee.numeric_std.all; -- to_integer()
use work.axi_pkg.all;
entity sha256_pl is
port (
aclk : in std_logic; -- clock
aresetn : in std_logic; -- asynchronous active low reset
done : out std_logic; -- done signal
--------------------------------
-- AXI lite slave port s0_axi --
--------------------------------
-- Inputs (master to slave) --
------------------------------
-- Read address channel
s0_axi_araddr: in std_logic_vector(29 downto 0);
s0_axi_arprot: in std_logic_vector(2 downto 0);
s0_axi_arvalid: in std_logic;
-- Read data channel
s0_axi_rready: in std_logic;
-- Write address channel
s0_axi_awaddr: in std_logic_vector(29 downto 0);
s0_axi_awprot: in std_logic_vector(2 downto 0);
s0_axi_awvalid: in std_logic;
-- Write data channel
s0_axi_wdata: in std_logic_vector(31 downto 0);
s0_axi_wstrb: in std_logic_vector(3 downto 0);
s0_axi_wvalid: in std_logic;
-- Write response channel
s0_axi_bready: in std_logic;
-------------------------------
-- Outputs (slave to master) --
-------------------------------
-- Read address channel
s0_axi_arready: out std_logic;
-- Read data channel
s0_axi_rdata: out std_logic_vector(31 downto 0);
s0_axi_rresp: out std_logic_vector(1 downto 0);
s0_axi_rvalid: out std_logic;
-- Write address channel
s0_axi_awready: out std_logic;
-- Write data channel
s0_axi_wready: out std_logic;
-- Write response channel
s0_axi_bresp: out std_logic_vector(1 downto 0);
s0_axi_bvalid: out std_logic
);
end entity sha256_pl;
architecture rtl of sha256_pl is
-- Or reduction of std_ulogic_vector
function or_reduce(v: std_ulogic_vector) return std_ulogic is
variable tmp: std_ulogic_vector(v'length - 1 downto 0) := v;
begin
if tmp'length = 0 then
return '0';
elsif tmp'length = 1 then
return tmp(0);
else
return or_reduce(tmp(tmp'length - 1 downto tmp'length / 2)) or
or_reduce(tmp(tmp'length / 2 - 1 downto 0));
end if;
end function or_reduce;
-- signals
-- Record versions of AXI signals
signal s0_axi_m2s : axilite_gp_m2s;
signal s0_axi_s2m : axilite_gp_s2m;
-- STATUS register
signal status : std_ulogic_vector(31 downto 0);
-- M_j_memory
signal M_j_memory_wcs_n_in,
M_j_memory_we_n_in : std_ulogic;
signal M_j_memory_w_addr_in : std_ulogic_vector(3 downto 0);
signal M_j_memory_data_in : std_ulogic_vector(31 downto 0);
signal M_j_memory_data_out : std_ulogic_vector(31 downto 0);
-- start_FF
signal start_FF_start_in : std_ulogic;
signal start_FF_start_out : std_ulogic;
-- sha256
signal M_j_memory_rcs_n_out : std_ulogic;
signal M_j_memory_r_addr_out : std_ulogic_vector(3 downto 0);
signal done_out : std_ulogic;
signal H_i_A_out,
H_i_B_out,
H_i_C_out,
H_i_D_out,
H_i_E_out,
H_i_F_out,
H_i_G_out,
H_i_H_out : std_ulogic_vector(31 downto 0);
begin
pl_M_j_memory1 : entity work.M_j_memory
generic map (
row_size => 32,
address_size => 4
)
port map (
clk => aclk,
rcs_n => M_j_memory_rcs_n_out,
wcs_n => M_j_memory_wcs_n_in,
we_n => M_j_memory_we_n_in,
r_addr => M_j_memory_r_addr_out,
w_addr => M_j_memory_w_addr_in,
data_in => M_j_memory_data_in,
data_out => M_j_memory_data_out
);
pl_start_FF1 : entity work.start_FF
port map (
clk => aclk,
d => start_FF_start_in,
start => start_FF_start_out
);
pl_sha256 : entity work.sha256
port map (
clk => aclk,
rstn => aresetn,
start => start_FF_start_out,
M_i_j => M_j_memory_data_out,
M_j_memory_rcs_n => M_j_memory_rcs_n_out,
M_j_memory_r_addr => M_j_memory_r_addr_out,
H_i_A => H_i_A_out,
H_i_B => H_i_B_out,
H_i_C => H_i_C_out,
H_i_D => H_i_D_out,
H_i_E => H_i_E_out,
H_i_F => H_i_F_out,
H_i_G => H_i_G_out,
H_i_H => H_i_H_out,
done => done_out
);
-- S0_AXI read-write requests
s0_axi_pr: process(aclk, aresetn)
-- idle: waiting for AXI master requests: when receiving write address and data valid (higher priority than read), perform the write, assert write address
-- ready, write data ready and bvalid, go to w1, else, when receiving address read valid, perform the read, assert read address ready, read data valid
-- and go to r1
-- w1: deassert write address ready and write data ready, wait for write response ready: when receiving it, deassert write response valid, go to idle
-- r1: deassert read address ready, wait for read response ready: when receiving it, deassert read data valid, go to idle
type state_type is (idle, w1, r1);
variable state: state_type;
begin
if aresetn = '0' then
s0_axi_s2m <= (rdata => (others => '0'), rresp => axi_resp_okay, bresp => axi_resp_okay, others => '0');
M_j_memory_wcs_n_in <= '1';
M_j_memory_we_n_in <= '1';
start_FF_start_in <= '0';
state := idle;
elsif aclk'event and aclk = '1' then
-- s0_axi write and read
case state is
when idle =>
if s0_axi_m2s.awvalid = '1' and s0_axi_m2s.wvalid = '1' then -- Write address and data
if or_reduce(s0_axi_m2s.awaddr(31 downto 7)) /= '0' then -- If unmapped address
s0_axi_s2m.bresp <= axi_resp_decerr;
elsif s0_axi_m2s.awaddr(7 downto 0) = x"00" or s0_axi_m2s.awaddr(7 downto 0) > x"44" then -- If read-only status register or H_(i-1)
s0_axi_s2m.bresp <= axi_resp_slverr;
else
s0_axi_s2m.bresp <= axi_resp_okay;
if s0_axi_m2s.awaddr(7 downto 0) >= x"04" and s0_axi_m2s.awaddr(7 downto 0) < x"44" then -- If M_j memory
for i in 0 to 3 loop
if s0_axi_m2s.wstrb(i) = '1' then
M_j_memory_data_in(8 * i + 7 downto 8 * i) <= s0_axi_m2s.wdata(8 * i + 7 downto 8 * i);
end if;
end loop;
-- every row in the memory can contain 32 bits, while the input address refers to byte:
-- it is first divided by 4 (i.e. 2-bit right shift), then 1 is subtracted (the first address is the status register)
-- then it is converted back to a ulogic_vector
M_j_memory_w_addr_in <= std_ulogic_vector(to_unsigned((to_integer(unsigned("00" & s0_axi_m2s.awaddr(7 downto 2))) - 1), 4));
M_j_memory_wcs_n_in <= '0';
M_j_memory_we_n_in <= '0';
elsif s0_axi_m2s.awaddr(7 downto 0) = x"44" then -- start command
start_FF_start_in <= '1';
end if;
end if;
s0_axi_s2m.awready <= '1';
s0_axi_s2m.wready <= '1';
s0_axi_s2m.bvalid <= '1';
state := w1;
elsif s0_axi_m2s.arvalid = '1' then
if or_reduce(s0_axi_m2s.araddr(31 downto 7)) /= '0' then -- If unmapped address
s0_axi_s2m.rdata <= (others => '0');
s0_axi_s2m.rresp <= axi_resp_decerr;
elsif s0_axi_m2s.araddr(7 downto 0) > x"00" and s0_axi_m2s.araddr(7 downto 0) <= x"44" then -- If write-only Mj or start
s0_axi_s2m.rresp <= axi_resp_slverr;
else
s0_axi_s2m.rresp <= axi_resp_okay;
case s0_axi_m2s.araddr(7 downto 0) is
when x"00" => -- status register
s0_axi_s2m.rdata <= status;
-- H(i-1)
when x"48" =>
s0_axi_s2m.rdata <= H_i_A_out;
when x"4c" =>
s0_axi_s2m.rdata <= H_i_B_out;
when x"50" =>
s0_axi_s2m.rdata <= H_i_C_out;
when x"54" =>
s0_axi_s2m.rdata <= H_i_D_out;
when x"58" =>
s0_axi_s2m.rdata <= H_i_E_out;
when x"5c" =>
s0_axi_s2m.rdata <= H_i_F_out;
when x"60" =>
s0_axi_s2m.rdata <= H_i_G_out;
when x"64" =>
s0_axi_s2m.rdata <= H_i_H_out;
when others =>
s0_axi_s2m.rdata <= x"00000000";
end case;
end if;
s0_axi_s2m.arready <= '1';
s0_axi_s2m.rvalid <= '1';
state := r1;
end if;
when w1 =>
s0_axi_s2m.awready <= '0';
s0_axi_s2m.wready <= '0';
M_j_memory_wcs_n_in <= '1';
M_j_memory_we_n_in <= '1';
start_FF_start_in <= '0';
if s0_axi_m2s.bready = '1' then
s0_axi_s2m.bvalid <= '0';
state := idle;
end if;
when r1 =>
s0_axi_s2m.arready <= '0';
if s0_axi_m2s.rready = '1' then
s0_axi_s2m.rvalid <= '0';
state := idle;
end if;
end case;
end if;
end process s0_axi_pr;
-- Record types to flat signals
s0_axi_m2s.araddr <= std_ulogic_vector("00" & s0_axi_araddr);
s0_axi_m2s.arprot <= std_ulogic_vector(s0_axi_arprot);
s0_axi_m2s.arvalid <= s0_axi_arvalid;
s0_axi_m2s.rready <= s0_axi_rready;
s0_axi_m2s.awaddr <= std_ulogic_vector("00" & s0_axi_awaddr);
s0_axi_m2s.awprot <= std_ulogic_vector(s0_axi_awprot);
s0_axi_m2s.awvalid <= s0_axi_awvalid;
s0_axi_m2s.wdata <= std_ulogic_vector(s0_axi_wdata);
s0_axi_m2s.wstrb <= std_ulogic_vector(s0_axi_wstrb);
s0_axi_m2s.wvalid <= s0_axi_wvalid;
s0_axi_m2s.bready <= s0_axi_bready;
s0_axi_arready <= s0_axi_s2m.arready;
s0_axi_rdata <= std_logic_vector(s0_axi_s2m.rdata);
s0_axi_rresp <= std_logic_vector(s0_axi_s2m.rresp);
s0_axi_rvalid <= s0_axi_s2m.rvalid;
s0_axi_awready <= s0_axi_s2m.awready;
s0_axi_wready <= s0_axi_s2m.wready;
s0_axi_bvalid <= s0_axi_s2m.bvalid;
s0_axi_bresp <= std_logic_vector(s0_axi_s2m.bresp);
status(0) <= done_out;
done <= done_out;
end architecture rtl;
|
library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_differential_inputs;
|
library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_differential_inputs;
|
library verilog;
use verilog.vl_types.all;
entity drive_differential_inputs is
port(
volt_vect : in vl_logic_vector(63 downto 0);
delta_vect : in vl_logic_vector(63 downto 0);
av : out vl_logic;
ac : out vl_logic
);
end drive_differential_inputs;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fmul_6_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fmul_6_max_dsp_32;
ARCHITECTURE convolve_kernel_ap_fmul_6_max_dsp_32_arch OF convolve_kernel_ap_fmul_6_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_6_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=6,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 6,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fmul_6_max_dsp_32_arch;
|
library ieee;
use ieee.std_logic_1164.all;
package testbench is
constant zero: std_logic_vector(3 downto 0) := x"0";
constant one: std_logic_vector(3 downto 0) := x"1";
constant two: std_logic_vector(3 downto 0) := x"2";
constant three: std_logic_vector(3 downto 0) := x"3";
constant four: std_logic_vector(3 downto 0) := x"4";
constant five: std_logic_vector(3 downto 0) := x"5";
constant six: std_logic_vector(3 downto 0) := x"6";
constant seven: std_logic_vector(3 downto 0) := x"7";
constant eight: std_logic_vector(3 downto 0) := x"8";
constant nine: std_logic_vector(3 downto 0) := x"9";
constant ten: std_logic_vector(3 downto 0) := x"a";
constant eleven: std_logic_vector(3 downto 0) := x"b";
constant twelve: std_logic_vector(3 downto 0) := x"c";
constant thirteen: std_logic_vector(3 downto 0) := x"d";
constant fourteen: std_logic_vector(3 downto 0) := x"e";
constant fifteen: std_logic_vector(3 downto 0) := x"f";
constant counter_width: positive := 24;
constant Disable: std_logic := '0';
constant enable: std_logic := '1';
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.testbench.all;
use work.definitions.all;
entity tb_alu is
end;
architecture struct_tb_alu of tb_alu is
component clkgen is
port(
clk_out: out std_logic;
resetn: out std_logic
);
end component;
component synchronous_latchN is
generic(
N: positive
);
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic_vector((N-1) downto 0);
q: out std_logic_vector((N-1) downto 0)
);
end component;
component synchronous_latch_autoclear is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
component counterN is
generic(
N: positive
);
port(
clock: in std_logic;
carry_in: in std_logic;
clock_enable: in std_logic;
resetn: in std_logic;
output: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end component;
component alu is
port(
-- control
operation: in std_logic_vector(4 downto 0);
-- operands
primary_operand: in std_logic_vector(7 downto 0);
secondary_operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
-- results
output, flags_out: out std_logic_vector(7 downto 0);
secondary_out: out std_logic_vector(7 downto 0)
);
end component;
component magnitudeN is
generic(
N: positive
);
port(
a, b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end component;
signal clock: std_logic;
signal resetn: std_logic;
signal notclock: std_logic;
signal next_state: std_logic_vector(3 downto 0);
signal nxt_state: std_logic_vector(3 downto 0);
signal current_state: std_logic_vector(3 downto 0);
signal counter_state: std_logic;
signal counter_clock: std_logic;
signal counter_clock_enable: std_logic;
signal counter_out: std_logic_vector((counter_width - 1) downto 0);
signal counter_zero: std_logic;
signal zero_secondary_alu_result: std_logic;
signal test_bits: std_logic;
signal res_bits: std_logic;
signal res_result: std_logic_vector(7 downto 0);
signal alu_result: std_logic_vector(7 downto 0);
signal secondary_alu_result: std_logic_vector(7 downto 0);
signal flags_in: std_logic_vector(7 downto 0);
signal flags: std_logic_vector(7 downto 0);
signal sum_check: std_logic_vector(8 downto 0);
signal sum_overflow_check: std_logic;
signal sum_zero_check: std_logic;
signal half_sum_check: std_logic_vector(4 downto 0);
signal sum_checker: std_logic;
signal subtract_check: std_logic_vector(8 downto 0);
signal subtract_overflow_check: std_logic;
signal subtract_zero_check: std_logic;
signal half_difference_check: std_logic_vector(4 downto 0);
signal subtract_checker: std_logic;
signal and_check: std_logic_vector(7 downto 0);
signal and_zero_check: std_logic;
signal and_parity_check: std_logic;
signal and_checker: std_logic;
signal xor_check: std_logic_vector(7 downto 0);
signal xor_zero_check: std_logic;
signal xor_parity_check: std_logic;
signal xor_checker: std_logic;
signal or_check: std_logic_vector(7 downto 0);
signal or_zero_check: std_logic;
signal or_parity_check: std_logic;
signal or_checker: std_logic;
signal rlc_check: std_logic_vector(7 downto 0);
signal rlc_zero_check: std_logic;
signal rlc_parity_check: std_logic;
signal rlc_checker: std_logic;
signal rrc_check: std_logic_vector(7 downto 0);
signal rrc_zero_check: std_logic;
signal rrc_parity_check: std_logic;
signal rrc_checker: std_logic;
signal rl_check: std_logic_vector(7 downto 0);
signal rl_zero_check: std_logic;
signal rl_parity_check: std_logic;
signal rl_checker: std_logic;
signal rr_check: std_logic_vector(7 downto 0);
signal rr_zero_check: std_logic;
signal rr_parity_check: std_logic;
signal rr_checker: std_logic;
signal daa_unimp: std_logic;
signal cpl_check: std_logic_vector(7 downto 0);
signal cpl_checker: std_logic;
signal scf_checker: std_logic;
signal ccf_flags: std_logic_vector(7 downto 0);
signal sla_check: std_logic_vector(7 downto 0);
signal sla_zero_check: std_logic;
signal sla_parity_check: std_logic;
signal sla_checker: std_logic;
signal sra_check: std_logic_vector(7 downto 0);
signal sra_zero_check: std_logic;
signal sra_parity_check: std_logic;
signal sra_checker: std_logic;
signal sll_check: std_logic_vector(7 downto 0);
signal sll_zero_check: std_logic;
signal sll_parity_check: std_logic;
signal sll_checker: std_logic;
signal srl_check: std_logic_vector(7 downto 0);
signal srl_zero_check: std_logic;
signal srl_parity_check: std_logic;
signal srl_checker: std_logic;
signal bit_checker: std_logic;
signal bit_check: std_logic_vector(7 downto 0);
signal bit_zero_checker: std_logic;
signal res_checker: std_logic;
signal set_checker: std_logic;
signal inrc_zero: std_logic;
signal inrc_parity: std_logic;
signal primary_rld_check: std_logic_vector(7 downto 0);
signal secondary_rld_check: std_logic_vector(7 downto 0);
signal rld_zero_check: std_logic;
signal rld_parity_check: std_logic;
signal primary_rld_checker: std_logic;
signal secondary_rld_checker: std_logic;
signal primary_rrd_check: std_logic_vector(7 downto 0);
signal secondary_rrd_check: std_logic_vector(7 downto 0);
signal rrd_zero_check: std_logic;
signal rrd_parity_check: std_logic;
signal primary_rrd_checker: std_logic;
signal secondary_rrd_checker: std_logic;
signal bmtc_check: std_logic_vector(7 downto 0);
signal bmtc_parity_check: std_logic;
signal bmtc_checker: std_logic;
signal done: std_logic;
begin
u1: clkgen port map(
clk_out => clock,
resetn => resetn
);
notclock <= not clock;
u2: synchronous_latchN
generic map(
N => 4
)
port map(
rstn => resetn,
clock => notclock,
clock_enable => '1',
d => next_state,
q => nxt_state
);
u3: synchronous_latchN
generic map(
N => 4
)
port map(
rstn => resetn,
clock => clock,
clock_enable => '1',
d => nxt_state,
q => current_state
);
u4: synchronous_latch_autoclear port map(
rstn => resetn,
clock => notclock,
clock_enable => counter_clock,
d => counter_state,
q => counter_clock_enable
);
u5: counterN
generic map(
N => counter_width
)
port map(
clock => clock,
carry_in => '1',
clock_enable => counter_clock_enable,
resetn => resetn,
output => counter_out((counter_width - 1) downto 0),
carry_out => open
);
u6: alu port map(
operation => counter_out(21 downto 17),
primary_operand => counter_out(7 downto 0),
secondary_operand => counter_out(15 downto 8),
flags_in => flags_in,
output => alu_result,
flags_out => flags,
secondary_out => secondary_alu_result
);
flags_in <= ( carry_bit => counter_out(16),
others => '0');
u7: magnitudeN
generic map(
N => counter_width
)
port map(
a => counter_out,
b => x"000000",
equal => counter_zero,
lt => open,
gt => open
);
u8: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sum_check(7 downto 0),
equal => sum_checker,
lt => open,
gt => open
);
u9: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => x"00",
equal => zero_secondary_alu_result,
lt => open,
gt => open
);
u10: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => subtract_check(7 downto 0),
equal => subtract_checker,
lt => open,
gt => open
);
u11: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => and_check(7 downto 0),
equal => and_checker,
lt => open,
gt => open
);
u12: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => xor_check(7 downto 0),
equal => xor_checker,
lt => open,
gt => open
);
u13: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => or_check(7 downto 0),
equal => or_checker,
lt => open,
gt => open
);
u14: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rlc_check(7 downto 0),
equal => rlc_checker,
lt => open,
gt => open
);
u15: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rrc_check(7 downto 0),
equal => rrc_checker,
lt => open,
gt => open
);
u16: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rl_check(7 downto 0),
equal => rl_checker,
lt => open,
gt => open
);
u17: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rr_check(7 downto 0),
equal => rr_checker,
lt => open,
gt => open
);
u18: magnitudeN
generic map(
N => 17
)
port map(
a => counter_out(16 downto 0),
b => "00000000000000000",
equal => daa_unimp,
lt => open,
gt => open
);
u19: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => cpl_check(7 downto 0),
equal => cpl_checker,
lt => open,
gt => open
);
u20: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => counter_out(7 downto 0),
equal => scf_checker,
lt => open,
gt => open
);
u21: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sla_check(7 downto 0),
equal => sla_checker,
lt => open,
gt => open
);
u22: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sra_check(7 downto 0),
equal => sra_checker,
lt => open,
gt => open
);
u23: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sll_check(7 downto 0),
equal => sll_checker,
lt => open,
gt => open
);
u24: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => srl_check(7 downto 0),
equal => srl_checker,
lt => open,
gt => open
);
u25: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => counter_out(15 downto 8),
equal => bit_checker,
lt => open,
gt => open
);
bit_check <= (counter_out(7 downto 0) and counter_out(15 downto 8));
u26: magnitudeN
generic map(
N => 8
)
port map(
a => x"00",
b => bit_check,
equal => bit_zero_checker,
lt => open,
gt => open
);
u27: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => res_result,
equal => res_checker,
lt => open,
gt => open
);
u28: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => primary_rld_check,
equal => primary_rld_checker,
lt => open,
gt => open
);
u29: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => secondary_rld_check,
equal => secondary_rld_checker,
lt => open,
gt => open
);
u30: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => primary_rrd_check,
equal => primary_rrd_checker,
lt => open,
gt => open
);
u31: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => secondary_rrd_check,
equal => secondary_rrd_checker,
lt => open,
gt => open
);
u32: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => bmtc_check,
equal => bmtc_checker,
lt => open,
gt => open
);
u33: magnitudeN
generic map(
N => 22
)
port map(
a => counter_out(21 downto 0),
b => (others => '1'), -- x"3fffff",
equal => done,
lt => open,
gt => open
);
process(current_state, resetn) begin
if resetn = '0' then
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= zero;
else
case current_state is
when zero =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= one;
when one =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
assert counter_zero = '1'
report "counter initialisation failure"
severity failure;
next_state <= two;
when two =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= three;
when three =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
case counter_out(21 downto 17) is
when add_operation | adc_operation =>
assert sum_checker = '1'
report "incorrect sum"
severity failure;
assert sum_check(8) = flags(carry_bit)
report "incorrect addition carry flag"
severity failure;
assert sum_overflow_check = flags(parity_overflow_bit)
report "incorrect addition overflow flag"
severity failure;
assert sum_zero_check = flags(zero_bit)
report "incorrect addition zero flag"
severity failure;
assert half_sum_check(4) = flags(half_carry_bit)
report "incorrect interdigit carry flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect addition sign flag"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect addition add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for add/adc"
severity failure;
when sub_operation | sbc_operation =>
assert subtract_checker = '1'
report "incorrect difference"
severity failure;
assert subtract_check(8) = flags(carry_bit)
report "incorrect subtraction borrow flag"
severity failure;
assert subtract_overflow_check = flags(parity_overflow_bit)
report "incorrect subtraction overflow flag"
severity failure;
assert subtract_zero_check = flags(zero_bit)
report "incorrect subtraction zero flag"
severity failure;
assert half_difference_check(4) = flags(half_carry_bit)
report "incorrect interdigit borrow flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect subtraction sign flag"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect subtraction add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sub/sbc"
severity failure;
when and_operation =>
assert and_checker = '1'
report "incorrect logical AND result"
severity failure;
assert and_zero_check = flags(zero_bit)
report "incorrect logical AND zero flag"
severity failure;
assert and_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical AND"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical AND"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical AND"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract bit for logical AND"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry bit for logical AND"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for and"
severity failure;
when xor_operation =>
assert xor_checker = '1'
report "incorrect logical XOR result"
severity failure;
assert xor_zero_check = flags(zero_bit)
report "incorrect logical XOR zero flag"
severity failure;
assert xor_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical XOR"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical XOR"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical XOR"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for logical XOR"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry bit for logical XOR"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for xor"
severity failure;
when or_operation =>
assert or_checker = '1'
report "incorrect logical OR result"
severity failure;
assert or_zero_check = flags(zero_bit)
report "incorrect logical OR zero flag"
severity failure;
assert or_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical OR"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical OR"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical OR"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for logical OR"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry flag for logical OR"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for OR operation"
severity failure;
when cmp_operation =>
assert subtract_checker = '1'
report "incorrect compare result"
severity failure;
assert subtract_check(8) = flags(carry_bit)
report "incorrect compare borrow flag"
severity failure;
assert subtract_overflow_check = flags(parity_overflow_bit)
report "incorrect compare overflow flag"
severity failure;
assert subtract_zero_check = flags(zero_bit)
report "incorrect compare zero flag"
severity failure;
assert half_difference_check(4) = flags(half_carry_bit)
report "incorrect compare interdigit borrow flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect compare sign flag"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect compare add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for compare"
severity failure;
when rlc_operation =>
assert rlc_checker = '1'
report "incorrect rlc result"
severity failure;
assert rlc_zero_check = flags(zero_bit)
report "incorrect rlc zero flag"
severity failure;
assert rlc_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rlc"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rlc"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rlc"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rlc"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for rlc"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rls"
severity failure;
when rrc_operation =>
assert rrc_checker = '1'
report "incorrect rrc result"
severity failure;
assert rrc_zero_check = flags(zero_bit)
report "incorrect rrc zero bit"
severity failure;
assert rrc_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rrc"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rrc"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rrc"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rrc"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for rrc"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rrc"
severity failure;
when rl_operation =>
assert rl_checker = '1'
report "incorrect rl result"
severity failure;
assert rl_zero_check = flags(zero_bit)
report "incorrect rl zero bit"
severity failure;
assert rl_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rl"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rl"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rl"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rl"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for rl"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rl"
severity failure;
when rr_operation =>
assert rr_checker = '1'
report "incorrect rr result"
severity failure;
assert rr_zero_check = flags(zero_bit)
report "incorrect rr zero bit"
severity failure;
assert rr_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rr"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rr"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rr"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rr"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for rr"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rr"
severity failure;
when daa_operation =>
assert daa_unimp = '0'
report "DAA is not implemented"
severity note;
when cpl_operation =>
assert cpl_checker = '1'
report "incorrect cpl result"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect cpl add/sub flag"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect cpl half-carry flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for cpl"
severity failure;
when scf_operation =>
assert scf_checker = '1'
report "incorrect scf result"
severity failure;
assert flags(carry_bit) = '1'
report "incorrect carry flag for scf"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for scf"
severity failure;
when ccf_operation =>
assert scf_checker = '1'
report "incorrect ccf result"
severity failure;
assert flags(carry_bit) = not (counter_out(16))
report "incorrect ccf carry flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for ccf"
severity failure;
when sla_operation =>
assert sla_checker = '1'
report "incorrect sla result"
severity failure;
assert sla_zero_check = flags(zero_bit)
report "incorrect sla zero flag"
severity failure;
assert sla_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sla"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sla"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sla"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sla"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry bit for flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sla"
severity failure;
when sra_operation =>
assert sra_checker = '1'
report "incorrect sra result"
severity failure;
assert sra_zero_check = flags(zero_bit)
report "incorrect sra zero flag"
severity failure;
assert sra_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sra"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sra"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sra"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sra"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for sra"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sra"
severity failure;
when sll_operation =>
assert sll_checker = '1'
report "incorrect sll result"
severity failure;
assert sll_zero_check = flags(zero_bit)
report "incorrect sll zero flag"
severity failure;
assert sll_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sll"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sll"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sll"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sll"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for sll"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sll"
severity failure;
when srl_operation =>
assert srl_checker = '1'
report "incorrect srl result"
severity failure;
assert srl_zero_check = flags(zero_bit)
report "incorrect srl zero flag"
severity failure;
assert srl_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for srl"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for srl"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for srl"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for srl"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for srl"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for srl"
severity failure;
when bit_operation =>
assert bit_checker = '1'
report "incorrect result for bit operation"
severity failure;
if test_bits = '1' then
if bit_zero_checker = '1' then
assert flags(zero_bit) = '1'
report "BIT: zero flag != '1'"
severity failure;
elsif bit_zero_checker = '0' then
assert flags(zero_bit) = '0'
report "BIT: zero flag != '0'"
severity failure;
end if;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for bit"
severity failure;
when res_operation =>
if test_bits = '1' then
assert res_checker = '1'
report "incorrect result for RES"
severity failure;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for res"
severity failure;
when set_operation =>
if test_bits = '1' then
assert or_checker = '1'
report "incorrect result for SET"
severity failure;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for set"
severity failure;
when in16_operation =>
assert scf_checker = '1'
report "incorrect result for in r,(C)"
severity failure;
assert flags(zero_bit) = inrc_zero
report "incorrect zero flag for in r,(c)"
severity failure;
assert flags(parity_overflow_bit) = inrc_parity
report "incorrect parity flag for in r,(c)"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for in r,(c)"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for in r,(c)"
severity failure;
assert flags(sign_bit) = alu_result(sign_bit)
report "incorrect sign flag for in r,(c)"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for in r, (c)"
severity failure;
when rld_operation =>
assert primary_rld_checker = '1'
report "incorrect primary result for rld"
severity failure;
assert secondary_rld_checker = '1'
report "incorrect secondary rld result"
severity failure;
assert alu_result(sign_bit) = flags(sign_bit)
report "incorrect sign flag for rld"
severity failure;
assert rld_zero_check = flags(zero_bit)
report "incorrect zero flag for rld"
severity failure;
assert rld_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rld"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rld"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rld"
severity failure;
when rrd_operation =>
assert primary_rrd_checker = '1'
report "incorrect primary result for rrd"
severity failure;
assert secondary_rrd_checker = '1'
report "incorrect secondary rrd result"
severity failure;
assert alu_result(sign_bit) = flags(sign_bit)
report "incorrect sign flag for rrd"
severity failure;
assert rrd_zero_check = flags(zero_bit)
report "incorrect zero flag for rrd"
severity failure;
assert rrd_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rrd"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rrd"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rrd"
severity failure;
when blockterm16_operation =>
assert bmtc_checker = '1'
report "incorrect bmtc result"
severity failure;
assert bmtc_parity_check = flags(parity_overflow_bit)
report "incorrect bmtc parity bit"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for block termination"
severity failure;
when others =>
-- assert counter_out(16 downto 0) /= ('0' & x"0000")
-- report "unimplemented alu operation"
-- severity warning;
end case;
if done = '1' then
counter_state <= Disable;
counter_clock <= Disable;
next_state <= fifteen;
else
counter_clock <= enable;
counter_state <= enable;
next_state <= two;
end if;
when four =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= five;
when five =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= six;
when six =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= seven;
when seven =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= eight;
when eight =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= nine;
when nine =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= ten;
when ten =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= eleven;
when eleven =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= twelve;
when twelve =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= thirteen;
when thirteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= fourteen;
when fourteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= fifteen;
when fifteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
assert false
report "test success"
severity note;
when others =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= zero;
assert false
report "state machine failure"
severity failure;
end case;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
package testbench is
constant zero: std_logic_vector(3 downto 0) := x"0";
constant one: std_logic_vector(3 downto 0) := x"1";
constant two: std_logic_vector(3 downto 0) := x"2";
constant three: std_logic_vector(3 downto 0) := x"3";
constant four: std_logic_vector(3 downto 0) := x"4";
constant five: std_logic_vector(3 downto 0) := x"5";
constant six: std_logic_vector(3 downto 0) := x"6";
constant seven: std_logic_vector(3 downto 0) := x"7";
constant eight: std_logic_vector(3 downto 0) := x"8";
constant nine: std_logic_vector(3 downto 0) := x"9";
constant ten: std_logic_vector(3 downto 0) := x"a";
constant eleven: std_logic_vector(3 downto 0) := x"b";
constant twelve: std_logic_vector(3 downto 0) := x"c";
constant thirteen: std_logic_vector(3 downto 0) := x"d";
constant fourteen: std_logic_vector(3 downto 0) := x"e";
constant fifteen: std_logic_vector(3 downto 0) := x"f";
constant counter_width: positive := 24;
constant Disable: std_logic := '0';
constant enable: std_logic := '1';
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.testbench.all;
use work.definitions.all;
entity tb_alu is
end;
architecture struct_tb_alu of tb_alu is
component clkgen is
port(
clk_out: out std_logic;
resetn: out std_logic
);
end component;
component synchronous_latchN is
generic(
N: positive
);
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic_vector((N-1) downto 0);
q: out std_logic_vector((N-1) downto 0)
);
end component;
component synchronous_latch_autoclear is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
component counterN is
generic(
N: positive
);
port(
clock: in std_logic;
carry_in: in std_logic;
clock_enable: in std_logic;
resetn: in std_logic;
output: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end component;
component alu is
port(
-- control
operation: in std_logic_vector(4 downto 0);
-- operands
primary_operand: in std_logic_vector(7 downto 0);
secondary_operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
-- results
output, flags_out: out std_logic_vector(7 downto 0);
secondary_out: out std_logic_vector(7 downto 0)
);
end component;
component magnitudeN is
generic(
N: positive
);
port(
a, b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end component;
signal clock: std_logic;
signal resetn: std_logic;
signal notclock: std_logic;
signal next_state: std_logic_vector(3 downto 0);
signal nxt_state: std_logic_vector(3 downto 0);
signal current_state: std_logic_vector(3 downto 0);
signal counter_state: std_logic;
signal counter_clock: std_logic;
signal counter_clock_enable: std_logic;
signal counter_out: std_logic_vector((counter_width - 1) downto 0);
signal counter_zero: std_logic;
signal zero_secondary_alu_result: std_logic;
signal test_bits: std_logic;
signal res_bits: std_logic;
signal res_result: std_logic_vector(7 downto 0);
signal alu_result: std_logic_vector(7 downto 0);
signal secondary_alu_result: std_logic_vector(7 downto 0);
signal flags_in: std_logic_vector(7 downto 0);
signal flags: std_logic_vector(7 downto 0);
signal sum_check: std_logic_vector(8 downto 0);
signal sum_overflow_check: std_logic;
signal sum_zero_check: std_logic;
signal half_sum_check: std_logic_vector(4 downto 0);
signal sum_checker: std_logic;
signal subtract_check: std_logic_vector(8 downto 0);
signal subtract_overflow_check: std_logic;
signal subtract_zero_check: std_logic;
signal half_difference_check: std_logic_vector(4 downto 0);
signal subtract_checker: std_logic;
signal and_check: std_logic_vector(7 downto 0);
signal and_zero_check: std_logic;
signal and_parity_check: std_logic;
signal and_checker: std_logic;
signal xor_check: std_logic_vector(7 downto 0);
signal xor_zero_check: std_logic;
signal xor_parity_check: std_logic;
signal xor_checker: std_logic;
signal or_check: std_logic_vector(7 downto 0);
signal or_zero_check: std_logic;
signal or_parity_check: std_logic;
signal or_checker: std_logic;
signal rlc_check: std_logic_vector(7 downto 0);
signal rlc_zero_check: std_logic;
signal rlc_parity_check: std_logic;
signal rlc_checker: std_logic;
signal rrc_check: std_logic_vector(7 downto 0);
signal rrc_zero_check: std_logic;
signal rrc_parity_check: std_logic;
signal rrc_checker: std_logic;
signal rl_check: std_logic_vector(7 downto 0);
signal rl_zero_check: std_logic;
signal rl_parity_check: std_logic;
signal rl_checker: std_logic;
signal rr_check: std_logic_vector(7 downto 0);
signal rr_zero_check: std_logic;
signal rr_parity_check: std_logic;
signal rr_checker: std_logic;
signal daa_unimp: std_logic;
signal cpl_check: std_logic_vector(7 downto 0);
signal cpl_checker: std_logic;
signal scf_checker: std_logic;
signal ccf_flags: std_logic_vector(7 downto 0);
signal sla_check: std_logic_vector(7 downto 0);
signal sla_zero_check: std_logic;
signal sla_parity_check: std_logic;
signal sla_checker: std_logic;
signal sra_check: std_logic_vector(7 downto 0);
signal sra_zero_check: std_logic;
signal sra_parity_check: std_logic;
signal sra_checker: std_logic;
signal sll_check: std_logic_vector(7 downto 0);
signal sll_zero_check: std_logic;
signal sll_parity_check: std_logic;
signal sll_checker: std_logic;
signal srl_check: std_logic_vector(7 downto 0);
signal srl_zero_check: std_logic;
signal srl_parity_check: std_logic;
signal srl_checker: std_logic;
signal bit_checker: std_logic;
signal bit_check: std_logic_vector(7 downto 0);
signal bit_zero_checker: std_logic;
signal res_checker: std_logic;
signal set_checker: std_logic;
signal inrc_zero: std_logic;
signal inrc_parity: std_logic;
signal primary_rld_check: std_logic_vector(7 downto 0);
signal secondary_rld_check: std_logic_vector(7 downto 0);
signal rld_zero_check: std_logic;
signal rld_parity_check: std_logic;
signal primary_rld_checker: std_logic;
signal secondary_rld_checker: std_logic;
signal primary_rrd_check: std_logic_vector(7 downto 0);
signal secondary_rrd_check: std_logic_vector(7 downto 0);
signal rrd_zero_check: std_logic;
signal rrd_parity_check: std_logic;
signal primary_rrd_checker: std_logic;
signal secondary_rrd_checker: std_logic;
signal bmtc_check: std_logic_vector(7 downto 0);
signal bmtc_parity_check: std_logic;
signal bmtc_checker: std_logic;
signal done: std_logic;
begin
u1: clkgen port map(
clk_out => clock,
resetn => resetn
);
notclock <= not clock;
u2: synchronous_latchN
generic map(
N => 4
)
port map(
rstn => resetn,
clock => notclock,
clock_enable => '1',
d => next_state,
q => nxt_state
);
u3: synchronous_latchN
generic map(
N => 4
)
port map(
rstn => resetn,
clock => clock,
clock_enable => '1',
d => nxt_state,
q => current_state
);
u4: synchronous_latch_autoclear port map(
rstn => resetn,
clock => notclock,
clock_enable => counter_clock,
d => counter_state,
q => counter_clock_enable
);
u5: counterN
generic map(
N => counter_width
)
port map(
clock => clock,
carry_in => '1',
clock_enable => counter_clock_enable,
resetn => resetn,
output => counter_out((counter_width - 1) downto 0),
carry_out => open
);
u6: alu port map(
operation => counter_out(21 downto 17),
primary_operand => counter_out(7 downto 0),
secondary_operand => counter_out(15 downto 8),
flags_in => flags_in,
output => alu_result,
flags_out => flags,
secondary_out => secondary_alu_result
);
flags_in <= ( carry_bit => counter_out(16),
others => '0');
u7: magnitudeN
generic map(
N => counter_width
)
port map(
a => counter_out,
b => x"000000",
equal => counter_zero,
lt => open,
gt => open
);
u8: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sum_check(7 downto 0),
equal => sum_checker,
lt => open,
gt => open
);
u9: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => x"00",
equal => zero_secondary_alu_result,
lt => open,
gt => open
);
u10: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => subtract_check(7 downto 0),
equal => subtract_checker,
lt => open,
gt => open
);
u11: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => and_check(7 downto 0),
equal => and_checker,
lt => open,
gt => open
);
u12: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => xor_check(7 downto 0),
equal => xor_checker,
lt => open,
gt => open
);
u13: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => or_check(7 downto 0),
equal => or_checker,
lt => open,
gt => open
);
u14: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rlc_check(7 downto 0),
equal => rlc_checker,
lt => open,
gt => open
);
u15: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rrc_check(7 downto 0),
equal => rrc_checker,
lt => open,
gt => open
);
u16: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rl_check(7 downto 0),
equal => rl_checker,
lt => open,
gt => open
);
u17: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rr_check(7 downto 0),
equal => rr_checker,
lt => open,
gt => open
);
u18: magnitudeN
generic map(
N => 17
)
port map(
a => counter_out(16 downto 0),
b => "00000000000000000",
equal => daa_unimp,
lt => open,
gt => open
);
u19: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => cpl_check(7 downto 0),
equal => cpl_checker,
lt => open,
gt => open
);
u20: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => counter_out(7 downto 0),
equal => scf_checker,
lt => open,
gt => open
);
u21: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sla_check(7 downto 0),
equal => sla_checker,
lt => open,
gt => open
);
u22: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sra_check(7 downto 0),
equal => sra_checker,
lt => open,
gt => open
);
u23: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sll_check(7 downto 0),
equal => sll_checker,
lt => open,
gt => open
);
u24: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => srl_check(7 downto 0),
equal => srl_checker,
lt => open,
gt => open
);
u25: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => counter_out(15 downto 8),
equal => bit_checker,
lt => open,
gt => open
);
bit_check <= (counter_out(7 downto 0) and counter_out(15 downto 8));
u26: magnitudeN
generic map(
N => 8
)
port map(
a => x"00",
b => bit_check,
equal => bit_zero_checker,
lt => open,
gt => open
);
u27: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => res_result,
equal => res_checker,
lt => open,
gt => open
);
u28: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => primary_rld_check,
equal => primary_rld_checker,
lt => open,
gt => open
);
u29: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => secondary_rld_check,
equal => secondary_rld_checker,
lt => open,
gt => open
);
u30: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => primary_rrd_check,
equal => primary_rrd_checker,
lt => open,
gt => open
);
u31: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => secondary_rrd_check,
equal => secondary_rrd_checker,
lt => open,
gt => open
);
u32: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => bmtc_check,
equal => bmtc_checker,
lt => open,
gt => open
);
u33: magnitudeN
generic map(
N => 22
)
port map(
a => counter_out(21 downto 0),
b => (others => '1'), -- x"3fffff",
equal => done,
lt => open,
gt => open
);
process(current_state, resetn) begin
if resetn = '0' then
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= zero;
else
case current_state is
when zero =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= one;
when one =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
assert counter_zero = '1'
report "counter initialisation failure"
severity failure;
next_state <= two;
when two =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= three;
when three =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
case counter_out(21 downto 17) is
when add_operation | adc_operation =>
assert sum_checker = '1'
report "incorrect sum"
severity failure;
assert sum_check(8) = flags(carry_bit)
report "incorrect addition carry flag"
severity failure;
assert sum_overflow_check = flags(parity_overflow_bit)
report "incorrect addition overflow flag"
severity failure;
assert sum_zero_check = flags(zero_bit)
report "incorrect addition zero flag"
severity failure;
assert half_sum_check(4) = flags(half_carry_bit)
report "incorrect interdigit carry flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect addition sign flag"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect addition add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for add/adc"
severity failure;
when sub_operation | sbc_operation =>
assert subtract_checker = '1'
report "incorrect difference"
severity failure;
assert subtract_check(8) = flags(carry_bit)
report "incorrect subtraction borrow flag"
severity failure;
assert subtract_overflow_check = flags(parity_overflow_bit)
report "incorrect subtraction overflow flag"
severity failure;
assert subtract_zero_check = flags(zero_bit)
report "incorrect subtraction zero flag"
severity failure;
assert half_difference_check(4) = flags(half_carry_bit)
report "incorrect interdigit borrow flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect subtraction sign flag"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect subtraction add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sub/sbc"
severity failure;
when and_operation =>
assert and_checker = '1'
report "incorrect logical AND result"
severity failure;
assert and_zero_check = flags(zero_bit)
report "incorrect logical AND zero flag"
severity failure;
assert and_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical AND"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical AND"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical AND"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract bit for logical AND"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry bit for logical AND"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for and"
severity failure;
when xor_operation =>
assert xor_checker = '1'
report "incorrect logical XOR result"
severity failure;
assert xor_zero_check = flags(zero_bit)
report "incorrect logical XOR zero flag"
severity failure;
assert xor_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical XOR"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical XOR"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical XOR"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for logical XOR"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry bit for logical XOR"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for xor"
severity failure;
when or_operation =>
assert or_checker = '1'
report "incorrect logical OR result"
severity failure;
assert or_zero_check = flags(zero_bit)
report "incorrect logical OR zero flag"
severity failure;
assert or_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical OR"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical OR"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical OR"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for logical OR"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry flag for logical OR"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for OR operation"
severity failure;
when cmp_operation =>
assert subtract_checker = '1'
report "incorrect compare result"
severity failure;
assert subtract_check(8) = flags(carry_bit)
report "incorrect compare borrow flag"
severity failure;
assert subtract_overflow_check = flags(parity_overflow_bit)
report "incorrect compare overflow flag"
severity failure;
assert subtract_zero_check = flags(zero_bit)
report "incorrect compare zero flag"
severity failure;
assert half_difference_check(4) = flags(half_carry_bit)
report "incorrect compare interdigit borrow flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect compare sign flag"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect compare add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for compare"
severity failure;
when rlc_operation =>
assert rlc_checker = '1'
report "incorrect rlc result"
severity failure;
assert rlc_zero_check = flags(zero_bit)
report "incorrect rlc zero flag"
severity failure;
assert rlc_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rlc"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rlc"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rlc"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rlc"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for rlc"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rls"
severity failure;
when rrc_operation =>
assert rrc_checker = '1'
report "incorrect rrc result"
severity failure;
assert rrc_zero_check = flags(zero_bit)
report "incorrect rrc zero bit"
severity failure;
assert rrc_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rrc"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rrc"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rrc"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rrc"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for rrc"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rrc"
severity failure;
when rl_operation =>
assert rl_checker = '1'
report "incorrect rl result"
severity failure;
assert rl_zero_check = flags(zero_bit)
report "incorrect rl zero bit"
severity failure;
assert rl_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rl"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rl"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rl"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rl"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for rl"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rl"
severity failure;
when rr_operation =>
assert rr_checker = '1'
report "incorrect rr result"
severity failure;
assert rr_zero_check = flags(zero_bit)
report "incorrect rr zero bit"
severity failure;
assert rr_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rr"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rr"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rr"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rr"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for rr"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rr"
severity failure;
when daa_operation =>
assert daa_unimp = '0'
report "DAA is not implemented"
severity note;
when cpl_operation =>
assert cpl_checker = '1'
report "incorrect cpl result"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect cpl add/sub flag"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect cpl half-carry flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for cpl"
severity failure;
when scf_operation =>
assert scf_checker = '1'
report "incorrect scf result"
severity failure;
assert flags(carry_bit) = '1'
report "incorrect carry flag for scf"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for scf"
severity failure;
when ccf_operation =>
assert scf_checker = '1'
report "incorrect ccf result"
severity failure;
assert flags(carry_bit) = not (counter_out(16))
report "incorrect ccf carry flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for ccf"
severity failure;
when sla_operation =>
assert sla_checker = '1'
report "incorrect sla result"
severity failure;
assert sla_zero_check = flags(zero_bit)
report "incorrect sla zero flag"
severity failure;
assert sla_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sla"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sla"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sla"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sla"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry bit for flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sla"
severity failure;
when sra_operation =>
assert sra_checker = '1'
report "incorrect sra result"
severity failure;
assert sra_zero_check = flags(zero_bit)
report "incorrect sra zero flag"
severity failure;
assert sra_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sra"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sra"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sra"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sra"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for sra"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sra"
severity failure;
when sll_operation =>
assert sll_checker = '1'
report "incorrect sll result"
severity failure;
assert sll_zero_check = flags(zero_bit)
report "incorrect sll zero flag"
severity failure;
assert sll_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sll"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sll"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sll"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sll"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for sll"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sll"
severity failure;
when srl_operation =>
assert srl_checker = '1'
report "incorrect srl result"
severity failure;
assert srl_zero_check = flags(zero_bit)
report "incorrect srl zero flag"
severity failure;
assert srl_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for srl"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for srl"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for srl"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for srl"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for srl"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for srl"
severity failure;
when bit_operation =>
assert bit_checker = '1'
report "incorrect result for bit operation"
severity failure;
if test_bits = '1' then
if bit_zero_checker = '1' then
assert flags(zero_bit) = '1'
report "BIT: zero flag != '1'"
severity failure;
elsif bit_zero_checker = '0' then
assert flags(zero_bit) = '0'
report "BIT: zero flag != '0'"
severity failure;
end if;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for bit"
severity failure;
when res_operation =>
if test_bits = '1' then
assert res_checker = '1'
report "incorrect result for RES"
severity failure;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for res"
severity failure;
when set_operation =>
if test_bits = '1' then
assert or_checker = '1'
report "incorrect result for SET"
severity failure;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for set"
severity failure;
when in16_operation =>
assert scf_checker = '1'
report "incorrect result for in r,(C)"
severity failure;
assert flags(zero_bit) = inrc_zero
report "incorrect zero flag for in r,(c)"
severity failure;
assert flags(parity_overflow_bit) = inrc_parity
report "incorrect parity flag for in r,(c)"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for in r,(c)"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for in r,(c)"
severity failure;
assert flags(sign_bit) = alu_result(sign_bit)
report "incorrect sign flag for in r,(c)"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for in r, (c)"
severity failure;
when rld_operation =>
assert primary_rld_checker = '1'
report "incorrect primary result for rld"
severity failure;
assert secondary_rld_checker = '1'
report "incorrect secondary rld result"
severity failure;
assert alu_result(sign_bit) = flags(sign_bit)
report "incorrect sign flag for rld"
severity failure;
assert rld_zero_check = flags(zero_bit)
report "incorrect zero flag for rld"
severity failure;
assert rld_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rld"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rld"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rld"
severity failure;
when rrd_operation =>
assert primary_rrd_checker = '1'
report "incorrect primary result for rrd"
severity failure;
assert secondary_rrd_checker = '1'
report "incorrect secondary rrd result"
severity failure;
assert alu_result(sign_bit) = flags(sign_bit)
report "incorrect sign flag for rrd"
severity failure;
assert rrd_zero_check = flags(zero_bit)
report "incorrect zero flag for rrd"
severity failure;
assert rrd_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rrd"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rrd"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rrd"
severity failure;
when blockterm16_operation =>
assert bmtc_checker = '1'
report "incorrect bmtc result"
severity failure;
assert bmtc_parity_check = flags(parity_overflow_bit)
report "incorrect bmtc parity bit"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for block termination"
severity failure;
when others =>
-- assert counter_out(16 downto 0) /= ('0' & x"0000")
-- report "unimplemented alu operation"
-- severity warning;
end case;
if done = '1' then
counter_state <= Disable;
counter_clock <= Disable;
next_state <= fifteen;
else
counter_clock <= enable;
counter_state <= enable;
next_state <= two;
end if;
when four =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= five;
when five =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= six;
when six =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= seven;
when seven =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= eight;
when eight =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= nine;
when nine =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= ten;
when ten =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= eleven;
when eleven =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= twelve;
when twelve =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= thirteen;
when thirteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= fourteen;
when fourteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= fifteen;
when fifteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
assert false
report "test success"
severity note;
when others =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= zero;
assert false
report "state machine failure"
severity failure;
end case;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
architecture behavior of c_comparator is
begin
P0 : process (input1, input2)
variable result : std_logic_vector(2 downto 0);
begin
result := "000";
if (input1 = input2) then
result(0) := '1';
elsif (input1 > input2) then
result(1) := '1';
elsif (input1 < input2) then
result(2) := '1';
end if;
output <= result;
end process P0;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
architecture behavior of c_comparator is
begin
P0 : process (input1, input2)
variable result : std_logic_vector(2 downto 0);
begin
result := "000";
if (input1 = input2) then
result(0) := '1';
elsif (input1 > input2) then
result(1) := '1';
elsif (input1 < input2) then
result(2) := '1';
end if;
output <= result;
end process P0;
end behavior; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2548.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p08n01i02548ent IS
END c07s03b05x00p08n01i02548ent;
ARCHITECTURE c07s03b05x00p08n01i02548arch OF c07s03b05x00p08n01i02548ent IS
BEGIN
TESTING: PROCESS
type century is array (1 to 1000) of real ;
type millenia is array (1 to 100 ) of real ;
variable hundreds : century ;
variable thousand : millenia ;
BEGIN
thousand := millenia (hundreds);
-- Failure_here
-- dimensionality not same.
assert FALSE
report "***FAILED TEST: c07s03b05x00p08n01i02548 - Operand and the target type should have the same dimensionality in a type conversion."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p08n01i02548arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2548.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p08n01i02548ent IS
END c07s03b05x00p08n01i02548ent;
ARCHITECTURE c07s03b05x00p08n01i02548arch OF c07s03b05x00p08n01i02548ent IS
BEGIN
TESTING: PROCESS
type century is array (1 to 1000) of real ;
type millenia is array (1 to 100 ) of real ;
variable hundreds : century ;
variable thousand : millenia ;
BEGIN
thousand := millenia (hundreds);
-- Failure_here
-- dimensionality not same.
assert FALSE
report "***FAILED TEST: c07s03b05x00p08n01i02548 - Operand and the target type should have the same dimensionality in a type conversion."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p08n01i02548arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2548.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p08n01i02548ent IS
END c07s03b05x00p08n01i02548ent;
ARCHITECTURE c07s03b05x00p08n01i02548arch OF c07s03b05x00p08n01i02548ent IS
BEGIN
TESTING: PROCESS
type century is array (1 to 1000) of real ;
type millenia is array (1 to 100 ) of real ;
variable hundreds : century ;
variable thousand : millenia ;
BEGIN
thousand := millenia (hundreds);
-- Failure_here
-- dimensionality not same.
assert FALSE
report "***FAILED TEST: c07s03b05x00p08n01i02548 - Operand and the target type should have the same dimensionality in a type conversion."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p08n01i02548arch;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Fri May 9 13:48:22 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_182/clk_182_funcsim.vhdl
-- Design : clk_182
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_182clk_182_clk_wiz is
port (
clk_200MHz : in STD_LOGIC;
clk_182MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_182clk_182_clk_wiz : entity is "clk_182_clk_wiz";
end clk_182clk_182_clk_wiz;
architecture STRUCTURE of clk_182clk_182_clk_wiz is
signal clk_182MHz_clk_182 : STD_LOGIC;
signal clk_200MHz_clk_182 : STD_LOGIC;
signal clkfbout_buf_clk_182 : STD_LOGIC;
signal clkfbout_clk_182 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute box_type of clkin1_ibufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_182,
O => clkfbout_buf_clk_182
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_200MHz,
O => clk_200MHz_clk_182
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_182MHz_clk_182,
O => clk_182MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 9.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 5.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_182,
CLKFBOUT => clkfbout_clk_182,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_200MHz_clk_182,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_182MHz_clk_182,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_182 is
port (
clk_200MHz : in STD_LOGIC;
clk_182MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_182 : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_182 : entity is "clk_182,clk_wiz_v5_1,{component_name=clk_182,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_182;
architecture STRUCTURE of clk_182 is
begin
U0: entity work.clk_182clk_182_clk_wiz
port map (
clk_182MHz => clk_182MHz,
clk_200MHz => clk_200MHz,
locked => locked
);
end STRUCTURE;
|
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
entity test_lfsr is
end test_lfsr;
architecture behave of test_lfsr is
constant num_rng : integer := 4;
constant width : integer := 8;
type state_array_t is array(1 to num_rng) of
std_logic_vector(width-1 downto 0);
subtype state_uns_t is unsigned(width+2-1 downto 0);
type state_uns_array_t is array(1 to num_rng) of
state_uns_t;
constant seeds : state_array_t := (
1 => "11111111",
2 => "00001111",
3 => "11110000",
4 => "00000001"
);
signal clk, reset : std_ulogic;
signal rand_out : state_array_t;
signal rng : state_uns_array_t;
signal sum : state_uns_t;
signal ctr : integer range 1 to width;
begin
clock_generation: process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
gen_rngs: for rng_i in 1 to num_rng generate
uut : entity work.lfsr
generic map (
width => width
)
port map (
clk => clk,
reset => reset,
seed => seeds(rng_i),
poly => "10111000",
rand_out => rand_out(rng_i)
);
rng(rng_i) <= "00" & unsigned(rand_out(rng_i));
end generate gen_rngs;
process (clk, reset)
begin
if reset = '1' then
ctr <= 1;
elsif rising_edge(clk) then
if ctr < width then
ctr <= ctr + 1;
else
ctr <= 1;
end if;
end if;
end process;
sum <= (rng(1) + rng(2)) + (rng(3) + rng(4)) when ctr = 1
else sum;
stimulus: process
variable l : line;
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait until clk'event and clk = '1';
write(l, string'("releasing reset"));
writeline(output, l);
for i in 0 to 19 loop
write(l, string'("rand_out = "));
for rng_i in 1 to num_rng loop
hwrite(l, rand_out(rng_i));
write(l, string'(" "));
end loop;
write(l, string'(" sum="));
write(l, std_logic_vector(sum));
writeline(output, l);
wait until rising_edge(clk);
end loop;
wait;
end process;
end behave;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package stimulus_types is
constant stimulus_vector_length : positive := 10;
type stimulus_element is record
application_time : delay_length;
pattern : std_logic_vector(0 to stimulus_vector_length - 1);
end record stimulus_element;
function stimulus_key ( stimulus : stimulus_element ) return delay_length;
end package stimulus_types;
--------------------------------------------------
package body stimulus_types is
function stimulus_key ( stimulus : stimulus_element ) return delay_length is
begin
return stimulus.application_time;
end function stimulus_key;
end package body stimulus_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package stimulus_types is
constant stimulus_vector_length : positive := 10;
type stimulus_element is record
application_time : delay_length;
pattern : std_logic_vector(0 to stimulus_vector_length - 1);
end record stimulus_element;
function stimulus_key ( stimulus : stimulus_element ) return delay_length;
end package stimulus_types;
--------------------------------------------------
package body stimulus_types is
function stimulus_key ( stimulus : stimulus_element ) return delay_length is
begin
return stimulus.application_time;
end function stimulus_key;
end package body stimulus_types;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package stimulus_types is
constant stimulus_vector_length : positive := 10;
type stimulus_element is record
application_time : delay_length;
pattern : std_logic_vector(0 to stimulus_vector_length - 1);
end record stimulus_element;
function stimulus_key ( stimulus : stimulus_element ) return delay_length;
end package stimulus_types;
--------------------------------------------------
package body stimulus_types is
function stimulus_key ( stimulus : stimulus_element ) return delay_length is
begin
return stimulus.application_time;
end function stimulus_key;
end package body stimulus_types;
|
--------------------------------------------------------------------
-- _ __ __ __ ____ __ = --
-- | | / // / / // __ \ / / = --
-- | | / // /_/ // / / // / = .__ |/ _/_ .__ .__ __ --
-- | |/ // __ // /_/ // /___ = /___) | / / ) / ) (_ ` --
-- |___//_/ /_//_____//_____/ = (___ /| (_ / (___(_ (__) --
-- ===== / --
-- === --
----------------------------- = ----------------------------------
--# synchronizing.vhdl - Clock domain synchronization components
--# $Id$
--# Freely available from VHDL-extras (http://code.google.com/p/vhdl-extras)
--#
--# Copyright � 2010 Kevin Thibedeau
--# (kevin 'period' thibedeau 'at' gmail 'punto' com)
--#
--# Permission is hereby granted, free of charge, to any person obtaining a
--# copy of this software and associated documentation files (the "Software"),
--# to deal in the Software without restriction, including without limitation
--# the rights to use, copy, modify, merge, publish, distribute, sublicense,
--# and/or sell copies of the Software, and to permit persons to whom the
--# Software is furnished to do so, subject to the following conditions:
--#
--# The above copyright notice and this permission notice shall be included in
--# all copies or substantial portions of the Software.
--#
--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
--# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
--# DEALINGS IN THE SOFTWARE.
--#
--# DEPENDENCIES: none
--#
--# DESCRIPTION:
--# This package provides a number of synchronizer components for managing
--# data transmission between clock domains.
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package synchronizing is
--## A basic synchronizer with a configurable number of stages
component bit_synchronizer is
generic (
STAGES : natural := 2; -- number of flip-flops in the synchronizer
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Bit_in : in std_ulogic; -- Unsynchronized signal
Sync : out std_ulogic -- Synchronized to Clock's domain
);
end component;
--## Synchronizer for generating a synchronized reset
component reset_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Sync_reset : out std_ulogic -- Synchronized reset
);
end component;
--## A handshaking synchronizer for sending an array between clock domains
--# This uses the four-phase handshake protocol.
component handshake_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock_tx : in std_ulogic; -- Transmitting domain clock
Reset_tx : in std_ulogic;
Clock_rx : in std_ulogic; -- Receiving domain clock
Reset_rx : in std_ulogic;
Tx_data : in std_ulogic_vector; -- Data to send
Send_data : in std_ulogic; -- Control signal to send new data
Sending : out std_ulogic; -- Active while TX is in process
Data_sent : out std_ulogic; -- Flag to indicate TX completion
Rx_data : out std_ulogic_vector; -- Data received in clock_rx domain
New_data : out std_ulogic -- Flag to indicate new data
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
--## A basic synchronizer with a configurable number of stages
entity bit_synchronizer is
generic (
STAGES : natural := 2; -- number of flip-flops in the synchronizer
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Bit_in : in std_ulogic; -- Unsynchronized signal
Sync : out std_ulogic -- Synchronized to Clock's domain
);
end entity;
architecture rtl of bit_synchronizer is
signal sr : std_ulogic_vector(1 to STAGES);
begin
reg: process(Clock, Reset) is
begin
if Reset = RESET_ACTIVE_LEVEL then
sr <= (others => '0');
elsif rising_edge(Clock) then
sr <= to_X01(Bit_in) & sr(1 to sr'right-1);
end if;
end process;
Sync <= sr(sr'right);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
--## Synchronizer for generating a synchronized reset
entity reset_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock : in std_ulogic;
Reset : in std_ulogic; -- Asynchronous reset
Sync_reset : out std_ulogic -- Synchronized reset
);
end entity;
architecture rtl of reset_synchronizer is
signal sr : std_ulogic_vector(1 to STAGES);
begin
reg: process(Clock, Reset) is
begin
if Reset = RESET_ACTIVE_LEVEL then
sr <= (others => RESET_ACTIVE_LEVEL);
elsif rising_edge(Clock) then
sr <= (not RESET_ACTIVE_LEVEL) & sr(1 to sr'right-1);
end if;
end process;
Sync_reset <= sr(sr'right);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.synchronizing.bit_synchronizer;
--## A handshaking synchronizer for sending an array between clock domains
--# This uses the four-phase handshake protocol.
entity handshake_synchronizer is
generic (
STAGES : natural := 2;
RESET_ACTIVE_LEVEL : std_ulogic := '1'
);
port (
Clock_tx : in std_ulogic; -- Transmitting domain clock
Reset_tx : in std_ulogic;
Clock_rx : in std_ulogic; -- Receiving domain clock
Reset_rx : in std_ulogic;
Tx_data : in std_ulogic_vector; -- Data to send
Send_data : in std_ulogic; -- Control signal to send new data
Sending : out std_ulogic; -- Active while TX is in process
Data_sent : out std_ulogic; -- Flag to indicate TX completion
Rx_data : out std_ulogic_vector; -- Data received in clock_rx domain
New_data : out std_ulogic -- Flag to indicate new data
);
end entity;
architecture rtl of handshake_synchronizer is
signal ack_rx, ack_tx : std_ulogic;
signal prev_ack : std_ulogic;
signal tx_reg_en : std_ulogic;
signal tx_data_reg : std_ulogic_vector(Tx_data'range);
signal req_tx, req_rx : std_ulogic;
signal prev_req : std_ulogic;
begin
-----------
-- TX logic
-----------
as: bit_synchronizer
generic map (
STAGES => STAGES,
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Clock_tx,
Reset => Reset_tx,
Bit_in => ack_rx,
Sync => ack_tx
);
ack_change: process(Clock_tx, Reset_tx) is
begin
if Reset_tx = RESET_ACTIVE_LEVEL then
prev_ack <= '0';
elsif rising_edge(Clock_tx) then
prev_ack <= ack_tx;
end if;
end process;
Data_sent <= '1' when ack_tx = '0' and prev_ack = '1' else '0';
fsm: block
type states is (IDLE, SEND, FINISH);
signal cur_state : states;
begin
process(Clock_tx, Reset_tx) is
variable next_state : states;
begin
if Reset_tx = RESET_ACTIVE_LEVEL then
cur_state <= IDLE;
tx_reg_en <= '0';
req_tx <= '0';
Sending <= '0';
elsif rising_edge(Clock_tx) then
next_state := cur_state;
tx_reg_en <= '0';
case cur_state is
when IDLE =>
if Send_data = '1' then
next_state := SEND;
tx_reg_en <= '1';
end if;
when SEND => -- Wait for Rx side to assert ack
if ack_tx = '1' then
next_state := FINISH;
end if;
when FINISH => -- Wait for Rx side to deassert ack
if ack_tx = '0' then
next_state := IDLE;
end if;
when others =>
next_state := IDLE;
end case;
cur_state <= next_state;
req_tx <= '0';
Sending <= '0';
case next_state is
when IDLE =>
null;
when SEND =>
req_tx <= '1';
Sending <= '1';
when FINISH =>
Sending <= '1';
when others =>
null;
end case;
end if;
end process;
end block;
tx_reg: process(Clock_tx, Reset_tx) is
begin
if Reset_tx = RESET_ACTIVE_LEVEL then
tx_data_reg <= (others => '0');
elsif rising_edge(Clock_tx) then
if tx_reg_en = '1' then
tx_data_reg <= Tx_data;
end if;
end if;
end process;
-----------
-- RX logic
-----------
rs: bit_synchronizer
generic map (
STAGES => STAGES,
RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
)
port map (
Clock => Clock_rx,
Reset => Reset_rx,
Bit_in => req_tx,
Sync => req_rx
);
ack_rx <= req_rx;
req_change: process(Clock_rx, Reset_rx) is
begin
if Reset_rx = RESET_ACTIVE_LEVEL then
prev_req <= '0';
Rx_data <= (Rx_data'range => '0');
New_data <= '0';
elsif rising_edge(Clock_rx) then
prev_req <= req_rx;
New_data <= '0';
if req_rx = '1' and prev_req = '0' then -- Capture data
Rx_data <= tx_data_reg;
New_data <= '1';
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_register is
generic(
C_NUM_REGISTERS : integer := 8 ;
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
C_LINEBUFFER_THRESH : integer range 1 to 65536 := 1 ;
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ; -- CR591965
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
frame_sync : in std_logic ; --
fsync_mask : in std_logic ; -- CR 578591
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqdelay_wren : out std_logic ; --
irqthresh_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; --
--
-- Error Control --
fsize_mismatch_err : in std_logic ; --
lsize_mismatch_err : in std_logic ; --
lsize_more_mismatch_err : in std_logic ; --
s2mm_fsize_more_or_sof_late : in std_logic ; --
dma_interr_set_minus_frame_errors : in std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_err_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
frmstr_err_addr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
update_frmstore : in std_logic ; --
new_frmstr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
frm_store : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
dma_irq_mask : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
reg_index : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
num_frame_store_regmux : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
num_frame_store : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
linebuf_threshold : out std_logic_vector --
(THRESH_MSB_BIT downto 0); --
--
introut : out std_logic --
);
end axi_vdma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
constant FRAME_STORE_INDEX : integer := 6; -- Frame Store Reg index
constant THRESHOLD_INDEX : integer := 7; -- Threshold Reg index
constant REG_IND : integer := 5; -- Reg index
constant DMA_IRQ_MASK_IND : integer := 3; --
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal reg_index_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dma_irq_mask_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal num_frame_store_regmux_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal num_frame_store_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal linebuf_threshold_i : std_logic_vector
(LINEBUFFER_THRESH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal err : std_logic := '0';
signal err_p : std_logic := '0';
signal fsize_err : std_logic := '0';
signal lsize_err : std_logic := '0';
signal lsize_more_err : std_logic := '0';
signal s2mm_fsize_more_or_sof_late_bit : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_interr_minus_frame_errors : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal err_d1 : std_logic := '0';
signal err_re : std_logic := '0';
--signal err_fe : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_err : std_logic := '0';
signal err_pointer_set : std_logic := '0';
signal err_frmstore_set : std_logic := '0';
-- Interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- Soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal reset_counts : std_logic := '0';
signal irqdelay_wren_i : std_logic := '0';
signal irqthresh_wren_i : std_logic := '0';
-- Frame Store support signal
signal frmstore_is_zero : std_logic := '0';
signal frm_store_i : std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0') ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frm_store <= frm_store_i ;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i ;
dma_irq_mask <= dma_irq_mask_i ;
reg_index <= reg_index_i ;
taildesc_msb <= taildesc_msb_i ;
num_frame_store <= num_frame_store_i;
num_frame_store_regmux <= num_frame_store_regmux_i;
linebuf_threshold <= linebuf_threshold_i;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DISABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqdelay_wren <= '0';
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
end generate DISABLE_DMACR_DELAY_CNTR;
ENABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
DMACR_DELAY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- Delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqdelay_wren_i <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren_i <= '1';
else
irqdelay_wren_i <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-- Reset delay irq counter on new delay write, or reset, or frame sync
irqdelay_wren <= irqdelay_wren_i or reset_counts or frame_sync;
end generate ENABLE_DMACR_DELAY_CNTR;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
DISABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqthresh_wren <= '0';
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
end generate DISABLE_DMACR_FRM_CNTR;
ENABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqthresh_wren_i <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
-- If paused then hold frame counter from counting
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren_i <= '1';
else
irqthresh_wren_i <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
irqthresh_wren <= irqthresh_wren_i or reset_counts;
end generate ENABLE_DMACR_FRM_CNTR;
-- Due to seperate MM2S and S2MM resets the delay and frame count registers
-- is axi_sg must be reset with a physical write to axi_sg during a soft reset.
REG_RESET_IRQ_COUNTS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
reset_counts <= '0';
elsif(prmry_resetn = '0' and dmacr_i(DMACR_RESET_BIT) = '1')then
reset_counts <= '1';
end if;
end if;
end process REG_RESET_IRQ_COUNTS;
-----------------------------------------------------------------------------------
------ DMACR - Remainder of DMA Control Register
-----------------------------------------------------------------------------------
GEN_NO_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 0 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_NO_INTERNAL_GENLOCK;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register
-------------------------------------------------------------------------------
GEN_FOR_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 1 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_FOR_INTERNAL_GENLOCK;
----M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
----begin
----M_DMACR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= (others => '0');
----
---- elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT) -- bit 15
---- & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
---- & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
---- & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
---- & ZERO_VALUE(DMACR_PNTR_NUM_MSB
---- downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
---- & '0' -- bit 7
---- & axi2ip_wrdata(DMACR_FSYNCSEL_MSB
---- downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
---- & axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
---- end if;
---- end if;
---- end process M_DMACR_REGISTER;
----end generate M_GEN_DMACR_REGISTER;
M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
begin
M_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& ZERO_VALUE(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& '0' -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process M_DMACR_REGISTER;
end generate M_GEN_DMACR_REGISTER;
-------------------------------------------------------------------------------
-- DMACR - GenLock Sync Enable Bit (CR577698)
-------------------------------------------------------------------------------
-- Dynamic Genlock Slave mode therefore instantiate a register for sync enable.
DS_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DS_DMACR_SYNCEN;
end generate DS_GEN_SYNCEN_BIT;
-- Dynamic Genlock Master mode therefore instantiate a register for sync enable.
DM_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; --CR 713581
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process DM_DMACR_SYNCEN;
end generate DM_GEN_SYNCEN_BIT;
-- Genlock Slave mode therefore instantiate a register for sync enable.
GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 1 generate
begin
DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DMACR_SYNCEN;
end generate GEN_SYNCEN_BIT;
-- Genlock Master mode therefore make DMACR.SyncEn bit RO and set to zero
GEN_NOSYNCEN_BIT : if C_GENLOCK_MODE = 0 generate
begin
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
M_DMACR_REPEAT_EN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; -- CR 713581
-- If DMACR Write then pass axi lite write bus to DMACR bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process M_DMACR_REPEAT_EN;
end generate GEN_NOSYNCEN_BIT;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Circular Buffere/ Park Enable
-------------------------------------------------------------------------------
DMACR_TAILPTREN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_CRCLPRK_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC tailptr en bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_CRCLPRK_BIT) <= axi2ip_wrdata(DMACR_CRCLPRK_BIT);
end if;
end if;
end process DMACR_TAILPTREN;
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when (stop_dma = '1') -- Stop due to error/rs clear
or (soft_reset_i = '1') -- Soft Reset
or (dmacr_i(DMACR_FRMCNTEN_BIT) = '1' -- Frame Count Enable
and ioc_irq_set = '1') -- and threshold met
else '0';
DMACR_RUNSTOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
DMASR_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
end generate GEN_FOR_SG;
-- CR588712 - Hard code Idle to 0 when Scatter Gather engine not included
GEN_NO_SG : if C_INCLUDE_SG = 0 generate
begin
idle <= '0';
end generate GEN_NO_SG;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
MM2S_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 1 generate
begin
err <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
end generate MM2S_ERR_FOR_IRQ;
S2MM_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 0 generate
begin
err_p <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
err <= dma_interr_minus_frame_errors
or (fsize_err and not dma_irq_mask_i(0))
or (lsize_err and not dma_irq_mask_i(1))
or (s2mm_fsize_more_or_sof_late_bit and not dma_irq_mask_i(2))
or (lsize_more_err and not dma_irq_mask_i(3))
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err_p = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
DMAINTERR_MINUS_FRAME_ERRORS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr_minus_frame_errors <= '0';
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr_minus_frame_errors <= (dma_interr_minus_frame_errors and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set_minus_frame_errors;
elsif(dma_interr_set_minus_frame_errors = '1' )then
dma_interr_minus_frame_errors <= '1';
end if;
end if;
end process DMAINTERR_MINUS_FRAME_ERRORS;
end generate S2MM_ERR_FOR_IRQ;
-- Scatter Gather Error
sg_ftch_err <= ftch_slverr_set or ftch_decerr_set;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
-- If flush on frame sync disable then only reset will clear bit
GEN_FOR_NO_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
----DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
---- DMASR_LSIZE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_err <= '0';
---- elsif(lsize_mismatch_err = '1' )then
---- lsize_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_ERR;
----
---- DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_more_err <= '0';
---- elsif(lsize_more_mismatch_err = '1' )then
---- lsize_more_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_MORE_ERR;
end generate GEN_FOR_NO_FLUSH;
-- Flush on frame sync enabled therefore can clear with a write of '1'
GEN_FOR_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 1 generate
begin
---- DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- -- CPU Writing a '1' to clear - OR'ed with setting to prevent
---- -- missing a 'set' during the write.
---- elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
---- dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
---- or dma_interr_set;
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
fsize_err <= (fsize_err and not(axi2ip_wrdata(DMASR_FSIZEERR_BIT)))
or fsize_mismatch_err;
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
DMASR_FSIZE_MORE_OR_SOF_LATE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s2mm_fsize_more_or_sof_late_bit <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
s2mm_fsize_more_or_sof_late_bit <= (s2mm_fsize_more_or_sof_late_bit and not(axi2ip_wrdata(DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT)))
or s2mm_fsize_more_or_sof_late;
elsif(s2mm_fsize_more_or_sof_late = '1' )then
s2mm_fsize_more_or_sof_late_bit <= '1';
end if;
end if;
end process DMASR_FSIZE_MORE_OR_SOF_LATE_ERR;
end generate GEN_FOR_FLUSH;
DMASR_LSIZE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_err <= (lsize_err and not(axi2ip_wrdata(DMASR_LSIZEERR_BIT)))
or lsize_mismatch_err;
elsif(lsize_mismatch_err = '1' )then
lsize_err <= '1';
end if;
end if;
end process DMASR_LSIZE_ERR;
DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_more_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_more_err <= (lsize_more_err and not(axi2ip_wrdata(DMASR_LSIZE_MORE_ERR_BIT)))
or lsize_more_mismatch_err;
elsif(lsize_more_mismatch_err = '1' )then
lsize_more_err <= '1';
end if;
end if;
end process DMASR_LSIZE_MORE_ERR;
DMASR_DMAINTERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set;
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- Disable delay timer if halted or on delay irq set
dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) or dmasr_i(DMASR_DLYIRQ_BIT)
or fsync_mask; -- CR 578591
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERR_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_d1 <= '0';
else
err_d1 <= err;
end if;
end if;
end process GEN_ERR_RE;
-- Generate rising edge pulse on error
err_re <= err and not err_d1;
--err_fe <= not err and err_d1;
DMASR_ERRIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or err_re;
elsif(err_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& lsize_more_err -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& s2mm_fsize_more_or_sof_late_bit -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& lsize_err -- Bit 8
& fsize_err -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& '0' -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-------------------------------------------------------------------------------
-- Frame Store Pointer Field - Reference of current frame buffer pointer being
-- used.
-------------------------------------------------------------------------------
----FRMSTR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- --if(prmry_resetn = '0' or err_fe = '1')then
---- if(prmry_resetn = '0' )then
---- frm_store <= (others => '0');
---- err_frmstore_set <= '0';
---- -- Detected error has NOT register a desc pointer
---- elsif(err_frmstore_set = '0')then
----
---- -- CR582182 qualified with update_frmstore
---- -- DMA Error Error
---- if(update_frmstore = '1' and err = '1')then
---- frm_store <= frmstr_err_addr;
---- err_frmstore_set <= '1';
----
---- -- CR582182 qualified with update_frmstore
---- -- Commanded to update frame store value - used for indicating
---- -- current frame begin processed by dma controller
---- elsif(update_frmstore = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
---- frm_store <= new_frmstr;
---- err_frmstore_set <= err_frmstore_set;
----
---- end if;
---- end if;
---- end if;
---- end process FRMSTR_REGISTER;
-- If SG engine is included then instantiate sg specific logic
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
reg_index_i <= (others => '0'); -- Not used in SCATTER GATHER mode
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_lsb_i <= (others => '0');
err_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_lsb_i <= ftch_err_addr(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT)-- Curdesc bit 5
& "00000"; -- Reserved bits 4 downto 0
err_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& "00000";
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_msb_i <= ftch_err_addr((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc
((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_SCATTER_GATHER_MODE;
-- If SG engine is not included then instantiate register direct mode
GEN_NO_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Tie off unused scatter gather specific signals
sg_decerr <= '0'; -- Not used in Register Direct Mode
sg_slverr <= '0'; -- Not used in Register Direct Mode
curdesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
curdesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
tailpntr_updated <= '0'; -- Not used in Register Direct Mode
GEN_NO_REG_INDEX_REG : if C_NUM_FSTORES < 17 generate
begin
reg_index_i <= (others => '0'); -- Not used if C_NUM_FSTORE =< 16
end generate GEN_NO_REG_INDEX_REG;
GEN_REG_INDEX_REG : if C_NUM_FSTORES > 16 generate
begin
---------------------------------------------------------------------------
-- Reg Index
---------------------------------------------------------------------------
reg_index : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_index_i <= (others => '0');
elsif(axi2ip_wrce(REG_IND) = '1')then
reg_index_i(0) <= axi2ip_wrdata(0);
end if;
end if;
end process reg_index;
end generate GEN_REG_INDEX_REG;
end generate GEN_NO_SCATTER_GATHER_MODE;
---------------------------------------------------------------------------
-- Number of Frame Stores
---------------------------------------------------------------------------
ENABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
NUM_FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
elsif(axi2ip_wrce(FRAME_STORE_INDEX) = '1')then
-- If value is 0 then set frame store to 1
if(frmstore_is_zero='1')then
num_frame_store_i <= ONE_FRAMESTORE;
else
num_frame_store_i <= axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT);
end if;
end if;
end if;
end process NUM_FRMSTR_REGISTER;
frmstore_is_zero <= '1' when axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT) = ZERO_FRAMESTORE
else '0';
num_frame_store_regmux_i <= num_frame_store_i;
end generate ENABLE_NUM_FRMSTR_REGISTER;
DISABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
num_frame_store_regmux_i <= (others => '0');
end generate DISABLE_NUM_FRMSTR_REGISTER;
---------------------------------------------------------------------------
-- Line Buffer Threshold
---------------------------------------------------------------------------
ENABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
LB_THRESH_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
linebuf_threshold_i <= std_logic_vector(to_unsigned(C_LINEBUFFER_THRESH,LINEBUFFER_THRESH_WIDTH));
elsif(axi2ip_wrce(THRESHOLD_INDEX) = '1')then
linebuf_threshold_i <= axi2ip_wrdata(THRESH_MSB_BIT
downto THRESH_LSB_BIT);
end if;
end if;
end process LB_THRESH_REGISTER;
end generate ENABLE_LB_THRESH_REGISTER;
DISABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
linebuf_threshold_i <= (others => '0');
end generate DISABLE_LB_THRESH_REGISTER;
DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 0 generate
begin
---------------------------------------------------------------------------
-- S2MM DMA IRQ MASK
---------------------------------------------------------------------------
dma_irq_mask : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_irq_mask_i <= (others => '0');
elsif(axi2ip_wrce(DMA_IRQ_MASK_IND) = '1')then
dma_irq_mask_i(3 downto 0) <= axi2ip_wrdata(3 downto 0);
end if;
end if;
end process dma_irq_mask;
end generate DMA_IRQ_MASK_GEN;
NO_DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 1 generate
begin
dma_irq_mask_i <= (others => '0');
end generate NO_DMA_IRQ_MASK_GEN;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_register is
generic(
C_NUM_REGISTERS : integer := 8 ;
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
C_LINEBUFFER_THRESH : integer range 1 to 65536 := 1 ;
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ; -- CR591965
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
frame_sync : in std_logic ; --
fsync_mask : in std_logic ; -- CR 578591
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqdelay_wren : out std_logic ; --
irqthresh_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; --
--
-- Error Control --
fsize_mismatch_err : in std_logic ; --
lsize_mismatch_err : in std_logic ; --
lsize_more_mismatch_err : in std_logic ; --
s2mm_fsize_more_or_sof_late : in std_logic ; --
dma_interr_set_minus_frame_errors : in std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_err_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
frmstr_err_addr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
update_frmstore : in std_logic ; --
new_frmstr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
frm_store : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
dma_irq_mask : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
reg_index : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
num_frame_store_regmux : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
num_frame_store : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
linebuf_threshold : out std_logic_vector --
(THRESH_MSB_BIT downto 0); --
--
introut : out std_logic --
);
end axi_vdma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
constant FRAME_STORE_INDEX : integer := 6; -- Frame Store Reg index
constant THRESHOLD_INDEX : integer := 7; -- Threshold Reg index
constant REG_IND : integer := 5; -- Reg index
constant DMA_IRQ_MASK_IND : integer := 3; --
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal reg_index_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dma_irq_mask_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal num_frame_store_regmux_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal num_frame_store_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal linebuf_threshold_i : std_logic_vector
(LINEBUFFER_THRESH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal err : std_logic := '0';
signal err_p : std_logic := '0';
signal fsize_err : std_logic := '0';
signal lsize_err : std_logic := '0';
signal lsize_more_err : std_logic := '0';
signal s2mm_fsize_more_or_sof_late_bit : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_interr_minus_frame_errors : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal err_d1 : std_logic := '0';
signal err_re : std_logic := '0';
--signal err_fe : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_err : std_logic := '0';
signal err_pointer_set : std_logic := '0';
signal err_frmstore_set : std_logic := '0';
-- Interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- Soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal reset_counts : std_logic := '0';
signal irqdelay_wren_i : std_logic := '0';
signal irqthresh_wren_i : std_logic := '0';
-- Frame Store support signal
signal frmstore_is_zero : std_logic := '0';
signal frm_store_i : std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0') ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frm_store <= frm_store_i ;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i ;
dma_irq_mask <= dma_irq_mask_i ;
reg_index <= reg_index_i ;
taildesc_msb <= taildesc_msb_i ;
num_frame_store <= num_frame_store_i;
num_frame_store_regmux <= num_frame_store_regmux_i;
linebuf_threshold <= linebuf_threshold_i;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DISABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqdelay_wren <= '0';
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
end generate DISABLE_DMACR_DELAY_CNTR;
ENABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
DMACR_DELAY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- Delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqdelay_wren_i <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren_i <= '1';
else
irqdelay_wren_i <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-- Reset delay irq counter on new delay write, or reset, or frame sync
irqdelay_wren <= irqdelay_wren_i or reset_counts or frame_sync;
end generate ENABLE_DMACR_DELAY_CNTR;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
DISABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqthresh_wren <= '0';
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
end generate DISABLE_DMACR_FRM_CNTR;
ENABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqthresh_wren_i <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
-- If paused then hold frame counter from counting
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren_i <= '1';
else
irqthresh_wren_i <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
irqthresh_wren <= irqthresh_wren_i or reset_counts;
end generate ENABLE_DMACR_FRM_CNTR;
-- Due to seperate MM2S and S2MM resets the delay and frame count registers
-- is axi_sg must be reset with a physical write to axi_sg during a soft reset.
REG_RESET_IRQ_COUNTS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
reset_counts <= '0';
elsif(prmry_resetn = '0' and dmacr_i(DMACR_RESET_BIT) = '1')then
reset_counts <= '1';
end if;
end if;
end process REG_RESET_IRQ_COUNTS;
-----------------------------------------------------------------------------------
------ DMACR - Remainder of DMA Control Register
-----------------------------------------------------------------------------------
GEN_NO_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 0 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_NO_INTERNAL_GENLOCK;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register
-------------------------------------------------------------------------------
GEN_FOR_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 1 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_FOR_INTERNAL_GENLOCK;
----M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
----begin
----M_DMACR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= (others => '0');
----
---- elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT) -- bit 15
---- & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
---- & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
---- & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
---- & ZERO_VALUE(DMACR_PNTR_NUM_MSB
---- downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
---- & '0' -- bit 7
---- & axi2ip_wrdata(DMACR_FSYNCSEL_MSB
---- downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
---- & axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
---- end if;
---- end if;
---- end process M_DMACR_REGISTER;
----end generate M_GEN_DMACR_REGISTER;
M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
begin
M_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& ZERO_VALUE(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& '0' -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process M_DMACR_REGISTER;
end generate M_GEN_DMACR_REGISTER;
-------------------------------------------------------------------------------
-- DMACR - GenLock Sync Enable Bit (CR577698)
-------------------------------------------------------------------------------
-- Dynamic Genlock Slave mode therefore instantiate a register for sync enable.
DS_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DS_DMACR_SYNCEN;
end generate DS_GEN_SYNCEN_BIT;
-- Dynamic Genlock Master mode therefore instantiate a register for sync enable.
DM_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; --CR 713581
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process DM_DMACR_SYNCEN;
end generate DM_GEN_SYNCEN_BIT;
-- Genlock Slave mode therefore instantiate a register for sync enable.
GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 1 generate
begin
DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DMACR_SYNCEN;
end generate GEN_SYNCEN_BIT;
-- Genlock Master mode therefore make DMACR.SyncEn bit RO and set to zero
GEN_NOSYNCEN_BIT : if C_GENLOCK_MODE = 0 generate
begin
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
M_DMACR_REPEAT_EN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; -- CR 713581
-- If DMACR Write then pass axi lite write bus to DMACR bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process M_DMACR_REPEAT_EN;
end generate GEN_NOSYNCEN_BIT;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Circular Buffere/ Park Enable
-------------------------------------------------------------------------------
DMACR_TAILPTREN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_CRCLPRK_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC tailptr en bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_CRCLPRK_BIT) <= axi2ip_wrdata(DMACR_CRCLPRK_BIT);
end if;
end if;
end process DMACR_TAILPTREN;
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when (stop_dma = '1') -- Stop due to error/rs clear
or (soft_reset_i = '1') -- Soft Reset
or (dmacr_i(DMACR_FRMCNTEN_BIT) = '1' -- Frame Count Enable
and ioc_irq_set = '1') -- and threshold met
else '0';
DMACR_RUNSTOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
DMASR_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
end generate GEN_FOR_SG;
-- CR588712 - Hard code Idle to 0 when Scatter Gather engine not included
GEN_NO_SG : if C_INCLUDE_SG = 0 generate
begin
idle <= '0';
end generate GEN_NO_SG;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
MM2S_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 1 generate
begin
err <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
end generate MM2S_ERR_FOR_IRQ;
S2MM_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 0 generate
begin
err_p <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
err <= dma_interr_minus_frame_errors
or (fsize_err and not dma_irq_mask_i(0))
or (lsize_err and not dma_irq_mask_i(1))
or (s2mm_fsize_more_or_sof_late_bit and not dma_irq_mask_i(2))
or (lsize_more_err and not dma_irq_mask_i(3))
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err_p = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
DMAINTERR_MINUS_FRAME_ERRORS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr_minus_frame_errors <= '0';
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr_minus_frame_errors <= (dma_interr_minus_frame_errors and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set_minus_frame_errors;
elsif(dma_interr_set_minus_frame_errors = '1' )then
dma_interr_minus_frame_errors <= '1';
end if;
end if;
end process DMAINTERR_MINUS_FRAME_ERRORS;
end generate S2MM_ERR_FOR_IRQ;
-- Scatter Gather Error
sg_ftch_err <= ftch_slverr_set or ftch_decerr_set;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
-- If flush on frame sync disable then only reset will clear bit
GEN_FOR_NO_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
----DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
---- DMASR_LSIZE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_err <= '0';
---- elsif(lsize_mismatch_err = '1' )then
---- lsize_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_ERR;
----
---- DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_more_err <= '0';
---- elsif(lsize_more_mismatch_err = '1' )then
---- lsize_more_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_MORE_ERR;
end generate GEN_FOR_NO_FLUSH;
-- Flush on frame sync enabled therefore can clear with a write of '1'
GEN_FOR_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 1 generate
begin
---- DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- -- CPU Writing a '1' to clear - OR'ed with setting to prevent
---- -- missing a 'set' during the write.
---- elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
---- dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
---- or dma_interr_set;
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
fsize_err <= (fsize_err and not(axi2ip_wrdata(DMASR_FSIZEERR_BIT)))
or fsize_mismatch_err;
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
DMASR_FSIZE_MORE_OR_SOF_LATE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s2mm_fsize_more_or_sof_late_bit <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
s2mm_fsize_more_or_sof_late_bit <= (s2mm_fsize_more_or_sof_late_bit and not(axi2ip_wrdata(DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT)))
or s2mm_fsize_more_or_sof_late;
elsif(s2mm_fsize_more_or_sof_late = '1' )then
s2mm_fsize_more_or_sof_late_bit <= '1';
end if;
end if;
end process DMASR_FSIZE_MORE_OR_SOF_LATE_ERR;
end generate GEN_FOR_FLUSH;
DMASR_LSIZE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_err <= (lsize_err and not(axi2ip_wrdata(DMASR_LSIZEERR_BIT)))
or lsize_mismatch_err;
elsif(lsize_mismatch_err = '1' )then
lsize_err <= '1';
end if;
end if;
end process DMASR_LSIZE_ERR;
DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_more_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_more_err <= (lsize_more_err and not(axi2ip_wrdata(DMASR_LSIZE_MORE_ERR_BIT)))
or lsize_more_mismatch_err;
elsif(lsize_more_mismatch_err = '1' )then
lsize_more_err <= '1';
end if;
end if;
end process DMASR_LSIZE_MORE_ERR;
DMASR_DMAINTERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set;
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- Disable delay timer if halted or on delay irq set
dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) or dmasr_i(DMASR_DLYIRQ_BIT)
or fsync_mask; -- CR 578591
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERR_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_d1 <= '0';
else
err_d1 <= err;
end if;
end if;
end process GEN_ERR_RE;
-- Generate rising edge pulse on error
err_re <= err and not err_d1;
--err_fe <= not err and err_d1;
DMASR_ERRIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or err_re;
elsif(err_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& lsize_more_err -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& s2mm_fsize_more_or_sof_late_bit -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& lsize_err -- Bit 8
& fsize_err -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& '0' -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-------------------------------------------------------------------------------
-- Frame Store Pointer Field - Reference of current frame buffer pointer being
-- used.
-------------------------------------------------------------------------------
----FRMSTR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- --if(prmry_resetn = '0' or err_fe = '1')then
---- if(prmry_resetn = '0' )then
---- frm_store <= (others => '0');
---- err_frmstore_set <= '0';
---- -- Detected error has NOT register a desc pointer
---- elsif(err_frmstore_set = '0')then
----
---- -- CR582182 qualified with update_frmstore
---- -- DMA Error Error
---- if(update_frmstore = '1' and err = '1')then
---- frm_store <= frmstr_err_addr;
---- err_frmstore_set <= '1';
----
---- -- CR582182 qualified with update_frmstore
---- -- Commanded to update frame store value - used for indicating
---- -- current frame begin processed by dma controller
---- elsif(update_frmstore = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
---- frm_store <= new_frmstr;
---- err_frmstore_set <= err_frmstore_set;
----
---- end if;
---- end if;
---- end if;
---- end process FRMSTR_REGISTER;
-- If SG engine is included then instantiate sg specific logic
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
reg_index_i <= (others => '0'); -- Not used in SCATTER GATHER mode
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_lsb_i <= (others => '0');
err_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_lsb_i <= ftch_err_addr(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT)-- Curdesc bit 5
& "00000"; -- Reserved bits 4 downto 0
err_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& "00000";
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_msb_i <= ftch_err_addr((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc
((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_SCATTER_GATHER_MODE;
-- If SG engine is not included then instantiate register direct mode
GEN_NO_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Tie off unused scatter gather specific signals
sg_decerr <= '0'; -- Not used in Register Direct Mode
sg_slverr <= '0'; -- Not used in Register Direct Mode
curdesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
curdesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
tailpntr_updated <= '0'; -- Not used in Register Direct Mode
GEN_NO_REG_INDEX_REG : if C_NUM_FSTORES < 17 generate
begin
reg_index_i <= (others => '0'); -- Not used if C_NUM_FSTORE =< 16
end generate GEN_NO_REG_INDEX_REG;
GEN_REG_INDEX_REG : if C_NUM_FSTORES > 16 generate
begin
---------------------------------------------------------------------------
-- Reg Index
---------------------------------------------------------------------------
reg_index : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_index_i <= (others => '0');
elsif(axi2ip_wrce(REG_IND) = '1')then
reg_index_i(0) <= axi2ip_wrdata(0);
end if;
end if;
end process reg_index;
end generate GEN_REG_INDEX_REG;
end generate GEN_NO_SCATTER_GATHER_MODE;
---------------------------------------------------------------------------
-- Number of Frame Stores
---------------------------------------------------------------------------
ENABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
NUM_FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
elsif(axi2ip_wrce(FRAME_STORE_INDEX) = '1')then
-- If value is 0 then set frame store to 1
if(frmstore_is_zero='1')then
num_frame_store_i <= ONE_FRAMESTORE;
else
num_frame_store_i <= axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT);
end if;
end if;
end if;
end process NUM_FRMSTR_REGISTER;
frmstore_is_zero <= '1' when axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT) = ZERO_FRAMESTORE
else '0';
num_frame_store_regmux_i <= num_frame_store_i;
end generate ENABLE_NUM_FRMSTR_REGISTER;
DISABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
num_frame_store_regmux_i <= (others => '0');
end generate DISABLE_NUM_FRMSTR_REGISTER;
---------------------------------------------------------------------------
-- Line Buffer Threshold
---------------------------------------------------------------------------
ENABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
LB_THRESH_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
linebuf_threshold_i <= std_logic_vector(to_unsigned(C_LINEBUFFER_THRESH,LINEBUFFER_THRESH_WIDTH));
elsif(axi2ip_wrce(THRESHOLD_INDEX) = '1')then
linebuf_threshold_i <= axi2ip_wrdata(THRESH_MSB_BIT
downto THRESH_LSB_BIT);
end if;
end if;
end process LB_THRESH_REGISTER;
end generate ENABLE_LB_THRESH_REGISTER;
DISABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
linebuf_threshold_i <= (others => '0');
end generate DISABLE_LB_THRESH_REGISTER;
DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 0 generate
begin
---------------------------------------------------------------------------
-- S2MM DMA IRQ MASK
---------------------------------------------------------------------------
dma_irq_mask : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_irq_mask_i <= (others => '0');
elsif(axi2ip_wrce(DMA_IRQ_MASK_IND) = '1')then
dma_irq_mask_i(3 downto 0) <= axi2ip_wrdata(3 downto 0);
end if;
end if;
end process dma_irq_mask;
end generate DMA_IRQ_MASK_GEN;
NO_DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 1 generate
begin
dma_irq_mask_i <= (others => '0');
end generate NO_DMA_IRQ_MASK_GEN;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_register is
generic(
C_NUM_REGISTERS : integer := 8 ;
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
C_LINEBUFFER_THRESH : integer range 1 to 65536 := 1 ;
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ; -- CR591965
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
frame_sync : in std_logic ; --
fsync_mask : in std_logic ; -- CR 578591
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqdelay_wren : out std_logic ; --
irqthresh_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; --
--
-- Error Control --
fsize_mismatch_err : in std_logic ; --
lsize_mismatch_err : in std_logic ; --
lsize_more_mismatch_err : in std_logic ; --
s2mm_fsize_more_or_sof_late : in std_logic ; --
dma_interr_set_minus_frame_errors : in std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_err_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
frmstr_err_addr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
update_frmstore : in std_logic ; --
new_frmstr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
frm_store : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
dma_irq_mask : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
reg_index : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
num_frame_store_regmux : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
num_frame_store : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
linebuf_threshold : out std_logic_vector --
(THRESH_MSB_BIT downto 0); --
--
introut : out std_logic --
);
end axi_vdma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
constant FRAME_STORE_INDEX : integer := 6; -- Frame Store Reg index
constant THRESHOLD_INDEX : integer := 7; -- Threshold Reg index
constant REG_IND : integer := 5; -- Reg index
constant DMA_IRQ_MASK_IND : integer := 3; --
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal reg_index_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dma_irq_mask_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal num_frame_store_regmux_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal num_frame_store_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal linebuf_threshold_i : std_logic_vector
(LINEBUFFER_THRESH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal err : std_logic := '0';
signal err_p : std_logic := '0';
signal fsize_err : std_logic := '0';
signal lsize_err : std_logic := '0';
signal lsize_more_err : std_logic := '0';
signal s2mm_fsize_more_or_sof_late_bit : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_interr_minus_frame_errors : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal err_d1 : std_logic := '0';
signal err_re : std_logic := '0';
--signal err_fe : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_err : std_logic := '0';
signal err_pointer_set : std_logic := '0';
signal err_frmstore_set : std_logic := '0';
-- Interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- Soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal reset_counts : std_logic := '0';
signal irqdelay_wren_i : std_logic := '0';
signal irqthresh_wren_i : std_logic := '0';
-- Frame Store support signal
signal frmstore_is_zero : std_logic := '0';
signal frm_store_i : std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0') ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frm_store <= frm_store_i ;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i ;
dma_irq_mask <= dma_irq_mask_i ;
reg_index <= reg_index_i ;
taildesc_msb <= taildesc_msb_i ;
num_frame_store <= num_frame_store_i;
num_frame_store_regmux <= num_frame_store_regmux_i;
linebuf_threshold <= linebuf_threshold_i;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DISABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqdelay_wren <= '0';
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
end generate DISABLE_DMACR_DELAY_CNTR;
ENABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
DMACR_DELAY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- Delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqdelay_wren_i <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren_i <= '1';
else
irqdelay_wren_i <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-- Reset delay irq counter on new delay write, or reset, or frame sync
irqdelay_wren <= irqdelay_wren_i or reset_counts or frame_sync;
end generate ENABLE_DMACR_DELAY_CNTR;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
DISABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqthresh_wren <= '0';
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
end generate DISABLE_DMACR_FRM_CNTR;
ENABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqthresh_wren_i <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
-- If paused then hold frame counter from counting
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren_i <= '1';
else
irqthresh_wren_i <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
irqthresh_wren <= irqthresh_wren_i or reset_counts;
end generate ENABLE_DMACR_FRM_CNTR;
-- Due to seperate MM2S and S2MM resets the delay and frame count registers
-- is axi_sg must be reset with a physical write to axi_sg during a soft reset.
REG_RESET_IRQ_COUNTS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
reset_counts <= '0';
elsif(prmry_resetn = '0' and dmacr_i(DMACR_RESET_BIT) = '1')then
reset_counts <= '1';
end if;
end if;
end process REG_RESET_IRQ_COUNTS;
-----------------------------------------------------------------------------------
------ DMACR - Remainder of DMA Control Register
-----------------------------------------------------------------------------------
GEN_NO_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 0 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_NO_INTERNAL_GENLOCK;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register
-------------------------------------------------------------------------------
GEN_FOR_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 1 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_FOR_INTERNAL_GENLOCK;
----M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
----begin
----M_DMACR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= (others => '0');
----
---- elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT) -- bit 15
---- & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
---- & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
---- & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
---- & ZERO_VALUE(DMACR_PNTR_NUM_MSB
---- downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
---- & '0' -- bit 7
---- & axi2ip_wrdata(DMACR_FSYNCSEL_MSB
---- downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
---- & axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
---- end if;
---- end if;
---- end process M_DMACR_REGISTER;
----end generate M_GEN_DMACR_REGISTER;
M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
begin
M_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& ZERO_VALUE(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& '0' -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process M_DMACR_REGISTER;
end generate M_GEN_DMACR_REGISTER;
-------------------------------------------------------------------------------
-- DMACR - GenLock Sync Enable Bit (CR577698)
-------------------------------------------------------------------------------
-- Dynamic Genlock Slave mode therefore instantiate a register for sync enable.
DS_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DS_DMACR_SYNCEN;
end generate DS_GEN_SYNCEN_BIT;
-- Dynamic Genlock Master mode therefore instantiate a register for sync enable.
DM_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; --CR 713581
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process DM_DMACR_SYNCEN;
end generate DM_GEN_SYNCEN_BIT;
-- Genlock Slave mode therefore instantiate a register for sync enable.
GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 1 generate
begin
DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DMACR_SYNCEN;
end generate GEN_SYNCEN_BIT;
-- Genlock Master mode therefore make DMACR.SyncEn bit RO and set to zero
GEN_NOSYNCEN_BIT : if C_GENLOCK_MODE = 0 generate
begin
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
M_DMACR_REPEAT_EN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; -- CR 713581
-- If DMACR Write then pass axi lite write bus to DMACR bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process M_DMACR_REPEAT_EN;
end generate GEN_NOSYNCEN_BIT;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Circular Buffere/ Park Enable
-------------------------------------------------------------------------------
DMACR_TAILPTREN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_CRCLPRK_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC tailptr en bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_CRCLPRK_BIT) <= axi2ip_wrdata(DMACR_CRCLPRK_BIT);
end if;
end if;
end process DMACR_TAILPTREN;
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when (stop_dma = '1') -- Stop due to error/rs clear
or (soft_reset_i = '1') -- Soft Reset
or (dmacr_i(DMACR_FRMCNTEN_BIT) = '1' -- Frame Count Enable
and ioc_irq_set = '1') -- and threshold met
else '0';
DMACR_RUNSTOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
DMASR_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
end generate GEN_FOR_SG;
-- CR588712 - Hard code Idle to 0 when Scatter Gather engine not included
GEN_NO_SG : if C_INCLUDE_SG = 0 generate
begin
idle <= '0';
end generate GEN_NO_SG;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
MM2S_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 1 generate
begin
err <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
end generate MM2S_ERR_FOR_IRQ;
S2MM_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 0 generate
begin
err_p <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
err <= dma_interr_minus_frame_errors
or (fsize_err and not dma_irq_mask_i(0))
or (lsize_err and not dma_irq_mask_i(1))
or (s2mm_fsize_more_or_sof_late_bit and not dma_irq_mask_i(2))
or (lsize_more_err and not dma_irq_mask_i(3))
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err_p = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
DMAINTERR_MINUS_FRAME_ERRORS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr_minus_frame_errors <= '0';
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr_minus_frame_errors <= (dma_interr_minus_frame_errors and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set_minus_frame_errors;
elsif(dma_interr_set_minus_frame_errors = '1' )then
dma_interr_minus_frame_errors <= '1';
end if;
end if;
end process DMAINTERR_MINUS_FRAME_ERRORS;
end generate S2MM_ERR_FOR_IRQ;
-- Scatter Gather Error
sg_ftch_err <= ftch_slverr_set or ftch_decerr_set;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
-- If flush on frame sync disable then only reset will clear bit
GEN_FOR_NO_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
----DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
---- DMASR_LSIZE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_err <= '0';
---- elsif(lsize_mismatch_err = '1' )then
---- lsize_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_ERR;
----
---- DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_more_err <= '0';
---- elsif(lsize_more_mismatch_err = '1' )then
---- lsize_more_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_MORE_ERR;
end generate GEN_FOR_NO_FLUSH;
-- Flush on frame sync enabled therefore can clear with a write of '1'
GEN_FOR_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 1 generate
begin
---- DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- -- CPU Writing a '1' to clear - OR'ed with setting to prevent
---- -- missing a 'set' during the write.
---- elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
---- dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
---- or dma_interr_set;
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
fsize_err <= (fsize_err and not(axi2ip_wrdata(DMASR_FSIZEERR_BIT)))
or fsize_mismatch_err;
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
DMASR_FSIZE_MORE_OR_SOF_LATE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s2mm_fsize_more_or_sof_late_bit <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
s2mm_fsize_more_or_sof_late_bit <= (s2mm_fsize_more_or_sof_late_bit and not(axi2ip_wrdata(DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT)))
or s2mm_fsize_more_or_sof_late;
elsif(s2mm_fsize_more_or_sof_late = '1' )then
s2mm_fsize_more_or_sof_late_bit <= '1';
end if;
end if;
end process DMASR_FSIZE_MORE_OR_SOF_LATE_ERR;
end generate GEN_FOR_FLUSH;
DMASR_LSIZE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_err <= (lsize_err and not(axi2ip_wrdata(DMASR_LSIZEERR_BIT)))
or lsize_mismatch_err;
elsif(lsize_mismatch_err = '1' )then
lsize_err <= '1';
end if;
end if;
end process DMASR_LSIZE_ERR;
DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_more_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_more_err <= (lsize_more_err and not(axi2ip_wrdata(DMASR_LSIZE_MORE_ERR_BIT)))
or lsize_more_mismatch_err;
elsif(lsize_more_mismatch_err = '1' )then
lsize_more_err <= '1';
end if;
end if;
end process DMASR_LSIZE_MORE_ERR;
DMASR_DMAINTERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set;
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- Disable delay timer if halted or on delay irq set
dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) or dmasr_i(DMASR_DLYIRQ_BIT)
or fsync_mask; -- CR 578591
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERR_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_d1 <= '0';
else
err_d1 <= err;
end if;
end if;
end process GEN_ERR_RE;
-- Generate rising edge pulse on error
err_re <= err and not err_d1;
--err_fe <= not err and err_d1;
DMASR_ERRIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or err_re;
elsif(err_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& lsize_more_err -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& s2mm_fsize_more_or_sof_late_bit -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& lsize_err -- Bit 8
& fsize_err -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& '0' -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-------------------------------------------------------------------------------
-- Frame Store Pointer Field - Reference of current frame buffer pointer being
-- used.
-------------------------------------------------------------------------------
----FRMSTR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- --if(prmry_resetn = '0' or err_fe = '1')then
---- if(prmry_resetn = '0' )then
---- frm_store <= (others => '0');
---- err_frmstore_set <= '0';
---- -- Detected error has NOT register a desc pointer
---- elsif(err_frmstore_set = '0')then
----
---- -- CR582182 qualified with update_frmstore
---- -- DMA Error Error
---- if(update_frmstore = '1' and err = '1')then
---- frm_store <= frmstr_err_addr;
---- err_frmstore_set <= '1';
----
---- -- CR582182 qualified with update_frmstore
---- -- Commanded to update frame store value - used for indicating
---- -- current frame begin processed by dma controller
---- elsif(update_frmstore = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
---- frm_store <= new_frmstr;
---- err_frmstore_set <= err_frmstore_set;
----
---- end if;
---- end if;
---- end if;
---- end process FRMSTR_REGISTER;
-- If SG engine is included then instantiate sg specific logic
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
reg_index_i <= (others => '0'); -- Not used in SCATTER GATHER mode
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_lsb_i <= (others => '0');
err_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_lsb_i <= ftch_err_addr(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT)-- Curdesc bit 5
& "00000"; -- Reserved bits 4 downto 0
err_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& "00000";
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_msb_i <= ftch_err_addr((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc
((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_SCATTER_GATHER_MODE;
-- If SG engine is not included then instantiate register direct mode
GEN_NO_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Tie off unused scatter gather specific signals
sg_decerr <= '0'; -- Not used in Register Direct Mode
sg_slverr <= '0'; -- Not used in Register Direct Mode
curdesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
curdesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
tailpntr_updated <= '0'; -- Not used in Register Direct Mode
GEN_NO_REG_INDEX_REG : if C_NUM_FSTORES < 17 generate
begin
reg_index_i <= (others => '0'); -- Not used if C_NUM_FSTORE =< 16
end generate GEN_NO_REG_INDEX_REG;
GEN_REG_INDEX_REG : if C_NUM_FSTORES > 16 generate
begin
---------------------------------------------------------------------------
-- Reg Index
---------------------------------------------------------------------------
reg_index : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_index_i <= (others => '0');
elsif(axi2ip_wrce(REG_IND) = '1')then
reg_index_i(0) <= axi2ip_wrdata(0);
end if;
end if;
end process reg_index;
end generate GEN_REG_INDEX_REG;
end generate GEN_NO_SCATTER_GATHER_MODE;
---------------------------------------------------------------------------
-- Number of Frame Stores
---------------------------------------------------------------------------
ENABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
NUM_FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
elsif(axi2ip_wrce(FRAME_STORE_INDEX) = '1')then
-- If value is 0 then set frame store to 1
if(frmstore_is_zero='1')then
num_frame_store_i <= ONE_FRAMESTORE;
else
num_frame_store_i <= axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT);
end if;
end if;
end if;
end process NUM_FRMSTR_REGISTER;
frmstore_is_zero <= '1' when axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT) = ZERO_FRAMESTORE
else '0';
num_frame_store_regmux_i <= num_frame_store_i;
end generate ENABLE_NUM_FRMSTR_REGISTER;
DISABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
num_frame_store_regmux_i <= (others => '0');
end generate DISABLE_NUM_FRMSTR_REGISTER;
---------------------------------------------------------------------------
-- Line Buffer Threshold
---------------------------------------------------------------------------
ENABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
LB_THRESH_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
linebuf_threshold_i <= std_logic_vector(to_unsigned(C_LINEBUFFER_THRESH,LINEBUFFER_THRESH_WIDTH));
elsif(axi2ip_wrce(THRESHOLD_INDEX) = '1')then
linebuf_threshold_i <= axi2ip_wrdata(THRESH_MSB_BIT
downto THRESH_LSB_BIT);
end if;
end if;
end process LB_THRESH_REGISTER;
end generate ENABLE_LB_THRESH_REGISTER;
DISABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
linebuf_threshold_i <= (others => '0');
end generate DISABLE_LB_THRESH_REGISTER;
DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 0 generate
begin
---------------------------------------------------------------------------
-- S2MM DMA IRQ MASK
---------------------------------------------------------------------------
dma_irq_mask : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_irq_mask_i <= (others => '0');
elsif(axi2ip_wrce(DMA_IRQ_MASK_IND) = '1')then
dma_irq_mask_i(3 downto 0) <= axi2ip_wrdata(3 downto 0);
end if;
end if;
end process dma_irq_mask;
end generate DMA_IRQ_MASK_GEN;
NO_DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 1 generate
begin
dma_irq_mask_i <= (others => '0');
end generate NO_DMA_IRQ_MASK_GEN;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_register is
generic(
C_NUM_REGISTERS : integer := 8 ;
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
C_LINEBUFFER_THRESH : integer range 1 to 65536 := 1 ;
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ; -- CR591965
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
frame_sync : in std_logic ; --
fsync_mask : in std_logic ; -- CR 578591
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqdelay_wren : out std_logic ; --
irqthresh_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; --
--
-- Error Control --
fsize_mismatch_err : in std_logic ; --
lsize_mismatch_err : in std_logic ; --
lsize_more_mismatch_err : in std_logic ; --
s2mm_fsize_more_or_sof_late : in std_logic ; --
dma_interr_set_minus_frame_errors : in std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_err_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
frmstr_err_addr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
update_frmstore : in std_logic ; --
new_frmstr : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
frm_store : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
dma_irq_mask : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
reg_index : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
num_frame_store_regmux : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
num_frame_store : out std_logic_vector --
(FRMSTORE_MSB_BIT downto 0); --
linebuf_threshold : out std_logic_vector --
(THRESH_MSB_BIT downto 0); --
--
introut : out std_logic --
);
end axi_vdma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
constant FRAME_STORE_INDEX : integer := 6; -- Frame Store Reg index
constant THRESHOLD_INDEX : integer := 7; -- Threshold Reg index
constant REG_IND : integer := 5; -- Reg index
constant DMA_IRQ_MASK_IND : integer := 3; --
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal reg_index_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dma_irq_mask_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal num_frame_store_regmux_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal num_frame_store_i : std_logic_vector
(FRMSTORE_MSB_BIT downto 0) := (others =>'0');
signal linebuf_threshold_i : std_logic_vector
(LINEBUFFER_THRESH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal err : std_logic := '0';
signal err_p : std_logic := '0';
signal fsize_err : std_logic := '0';
signal lsize_err : std_logic := '0';
signal lsize_more_err : std_logic := '0';
signal s2mm_fsize_more_or_sof_late_bit : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_interr_minus_frame_errors : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal err_d1 : std_logic := '0';
signal err_re : std_logic := '0';
--signal err_fe : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_err : std_logic := '0';
signal err_pointer_set : std_logic := '0';
signal err_frmstore_set : std_logic := '0';
-- Interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- Soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal reset_counts : std_logic := '0';
signal irqdelay_wren_i : std_logic := '0';
signal irqthresh_wren_i : std_logic := '0';
-- Frame Store support signal
signal frmstore_is_zero : std_logic := '0';
signal frm_store_i : std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0') ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
frm_store <= frm_store_i ;
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i ;
dma_irq_mask <= dma_irq_mask_i ;
reg_index <= reg_index_i ;
taildesc_msb <= taildesc_msb_i ;
num_frame_store <= num_frame_store_i;
num_frame_store_regmux <= num_frame_store_regmux_i;
linebuf_threshold <= linebuf_threshold_i;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DISABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqdelay_wren <= '0';
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
end generate DISABLE_DMACR_DELAY_CNTR;
ENABLE_DMACR_DELAY_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_6 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_14 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
DMACR_DELAY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- Delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqdelay_wren_i <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren_i <= '1';
else
irqdelay_wren_i <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-- Reset delay irq counter on new delay write, or reset, or frame sync
irqdelay_wren <= irqdelay_wren_i or reset_counts or frame_sync;
end generate ENABLE_DMACR_DELAY_CNTR;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
DISABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
irqthresh_wren <= '0';
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
end generate DISABLE_DMACR_FRM_CNTR;
ENABLE_DMACR_FRM_CNTR : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_7 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_15 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
irqthresh_wren_i <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
-- If paused then hold frame counter from counting
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren_i <= '1';
else
irqthresh_wren_i <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
irqthresh_wren <= irqthresh_wren_i or reset_counts;
end generate ENABLE_DMACR_FRM_CNTR;
-- Due to seperate MM2S and S2MM resets the delay and frame count registers
-- is axi_sg must be reset with a physical write to axi_sg during a soft reset.
REG_RESET_IRQ_COUNTS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
reset_counts <= '0';
elsif(prmry_resetn = '0' and dmacr_i(DMACR_RESET_BIT) = '1')then
reset_counts <= '1';
end if;
end if;
end process REG_RESET_IRQ_COUNTS;
-----------------------------------------------------------------------------------
------ DMACR - Remainder of DMA Control Register
-----------------------------------------------------------------------------------
GEN_NO_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 0 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& ZERO_VALUE(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_NO_INTERNAL_GENLOCK;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register
-------------------------------------------------------------------------------
GEN_FOR_INTERNAL_GENLOCK : if C_INTERNAL_GENLOCK_ENABLE = 1 generate
begin
DS_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DS_DMACR_REGISTER;
end generate DS_GEN_DMACR_REGISTER;
DM_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process DM_DMACR_REGISTER;
end generate DM_GEN_DMACR_REGISTER;
S_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(14 downto 8) <= (others => '0');
dmacr_i(7) <= '1';
dmacr_i(6 downto 4) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& axi2ip_wrdata(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& axi2ip_wrdata(DMACR_GENLOCK_SEL_BIT) -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process S_DMACR_REGISTER;
end generate S_GEN_DMACR_REGISTER;
end generate GEN_FOR_INTERNAL_GENLOCK;
----M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
----begin
----M_DMACR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= (others => '0');
----
---- elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
---- dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
---- downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT) -- bit 15
---- & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
---- & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
---- & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
---- & ZERO_VALUE(DMACR_PNTR_NUM_MSB
---- downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
---- & '0' -- bit 7
---- & axi2ip_wrdata(DMACR_FSYNCSEL_MSB
---- downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
---- & axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
---- end if;
---- end if;
---- end process M_DMACR_REGISTER;
----end generate M_GEN_DMACR_REGISTER;
M_GEN_DMACR_REGISTER : if C_GENLOCK_MODE = 0 generate
begin
M_DMACR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-2
downto DMACR_FRMCNTEN_BIT) <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 13
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& ZERO_VALUE(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) -- bits 11 downto 8
& '0' -- bit 7
& axi2ip_wrdata(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) -- bits 6 downto 5
& axi2ip_wrdata(DMACR_FRMCNTEN_BIT); -- bit 4
end if;
end if;
end process M_DMACR_REGISTER;
end generate M_GEN_DMACR_REGISTER;
-------------------------------------------------------------------------------
-- DMACR - GenLock Sync Enable Bit (CR577698)
-------------------------------------------------------------------------------
-- Dynamic Genlock Slave mode therefore instantiate a register for sync enable.
DS_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 3 generate
begin
DS_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DS_DMACR_SYNCEN;
end generate DS_GEN_SYNCEN_BIT;
-- Dynamic Genlock Master mode therefore instantiate a register for sync enable.
DM_GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 2 generate
begin
DM_DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; --CR 713581
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process DM_DMACR_SYNCEN;
end generate DM_GEN_SYNCEN_BIT;
-- Genlock Slave mode therefore instantiate a register for sync enable.
GEN_SYNCEN_BIT : if C_GENLOCK_MODE = 1 generate
begin
DMACR_SYNCEN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SYNCEN_BIT) <= axi2ip_wrdata(DMACR_SYNCEN_BIT);
end if;
end if;
end process DMACR_SYNCEN;
end generate GEN_SYNCEN_BIT;
-- Genlock Master mode therefore make DMACR.SyncEn bit RO and set to zero
GEN_NOSYNCEN_BIT : if C_GENLOCK_MODE = 0 generate
begin
dmacr_i(DMACR_SYNCEN_BIT) <= '0';
M_DMACR_REPEAT_EN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
--dmacr_i(DMACR_REPEAT_EN_BIT) <= '1';
dmacr_i(DMACR_REPEAT_EN_BIT) <= '0'; -- CR 713581
-- If DMACR Write then pass axi lite write bus to DMACR bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_REPEAT_EN_BIT) <= axi2ip_wrdata(DMACR_REPEAT_EN_BIT);
end if;
end if;
end process M_DMACR_REPEAT_EN;
end generate GEN_NOSYNCEN_BIT;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Circular Buffere/ Park Enable
-------------------------------------------------------------------------------
DMACR_TAILPTREN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_CRCLPRK_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC tailptr en bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_CRCLPRK_BIT) <= axi2ip_wrdata(DMACR_CRCLPRK_BIT);
end if;
end if;
end process DMACR_TAILPTREN;
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when (stop_dma = '1') -- Stop due to error/rs clear
or (soft_reset_i = '1') -- Soft Reset
or (dmacr_i(DMACR_FRMCNTEN_BIT) = '1' -- Frame Count Enable
and ioc_irq_set = '1') -- and threshold met
else '0';
DMACR_RUNSTOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
DMASR_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
end generate GEN_FOR_SG;
-- CR588712 - Hard code Idle to 0 when Scatter Gather engine not included
GEN_NO_SG : if C_INCLUDE_SG = 0 generate
begin
idle <= '0';
end generate GEN_NO_SG;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
MM2S_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 1 generate
begin
err <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
end generate MM2S_ERR_FOR_IRQ;
S2MM_ERR_FOR_IRQ : if C_CHANNEL_IS_MM2S = 0 generate
begin
err_p <= dma_interr
or lsize_err
or lsize_more_err
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
err <= dma_interr_minus_frame_errors
or (fsize_err and not dma_irq_mask_i(0))
or (lsize_err and not dma_irq_mask_i(1))
or (s2mm_fsize_more_or_sof_late_bit and not dma_irq_mask_i(2))
or (lsize_more_err and not dma_irq_mask_i(3))
or dma_slverr
or dma_decerr
or sg_slverr
or sg_decerr;
FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
frm_store_i <= (others => '0');
-- elsif(err = '1')then
-- frm_store_i <= frm_store_i;
elsif(err_p = '0')then
frm_store_i <= new_frmstr;
end if;
end if;
end process FRMSTR_REGISTER;
DMAINTERR_MINUS_FRAME_ERRORS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr_minus_frame_errors <= '0';
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr_minus_frame_errors <= (dma_interr_minus_frame_errors and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set_minus_frame_errors;
elsif(dma_interr_set_minus_frame_errors = '1' )then
dma_interr_minus_frame_errors <= '1';
end if;
end if;
end process DMAINTERR_MINUS_FRAME_ERRORS;
end generate S2MM_ERR_FOR_IRQ;
-- Scatter Gather Error
sg_ftch_err <= ftch_slverr_set or ftch_decerr_set;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
-- If flush on frame sync disable then only reset will clear bit
GEN_FOR_NO_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 0 generate
begin
----DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
---- DMASR_LSIZE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_err <= '0';
---- elsif(lsize_mismatch_err = '1' )then
---- lsize_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_ERR;
----
---- DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- lsize_more_err <= '0';
---- elsif(lsize_more_mismatch_err = '1' )then
---- lsize_more_err <= '1';
---- end if;
---- end if;
---- end process DMASR_LSIZE_MORE_ERR;
end generate GEN_FOR_NO_FLUSH;
-- Flush on frame sync enabled therefore can clear with a write of '1'
GEN_FOR_FLUSH : if C_ENABLE_FLUSH_ON_FSYNC = 1 generate
begin
---- DMASR_DMAINTERR : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- dma_interr <= '0';
---- -- CPU Writing a '1' to clear - OR'ed with setting to prevent
---- -- missing a 'set' during the write.
---- elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
---- dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
---- or dma_interr_set;
---- elsif(dma_interr_set = '1' )then
---- dma_interr <= '1';
---- end if;
---- end if;
---- end process DMASR_DMAINTERR;
DMASR_FSIZEERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
fsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
fsize_err <= (fsize_err and not(axi2ip_wrdata(DMASR_FSIZEERR_BIT)))
or fsize_mismatch_err;
elsif(fsize_mismatch_err = '1' )then
fsize_err <= '1';
end if;
end if;
end process DMASR_FSIZEERR;
DMASR_FSIZE_MORE_OR_SOF_LATE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s2mm_fsize_more_or_sof_late_bit <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
s2mm_fsize_more_or_sof_late_bit <= (s2mm_fsize_more_or_sof_late_bit and not(axi2ip_wrdata(DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT)))
or s2mm_fsize_more_or_sof_late;
elsif(s2mm_fsize_more_or_sof_late = '1' )then
s2mm_fsize_more_or_sof_late_bit <= '1';
end if;
end if;
end process DMASR_FSIZE_MORE_OR_SOF_LATE_ERR;
end generate GEN_FOR_FLUSH;
DMASR_LSIZE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_err <= (lsize_err and not(axi2ip_wrdata(DMASR_LSIZEERR_BIT)))
or lsize_mismatch_err;
elsif(lsize_mismatch_err = '1' )then
lsize_err <= '1';
end if;
end if;
end process DMASR_LSIZE_ERR;
DMASR_LSIZE_MORE_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
lsize_more_err <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
lsize_more_err <= (lsize_more_err and not(axi2ip_wrdata(DMASR_LSIZE_MORE_ERR_BIT)))
or lsize_more_mismatch_err;
elsif(lsize_more_mismatch_err = '1' )then
lsize_more_err <= '1';
end if;
end if;
end process DMASR_LSIZE_MORE_ERR;
DMASR_DMAINTERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_interr <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dma_interr <= (dma_interr and not(axi2ip_wrdata(DMASR_DMAINTERR_BIT)))
or dma_interr_set;
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- Disable delay timer if halted or on delay irq set
dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) or dmasr_i(DMASR_DLYIRQ_BIT)
or fsync_mask; -- CR 578591
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERR_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_d1 <= '0';
else
err_d1 <= err;
end if;
end if;
end process GEN_ERR_RE;
-- Generate rising edge pulse on error
err_re <= err and not err_d1;
--err_fe <= not err and err_d1;
DMASR_ERRIRQ : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or err_re;
elsif(err_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& lsize_more_err -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& s2mm_fsize_more_or_sof_late_bit -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& lsize_err -- Bit 8
& fsize_err -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& '0' -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-------------------------------------------------------------------------------
-- Frame Store Pointer Field - Reference of current frame buffer pointer being
-- used.
-------------------------------------------------------------------------------
----FRMSTR_REGISTER : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- --if(prmry_resetn = '0' or err_fe = '1')then
---- if(prmry_resetn = '0' )then
---- frm_store <= (others => '0');
---- err_frmstore_set <= '0';
---- -- Detected error has NOT register a desc pointer
---- elsif(err_frmstore_set = '0')then
----
---- -- CR582182 qualified with update_frmstore
---- -- DMA Error Error
---- if(update_frmstore = '1' and err = '1')then
---- frm_store <= frmstr_err_addr;
---- err_frmstore_set <= '1';
----
---- -- CR582182 qualified with update_frmstore
---- -- Commanded to update frame store value - used for indicating
---- -- current frame begin processed by dma controller
---- elsif(update_frmstore = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
---- frm_store <= new_frmstr;
---- err_frmstore_set <= err_frmstore_set;
----
---- end if;
---- end if;
---- end if;
---- end process FRMSTR_REGISTER;
-- If SG engine is included then instantiate sg specific logic
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
reg_index_i <= (others => '0'); -- Not used in SCATTER GATHER mode
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_lsb_i <= (others => '0');
err_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_lsb_i <= ftch_err_addr(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT)-- Curdesc bit 5
& "00000"; -- Reserved bits 4 downto 0
err_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT -- Curdesc bit 31 downto
downto CURDESC_LOWER_LSB_BIT) -- Curdesc bit 5
& "00000"; -- Reserved bit 4 downto 0
err_pointer_set <= err_pointer_set;
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& "00000";
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(err_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_err = '1')then
curdesc_msb_i <= ftch_err_addr((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc
((C_M_AXI_SG_ADDR_WIDTH
- C_S_AXI_LITE_DATA_WIDTH)-1
downto 0);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated <= '1';
else
tailpntr_updated <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_SCATTER_GATHER_MODE;
-- If SG engine is not included then instantiate register direct mode
GEN_NO_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Tie off unused scatter gather specific signals
sg_decerr <= '0'; -- Not used in Register Direct Mode
sg_slverr <= '0'; -- Not used in Register Direct Mode
curdesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
curdesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_lsb_i <= (others => '0'); -- Not used in Register Direct Mode
taildesc_msb_i <= (others => '0'); -- Not used in Register Direct Mode
tailpntr_updated <= '0'; -- Not used in Register Direct Mode
GEN_NO_REG_INDEX_REG : if C_NUM_FSTORES < 17 generate
begin
reg_index_i <= (others => '0'); -- Not used if C_NUM_FSTORE =< 16
end generate GEN_NO_REG_INDEX_REG;
GEN_REG_INDEX_REG : if C_NUM_FSTORES > 16 generate
begin
---------------------------------------------------------------------------
-- Reg Index
---------------------------------------------------------------------------
reg_index : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_index_i <= (others => '0');
elsif(axi2ip_wrce(REG_IND) = '1')then
reg_index_i(0) <= axi2ip_wrdata(0);
end if;
end if;
end process reg_index;
end generate GEN_REG_INDEX_REG;
end generate GEN_NO_SCATTER_GATHER_MODE;
---------------------------------------------------------------------------
-- Number of Frame Stores
---------------------------------------------------------------------------
ENABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
NUM_FRMSTR_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
elsif(axi2ip_wrce(FRAME_STORE_INDEX) = '1')then
-- If value is 0 then set frame store to 1
if(frmstore_is_zero='1')then
num_frame_store_i <= ONE_FRAMESTORE;
else
num_frame_store_i <= axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT);
end if;
end if;
end if;
end process NUM_FRMSTR_REGISTER;
frmstore_is_zero <= '1' when axi2ip_wrdata(FRMSTORE_MSB_BIT
downto FRMSTORE_LSB_BIT) = ZERO_FRAMESTORE
else '0';
num_frame_store_regmux_i <= num_frame_store_i;
end generate ENABLE_NUM_FRMSTR_REGISTER;
DISABLE_NUM_FRMSTR_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_5 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_13 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
num_frame_store_i <= std_logic_vector(to_unsigned(C_NUM_FSTORES_64,NUM_FRM_STORE_WIDTH));
num_frame_store_regmux_i <= (others => '0');
end generate DISABLE_NUM_FRMSTR_REGISTER;
---------------------------------------------------------------------------
-- Line Buffer Threshold
---------------------------------------------------------------------------
ENABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1) ))generate
begin
LB_THRESH_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
linebuf_threshold_i <= std_logic_vector(to_unsigned(C_LINEBUFFER_THRESH,LINEBUFFER_THRESH_WIDTH));
elsif(axi2ip_wrce(THRESHOLD_INDEX) = '1')then
linebuf_threshold_i <= axi2ip_wrdata(THRESH_MSB_BIT
downto THRESH_LSB_BIT);
end if;
end if;
end process LB_THRESH_REGISTER;
end generate ENABLE_LB_THRESH_REGISTER;
DISABLE_LB_THRESH_REGISTER : if ((C_CHANNEL_IS_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) ) or (C_CHANNEL_IS_MM2S = 0 and (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0) ))generate
begin
linebuf_threshold_i <= (others => '0');
end generate DISABLE_LB_THRESH_REGISTER;
DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 0 generate
begin
---------------------------------------------------------------------------
-- S2MM DMA IRQ MASK
---------------------------------------------------------------------------
dma_irq_mask : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dma_irq_mask_i <= (others => '0');
elsif(axi2ip_wrce(DMA_IRQ_MASK_IND) = '1')then
dma_irq_mask_i(3 downto 0) <= axi2ip_wrdata(3 downto 0);
end if;
end if;
end process dma_irq_mask;
end generate DMA_IRQ_MASK_GEN;
NO_DMA_IRQ_MASK_GEN : if C_CHANNEL_IS_MM2S = 1 generate
begin
dma_irq_mask_i <= (others => '0');
end generate NO_DMA_IRQ_MASK_GEN;
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1670.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01670ent IS
END c09s01b00x00p05n01i01670ent;
ARCHITECTURE c09s01b00x00p05n01i01670arch OF c09s01b00x00p05n01i01670ent IS
BEGIN
B:block
begin
next; -- illegal location for next statement
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01670 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01670arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1670.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01670ent IS
END c09s01b00x00p05n01i01670ent;
ARCHITECTURE c09s01b00x00p05n01i01670arch OF c09s01b00x00p05n01i01670ent IS
BEGIN
B:block
begin
next; -- illegal location for next statement
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01670 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01670arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1670.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01670ent IS
END c09s01b00x00p05n01i01670ent;
ARCHITECTURE c09s01b00x00p05n01i01670arch OF c09s01b00x00p05n01i01670ent IS
BEGIN
B:block
begin
next; -- illegal location for next statement
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01670 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01670arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_unit is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_received_in : in STD_LOGIC;
interrupt : in STD_LOGIC;
crc_en : out STD_LOGIC := '0';
ethertype_en : out STD_LOGIC := '0';
ram_en : out STD_LOGIC := '0');
end control_unit;
architecture Behavioral of control_unit is
type state_type is (IDLE, WORKING, INTERRUPTED);
signal state, next_state : state_type;
signal counter : std_logic_vector(11 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
process (state)
begin
if state = IDLE then
crc_en <= '0';
elsif state = WORKING then
crc_en <= '1';
elsif state = INTERRUPTED then
crc_en <= '0';
end if;
end process;
process (state)
begin
if state = IDLE then
ethertype_en <= '0';
elsif state = WORKING then
ethertype_en <= '1';
elsif state = INTERRUPTED then
ethertype_en <= '0';
end if;
end process;
process (state)
begin
if state = IDLE then
ram_en <= '0';
elsif state = WORKING then
ram_en <= '1';
elsif state = INTERRUPTED then
ram_en <= '0';
end if;
end process;
process (state, clk)
begin
if rising_edge(clk) then
if state = IDLE then
counter <= (others=>'0');
elsif state = WORKING then
counter <= counter + 1;
elsif state = INTERRUPTED then
counter <= counter + 1;
end if;
end if;
end process;
process (state, clk, data_received_in, interrupt)
begin
next_state <= state;
case (state) is
when IDLE =>
if data_received_in = '1' then
next_state <= WORKING;
end if;
when WORKING =>
if interrupt = '1' then
next_state <= INTERRUPTED;
end if;
when INTERRUPTED =>
next_state <= IDLE;
when others =>
next_state <= IDLE;
end case;
end process;
end Behavioral;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_mux_2x1 IS END tb_mux_2x1;
ARCHITECTURE test OF tb_mux_2x1 IS
COMPONENT mux_2x1 IS
PORT(a, b, ctrl: IN STD_LOGIC;
q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL i1: STD_LOGIC:='0';
SIGNAL i2: STD_LOGIC:='1';
SIGNAL address, result: STD_LOGIC;
BEGIN
T1: mux_2x1 PORT MAP(a=>i1, b=>i2, ctrl=>address, q=>result);
address<='0',
'1' AFTER 20 ns;
i1<='1' AFTER 30 ns;
i2<='0' AFTER 30 ns;
END test; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library PoC;
--use PoC.utils.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
package SoFPGA_sim is
type T_PB_FUNCTIONS is (
UNKNOWN, p0_ERROR_BLOCK, p0__push_arg0, p0__pop_arg0, p0__push_arg1, p0__pop_arg1, p0__push_arg2, p0__pop_arg2, p0__push_arg3, p0__pop_arg3, p0__push_arg03, p0__push_arg30, p0__pop_arg03, p0__pop_arg30, p0__push_tmp0, p0__pop_tmp0, p0__push_tmp1, p0__pop_tmp1, p0__push_tmp2, p0__pop_tmp2, p0__push_tmp3, p0__pop_tmp3, p0__push_tmp03, p0__push_tmp30, p0__pop_tmp03, p0__pop_tmp30, p0__get0_arg0, p0__put0_arg0, p0__get1_arg0, p0__put1_arg0, p0__get2_arg0, p0__put2_arg0, p0__get3_arg0, p0__put3_arg0, p0__get1_arg1, p0__put1_arg1, p0__get2_arg2, p0__put2_arg2, p0__get3_arg3, p0__put3_arg3, p0__get_arg03, p0__put_arg03, p0__put_arg30, p0__get0_tmp0, p0__put0_tmp0, p0__get1_tmp0, p0__put1_tmp0, p0__get2_tmp0, p0__put2_tmp0, p0__get3_tmp0, p0__put3_tmp0, p0__get1_tmp1, p0__put1_tmp1, p0__get2_tmp2, p0__put2_tmp2, p0__get3_tmp3, p0__put3_tmp3, p0__get_tmp03, p0__put_tmp03, p0_sleep_n_cy, p0_sleep_1_us, p0_sleep_n_us, p0_sleep_1_ms, p0_sleep_n_ms, p0_sleep_1_s, p0_sleep_loop, p0__Str_ByteToAscii, p0__Str_ByteToAscii2, p0__Str_ByteToDecimal, p0__Str_DoubleByteToDecimal, p0__Str_QuadByteToDecimal, p0_uart_reset, p0_uart_enableraw, p0_uart_disableraw, p0__UART_WriteChar, p0__UART_WriteDoubleChar, p0__UART_WriteTripleChar, p0__UART_WriteQuadChar, p0__UART_WriteRegLaR, p0__UART_WriteNewline, p0__UART_WriteHorizontalLine, p0__UART_WriteString, p0__UART_WriteLine, p0_uart_doubleident, p0_uart_quadident, p0_uart_readchar, p0_uart_readchar_block, p0_UART_WaitBufferNotFull, p0_UART_WaitBufferHalfFree, p0_UART_WaitBufferEmpty, p0_ISR_UART, p0__io_IIC_CheckAddress, p0__io_IIC_WriteByte, p0__io_IIC_ReadByte, p0__io_IIC_WriteRegister, p0__io_IIC_WriteDoubleRegister, p0__io_IIC_ReadRegister, p0__io_IIC_ReadDoubleRegister, p0__io_BBIO_IIC_EnableRaw, p0__io_BBIO_IIC_DisableRaw, p0__io_BBIO_IIC_Initialise, p0__io_BBIO_IIC_SendStartCond, p0__io_BBIO_IIC_SendStopCond, p0__io_BBIO_IIC_SendByte, p0__io_BBIO_IIC_SendAck, p0__io_BBIO_IIC_SendNAck, p0__io_BBIO_IIC_ReceiveByte, p0__io_BBIO_IIC_ReceiveAck, p0__io_BBIO_IIC_Abort, p0_BBIO_IIC_ClockToZ, p0_BBIO_IIC_ClockToLow, p0_BBIO_IIC_DataToZ, p0_BBIO_IIC_DataToLow, p0_BBIO_IIC_ReceiveBit, p0_BBIO_IIC_ClockPulse, p0_BBIO_IIC_Delay_Xus, p0_ISR_Timer, p0__dev_Mult32_Mult8, p0__dev_Mult32_Mult16, p0__dev_Mult32_Mult24, p0__dev_Mult32_Mult32, p0__dev_Div32_Wait, p0__dev_Div32_Div8_Begin, p0__dev_Div32_Div8_End, p0__dev_Div32_Div16_Begin, p0__dev_Div32_Div16_End, p0__dev_Div32_Div24_Begin, p0__dev_Div32_Div32_End, p0__dev_Div32_Div32_Begin, p0__dev_Div32_Div32_End, p0_ISR_Div32, p0__dev_ConvBCD24_Wait, p0__dev_ConvBCD24_Begin, p0__dev_ConvBCD24_End, p0__ISR_ConvBCD24, p0_ISR_GPIO, p0_ISR_BBIO, p0__dev_Term_Initialize, p0__dev_Term_CursorUp, p0__dev_Term_CursorDown, p0__dev_Term_CursorForward, p0__dev_Term_CursorBackward, p0__dev_Term_CursorNextLine, p0__dev_Term_CursorPreLine, p0__dev_Term_SetColumn, p0__dev_Term_GoToHome, p0__dev_Term_SetPosition, p0__dev_Term_ClearScreen, p0__dev_Term_ClearLine, p0__dev_Term_ScrollUp, p0__dev_Term_ScrollDown, p0__dev_Term_TextColor_Reset, p0__dev_Term_TextColor_Default, p0__dev_Term_TextColor_Black, p0__dev_Term_TextColor_Red, p0__dev_Term_TextColor_Green, p0__dev_Term_TextColor_Yellow, p0__dev_Term_TextColor_Blue, p0__dev_Term_TextColor_Magenta, p0__dev_Term_TextColor_Cyan, p0__dev_Term_TextColor_Gray, p0__dev_Term_TextColor_White, p0_dev_Term_EscSequence, p0_IIC_scan_devicemap, p0__tui_IIC_Dump_RegMap, p0_BootUp, p0__FatalError, p0__Initialize, p0_main, p0_sendok_I2C, p0_senderr_I2C, p0__Pager_PageX_Call_Table1, p0__Pager_PageX_Call_Table2, p0__Pager_Page0_HandleInterrupt, p0_main_isr
);
function InstructionPointer2FunctionName(PageNumber : STD_LOGIC_VECTOR(2 downto 0); InstAdr : T_PB_ADDRESS) return T_PB_FUNCTIONS;
end;
package body SoFPGA_sim is
function InstructionPointer2FunctionName(PageNumber : STD_LOGIC_VECTOR(2 downto 0); InstAdr : T_PB_ADDRESS) return T_PB_FUNCTIONS is
variable InstructionPointer : UNSIGNED(InstAdr'range);
begin
InstructionPointer := unsigned(InstAdr);
if ((x"000" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0_ERROR_BLOCK;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_arg1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_arg1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_arg2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_arg2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_arg3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_arg3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_arg03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_arg30;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_arg03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_arg30;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_tmp1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_tmp1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_tmp2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_tmp2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_tmp3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_tmp3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_tmp03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__push_tmp30;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_tmp03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__pop_tmp30;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get0_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put0_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get1_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put1_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get2_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put2_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get3_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put3_arg0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get1_arg1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put1_arg1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get2_arg2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put2_arg2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get3_arg3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put3_arg3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get_arg03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put_arg03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put_arg30;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get0_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put0_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get1_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put1_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get2_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put2_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get3_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put3_tmp0;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get1_tmp1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put1_tmp1;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get2_tmp2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put2_tmp2;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get3_tmp3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put3_tmp3;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__get_tmp03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0__put_tmp03;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"010")) then
return p0_sleep_n_cy;
elsif ((x"010" <= InstructionPointer) and (InstructionPointer < x"015")) then
return p0_sleep_1_us;
elsif ((x"015" <= InstructionPointer) and (InstructionPointer < x"015")) then
return p0_sleep_n_us;
elsif ((x"015" <= InstructionPointer) and (InstructionPointer < x"015")) then
return p0_sleep_1_ms;
elsif ((x"015" <= InstructionPointer) and (InstructionPointer < x"015")) then
return p0_sleep_n_ms;
elsif ((x"015" <= InstructionPointer) and (InstructionPointer < x"018")) then
return p0_sleep_1_s;
elsif ((x"018" <= InstructionPointer) and (InstructionPointer < x"01D")) then
return p0_sleep_loop;
elsif ((x"01D" <= InstructionPointer) and (InstructionPointer < x"01D")) then
return p0__Str_ByteToAscii;
elsif ((x"01D" <= InstructionPointer) and (InstructionPointer < x"01D")) then
return p0__Str_ByteToAscii2;
elsif ((x"01D" <= InstructionPointer) and (InstructionPointer < x"01D")) then
return p0__Str_ByteToDecimal;
elsif ((x"01D" <= InstructionPointer) and (InstructionPointer < x"01D")) then
return p0__Str_DoubleByteToDecimal;
elsif ((x"01D" <= InstructionPointer) and (InstructionPointer < x"01D")) then
return p0__Str_QuadByteToDecimal;
elsif ((x"01D" <= InstructionPointer) and (InstructionPointer < x"01F")) then
return p0_uart_reset;
elsif ((x"01F" <= InstructionPointer) and (InstructionPointer < x"023")) then
return p0_uart_enableraw;
elsif ((x"023" <= InstructionPointer) and (InstructionPointer < x"023")) then
return p0_uart_disableraw;
elsif ((x"023" <= InstructionPointer) and (InstructionPointer < x"026")) then
return p0__UART_WriteChar;
elsif ((x"026" <= InstructionPointer) and (InstructionPointer < x"02A")) then
return p0__UART_WriteDoubleChar;
elsif ((x"02A" <= InstructionPointer) and (InstructionPointer < x"02A")) then
return p0__UART_WriteTripleChar;
elsif ((x"02A" <= InstructionPointer) and (InstructionPointer < x"030")) then
return p0__UART_WriteQuadChar;
elsif ((x"030" <= InstructionPointer) and (InstructionPointer < x"030")) then
return p0__UART_WriteRegLaR;
elsif ((x"030" <= InstructionPointer) and (InstructionPointer < x"033")) then
return p0__UART_WriteNewline;
elsif ((x"033" <= InstructionPointer) and (InstructionPointer < x"033")) then
return p0__UART_WriteHorizontalLine;
elsif ((x"033" <= InstructionPointer) and (InstructionPointer < x"033")) then
return p0__UART_WriteString;
elsif ((x"033" <= InstructionPointer) and (InstructionPointer < x"033")) then
return p0__UART_WriteLine;
elsif ((x"033" <= InstructionPointer) and (InstructionPointer < x"033")) then
return p0_uart_doubleident;
elsif ((x"033" <= InstructionPointer) and (InstructionPointer < x"033")) then
return p0_uart_quadident;
elsif ((x"033" <= InstructionPointer) and (InstructionPointer < x"033")) then
return p0_uart_readchar;
elsif ((x"033" <= InstructionPointer) and (InstructionPointer < x"039")) then
return p0_uart_readchar_block;
elsif ((x"039" <= InstructionPointer) and (InstructionPointer < x"03E")) then
return p0_UART_WaitBufferNotFull;
elsif ((x"03E" <= InstructionPointer) and (InstructionPointer < x"043")) then
return p0_UART_WaitBufferHalfFree;
elsif ((x"043" <= InstructionPointer) and (InstructionPointer < x"043")) then
return p0_UART_WaitBufferEmpty;
elsif ((x"043" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0_ISR_UART;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0__io_IIC_CheckAddress;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0__io_IIC_WriteByte;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0__io_IIC_ReadByte;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0__io_IIC_WriteRegister;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0__io_IIC_WriteDoubleRegister;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0__io_IIC_ReadRegister;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04B")) then
return p0__io_IIC_ReadDoubleRegister;
elsif ((x"04B" <= InstructionPointer) and (InstructionPointer < x"04F")) then
return p0__io_BBIO_IIC_EnableRaw;
elsif ((x"04F" <= InstructionPointer) and (InstructionPointer < x"04F")) then
return p0__io_BBIO_IIC_DisableRaw;
elsif ((x"04F" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_Initialise;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_SendStartCond;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_SendStopCond;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_SendByte;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_SendAck;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_SendNAck;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_ReceiveByte;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_ReceiveAck;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0__io_BBIO_IIC_Abort;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0_BBIO_IIC_ClockToZ;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0_BBIO_IIC_ClockToLow;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0_BBIO_IIC_DataToZ;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0_BBIO_IIC_DataToLow;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0_BBIO_IIC_ReceiveBit;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0_BBIO_IIC_ClockPulse;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"052")) then
return p0_BBIO_IIC_Delay_Xus;
elsif ((x"052" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0_ISR_Timer;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Mult32_Mult8;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Mult32_Mult16;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Mult32_Mult24;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Mult32_Mult32;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Wait;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div8_Begin;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div8_End;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div16_Begin;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div16_End;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div24_Begin;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div32_End;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div32_Begin;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"053")) then
return p0__dev_Div32_Div32_End;
elsif ((x"053" <= InstructionPointer) and (InstructionPointer < x"054")) then
return p0_ISR_Div32;
elsif ((x"054" <= InstructionPointer) and (InstructionPointer < x"054")) then
return p0__dev_ConvBCD24_Wait;
elsif ((x"054" <= InstructionPointer) and (InstructionPointer < x"054")) then
return p0__dev_ConvBCD24_Begin;
elsif ((x"054" <= InstructionPointer) and (InstructionPointer < x"054")) then
return p0__dev_ConvBCD24_End;
elsif ((x"054" <= InstructionPointer) and (InstructionPointer < x"055")) then
return p0__ISR_ConvBCD24;
elsif ((x"055" <= InstructionPointer) and (InstructionPointer < x"056")) then
return p0_ISR_GPIO;
elsif ((x"056" <= InstructionPointer) and (InstructionPointer < x"056")) then
return p0_ISR_BBIO;
elsif ((x"056" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_Initialize;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_CursorUp;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_CursorDown;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_CursorForward;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_CursorBackward;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_CursorNextLine;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_CursorPreLine;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_SetColumn;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_GoToHome;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"05E")) then
return p0__dev_Term_SetPosition;
elsif ((x"05E" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_ClearScreen;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_ClearLine;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_ScrollUp;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_ScrollDown;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Reset;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Default;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Black;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Red;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Green;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Yellow;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Blue;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Magenta;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Cyan;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_Gray;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"062")) then
return p0__dev_Term_TextColor_White;
elsif ((x"062" <= InstructionPointer) and (InstructionPointer < x"065")) then
return p0_dev_Term_EscSequence;
elsif ((x"065" <= InstructionPointer) and (InstructionPointer < x"065")) then
return p0_IIC_scan_devicemap;
elsif ((x"065" <= InstructionPointer) and (InstructionPointer < x"065")) then
return p0__tui_IIC_Dump_RegMap;
elsif ((x"065" <= InstructionPointer) and (InstructionPointer < x"070")) then
return p0_BootUp;
elsif ((x"070" <= InstructionPointer) and (InstructionPointer < x"070")) then
return p0__FatalError;
elsif ((x"070" <= InstructionPointer) and (InstructionPointer < x"07D")) then
return p0__Initialize;
elsif ((x"07D" <= InstructionPointer) and (InstructionPointer < x"0A1")) then
return p0_main;
elsif ((x"0A1" <= InstructionPointer) and (InstructionPointer < x"0D3")) then
return p0_sendok_I2C;
elsif ((x"0D3" <= InstructionPointer) and (InstructionPointer < x"FB0")) then
return p0_senderr_I2C;
elsif ((x"FB0" <= InstructionPointer) and (InstructionPointer < x"FC5")) then
return p0__Pager_PageX_Call_Table1;
elsif ((x"FC5" <= InstructionPointer) and (InstructionPointer < x"FDA")) then
return p0__Pager_PageX_Call_Table2;
elsif ((x"FDA" <= InstructionPointer) and (InstructionPointer < x"FE0")) then
return p0__Pager_Page0_HandleInterrupt;
elsif ((x"FE0" <= InstructionPointer) and (InstructionPointer < x"FFF")) then
return p0_main_isr;
else
return UNKNOWN;
end if;
end function;
end package body;
|
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- Microprocessor Systems Project
-- December, 6th 2018
--
-- Design: Testbench for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
-- controlled using Xilinx Picoblaze processor and whose output is displayed on seven segment
-- display
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use work.fir_filter_shared_package.all;
use work.ssg_display_shared_package.all;
entity top_testbench is
end top_testbench;
architecture top_test of top_testbench is
component top is
port (clk : in std_logic;
rst : in std_logic;
out_seg_p : out SEG_T;
out_dp_p : out std_logic;
out_digits_en_p : out DIGITS_EN_T
);
end component top;
-- clock and asynchronous reset
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal seg_sig : SEG_T := (others => DISABLE_SEG);
signal dp_out_sig : std_logic := DISABLE_DP;
signal digits_enable_sig : DIGITS_EN_T := (others => DISABLE_DIGIT);
begin
-- Create an instance of the FIR filter controlled
-- using Xilinx Picoblaze and whose output is displayed
-- using seven segment display
DUT: top
port map ( clk => clk,
rst => rst,
out_seg_p => seg_sig,
out_dp_p => dp_out_sig,
out_digits_en_p => digits_enable_sig
);
-- Clock generation
clk_gen: process
begin
clk <= '0';
wait for CLK_LOW_TIME;
clk <= '1';
wait for CLK_HIGH_TIME;
end process clk_gen;
-- Reset generation
rst <= '1',
'0' after CLK_CYCLE_TIME;
process
begin
wait for 100 * CLK_CYCLE_TIME;
end process;
-- print_messages: process begin
-- end process print_messages;
-- stop_sim: process begin
-- wait for 24*CLK_CYCLE_TIME;
-- std.env.stop;
-- end process stop_sim;
end architecture top_test;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axilite_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity axilite_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8;
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32;
GC_INSTANCE_IDX : natural := 1; -- Instance index for this AXILITE_VVCT instance
GC_AXILITE_CONFIG : t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
axilite_vvc_master_if : inout t_axilite_if := init_axilite_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (axilite_vvc_master_if.write_address_channel.awaddr'length = GC_ADDR_WIDTH) report "axilite_vvc_master_if.write_address_channel.awaddr'length =/ GC_ADDR_WIDTH" severity failure;
assert (axilite_vvc_master_if.read_address_channel.araddr'length = GC_ADDR_WIDTH) report "axilite_vvc_master_if.read_address_channel.araddr'length =/ GC_ADDR_WIDTH" severity failure;
assert (axilite_vvc_master_if.write_data_channel.wdata'length = GC_DATA_WIDTH) report "axilite_vvc_master_if.write_data_channel.wdata'length =/ GC_DATA_WIDTH" severity failure;
assert (axilite_vvc_master_if.write_data_channel.wstrb'length = GC_DATA_WIDTH/8) report "axilite_vvc_master_if.write_data_channel.wstrb'length =/ GC_DATA_WIDTH/8" severity failure;
assert (axilite_vvc_master_if.read_data_channel.rdata'length = GC_DATA_WIDTH) report "axilite_vvc_master_if.read_data_channel.rdata'length =/ GC_DATA_WIDTH" severity failure;
end entity axilite_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of axilite_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_axilite_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_axilite_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_axilite_transaction_info(GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AXILITE_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "axilite_write() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "axilite_write() called with to wide data. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.byte_enable := v_cmd.byte_enable;
-- Call the corresponding procedure in the BFM package.
axilite_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
byte_enable => v_cmd.byte_enable((GC_DATA_WIDTH/8-1) downto 0),
msg => format_msg(v_cmd),
clk => clk,
axilite_if => axilite_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when READ =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "axilite_read() called with to wide address. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
axilite_read(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
axilite_if => axilite_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "axilite_check() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "axilite_check() called with to wide data. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
-- Call the corresponding procedure in the BFM package.
axilite_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
axilite_if => axilite_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;
ENTITY design_1_dds_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END design_1_dds_compiler_0_0;
ARCHITECTURE design_1_dds_compiler_0_0_arch OF design_1_dds_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dds_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : dds_compiler_v6_0_12
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 16,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 0,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 1,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "11,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 8,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 0,
C_M_PHASE_TDATA_WIDTH => 1,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tready => '0'
);
END design_1_dds_compiler_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;
ENTITY design_1_dds_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END design_1_dds_compiler_0_0;
ARCHITECTURE design_1_dds_compiler_0_0_arch OF design_1_dds_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dds_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0_12 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : dds_compiler_v6_0_12
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 16,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 0,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 1,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "11,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 8,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 0,
C_M_PHASE_TDATA_WIDTH => 1,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tready => '0'
);
END design_1_dds_compiler_0_0_arch;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This package contains general types, constants and functions oftenly used in other vhdl files
/
**************************************************************************************************/
library std;
use std.textio.all;
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package common_pkg is
/* constants 0 */
/**************************************************************************************************/
--bit used as the first integer bit when representing a fixed point in a std_ulogic_vector. This
-- value should belong to the interval [0, 2**30]. It is also the value of the maximum number
-- of fractional values that will be representable
constant SULV_NEW_ZERO : integer := 2**30;
--maximum number of fractional bits that will be used when calculating a number like 1/3 in binary
constant FRACTIONAL_LIMIT : natural := 15;
--used paths:
--directory where the vhdl sources are
constant SOURCES_DIRECTORY : string := "C:\Users\Antonio\Desktop\Vivado_workspace\PFdC_vivado_project\PFdC_vivado\PFdC_vivado.srcs";
--directory where the solution .txt files are going to be stored
constant DATA_FILE_DIRECTORY : string := "C:\Users\Antonio\Desktop\Vivado_workspace\PFdC_vivado_project\PFdC_vivado\PFdC_vivado.srcs\data_files";
--same as the later but with double backslash \\
constant DATA_FILE_DIRECTORY_M : string := "C:\\Users\\Antonio\\Desktop\\Vivado_workspace\\PFdC_vivado_project\\PFdC_vivado\\PFdC_vivado.srcs\\data_files"; --double backslash for Matlab
--Active-HDL project directory
constant ACTIVE_HDL_PROJECT_PATH : string := "C:\Users\Antonio\Active_HDL\Active_HDL_workspace\PFdC_activeHDL";
--the length of the names used to name the real_const_mult solution files
constant FILE_NAME_LENGTH : positive := 16;
--to control when to show debugging messages
constant DEBUGGING : boolean := false;
constant SEPARATOR_STR : string := "*************************";
/* if then else functions 1 */
/**************************************************************************************************/
function ite(cond : boolean; if_true, if_false : integer) return integer;
function ite(cond : boolean; if_true, if_false : boolean) return boolean;
function ite(cond : boolean; if_true, if_false : real) return real;
function ite(cond : boolean; if_true, if_false : character) return character;
function ite(cond : boolean; if_true, if_false : string) return string;
function ite(cond : boolean; if_true, if_false : std_ulogic) return std_ulogic;
function ite(cond : boolean; if_true, if_false : std_ulogic_vector) return std_ulogic_vector;
function ite(cond : boolean; if_true, if_false : bit) return bit;
function ite(cond : boolean; if_true, if_false : bit_vector) return bit_vector;
function ite(cond : boolean; if_true, if_false : unsigned) return unsigned;
function ite(cond : boolean; if_true, if_false : signed) return signed;
function ite(cond : boolean; if_true, if_false : positive_exc) return positive_exc;
function ite(cond : boolean; if_true, if_false : natural_exc) return natural_exc;
function ite(cond : boolean; if_true, if_false : boolean_exc) return boolean_exc;
function ite(cond : boolean; if_true, if_false : T_round_style) return T_round_style;
function ite(cond : boolean; if_true, if_false : T_overflow_style) return T_overflow_style;
function ite(cond : boolean; if_true, if_false : u_ufixed) return u_ufixed;
function ite(cond : boolean; if_true, if_false : u_sfixed) return u_sfixed;
function ite(cond : boolean; if_true, if_false : boolean_v) return boolean_v;
/* math 2 */
/**************************************************************************************************/
--returns the ceiling of the log2
function log2ceil(
number : positive)
return integer;
--returns the floor of the log2
function log2floor(
number : positive)
return integer;
--returns the maximum of the two integers
function maximum(
a, b: integer)
return integer;
--returns the minimum of the two integers
function minimum(
a, b: integer)
return integer;
--reduces the numbe to an odd one via dividing by two until odd
function reduce_to_odd(
arg : positive)
return positive;
/* debugging 3 */
/**************************************************************************************************/
--shows a message, for debugging purposes
procedure msg_debug(arg: in positive_v; separator: string);
procedure msg_debug(arg: in string);
/* image extraction 4 */
/**************************************************************************************************/
procedure separator;
--returns the 'image attribute of integer type
function image(
sca: integer)
return string;
function real_rightest_dec_bit(
number: real)
return integer;
function real_image_length(
number : real)
return integer;
--returns the 'image attribute of positive_exc type
function image(
number : positive_exc)
return string;
--returns the 'image attribute of natural_exc type
function image(
number : natural_exc)
return string;
--returns the 'image attribute of boolean_exc type
function image(
bool : boolean_exc)
return string;
--returns the 'image attribute of T_round_style type
function image(
bool : T_round_style)
return string;
--returns the 'image attribute of real type
function image(
number: real)
return string;
--returns the 'image attribute of boolean type
function image(
sca: boolean)
return string;
--returns the 'image attribute of std_ulogic type
function image(
sca: std_ulogic)
return string;
--returns the 'image attribute of bit type
function image(
sca: bit)
return string;
--returns the 'image attribute of bit_vector type
function image(
vec : bit_vector)
return string;
--returns the 'image attribute of std_ulogic_vector type
function image(
vec : std_ulogic_vector)
return string;
--returns the 'image attribute of a T_csd type in the 0,1,-1 form
function image(
csd: T_csd)
return string;
--returns the 'image attribute of a u_ufixed type
function image(
u_u: u_ufixed)
return string;
--returns the 'image attribute of a u_sfixed type
function image(
u_s: u_sfixed)
return string;
/* vector manipulation 5 */
/**************************************************************************************************/
--calculates the absolute value of each real of the vector
function "abs"(
arg : real_v)
return real_v;
--returns the maximum positive in the vector
function maximum(
arg : positive_v)
return positive;
--returns the maximum integer in the vector
function maximum(
arg : integer_v)
return integer;
--returns the minimum integer in the vector
function minimum(
arg : integer_v)
return integer;
--returns the maximum real in the vector
function maximum(
arg : real_v)
return real;
--uses bubble sort in a vector of reals to order it from low to high
function order(
arg : real_v)
return real_v;
/* integer/binary conversion 6 */
/**************************************************************************************************/
--returns the minimum number of bits necessary to represent the number in signed/unsigned
function min_bits(
number : integer;
is_signed : boolean)
return natural;
--returns the minimum number of bits necessary to represent the number assuming the use of
-- unsigned for natural numbers and signed for negative
function min_bits(
number : integer)
return natural;
----------------------------------------------------------------------------------------------------
function error_pct(
A : real;
B : real)
return real;
--returns the smallest representation of a real number in u_ufixed form. The fractional bits are
-- limited by the constant FRACTIONAL_LIMIT.
function to_ufixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate)
return u_ufixed;
--returns the smallest representation of a real number in u_sfixed form. The fractional bits are
-- limited by the constant FRACTIONAL_LIMIT.
function to_sfixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate)
return u_sfixed;
----------------------------------------------------------------------------------------------------
--returns the std_ulogic_vector of the desired length that represents the number in signed/
-- unsigned. It asserts the desired length is enough, and that it is signed if number negative
function sulv_from_int(
number : integer;
is_signed : boolean;
length : positive)
return std_ulogic_vector;
--returns the std_ulogic_vector of minimum length that represents the number in signed/unsigned
function sulv_from_int(
number : integer;
is_signed : boolean)
return std_ulogic_vector;
--returns the the std_ulogic_vector of minimum length that represents the number, assuming
-- signed for negative numbers and unsigned for the rest
function sulv_from_int(
number : integer)
return std_ulogic_vector;
--returns the canonical signed digit of the input vector. It returns a type T_csd which is an
-- array of length 2-slv. It encodes three values 0, 1, and -1 as "00","01",and "11"
-- respectively. If the parameter is_signed is ignored it is assumed the vector represents a
-- positive value.
function to_csd(
vector : u_ufixed)
return T_csd;
function to_csd(
vector : u_sfixed)
return T_csd;
----------------------------------------------------------------------------------------------------
--returns the maximum signed that can be represented
function max_vec(
vector : signed)
return signed;
--returns the minimum signed that can be represented
function min_vec(
vector : signed)
return signed;
--returns the maximum unsigned that can be represented
function max_vec(
vector : unsigned)
return unsigned;
--returns the minimum unsigned that can be represented
function min_vec(
vector : unsigned)
return unsigned;
--returns the maximum signed(as slv) that can be represented
function max_vec(
vector : signed)
return std_ulogic_vector;
--returns the minimum signed(as slv) that can be represented
function min_vec(
vector : signed)
return std_ulogic_vector;
--returns the maximum unsigned(as slv) that can be represented
function max_vec(
vector : unsigned)
return std_ulogic_vector;
--returns the minimum unsigned(as slv) that can be represented
function min_vec(
vector : unsigned)
return std_ulogic_vector;
--returns the maximum std_ulogic_vector that can be represented
function max_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector;
--returns the minimum std_ulogic_vector that can be represented
function min_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector;
/* arithmetic operators 7 */
/**************************************************************************************************/
--several functions to complete the functionality of the numeric_std package's
-- operators "+" and "-" so they return std_ulogic_vectors as well
function "+"(
vector : unsigned;
number : integer)
return std_ulogic_vector;
function "+"(
vector : signed;
number : integer)
return std_ulogic_vector;
function "+"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector;
function "+"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector;
function "-"(
vector : unsigned;
number : integer)
return std_ulogic_vector;
function "-"(
vector : signed;
number : integer)
return std_ulogic_vector;
function "-"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector;
function "-"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector;
/* other operators 10 */
/**************************************************************************************************/
--several functions to complete the functionality of operators +, -, *, /, ** so they accept an
-- integer and a real as parameters. It converts the integer to real
function "+"(
i : integer;
r : real)
return real;
function "+"(
r : real;
i : integer)
return real;
function "-"(
i : integer;
r : real)
return real;
function "-"(
r : real;
i : integer)
return real;
function "*"(
i : integer;
r : real)
return real;
function "*"(
r : real;
i : integer)
return real;
function "/"(
i : integer;
r : real)
return real;
function "/"(
r : real;
i : integer)
return real;
function "**"(
i : integer;
r : real)
return real;
function "**"(
r : real;
i : integer)
return real;
/* pipeline functions 11 */
/**************************************************************************************************/
--generates a vector of booleans which indicates in which position to place the pipelines out of
--all the possible ones depending on the parameter SPEED
function generate_pipelines(
positions : natural;
speed : T_speed)
return boolean_v;
function is_pipelined(
positions : natural;
speed : T_speed;
position : natural)
return boolean;
function number_of_pipelines(
positions : natural;
speed : T_speed)
return natural;
end package;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
package body common_pkg is
/********************************************************************************************** 1 */
function ite(cond: boolean; if_true, if_false: integer) return integer is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: boolean) return boolean is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: real) return real is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: character) return character is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: string) return string is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: std_ulogic) return std_ulogic is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: std_ulogic_vector) return std_ulogic_vector is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: bit) return bit is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: bit_vector) return bit_vector is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: unsigned) return unsigned is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: signed) return signed is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: positive_exc) return positive_exc is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: natural_exc) return natural_exc is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: boolean_exc) return boolean_exc is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: T_round_style) return T_round_style is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: T_overflow_style) return T_overflow_style is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: u_ufixed) return u_ufixed is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: u_sfixed) return u_sfixed is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
function ite(cond: boolean; if_true, if_false: boolean_v) return boolean_v is
begin
if cond then
return(if_true);
else
return(if_false);
end if;
end function ite;
/********************************************************************************************** 2 */
function log2ceil(number: positive)
return integer is
begin
return integer(ceil(log2(real(number))));
end function;
function log2floor(number: positive)
return integer is
begin
return integer(floor(log2(real(number))));
end function;
--returns the maximum of the two integers
function maximum(
a, b: integer)
return integer is
begin
return ite(a>b, a, b);
end function;
--returns the minimum of the two integers
function minimum(
a, b: integer)
return integer is
begin
return ite(a<b, a, b);
end function;
--reduction to odd number
function reduce_to_odd(
arg : positive)
return positive is
variable aux : positive := arg;
begin
if arg mod 2 = 1 then
return arg;
else
return reduce_to_odd(arg/2);
end if;
end function;
/********************************************************************************************** 3 */
procedure msg_debug(arg: in positive_v; separator: string) is
constant left : integer := arg'left;
constant right : integer := arg'right;
variable message : line;
begin
write(message, image(arg(left)));
if left /= right then
for i in arg'range loop
if i /= left then
write(message, separator);
write(message, image(arg(i)));
end if;
end loop;
end if;
writeline(output, message);
end procedure;
procedure msg_debug(
arg : in string)
is
variable message : line;
begin
if DEBUGGING then
write(message, arg);
writeline(OUTPUT, message);
end if;
end procedure;
/********************************************************************************************** 4 */
procedure separator is
begin
assert false
report SEPARATOR_STR
severity warning;
end procedure;
function image(
sca: integer)
return string is
begin
return integer'image(sca);
end;
function real_rightest_dec_bit(
number: real)
return integer is
variable copy : real := "mod"(number, 1.0);
variable counter : integer := 0;
begin
--for i in -FRACTIONAL_LIMIT to 0 loop
while copy /= 0.0 and counter > -FRACTIONAL_LIMIT loop
copy := "mod"(10.0*copy, 1.0);
counter := counter - 1;
end loop;
return counter;
end function;
function real_image_length(
number : real)
return integer is
constant rightest_frac_bit : integer := real_rightest_dec_bit(number);
constant fractional_bits : natural := -rightest_frac_bit;
constant integer_bits : integer := 1+integer(floor(log10(realmax(abs(number),1.0))));--at least 1
variable result : positive;
begin
if number = 0.0 then --'0'
result := 3;
elsif abs(number)<1.0 then --'0,f..f'
result := 2+fractional_bits; -- +2 for the leading '0.'
elsif fractional_bits=0 then --'i..i'
result := integer_bits;
else --'i..i,f..f'
result := integer_bits+1+fractional_bits; -- +1 because of the comma
end if;
if number<0.0 then --add the minus sign
return result+1;
else
return result;
end if;
end function;
function image(
number: real)
return string is
constant rightest_frac_bit : integer := real_rightest_dec_bit(number);
variable remain : real := abs(number);
constant fractional_bits : natural := -rightest_frac_bit;
constant integer_bits : natural := 1+integer(floor(log10(realmax(remain,1.0))));--at least 1
constant string_length : integer := real_image_length(number);
variable result : string(1 to string_length);
variable j : integer := 1; --string index
begin
if number = real'low then
return "real'low";
elsif number = real'high then
return "real'high";
end if;
--minus sign
if number < 0.0 then
result(j) := '-';
j := j + 1;
end if;
--integer bits
result(j to j+integer_bits-1) := real'image(floor(remain))(1 to integer_bits);
j := j+integer_bits;
remain := "mod"(remain, 1.0);
--fractional bits with the '.'
if fractional_bits > 0 then
result(j) := '.';
j := j + 1;
for i in 1 to fractional_bits loop
remain := remain * 10;
result (j) := image(integer(floor(remain)))(1);
remain := "mod"(remain, 1.0);
j := j + 1;
end loop;
end if;
return result;
end;
function image(
number : positive_exc)
return string is
begin
return integer'image(integer(number));
end function;
function image(
number : natural_exc)
return string is
begin
return integer'image(integer(number));
end function;
function image(
bool : boolean_exc)
return string is
begin
return boolean_exc'image(bool);
end function;
function image(
bool : T_round_style)
return string is
begin
return T_round_style'image(bool);
end function;
function image(
sca: boolean)
return string is
begin
return boolean'image(sca);
end;
function image(
sca: std_ulogic)
return string is
begin
return std_ulogic'image(sca);
end;
function image(
sca: bit)
return string is
begin
return bit'image(sca);
end;
function image(
vec: bit_vector)
return string is
variable result : string(1 to vec'length);
variable iterator : integer;
begin
iterator := vec'left;
for i in result'range loop
if (vec(iterator) = '1') then
result(i) := '1';
else
result(i) := '0';
end if;
iterator := ite(vec'ascending, iterator+1, iterator-1);
end loop;
return result;
end;
function image(
vec: std_ulogic_vector)
return string is
variable result : string(1 to vec'length);
variable iterator : integer;
begin
iterator := vec'left;
for i in result'range loop
if (vec(iterator) = '1') then
result(i) := '1';
else
result(i) := '0';
end if;
iterator := ite(vec'ascending, iterator+1, iterator-1);
end loop;
return result;
end;
function image(
csd: T_csd)
return string is
variable message : string(1 to 2*csd'length+1);
variable i, j : positive := 1;
begin
for i in csd'range loop
if csd(i) = "00" then
message(j) := '0';
j := j+1;
elsif csd(i) = "01" then
message(j) := '1';
j := j+1;
elsif csd(i) = "11" then
message(j to j+1) := "-1";
j := j+2;
else
assert false
report
"ERRROR on function image(T_csd): received illegal value ""10""."
severity error;
end if;
if i = 0 then
message(j) := '.';
j := j + 1;
end if;
end loop;
return message;
end function;
function image(
u_u: u_ufixed)
return string is
constant string_length : positive := 2+1+maximum(1+u_u'high, 1)-u_u'low; --+2:quotes, +1:comma
variable message : string(1 to string_length);
variable i : integer;
variable j : positive := 1; --string index
begin
message(j) := '"';
j := j + 1;
if u_u'high < 0 then
message(j to j+1) := "0.";
if u_u'high < -1 then
message (j+2 to j -u_u'high) := (others =>'0');
end if;
end if;
for i in u_u'range loop
message(j) := image(u_u(i))(2);
j := j+1;
if i=0 then
message(j) := '.';
j := j + 1;
end if;
end loop;
message(j) := '"';
return message;
end function;
function image(
u_s: u_sfixed)
return string is
constant string_length : positive := 2+1+maximum(1+u_s'high, 1)-u_s'low; --+2:quotes, +1:comma
variable message : string(1 to string_length);
variable i : integer;
variable j : positive := 1; --string index
begin
message(j) := '"';
j := j + 1;
if u_s'high < 0 then
message(j to j+1) := "0.";
if u_s'high < -1 then
message (j+2 to j -u_s'high) := (others =>'0');
end if;
end if;
for i in u_s'range loop
message(j) := image(u_s(i))(2);
j := j+1;
if i=0 then
message(j) := '.';
j := j + 1;
end if;
end loop;
message(j) := '"';
return message;
end function;
/********************************************************************************************** 5 */
function "abs"(
arg : real_v)
return real_v is
variable result : real_v(arg'range);
begin
for i in arg'range loop
result(i) := abs(arg(i));
end loop;
return result;
end function;
function maximum(
arg : positive_v)
return positive is
variable result : positive := positive'low;
begin
for i in arg'range loop
if arg(i) > result then
result := arg(i);
end if;
end loop;
return result;
end function;
function maximum(
arg : integer_v)
return integer is
variable result : integer := integer'low;
begin
for i in arg'range loop
if arg(i) > result then
result := arg(i);
end if;
end loop;
return result;
end function;
function minimum(
arg : integer_v)
return integer is
variable result : integer := integer'high;
begin
for i in arg'range loop
if arg(i) < result then
result := arg(i);
end if;
end loop;
return result;
end function;
function maximum(
arg : real_v)
return real is
variable result : real := real'low;
begin
for i in arg'range loop
if arg(i) > result then
result := arg(i);
end if;
end loop;
return result;
end function;
function order(
arg : real_v)
return real_v is
variable result : real_v(1 to arg'length) := arg;
variable aux : real;
begin
for i in 1 to result'high-1 loop
for j in 1 to result'high-i loop
if result(i) > result(i+1) then
aux := result(i);
result(i) := result(i+1);
result(i+1) := aux;
end if;
end loop;
end loop;
return result;
end function;
/********************************************************************************************** 6 */
function min_bits(
number : integer;
is_signed : boolean)
return natural is
begin
if number=0 then
return 1;
end if;
if number=-1 then
return 1;
end if;
if is_signed then
if number<0 then
if number=integer'low then
return 32;
else
return 1+log2ceil(abs(number));
end if;
elsif number=integer'high then
return 32;
else
return 1+log2ceil(number+1);
end if;
else
if number<0 then
assert false
report
"ERROR in function min_bits: trying to represent negative numbers in unsigned"
severity error;
return 0; --trying to represent negative numbers in unsigned
elsif number=integer'high then -- in unsigned
return 31;
else
return log2ceil(number+1);
end if;
end if; --added the condition number<0 when is_signed is false
-- because when using ite to control which value of
-- is_signed will be sent to min_bits some errors will
-- appear even though the condition is never reached
end function;
function min_bits(
number : integer)
return natural is
begin
if number>=0 then
return min_bits(number, false);
else
return min_bits(number, true);
end if;
end function;
----------------------------------------------------------------------------------------------------
function error_pct(
A : real;
B : real)
return real is
begin
if B = 0.0 then
return real'high;
else
return abs(100*(A-B)/B);
end if;
end function;
function to_ufixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate) --fixed_truncate, fixed_round
return u_ufixed is
constant number_int : natural := integer(floor(abs(number)));
constant number_uf : u_ufixed := to_ufixed(abs(number),
-1,
-FRACTIONAL_LIMIT,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
constant int_bits : integer := min_bits(number_int);
constant frac_bits : integer := -find_rightmost(number_uf, '1');
variable result : u_ufixed(int_bits-1 downto -frac_bits);
variable new_low : integer := result'low;
begin
result := to_ufixed(number,
int_bits-1,
-frac_bits,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
assert number >= 0.0
report
"ERROR in function to_ufixed: real number must be natural"
severity error;
--check if the number is either real'low, real'high as their real'image is not a number representation, but "#INF"
-- Also with 0.0, 1.0, and -1.0 as their representation is 0 downto 0 and this generates errors with functions from
-- the fixed_generic_pkg
if number = real'high then
return to_ufixed(number,
int_bits-1,
-1,
round_style => round_style,
overflow_style => fixed_wrap);
elsif number = 0.0 then
return to_ufixed(0.0, 0, -1);
elsif number = 1.0 then
return to_ufixed(1.0, 0, -1);
end if;
--in this part the fractional bits that are unnecesary are discarded accordingly with the error_pct
if result'low <0 then
for i in result'low to minimum(result'high, -1) loop
if error_pct(to_real(resize(result,
result'high,
i)),
number)<= max_error_pct
then new_low := i;
end if;
end loop;
--number 0 causes an error because (0 downto 0) is not liked by the function cleanvec from the
-- fixed point package. So the first(-1) fractional bit is only discarded when the number
-- of integer bits is greater than 1
if result'high > 0 then
if error_pct(to_real(resize(result,
result'high,
0)),
number)<= max_error_pct
then new_low := 0;
end if;
end if;
end if;
return resize(result, result'high, new_low);
end function;
function to_sfixed(
number : real;
max_error_pct : real := 0.0;
round_style : T_round_style := fixed_truncate) --fixed_truncate, fixed_round
return u_sfixed is
constant number_int : integer := integer(floor(number));
constant number_uf : u_ufixed := to_ufixed(abs(number),
-1,
-FRACTIONAL_LIMIT,
round_style => round_style,
overflow_style => fixed_wrap);
constant int_bits : integer := min_bits(number_int, is_signed=>true);
constant frac_bits : integer := -find_rightmost(number_uf, '1');
constant result : u_sfixed := to_sfixed(number,
int_bits-1,
-frac_bits,
round_style => round_style,
overflow_style => fixed_wrap);
variable new_low : integer := result'low;
begin
--check if the number is either real'low, real'high as their real'image is not a number representation, but "-1.#INF00" and "1.#INF00"
-- Also with 0.0, 1.0, and -1.0 as their representation is 0 downto 0 and this generates errors with functions from
-- the fixed_generic_pkg
if number = real'low then
return to_sfixed(number,
int_bits-1,
-1,
round_style => round_style,
overflow_style => fixed_wrap);
elsif number = real'high then
return to_sfixed(number,
int_bits-1,
-1,
round_style => round_style,
overflow_style => fixed_wrap);
elsif number = 0.0 then
return to_sfixed(0, 0, -1);
elsif number = 1.0 then
return to_sfixed(1.0, 1, 0);
elsif number = -1.0 then
return tO_sfixed(-1.0, 0, -1);
end if;
--in this part the fractional bits that are unnecesary are discarded accordingly with the error_pct
if result'low <0 then
for i in result'low to minimum(result'high, -1) loop
if error_pct(to_real(resize(result,
result'high,
i)),
number)<= max_error_pct
then new_low := i;
end if;
end loop;
--number 0 causes an error because (0 downto 0) is not liked by the function cleanvec from the
-- fixed point package. So the first(-1) fractional bit is only discarded when the number
-- of integer bits is greater than 1
if result'high > 0 then
if error_pct(to_real(resize(result,
result'high,
0)),
number)<= max_error_pct
then new_low := 0;
end if;
end if;
end if;
return resize(result, result'high, new_low);
end function;
----------------------------------------------------------------------------------------------------
function sulv_from_int(
number : integer;
is_signed : boolean;
length : positive)
return std_ulogic_vector is
begin
if is_signed then
return std_ulogic_vector(to_signed(number, length));
else
return std_ulogic_vector(to_unsigned(abs(number), length));
end if;
end function;
function sulv_from_int(
number : integer;
is_signed : boolean)
return std_ulogic_vector is
begin
return sulv_from_int(number, is_signed, min_bits(number, is_signed));
end function;
function sulv_from_int(
number : integer)
return std_ulogic_vector is
begin
return sulv_from_int(number, number<0);
end function;
----------------------------------------------------------------------------------------------------
function to_csd(
vector : u_ufixed)
return T_csd is
constant aux_vector : u_ufixed := resize(vector, vector'high+1 , vector'low);
variable flag : integer := vector'low-1;
variable result : T_csd(aux_vector'range) := (others => "00");
begin
for i in result'reverse_range loop --from low to high
if aux_vector(i)='0' then
if flag = i-1 then
flag := i;
elsif flag = i-2 then
result(i-1) := "01"; -- 1
flag := i;
else
result(flag+1) := "11"; -- -1
result(i) := "01"; -- 1
flag := i-1;
end if;
end if;
end loop ;
return result(result'high-1 downto result'low); --discard higher bit as it is the "sign"(in csd the values of a number in its
--positive and negative form can be represented in the same amount of bits)
end function;
function to_csd(
vector : u_sfixed)
return T_csd is
constant is_negative : boolean := to_real(vector) < 0.0;
constant aux_vector : u_sfixed := "abs"(vector); --to_csd of the absolute value and then invert the values
variable result : T_csd(aux_vector'high+ 1 downto aux_vector'low);
begin
result := to_csd(to_ufixed(to_real(aux_vector), aux_vector'high, aux_vector'low));
--invert values: -1 to 1, and 1 to -1
if is_negative then
for i in result'range loop
case result(i) is
when "11" => result(i) := "01";
when "01" => result(i) := "11";
when others => null;
end case;
end loop;
end if;
return result;
end function;
----------------------------------------------------------------------------------------------------
function max_int(
bits : positive;
signed_data : boolean)
return integer is
begin
if signed_data then
return 2**(bits-1)-1;
else
return 2**bits-1;
end if;
end function;
function min_int(
bits : positive;
signed_data : boolean)
return integer is
begin
if signed_data then
return -2**(bits-1);
else
return 0;
end if;
end function;
----------------------------------------------------------------------------------------------------
function max_vec(
vector : signed)
return signed is
variable aux : signed(vector'length downto 1);
begin
aux := (others => '1');
aux(vector'length) := '0';
return aux;
end function;
function min_vec(
vector : signed)
return signed is
variable aux : signed(vector'length downto 1);
begin
aux := (others => '0');
aux(vector'length) := '1';
return aux;
end function;
function max_vec(
vector : unsigned)
return unsigned is
variable aux : unsigned(vector'range);
begin
aux := (others => '1');
return aux;
end function;
function min_vec(
vector : unsigned)
return unsigned is
variable aux : unsigned(vector'range);
begin
aux := (others => '0');
return aux;
end function;
function max_vec(
vector : signed)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := max_vec(vector);
return std_ulogic_vector(aux);
end function;
function min_vec(
vector : signed)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := min_vec(vector);
return std_ulogic_vector(aux);
end function;
function max_vec(
vector : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux := max_vec(vector);
return std_ulogic_vector(aux);
end function;
function min_vec(
vector : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux := min_vec(vector);
return std_ulogic_vector(aux);
end function;
function max_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector is
begin
if signed_data then
return max_vec(signed(vector));
else
return max_vec(unsigned(vector));
end if;
end function;
function min_vec(
vector : std_ulogic_vector;
signed_data : boolean)
return std_ulogic_vector is
begin
if signed_data then
return min_vec(signed(vector));
else
return min_vec(unsigned(vector));
end if;
end function;
/********************************************************************************************** 7 */
function "+"(
vector : unsigned;
number : integer)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux := vector + number;
return std_ulogic_vector(aux);
end function;
function "+"(
vector : signed;
number : integer)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := vector + number;
return std_ulogic_vector(aux);
end function;
function "+"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector1'range);
begin
aux := vector1 + vector2;
return std_ulogic_vector(aux);
end function;
function "+"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector is
variable aux : signed(vector1'range);
begin
aux := vector1 + vector2;
return std_ulogic_vector(aux);
end function;
function "-"(
vector : unsigned;
number : integer)
return std_ulogic_vector is
variable aux : unsigned(vector'range);
begin
aux :=vector - number;
return std_ulogic_vector(aux);
end function;
function "-"(
vector : signed;
number : integer)
return std_ulogic_vector is
variable aux : signed(vector'range);
begin
aux := vector - number;
return std_ulogic_vector(aux);
end function;
function "-"(
vector1 : unsigned;
vector2 : unsigned)
return std_ulogic_vector is
variable aux : unsigned(vector1'range);
begin
aux := vector1 - vector2;
return std_ulogic_vector(aux);
end function;
function "-"(
vector1 : signed;
vector2 : signed)
return std_ulogic_vector is
variable aux : signed(vector1'range);
begin
aux := vector1 - vector2;
return std_ulogic_vector(aux);
end function;
/********************************************************************************************* 10 */
function "+"(
i : integer;
r : real)
return real is
begin
return real(i) + r;
end function;
function "+"(
r : real;
i : integer)
return real is
begin
return real(i) + r;
end function;
function "-"(
i : integer;
r : real)
return real is
begin
return real(i) - r;
end function;
function "-"(
r : real;
i : integer)
return real is
begin
return r - real(i);
end function;
function "*"(
i : integer;
r : real)
return real is
begin
return real(i) * r;
end function;
function "*"(
r : real;
i : integer)
return real is
begin
return real(i) * r;
end function;
function "/"(
i : integer;
r : real)
return real is
begin
return real(i) / r;
end function;
function "/"(
r : real;
i : integer)
return real is
begin
return r / real(i);
end function;
function "**"(
i : integer;
r : real)
return real is
begin
return real(i) ** r;
end function;
function "**"(
r : real;
i : integer)
return real is
begin
return r ** real(i);
end function;
/********************************************************************************************* 11 */
function generate_pipelines(
positions : natural;
speed : T_speed)
return boolean_v is
variable pipelines : natural;
variable aux : natural := positions;
variable result : boolean_v(1 to positions) := (others => false);
begin
case speed is
when t_min => return result;
when t_low => pipelines := integer(ceil(0.25 * real(aux)));
when t_medium => pipelines := integer(ceil(0.5 * real(aux)));
when t_high => pipelines := integer(ceil(0.75 * real(aux)));
when t_max => result := (others => true);
return result;
when t_exc => return result; --no value assigned
end case;
if pipelines>0 then
result(aux) := true;
if pipelines>1 then
for i in pipelines downto 2 loop
aux := aux - aux/pipelines;
result(aux) := true;
end loop;
end if;
end if;
return result;
end function;
function is_pipelined(
positions : natural;
speed : T_speed;
position : natural)
return boolean is
variable indexes : boolean_v(1 to positions) := generate_pipelines(positions,
speed);
begin
return indexes(position);
end function;
function number_of_pipelines(
positions : natural;
speed : T_speed)
return natural is
begin
case speed is
when t_min => return 0;
when t_low => return integer(ceil(0.25 * real(positions)));
when t_medium => return integer(ceil(0.5 * real(positions)));
when t_high => return integer(ceil(0.75 * real(positions)));
when t_max => return positions;
when others => return 0; --no value assigned
end case;
end function;
end package body; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rd_fifo_256to64_pkg.ALL;
ENTITY rd_fifo_256to64_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF rd_fifo_256to64_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:rd_fifo_256to64_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:rd_fifo_256to64_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-------------------------------------
-- ?g word 32 bit SRAM --
-- PORT MAPPING --
-- DATA: 32 bit input value --
-- ADDR: ceil(log2(?g)) bit address--
-- WE : 1 bit write enable --
-- EN : 1 bit enable --
-- CLK : 1 bit RAM clock --
-------------------------------------
-- OUT: 32 bit output value --
-------------------------------------
USE WORK.ram_types.ALL;
LIBRARY ieee;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY ram IS
GENERIC
(
g_addr_width : POSITIVE := 10
);
PORT
(
in_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_addr : IN STD_LOGIC_VECTOR(g_addr_width - 1 DOWNTO 0);
in_we : IN STD_LOGIC;
in_en : IN STD_LOGIC;
in_clk : IN STD_LOGIC;
----------------------------------------------------------
out_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ram;
ARCHITECTURE behavioral OF ram IS
SIGNAL s_memory : ram_data(2**g_addr_width - 1 DOWNTO 0);
------------------------------------------------------------------
-- RAM initialization with data file --
ATTRIBUTE ram_init_file : string; --
ATTRIBUTE ram_init_file OF s_memory: SIGNAL IS "quanta.mif"; --
------------------------------------------------------------------
BEGIN
PROCESS(in_en, in_clk)
BEGIN
-- Read/Write to memory on rising edge if enabled
IF(in_en = '1' AND RISING_EDGE(in_clk)) THEN
IF(in_we = '1') THEN
-- Write input word to addr
s_memory(CONV_INTEGER(in_addr)) <= in_data;
ELSE
-- Read output word from addr
out_data <= s_memory(CONV_INTEGER(in_addr));
END IF;
END IF;
END PROCESS;
END behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LatchSR_AB is
Port ( Sn : in STD_LOGIC;
Rn : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end LatchSR_AB;
architecture Behavioral of LatchSR_AB is
signal Q_aux : std_logic := '0';
signal Qn_aux : std_logic := '0';
begin
Q <= Q_aux;
Qn <= Qn_aux;
Q_aux <= Sn nand Qn_aux;
Qn_aux <= Rn nand Q_aux;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1628.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01628ent IS
END c08s12b00x00p03n01i01628ent;
ARCHITECTURE c08s12b00x00p03n01i01628arch OF c08s12b00x00p03n01i01628ent IS
BEGIN
TESTING: PROCESS
BEGIN
L1: for b in boolean loop
return true; -- illegal in loop statement
end loop L1;
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01628 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01628arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1628.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01628ent IS
END c08s12b00x00p03n01i01628ent;
ARCHITECTURE c08s12b00x00p03n01i01628arch OF c08s12b00x00p03n01i01628ent IS
BEGIN
TESTING: PROCESS
BEGIN
L1: for b in boolean loop
return true; -- illegal in loop statement
end loop L1;
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01628 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01628arch;
|
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