content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:52:57 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- This module make the input visible to the output just for one clock cycle
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT s... |
entity foo is end;
architecture bar of foo is
constant A : std.standard.FILE_OPEN_KIND;
constant B : FILE_OPEN_KIND := READ_MODE;
constant C : FILE_OPEN_KIND := WRITE_MODE;
constant D : FILE_OPEN_KIND := APPEND_MODE;
begin end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Oct 20 06:53:04 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
carry : in std_logic;
Salida :... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
--library hdl_library_CommonFunctions;
--use hdl_library_CommonFunctions.CommonFunctions.all;
entity SignalGenerator is
gener... |
-------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26... |
architecture RTL of FIFO is
begin
end architecture RTL;
|
architecture RTL of FIFO is
begin
end architecture RTL;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
architecture RTL of FIFO is
begin
PROC_LABEL : process is
begin
end process PROC_LABEL;
-- Violations below
PROC_LABEL : process is
begin
end process proc_label;
end architecture RTL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the follow... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- NEED RESULT: ARCH00501: Aggregates in attribute specifications (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
------------------------------------------------... |
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your... |
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity n_register is
generic (
width:integer := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end n_regist... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is ... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is ... |
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is ... |
-- DDR2 memory interface
-- Andrew Read, March 2016
-- This project is based on a working DDR2 interface very kindly donated by a friend
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
entity fpga_top is port(
clk : in std_logic;
nrst : in std_logic;
led :... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cyc... |
-------------------------------------------------------------------------------
-- Title : Title String
-------------------------------------------------------------------------------
-- Author : AUTHOR
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity rc4_initer is
generic (
width: integer := 8
);
port (
CLK: in std_logic;
GO: in std_logic;
KEYLEN: in std_logic_vector((width - 1) downto 0);
MEMINPUT: in std_logic_vector((width - 1) downto 0);
KEYINPUT: in s... |
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------------
-- Project : FIR Filter
-- Author : James Gibbard (james@gibbard.me)
-- Date : 2017-03-25
-- File : mac_module.vhd
-- Module : mac_module
---------------------------------------------------------------------------
-- Description : ... |
-- File name: tb_bus_test.vhd
-- Created: 2009-02-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: bus_test tester
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_bus_test is
generic (
clk_per : time := 5 ns... |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:18:25 02/19/2014
-- Design Name:
-- Module Name: trigo - Behavioral
-- Project Name: R... |
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:18:25 02/19/2014
-- Design Name:
-- Module Name: trigo - Behavioral
-- Project Name: R... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY clr_mux IS
PORT
(
color : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
portb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
out_r : OUT STD_LOGIC;
out_g : OUT STD_LOGIC;
out_b : OUT STD_LOGIC
);
END clr_mux;
ARCHITECTURE bdf_type OF clr_mux IS
sig... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY clr_mux IS
PORT
(
color : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
portb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
out_r : OUT STD_LOGIC;
out_g : OUT STD_LOGIC;
out_b : OUT STD_LOGIC
);
END clr_mux;
ARCHITECTURE bdf_type OF clr_mux IS
sig... |
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r... |
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_arra... |
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_arra... |
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_arra... |
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_arra... |
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_arra... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.01.2016 18:07:39
-- Design Name:
-- Module Name: debouncer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.01.2016 18:07:39
-- Design Name:
-- Module Name: debouncer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Add_Frame_example is
end entity;
architecture rtl of tb_Add_Frame_example is
component tb_Add_Frame
end component;
begin
tb_Add_Frame_instance :
component tb_Add_Frame
port map();
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Add_Frame_example is
end entity;
architecture rtl of tb_Add_Frame_example is
component tb_Add_Frame
end component;
begin
tb_Add_Frame_instance :
component tb_Add_Frame
port map();
end architecture rtl;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
-- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 3:
-- Read nodes from p2 response queue, request node CSR/Info
-- NOTE: (P2 response queue = P3 request queue + graphInfo)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unis... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port (a, b : in std_logic_vector(7 downto 0);
o, p : out std_logic);
end test;
architecture behav of test is
begin
o <= or a;
p <= and b;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:03:07 11/04/2014
-- Design Name:
-- Module Name: modulo_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependenc... |
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either... |
library ieee;
use ieee.std_logic_1164.all;
-- Simulates the A and B signal of the rotatory key encoder
entity rotKeyGen is
port (
A: out std_logic;
B: out std_logic;
Push : out std_logic
);
end entity rotKeyGen;
architecture RTL of rotKeyGen is
begin
-- This process generates the A and B signals
-- YOU m... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
--... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
--... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block2.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- --------------------... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:18 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:18 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
------------------------------------------------------------------------------
-- hw_acc - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. ... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
port
(
nibble1, nibble2 : in unsigned(3 downto 0);
sum : out unsigned(3 downto 0);
carry_out : out std_logic
);
end entity adder;
architecture behavioral of adder is
signal temp : unsigned(4 dow... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_rnd;
architecture behaviour of ex2_rnd is
constant s1: std_logic_vector(4 downto 0) := "1110... |
------------------------------------------------------------------------------
-- Title : DSP48E1-based MAC and data registered data propagation (1 stage)
------------------------------------------------------------------------------
-- Author : Daniel Tavares
-- Company : CNPEM LNLS-DIG
-- Created : 201... |
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : SRAM-Model (a very very very simple model) for Simulation
-- Last update : 02.12.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
... |
library ieee;
use ieee.std_logic_1164.all;
package pkg is
constant mask : std_logic_vector (7 downto 0) := x"0f";
end pkg;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:37:46 11/22/2015
-- Design Name:
-- Module Name: Z:/Downloads/VMware Shared Files/ComputerOrganization/MadeCPUin21days/CPU_TEST.vhd
-- Project Name: MadeCPUin21days
-- Target Device: ... |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 11:42:22 11/04/2015
-- Design Name:
-- Module Name: Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use ... |
------------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2004 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 20... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-----------------------------------------------------------... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.