content stringlengths 1 1.04M ⌀ |
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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1628.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01628ent IS
END c08s12b00x00p03n01i01628ent;
ARCHITECTURE c08s12b00x00p03n01i01628arch OF c08s12b00x00p03n01i01628ent IS
BEGIN
TESTING: PROCESS
BEGIN
L1: for b in boolean loop
return true; -- illegal in loop statement
end loop L1;
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01628 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01628arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:52:57 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top affine_block_ieee754_fp_to_uint_0_0 -prefix
-- affine_block_ieee754_fp_to_uint_0_0_ affine_block_ieee754_fp_to_uint_0_1_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_to_uint_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint is
port (
y : out STD_LOGIC_VECTOR ( 9 downto 0 );
\y_8__s_port_\ : out STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 17 downto 0 );
\x[20]\ : in STD_LOGIC;
\x[25]\ : in STD_LOGIC;
\x_7__s_port_\ : in STD_LOGIC;
\x[22]\ : in STD_LOGIC;
\x[21]\ : in STD_LOGIC;
\x[22]_0\ : in STD_LOGIC;
\x[21]_0\ : in STD_LOGIC;
\x[27]\ : in STD_LOGIC;
\x[25]_0\ : in STD_LOGIC;
\x[22]_1\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
\x[25]_1\ : in STD_LOGIC;
\x[25]_2\ : in STD_LOGIC;
\x[23]\ : in STD_LOGIC;
\x[27]_0\ : in STD_LOGIC;
\x[24]\ : in STD_LOGIC;
\x[30]\ : in STD_LOGIC;
\x[25]_3\ : in STD_LOGIC;
\x[24]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\x[24]_1\ : in STD_LOGIC;
\x[25]_4\ : in STD_LOGIC
);
end affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint;
architecture STRUCTURE of affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint is
signal \x_7__s_net_1\ : STD_LOGIC;
signal y2 : STD_LOGIC;
signal \y2_carry__0_n_0\ : STD_LOGIC;
signal \y2_carry__0_n_1\ : STD_LOGIC;
signal \y2_carry__0_n_2\ : STD_LOGIC;
signal \y2_carry__0_n_3\ : STD_LOGIC;
signal \y2_carry__1_n_0\ : STD_LOGIC;
signal \y2_carry__1_n_1\ : STD_LOGIC;
signal \y2_carry__1_n_2\ : STD_LOGIC;
signal \y2_carry__1_n_3\ : STD_LOGIC;
signal \y2_carry__2_n_1\ : STD_LOGIC;
signal \y2_carry__2_n_2\ : STD_LOGIC;
signal \y2_carry__2_n_3\ : STD_LOGIC;
signal \y2_carry_i_1__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_1__2_n_0\ : STD_LOGIC;
signal y2_carry_i_1_n_0 : STD_LOGIC;
signal \y2_carry_i_2__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_2__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_2__2_n_0\ : STD_LOGIC;
signal y2_carry_i_2_n_0 : STD_LOGIC;
signal \y2_carry_i_3__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_3__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_3__2_n_0\ : STD_LOGIC;
signal y2_carry_i_3_n_0 : STD_LOGIC;
signal \y2_carry_i_4__0_n_0\ : STD_LOGIC;
signal \y2_carry_i_4__1_n_0\ : STD_LOGIC;
signal \y2_carry_i_4__2_n_0\ : STD_LOGIC;
signal y2_carry_i_4_n_0 : STD_LOGIC;
signal \y2_carry_i_5__0_n_0\ : STD_LOGIC;
signal y2_carry_i_5_n_0 : STD_LOGIC;
signal y2_carry_i_6_n_0 : STD_LOGIC;
signal y2_carry_i_7_n_0 : STD_LOGIC;
signal y2_carry_i_8_n_0 : STD_LOGIC;
signal y2_carry_n_0 : STD_LOGIC;
signal y2_carry_n_1 : STD_LOGIC;
signal y2_carry_n_2 : STD_LOGIC;
signal y2_carry_n_3 : STD_LOGIC;
signal y3 : STD_LOGIC_VECTOR ( 31 to 31 );
signal \y[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y_8__s_net_1\ : STD_LOGIC;
signal NLW_y2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of y2_carry_i_9 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[3]_INST_0_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[4]_INST_0_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[5]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[6]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_9\ : label is "soft_lutpair0";
begin
\x_7__s_net_1\ <= \x_7__s_port_\;
\y_8__s_port_\ <= \y_8__s_net_1\;
y2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y2_carry_n_0,
CO(2) => y2_carry_n_1,
CO(1) => y2_carry_n_2,
CO(0) => y2_carry_n_3,
CYINIT => '1',
DI(3) => y2_carry_i_1_n_0,
DI(2) => y2_carry_i_2_n_0,
DI(1) => y2_carry_i_3_n_0,
DI(0) => y2_carry_i_4_n_0,
O(3 downto 0) => NLW_y2_carry_O_UNCONNECTED(3 downto 0),
S(3) => y2_carry_i_5_n_0,
S(2) => y2_carry_i_6_n_0,
S(1) => y2_carry_i_7_n_0,
S(0) => y2_carry_i_8_n_0
);
\y2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y2_carry_n_0,
CO(3) => \y2_carry__0_n_0\,
CO(2) => \y2_carry__0_n_1\,
CO(1) => \y2_carry__0_n_2\,
CO(0) => \y2_carry__0_n_3\,
CYINIT => '0',
DI(3) => y3(31),
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => '1',
O(3 downto 0) => \NLW_y2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_2__2_n_0\,
S(2) => \y2_carry_i_3__2_n_0\,
S(1) => \y2_carry_i_4__2_n_0\,
S(0) => \y2_carry_i_5__0_n_0\
);
\y2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y2_carry__0_n_0\,
CO(3) => \y2_carry__1_n_0\,
CO(2) => \y2_carry__1_n_1\,
CO(1) => \y2_carry__1_n_2\,
CO(0) => \y2_carry__1_n_3\,
CYINIT => '0',
DI(3) => y3(31),
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => y3(31),
O(3 downto 0) => \NLW_y2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_1__2_n_0\,
S(2) => \y2_carry_i_2__1_n_0\,
S(1) => \y2_carry_i_3__1_n_0\,
S(0) => \y2_carry_i_4__1_n_0\
);
\y2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \y2_carry__1_n_0\,
CO(3) => y2,
CO(2) => \y2_carry__2_n_1\,
CO(1) => \y2_carry__2_n_2\,
CO(0) => \y2_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => y3(31),
DI(1) => y3(31),
DI(0) => y3(31),
O(3 downto 0) => \NLW_y2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \y2_carry_i_1__1_n_0\,
S(2) => \y2_carry_i_2__0_n_0\,
S(1) => \y2_carry_i_3__0_n_0\,
S(0) => \y2_carry_i_4__0_n_0\
);
y2_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEAA0155FFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => y2_carry_i_1_n_0
);
\y2_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEAA00000000"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => y3(31)
);
\y2_carry_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_1__1_n_0\
);
\y2_carry_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_1__2_n_0\
);
y2_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAAAA9555"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(11),
I3 => x(10),
I4 => x(13),
I5 => x(15),
O => y2_carry_i_2_n_0
);
\y2_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__0_n_0\
);
\y2_carry_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__1_n_0\
);
\y2_carry_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_2__2_n_0\
);
y2_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"EABF"
)
port map (
I0 => x(13),
I1 => x(10),
I2 => x(11),
I3 => x(12),
O => y2_carry_i_3_n_0
);
\y2_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__0_n_0\
);
\y2_carry_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__1_n_0\
);
\y2_carry_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_3__2_n_0\
);
y2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => x(10),
I1 => x(11),
O => y2_carry_i_4_n_0
);
\y2_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__0_n_0\
);
\y2_carry_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__1_n_0\
);
\y2_carry_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_4__2_n_0\
);
y2_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444442424222"
)
port map (
I0 => x(17),
I1 => x(16),
I2 => x(14),
I3 => \y_8__s_net_1\,
I4 => x(13),
I5 => x(15),
O => y2_carry_i_5_n_0
);
\y2_carry_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => \y_8__s_net_1\,
I3 => x(14),
I4 => x(16),
I5 => x(17),
O => \y2_carry_i_5__0_n_0\
);
y2_carry_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0111111154444444"
)
port map (
I0 => x(15),
I1 => x(13),
I2 => x(10),
I3 => x(11),
I4 => x(12),
I5 => x(14),
O => y2_carry_i_6_n_0
);
y2_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"006A"
)
port map (
I0 => x(12),
I1 => x(11),
I2 => x(10),
I3 => x(13),
O => y2_carry_i_7_n_0
);
y2_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => x(11),
I1 => x(10),
O => y2_carry_i_8_n_0
);
y2_carry_i_9: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => x(12),
I1 => x(11),
I2 => x(10),
O => \y_8__s_net_1\
);
\y[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[25]_0\,
I2 => x(10),
I3 => \x[22]_1\,
I4 => \y[0]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(0)
);
\y[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFB"
)
port map (
I0 => \y[2]_INST_0_i_4_n_0\,
I1 => x(0),
I2 => x(10),
I3 => y2,
I4 => O(0),
O => \y[0]_INST_0_i_2_n_0\
);
\y[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[27]\,
I2 => x(10),
I3 => \x[25]_0\,
I4 => \y[1]_INST_0_i_2_n_0\,
I5 => \y[9]_INST_0_i_4_n_0\,
O => y(1)
);
\y[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4F7FFFFFFFF"
)
port map (
I0 => x(0),
I1 => x(10),
I2 => \y[9]_INST_0_i_10_n_0\,
I3 => x(1),
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[9]_INST_0_i_9_n_0\,
O => \y[1]_INST_0_i_2_n_0\
);
\y[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[21]_0\,
I2 => x(10),
I3 => \x[27]\,
I4 => \y[2]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(2)
);
\y[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFCFAAAA"
)
port map (
I0 => \y[3]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(1),
I3 => \y[2]_INST_0_i_4_n_0\,
I4 => x(10),
I5 => y2,
O => \y[2]_INST_0_i_2_n_0\
);
\y[2]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CFFFCAFA"
)
port map (
I0 => O(2),
I1 => \x[25]_4\,
I2 => y2,
I3 => \x[25]_3\,
I4 => O(1),
O => \y[2]_INST_0_i_4_n_0\
);
\y[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[22]_0\,
I2 => x(10),
I3 => \x[21]_0\,
I4 => \y[3]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(3)
);
\y[3]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[4]_INST_0_i_4_n_0\,
I1 => \y[3]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[3]_INST_0_i_2_n_0\
);
\y[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4FFF7F"
)
port map (
I0 => x(0),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => x(2),
O => \y[3]_INST_0_i_4_n_0\
);
\y[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[21]\,
I2 => x(10),
I3 => \x[22]_0\,
I4 => \y[4]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(4)
);
\y[4]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[5]_INST_0_i_4_n_0\,
I1 => \y[4]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[4]_INST_0_i_2_n_0\
);
\y[4]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4FFF7F"
)
port map (
I0 => x(1),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => x(3),
O => \y[4]_INST_0_i_4_n_0\
);
\y[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510FFFF15101510"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => \x[22]\,
I2 => x(10),
I3 => \x[21]\,
I4 => \y[5]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(5)
);
\y[5]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[6]_INST_0_i_4_n_0\,
I1 => \y[5]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[5]_INST_0_i_2_n_0\
);
\y[5]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47CCFFFF47FF"
)
port map (
I0 => x(2),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(4),
I3 => \y[9]_INST_0_i_9_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => x(0),
O => \y[5]_INST_0_i_4_n_0\
);
\y[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0047FFFF00470047"
)
port map (
I0 => \x_7__s_net_1\,
I1 => x(10),
I2 => \x[22]\,
I3 => \y[7]_INST_0_i_3_n_0\,
I4 => \y[6]_INST_0_i_2_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(6)
);
\y[6]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[7]_INST_0_i_10_n_0\,
I1 => \y[6]_INST_0_i_4_n_0\,
I2 => x(10),
I3 => y2,
O => \y[6]_INST_0_i_2_n_0\
);
\y[6]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47CCFFFF47FF"
)
port map (
I0 => x(3),
I1 => \y[9]_INST_0_i_10_n_0\,
I2 => x(5),
I3 => \y[9]_INST_0_i_9_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => x(1),
O => \y[6]_INST_0_i_4_n_0\
);
\y[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0047FFFF00470047"
)
port map (
I0 => \x[20]\,
I1 => x(10),
I2 => \x_7__s_net_1\,
I3 => \y[7]_INST_0_i_3_n_0\,
I4 => \y[7]_INST_0_i_4_n_0\,
I5 => \y[7]_INST_0_i_5_n_0\,
O => y(7)
);
\y[7]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47FFFFFF4700"
)
port map (
I0 => x(4),
I1 => \y[9]_INST_0_i_9_n_0\,
I2 => x(0),
I3 => \y[9]_INST_0_i_10_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[7]_INST_0_i_15_n_0\,
O => \y[7]_INST_0_i_10_n_0\
);
\y[7]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"50115FDD"
)
port map (
I0 => x(6),
I1 => O(1),
I2 => \x[25]_3\,
I3 => y2,
I4 => x(2),
O => \y[7]_INST_0_i_15_n_0\
);
\y[7]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \x[23]\,
I1 => y2,
O => \y[7]_INST_0_i_3_n_0\
);
\y[7]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFCA"
)
port map (
I0 => \y[8]_INST_0_i_2_n_0\,
I1 => \y[7]_INST_0_i_10_n_0\,
I2 => x(10),
I3 => y2,
O => \y[7]_INST_0_i_4_n_0\
);
\y[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404040405F40"
)
port map (
I0 => \x[23]\,
I1 => \x[27]_0\,
I2 => y2,
I3 => \x[24]\,
I4 => \y[9]_INST_0_i_14_n_0\,
I5 => \x[30]\,
O => \y[7]_INST_0_i_5_n_0\
);
\y[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABFAAAA"
)
port map (
I0 => \y[8]_INST_0_i_1_n_0\,
I1 => \y[8]_INST_0_i_2_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_2_n_0\,
I4 => \y[9]_INST_0_i_4_n_0\,
O => y(8)
);
\y[8]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4501"
)
port map (
I0 => \y[7]_INST_0_i_3_n_0\,
I1 => x(10),
I2 => \x[20]\,
I3 => \x[25]\,
O => \y[8]_INST_0_i_1_n_0\
);
\y[8]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4700FFFF47FF"
)
port map (
I0 => x(5),
I1 => \y[9]_INST_0_i_9_n_0\,
I2 => x(1),
I3 => \y[9]_INST_0_i_10_n_0\,
I4 => \y[9]_INST_0_i_8_n_0\,
I5 => \y[8]_INST_0_i_3_n_0\,
O => \y[8]_INST_0_i_2_n_0\
);
\y[8]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFEEA022"
)
port map (
I0 => x(7),
I1 => O(1),
I2 => \x[25]_3\,
I3 => y2,
I4 => x(3),
O => \y[8]_INST_0_i_3_n_0\
);
\y[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABFAAAA"
)
port map (
I0 => \y[9]_INST_0_i_1_n_0\,
I1 => \y[9]_INST_0_i_2_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_3_n_0\,
I4 => \y[9]_INST_0_i_4_n_0\,
O => y(9)
);
\y[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => \x[25]\,
I1 => x(10),
I2 => \x[25]_1\,
I3 => x(11),
I4 => \x[25]_2\,
I5 => \y[7]_INST_0_i_3_n_0\,
O => \y[9]_INST_0_i_1_n_0\
);
\y[9]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => x(11),
I1 => x(10),
I2 => y2,
I3 => O(0),
O => \y[9]_INST_0_i_10_n_0\
);
\y[9]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5533FF0F"
)
port map (
I0 => x(0),
I1 => x(8),
I2 => x(4),
I3 => \y[9]_INST_0_i_8_n_0\,
I4 => \y[9]_INST_0_i_9_n_0\,
O => \y[9]_INST_0_i_11_n_0\
);
\y[9]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"5353F0FF"
)
port map (
I0 => x(1),
I1 => x(9),
I2 => \y[9]_INST_0_i_8_n_0\,
I3 => x(5),
I4 => \y[9]_INST_0_i_9_n_0\,
O => \y[9]_INST_0_i_12_n_0\
);
\y[9]_INST_0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y2,
I1 => \x[24]_0\(1),
I2 => \x[24]_0\(0),
I3 => \x[24]_0\(2),
I4 => \x[24]_1\,
O => \y[9]_INST_0_i_14_n_0\
);
\y[9]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFBFFFFABFB0000"
)
port map (
I0 => \y[9]_INST_0_i_8_n_0\,
I1 => x(2),
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => x(6),
I4 => \y[9]_INST_0_i_10_n_0\,
I5 => \y[9]_INST_0_i_11_n_0\,
O => \y[9]_INST_0_i_2_n_0\
);
\y[9]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFBFFFFABFB0000"
)
port map (
I0 => \y[9]_INST_0_i_8_n_0\,
I1 => x(3),
I2 => \y[9]_INST_0_i_9_n_0\,
I3 => x(7),
I4 => \y[9]_INST_0_i_10_n_0\,
I5 => \y[9]_INST_0_i_12_n_0\,
O => \y[9]_INST_0_i_3_n_0\
);
\y[9]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \x[24]\,
I1 => \y[9]_INST_0_i_14_n_0\,
I2 => \x[30]\,
O => \y[9]_INST_0_i_4_n_0\
);
\y[9]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => x(13),
I1 => x(10),
I2 => x(11),
I3 => x(12),
I4 => y2,
I5 => O(2),
O => \y[9]_INST_0_i_8_n_0\
);
\y[9]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"3FC05555"
)
port map (
I0 => O(1),
I1 => x(11),
I2 => x(10),
I3 => x(12),
I4 => y2,
O => \y[9]_INST_0_i_9_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_to_uint_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_to_uint_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_to_uint_0_0 : entity is "affine_block_ieee754_fp_to_uint_0_1,ieee754_fp_to_uint,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_to_uint_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_to_uint_0_0 : entity is "ieee754_fp_to_uint,Vivado 2016.4";
end affine_block_ieee754_fp_to_uint_0_0;
architecture STRUCTURE of affine_block_ieee754_fp_to_uint_0_0 is
signal U0_n_10 : STD_LOGIC;
signal y4 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \y[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_1\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_4\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_5\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_6\ : STD_LOGIC;
signal \y[0]_INST_0_i_5_n_7\ : STD_LOGIC;
signal \y[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \y[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_20_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_21_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_22_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_25_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_27_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_1\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_2\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_4\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_5\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_28_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_3\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_6\ : STD_LOGIC;
signal \y[9]_INST_0_i_42_n_7\ : STD_LOGIC;
signal \y[9]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \NLW_y[9]_INST_0_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y[9]_INST_0_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[0]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[1]_INST_0_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[2]_INST_0_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[3]_INST_0_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \y[4]_INST_0_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \y[5]_INST_0_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \y[6]_INST_0_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_12\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_13\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[7]_INST_0_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_17\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_18\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_19\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[9]_INST_0_i_5\ : label is "soft_lutpair9";
begin
U0: entity work.affine_block_ieee754_fp_to_uint_0_0_ieee754_fp_to_uint
port map (
O(2) => \y[0]_INST_0_i_5_n_5\,
O(1) => \y[0]_INST_0_i_5_n_6\,
O(0) => \y[0]_INST_0_i_5_n_7\,
x(17 downto 10) => x(30 downto 23),
x(9 downto 0) => x(9 downto 0),
\x[20]\ => \y[7]_INST_0_i_1_n_0\,
\x[21]\ => \y[5]_INST_0_i_1_n_0\,
\x[21]_0\ => \y[3]_INST_0_i_1_n_0\,
\x[22]\ => \y[6]_INST_0_i_1_n_0\,
\x[22]_0\ => \y[4]_INST_0_i_1_n_0\,
\x[22]_1\ => \y[0]_INST_0_i_1_n_0\,
\x[23]\ => \y[7]_INST_0_i_9_n_0\,
\x[24]\ => \y[9]_INST_0_i_13_n_0\,
\x[24]_0\(2) => \y[9]_INST_0_i_25_n_4\,
\x[24]_0\(1) => \y[9]_INST_0_i_25_n_5\,
\x[24]_0\(0) => \y[9]_INST_0_i_25_n_7\,
\x[24]_1\ => \y[9]_INST_0_i_26_n_0\,
\x[25]\ => \y[9]_INST_0_i_5_n_0\,
\x[25]_0\ => \y[1]_INST_0_i_1_n_0\,
\x[25]_1\ => \y[9]_INST_0_i_6_n_0\,
\x[25]_2\ => \y[9]_INST_0_i_7_n_0\,
\x[25]_3\ => \y[9]_INST_0_i_17_n_0\,
\x[25]_4\ => \y[9]_INST_0_i_18_n_0\,
\x[27]\ => \y[2]_INST_0_i_1_n_0\,
\x[27]_0\ => \y[7]_INST_0_i_11_n_0\,
\x[30]\ => \y[9]_INST_0_i_15_n_0\,
\x_7__s_port_\ => \y[7]_INST_0_i_2_n_0\,
y(9 downto 0) => y(9 downto 0),
\y_8__s_port_\ => U0_n_10
);
\y[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFB8B8FF00B8B800"
)
port map (
I0 => \y[0]_INST_0_i_3_n_0\,
I1 => x(25),
I2 => \y[0]_INST_0_i_4_n_0\,
I3 => x(23),
I4 => x(24),
I5 => \y[2]_INST_0_i_3_n_0\,
O => \y[0]_INST_0_i_1_n_0\
);
\y[0]_INST_0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => x(23),
I1 => x(24),
O => y4(1)
);
\y[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(8),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(0),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(16),
O => \y[0]_INST_0_i_3_n_0\
);
\y[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(12),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(4),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(20),
O => \y[0]_INST_0_i_4_n_0\
);
\y[0]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y[0]_INST_0_i_5_n_0\,
CO(2) => \y[0]_INST_0_i_5_n_1\,
CO(1) => \y[0]_INST_0_i_5_n_2\,
CO(0) => \y[0]_INST_0_i_5_n_3\,
CYINIT => y4(0),
DI(3 downto 0) => B"0000",
O(3) => \y[0]_INST_0_i_5_n_4\,
O(2) => \y[0]_INST_0_i_5_n_5\,
O(1) => \y[0]_INST_0_i_5_n_6\,
O(0) => \y[0]_INST_0_i_5_n_7\,
S(3) => \y[0]_INST_0_i_7_n_0\,
S(2) => \y[0]_INST_0_i_8_n_0\,
S(1) => \y[0]_INST_0_i_9_n_0\,
S(0) => y4(1)
);
\y[0]_INST_0_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x(23),
O => y4(0)
);
\y[0]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"1555EAAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
I4 => x(27),
O => \y[0]_INST_0_i_7_n_0\
);
\y[0]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"807F"
)
port map (
I0 => x(25),
I1 => x(24),
I2 => x(23),
I3 => x(26),
O => \y[0]_INST_0_i_8_n_0\
);
\y[0]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => x(24),
I1 => x(23),
I2 => x(25),
O => \y[0]_INST_0_i_9_n_0\
);
\y[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFB8B8FF00B8B800"
)
port map (
I0 => \y[1]_INST_0_i_3_n_0\,
I1 => x(25),
I2 => \y[1]_INST_0_i_4_n_0\,
I3 => x(23),
I4 => x(24),
I5 => \y[3]_INST_0_i_3_n_0\,
O => \y[1]_INST_0_i_1_n_0\
);
\y[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(9),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(1),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(17),
O => \y[1]_INST_0_i_3_n_0\
);
\y[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(13),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(5),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(21),
O => \y[1]_INST_0_i_4_n_0\
);
\y[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[2]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[4]_INST_0_i_3_n_0\,
O => \y[2]_INST_0_i_1_n_0\
);
\y[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EABF2A80"
)
port map (
I0 => \y[2]_INST_0_i_5_n_0\,
I1 => x(24),
I2 => x(23),
I3 => x(25),
I4 => \y[6]_INST_0_i_5_n_0\,
O => \y[2]_INST_0_i_3_n_0\
);
\y[2]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(10),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(2),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(18),
O => \y[2]_INST_0_i_5_n_0\
);
\y[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[3]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[5]_INST_0_i_3_n_0\,
O => \y[3]_INST_0_i_1_n_0\
);
\y[3]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAACF0FC00F"
)
port map (
I0 => \y[3]_INST_0_i_5_n_0\,
I1 => x(15),
I2 => \y[9]_INST_0_i_18_n_0\,
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(7),
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[3]_INST_0_i_3_n_0\
);
\y[3]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(11),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(3),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(19),
O => \y[3]_INST_0_i_5_n_0\
);
\y[4]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[4]_INST_0_i_3_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[6]_INST_0_i_3_n_0\,
O => \y[4]_INST_0_i_1_n_0\
);
\y[4]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8888888"
)
port map (
I0 => \y[0]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(16),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(8),
O => \y[4]_INST_0_i_3_n_0\
);
\y[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7D41"
)
port map (
I0 => \y[7]_INST_0_i_8_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[5]_INST_0_i_3_n_0\,
O => \y[5]_INST_0_i_1_n_0\
);
\y[5]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8888888B88888"
)
port map (
I0 => \y[1]_INST_0_i_4_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(9),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(17),
O => \y[5]_INST_0_i_3_n_0\
);
\y[6]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"82BE"
)
port map (
I0 => \y[7]_INST_0_i_6_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[6]_INST_0_i_3_n_0\,
O => \y[6]_INST_0_i_1_n_0\
);
\y[6]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8888888B88888"
)
port map (
I0 => \y[6]_INST_0_i_5_n_0\,
I1 => \y[9]_INST_0_i_17_n_0\,
I2 => x(10),
I3 => \y[9]_INST_0_i_18_n_0\,
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => x(18),
O => \y[6]_INST_0_i_3_n_0\
);
\y[6]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(14),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => x(6),
I3 => \y[7]_INST_0_i_11_n_0\,
I4 => x(22),
O => \y[6]_INST_0_i_5_n_0\
);
\y[7]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5CC5"
)
port map (
I0 => \y[9]_INST_0_i_7_n_0\,
I1 => \y[7]_INST_0_i_6_n_0\,
I2 => x(23),
I3 => x(24),
O => \y[7]_INST_0_i_1_n_0\
);
\y[7]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"1555EAAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
I4 => x(27),
O => \y[7]_INST_0_i_11_n_0\
);
\y[7]_INST_0_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(12),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(20),
O => \y[7]_INST_0_i_12_n_0\
);
\y[7]_INST_0_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(9),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(17),
O => \y[7]_INST_0_i_13_n_0\
);
\y[7]_INST_0_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"4C7C"
)
port map (
I0 => x(15),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(7),
O => \y[7]_INST_0_i_14_n_0\
);
\y[7]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5CC5"
)
port map (
I0 => \y[7]_INST_0_i_7_n_0\,
I1 => \y[7]_INST_0_i_8_n_0\,
I2 => x(23),
I3 => x(24),
O => \y[7]_INST_0_i_2_n_0\
);
\y[7]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F7F4F7F0000FFFF"
)
port map (
I0 => x(16),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(8),
I4 => \y[7]_INST_0_i_12_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_6_n_0\
);
\y[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000B080B080"
)
port map (
I0 => x(21),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(13),
I4 => \y[7]_INST_0_i_13_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_7_n_0\
);
\y[7]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00001FDF1FDF"
)
port map (
I0 => x(11),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(19),
I4 => \y[7]_INST_0_i_14_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[7]_INST_0_i_8_n_0\
);
\y[7]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBFFFFFFFFDDDDD"
)
port map (
I0 => x(30),
I1 => x(28),
I2 => x(26),
I3 => U0_n_10,
I4 => x(27),
I5 => x(29),
O => \y[7]_INST_0_i_9_n_0\
);
\y[9]_INST_0_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \y[9]_INST_0_i_20_n_4\,
I1 => \y[9]_INST_0_i_21_n_6\,
I2 => \y[9]_INST_0_i_20_n_6\,
I3 => \y[9]_INST_0_i_22_n_6\,
I4 => \y[9]_INST_0_i_23_n_0\,
I5 => \y[9]_INST_0_i_24_n_0\,
O => \y[9]_INST_0_i_13_n_0\
);
\y[9]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \y[9]_INST_0_i_27_n_7\,
I1 => \y[9]_INST_0_i_27_n_6\,
I2 => \y[9]_INST_0_i_28_n_6\,
I3 => \y[9]_INST_0_i_21_n_5\,
I4 => \y[9]_INST_0_i_29_n_0\,
O => \y[9]_INST_0_i_15_n_0\
);
\y[9]_INST_0_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"CACA0000FFF00000"
)
port map (
I0 => x(11),
I1 => x(19),
I2 => \y[9]_INST_0_i_18_n_0\,
I3 => x(15),
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[9]_INST_0_i_16_n_0\
);
\y[9]_INST_0_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => x(24),
I1 => x(23),
I2 => x(25),
O => \y[9]_INST_0_i_17_n_0\
);
\y[9]_INST_0_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => x(26),
I1 => x(23),
I2 => x(24),
I3 => x(25),
O => \y[9]_INST_0_i_18_n_0\
);
\y[9]_INST_0_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"E020"
)
port map (
I0 => x(10),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(18),
O => \y[9]_INST_0_i_19_n_0\
);
\y[9]_INST_0_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_27_n_0\,
CO(3) => \y[9]_INST_0_i_20_n_0\,
CO(2) => \y[9]_INST_0_i_20_n_1\,
CO(1) => \y[9]_INST_0_i_20_n_2\,
CO(0) => \y[9]_INST_0_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_20_n_4\,
O(2) => \y[9]_INST_0_i_20_n_5\,
O(1) => \y[9]_INST_0_i_20_n_6\,
O(0) => \y[9]_INST_0_i_20_n_7\,
S(3) => \y[9]_INST_0_i_30_n_0\,
S(2) => \y[9]_INST_0_i_31_n_0\,
S(1) => \y[9]_INST_0_i_32_n_0\,
S(0) => \y[9]_INST_0_i_33_n_0\
);
\y[9]_INST_0_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_28_n_0\,
CO(3) => \y[9]_INST_0_i_21_n_0\,
CO(2) => \y[9]_INST_0_i_21_n_1\,
CO(1) => \y[9]_INST_0_i_21_n_2\,
CO(0) => \y[9]_INST_0_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_21_n_4\,
O(2) => \y[9]_INST_0_i_21_n_5\,
O(1) => \y[9]_INST_0_i_21_n_6\,
O(0) => \y[9]_INST_0_i_21_n_7\,
S(3) => \y[9]_INST_0_i_34_n_0\,
S(2) => \y[9]_INST_0_i_35_n_0\,
S(1) => \y[9]_INST_0_i_36_n_0\,
S(0) => \y[9]_INST_0_i_37_n_0\
);
\y[9]_INST_0_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_20_n_0\,
CO(3) => \y[9]_INST_0_i_22_n_0\,
CO(2) => \y[9]_INST_0_i_22_n_1\,
CO(1) => \y[9]_INST_0_i_22_n_2\,
CO(0) => \y[9]_INST_0_i_22_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_22_n_4\,
O(2) => \y[9]_INST_0_i_22_n_5\,
O(1) => \y[9]_INST_0_i_22_n_6\,
O(0) => \y[9]_INST_0_i_22_n_7\,
S(3) => \y[9]_INST_0_i_38_n_0\,
S(2) => \y[9]_INST_0_i_39_n_0\,
S(1) => \y[9]_INST_0_i_40_n_0\,
S(0) => \y[9]_INST_0_i_41_n_0\
);
\y[9]_INST_0_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_42_n_6\,
I1 => \y[9]_INST_0_i_22_n_4\,
I2 => \y[9]_INST_0_i_42_n_7\,
I3 => \y[9]_INST_0_i_25_n_6\,
O => \y[9]_INST_0_i_23_n_0\
);
\y[9]_INST_0_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_27_n_5\,
I1 => \y[0]_INST_0_i_5_n_4\,
I2 => \y[9]_INST_0_i_28_n_4\,
I3 => \y[9]_INST_0_i_22_n_5\,
O => \y[9]_INST_0_i_24_n_0\
);
\y[9]_INST_0_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_21_n_0\,
CO(3) => \y[9]_INST_0_i_25_n_0\,
CO(2) => \y[9]_INST_0_i_25_n_1\,
CO(1) => \y[9]_INST_0_i_25_n_2\,
CO(0) => \y[9]_INST_0_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_25_n_4\,
O(2) => \y[9]_INST_0_i_25_n_5\,
O(1) => \y[9]_INST_0_i_25_n_6\,
O(0) => \y[9]_INST_0_i_25_n_7\,
S(3) => \y[9]_INST_0_i_43_n_0\,
S(2) => \y[9]_INST_0_i_44_n_0\,
S(1) => \y[9]_INST_0_i_45_n_0\,
S(0) => \y[9]_INST_0_i_46_n_0\
);
\y[9]_INST_0_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_20_n_7\,
I1 => \y[9]_INST_0_i_27_n_4\,
I2 => \y[9]_INST_0_i_28_n_5\,
I3 => \y[9]_INST_0_i_22_n_7\,
O => \y[9]_INST_0_i_26_n_0\
);
\y[9]_INST_0_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y[0]_INST_0_i_5_n_0\,
CO(3) => \y[9]_INST_0_i_27_n_0\,
CO(2) => \y[9]_INST_0_i_27_n_1\,
CO(1) => \y[9]_INST_0_i_27_n_2\,
CO(0) => \y[9]_INST_0_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_27_n_4\,
O(2) => \y[9]_INST_0_i_27_n_5\,
O(1) => \y[9]_INST_0_i_27_n_6\,
O(0) => \y[9]_INST_0_i_27_n_7\,
S(3) => \y[9]_INST_0_i_47_n_0\,
S(2) => \y[9]_INST_0_i_48_n_0\,
S(1) => \y[9]_INST_0_i_49_n_0\,
S(0) => \y[9]_INST_0_i_50_n_0\
);
\y[9]_INST_0_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_22_n_0\,
CO(3) => \y[9]_INST_0_i_28_n_0\,
CO(2) => \y[9]_INST_0_i_28_n_1\,
CO(1) => \y[9]_INST_0_i_28_n_2\,
CO(0) => \y[9]_INST_0_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y[9]_INST_0_i_28_n_4\,
O(2) => \y[9]_INST_0_i_28_n_5\,
O(1) => \y[9]_INST_0_i_28_n_6\,
O(0) => \y[9]_INST_0_i_28_n_7\,
S(3) => \y[9]_INST_0_i_51_n_0\,
S(2) => \y[9]_INST_0_i_52_n_0\,
S(1) => \y[9]_INST_0_i_53_n_0\,
S(0) => \y[9]_INST_0_i_54_n_0\
);
\y[9]_INST_0_i_29\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \y[9]_INST_0_i_28_n_7\,
I1 => \y[9]_INST_0_i_20_n_5\,
I2 => \y[9]_INST_0_i_21_n_4\,
I3 => \y[9]_INST_0_i_21_n_7\,
O => \y[9]_INST_0_i_29_n_0\
);
\y[9]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_30_n_0\
);
\y[9]_INST_0_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_31_n_0\
);
\y[9]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_32_n_0\
);
\y[9]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_33_n_0\
);
\y[9]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_34_n_0\
);
\y[9]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_35_n_0\
);
\y[9]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_36_n_0\
);
\y[9]_INST_0_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_37_n_0\
);
\y[9]_INST_0_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_38_n_0\
);
\y[9]_INST_0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_39_n_0\
);
\y[9]_INST_0_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_40_n_0\
);
\y[9]_INST_0_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_41_n_0\
);
\y[9]_INST_0_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \y[9]_INST_0_i_25_n_0\,
CO(3 downto 1) => \NLW_y[9]_INST_0_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y[9]_INST_0_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y[9]_INST_0_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \y[9]_INST_0_i_42_n_6\,
O(0) => \y[9]_INST_0_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \y[9]_INST_0_i_55_n_0\,
S(0) => \y[9]_INST_0_i_56_n_0\
);
\y[9]_INST_0_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_43_n_0\
);
\y[9]_INST_0_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_44_n_0\
);
\y[9]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_45_n_0\
);
\y[9]_INST_0_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_46_n_0\
);
\y[9]_INST_0_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_47_n_0\
);
\y[9]_INST_0_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"00001115FFFFEEEA"
)
port map (
I0 => x(29),
I1 => x(27),
I2 => U0_n_10,
I3 => x(26),
I4 => x(28),
I5 => x(30),
O => \y[9]_INST_0_i_48_n_0\
);
\y[9]_INST_0_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA9995"
)
port map (
I0 => x(29),
I1 => x(27),
I2 => U0_n_10,
I3 => x(26),
I4 => x(28),
O => \y[9]_INST_0_i_49_n_0\
);
\y[9]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"EB28"
)
port map (
I0 => \y[7]_INST_0_i_7_n_0\,
I1 => x(23),
I2 => x(24),
I3 => \y[9]_INST_0_i_16_n_0\,
O => \y[9]_INST_0_i_5_n_0\
);
\y[9]_INST_0_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999955555555"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => x(23),
I3 => x(24),
I4 => x(25),
I5 => x(27),
O => \y[9]_INST_0_i_50_n_0\
);
\y[9]_INST_0_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_51_n_0\
);
\y[9]_INST_0_i_52\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_52_n_0\
);
\y[9]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_53_n_0\
);
\y[9]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_54_n_0\
);
\y[9]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_55_n_0\
);
\y[9]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000155FFFFFFFF"
)
port map (
I0 => x(28),
I1 => x(26),
I2 => U0_n_10,
I3 => x(27),
I4 => x(29),
I5 => x(30),
O => \y[9]_INST_0_i_56_n_0\
);
\y[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0C00000AFA00000"
)
port map (
I0 => x(12),
I1 => x(20),
I2 => \y[9]_INST_0_i_17_n_0\,
I3 => x(16),
I4 => \y[7]_INST_0_i_11_n_0\,
I5 => \y[9]_INST_0_i_18_n_0\,
O => \y[9]_INST_0_i_6_n_0\
);
\y[9]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000B080B080"
)
port map (
I0 => x(22),
I1 => \y[9]_INST_0_i_18_n_0\,
I2 => \y[7]_INST_0_i_11_n_0\,
I3 => x(14),
I4 => \y[9]_INST_0_i_19_n_0\,
I5 => \y[9]_INST_0_i_17_n_0\,
O => \y[9]_INST_0_i_7_n_0\
);
end STRUCTURE;
|
-- This module make the input visible to the output just for one clock cycle
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic);
END SYNC_LATCH;
ARCHITECTURE structural_description OF SYNC_LATCH IS
COMPONENT ffd IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
SIGNAL d_sync : std_logic;
SIGNAL sync : std_logic;
BEGIN
FFD_OUT : ffd PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
D => d_sync,
Q => DOUT);
FFD_SYNC : ffd PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
D => DIN,
Q => sync);
d_sync <= DIN AND NOT(sync);
END structural_description;
|
entity foo is end;
architecture bar of foo is
constant A : std.standard.FILE_OPEN_KIND;
constant B : FILE_OPEN_KIND := READ_MODE;
constant C : FILE_OPEN_KIND := WRITE_MODE;
constant D : FILE_OPEN_KIND := APPEND_MODE;
begin end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_b
--
-- Generated
-- by: wig
-- on: Thu Oct 20 06:53:04 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_b-e.vhd,v 1.2 2005/12/14 12:49:24 wig Exp $
-- $Date: 2005/12/14 12:49:24 $
-- $Log: ent_b-e.vhd,v $
-- Revision 1.2 2005/12/14 12:49:24 wig
-- Updated some testcases (verilog, padio)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.38 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_b
--
entity ent_b is
-- Generics:
-- No Generated Generics for Entity ent_b
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_b
x_des_01 : out std_ulogic; -- des_01 lengthy comment
a_des_02 : out std_ulogic; -- des_02 0123456789 0123456789 0123456789
k_des_03 : out std_ulogic; -- des_03 0123456789
-- des_03 0123456789
-- des_03 0123456789
d_des_04 : out std_ulogic; -- des_04 0TEST_MACRO123456789 0123456789
v_des_05 : out std_ulogic; -- des_05 0123456789 0TEST_MACRO123456789 0123456789
t_des_06 : out std_ulogic; -- des_06 0123456789 0123456TEST_MACRO789 0123456789
b_des_07 : out std_ulogic; -- des_07 0123456789 0123456789TEST_MACRO 0123456789
c_des_08 : out std_ulogic; -- des_08 0123456789
-- des_08 0TEST_MACRO123456789
-- des_08 0123456789
c_des__09 : out std_ulogic; -- des_09 0123456789
-- des_09 0123456TEST_MACRO789
-- des_09 0123456789
c_des_10 : out std_ulogic -- des10 0123456789
-- des_10 0123456789TEST_MACRO
-- des_10 0123456789
-- End of Generated Port for Entity ent_b
);
end ent_b;
--
-- End of Generated Entity ent_b
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
carry : in std_logic;
Salida : out STD_LOGIC_VECTOR (31 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(ALUOP,Oper1,Oper2)
begin
case ALUOP is
when "000000" => --ADD
Salida <= Oper1 + Oper2;
when "000001" => --SUB
Salida <= Oper1 - Oper2;
when "000010" => --AND
Salida <= Oper1 and Oper2;
when "000011" => --ANDN
Salida <= Oper1 and not Oper2;
when "000100" => --OR
Salida <= Oper1 or Oper2;
when "000101" => --ORN
Salida <= Oper1 or not Oper2;
when "000110" => --XOR
Salida <= Oper1 xor Oper2;
when "000111" => --XNOR
Salida <= Oper1 xnor Oper2;
when "001000" => --SUBcc
Salida <= Oper1 - Oper2;
when "001001" => -- SUBx
Salida <= Oper1 - Oper2 - Carry;
when "001010" => --SUBxcc
Salida <= Oper1 - Oper2 - Carry;
when "001011" => --ANDcc
Salida <= Oper1 and Oper2;
when "001100" => --ANDNcc
Salida <= Oper1 and not Oper2;
when "001101" => --ORcc
Salida <= Oper1 or Oper2;
when "001110" => --ORNcc
Salida <= Oper1 or not Oper2;
when "001111" => --XORcc
Salida <= Oper1 xor Oper2;
when "010000" => --XNORcc
Salida <= Oper1 xnor Oper2;
when "010001" => --ADDx
Salida <= Oper1 + Oper2 + Carry;
when "010010" => --ADDxcc
Salida <= Oper1 + Oper2 + Carry;
when "010011" => --ADDcc
Salida <= Oper1 + Oper2;
when "100101" => --sll
Salida <= std_logic_vector(unsigned(Oper1) sll to_integer(unsigned(Oper2)));
when "100110" => --srl
Salida <= std_logic_vector(unsigned(Oper1) srl to_integer(unsigned(Oper2)));
--SAVE 57
when "111001" => Salida <= Oper1 + Oper2;
--RESTORE 58
when "111101" => Salida <= Oper1 + Oper2;
when others =>
Salida <= (others=>'1'); --error
end case;
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_17a is
end entity inline_17a;
----------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
architecture test of inline_17a is
-- code from book:
nature electrical_bus is record
strobe : electrical;
bus_lines : electrical_vector(0 to 15);
end record electrical_bus;
terminal address_bus, data_bus : electrical_bus;
quantity data_voltages across data_currents through data_bus;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_17a is
end entity inline_17a;
----------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
architecture test of inline_17a is
-- code from book:
nature electrical_bus is record
strobe : electrical;
bus_lines : electrical_vector(0 to 15);
end record electrical_bus;
terminal address_bus, data_bus : electrical_bus;
quantity data_voltages across data_currents through data_bus;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_17a is
end entity inline_17a;
----------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
architecture test of inline_17a is
-- code from book:
nature electrical_bus is record
strobe : electrical;
bus_lines : electrical_vector(0 to 15);
end record electrical_bus;
terminal address_bus, data_bus : electrical_bus;
quantity data_voltages across data_currents through data_bus;
-- end of code from book
begin
end architecture test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library hdl_library_CommonFunctions;
use hdl_library_CommonFunctions.MathHelpers.all;
--library hdl_library_CommonFunctions;
--use hdl_library_CommonFunctions.CommonFunctions.all;
entity SignalGenerator is
generic
(
G_CLOCK_FREQUENCY : integer;
G_SIGNAL_OUTPUT_RESOLUTION : integer;
G_CLOCK_COUNTER : integer;
G_SIGNAL_SHAPE : integer
);
port
(
clock : in std_logic;
enable : in std_logic;
output_signal : out std_logic_vector(G_SIGNAL_OUTPUT_RESOLUTION - 1 downto 0);
dirac_index : in integer
--ready : out std_logic
);
end entity; --SignalGenerator
architecture arch of SignalGenerator is
signal i_saw_counter : std_logic_vector(G_SIGNAL_OUTPUT_RESOLUTION - 1 downto 0) := (others => '0');
signal i_phase_counter : std_logic_vector(G_SIGNAL_OUTPUT_RESOLUTION - 1 downto 0) := (others => '0');
signal i_sine : std_logic_vector(G_SIGNAL_OUTPUT_RESOLUTION - 1 downto 0) := (others => '0');
signal i_dirac : std_logic_vector(G_SIGNAL_OUTPUT_RESOLUTION - 1 downto 0) := (others => '0');
signal i_clock_counter : std_logic_vector(log2(G_CLOCK_COUNTER)- 1 downto 0) := (others => '0');
begin
signal_type_saw: if G_SIGNAL_SHAPE = 0 generate
saw_counter:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
i_saw_counter <= i_saw_counter + 1;
end if;
output_signal <= i_saw_counter;
end if;
end process saw_counter; -- saw_counter
end generate signal_type_saw;
signal_type_sine: if G_SIGNAL_SHAPE = 1 generate
phase_counter:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
i_phase_counter <= i_phase_counter + 1;
end if;
end if;
end process phase_counter; -- phase_counter
sine_generator:process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
i_sine <= i_saw_counter + 1;
end if;
output_signal <= i_saw_counter;
end if;
end process sine_generator; -- saw_counter
end generate signal_type_sine;
signal_type_triangle: if G_SIGNAL_SHAPE = 2 generate
end generate signal_type_triangle;
signal_type_square: if G_SIGNAL_SHAPE = 3 generate
end generate signal_type_square;
signal_type_random: if G_SIGNAL_SHAPE = 4 generate
end generate signal_type_random;
signal_type_dirac: if G_SIGNAL_SHAPE = 5 generate
clock_counter:process(clock)
begin
if rising_edge(clock) then
i_dirac <= (others => '0');
if enable = '1' then
i_clock_counter <= i_clock_counter + 1;
if i_clock_counter = dirac_index - 1 then
i_dirac <= (others => '1');
else
end if;
end if;
output_signal <= i_dirac;
end if;
end process clock_counter; -- clock_counter
end generate signal_type_dirac;
end architecture; -- arch |
-------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is
end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is
component includeModuleVHDL is
end component;
signal probe : STD_LOGIC;
begin -- architectureecture Behavioral
probe <= '1';
include_module : includeModuleVHDL;
a : entity work.includeModuleAVHDL;
GEN : for i in 0 to 3 generate
B : entity work.includeModuleBVHDL;
end generate;
end architecture Behavioral;
|
architecture RTL of FIFO is
begin
end architecture RTL;
|
architecture RTL of FIFO is
begin
end architecture RTL;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_00_2 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_00_2;
ARCHITECTURE sys_axi_nic_00_2_arch OF sys_axi_nic_00_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_00_2_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_00_2_arch;
|
architecture RTL of FIFO is
begin
PROC_LABEL : process is
begin
end process PROC_LABEL;
-- Violations below
PROC_LABEL : process is
begin
end process proc_label;
end architecture RTL;
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
VudTi0E47xsjLsifh/4s4osrP2o76TRMiI25ZT+8lI+8vz5fNZYvjI6EP4aR+TUGluvHrQSgQ4Cc
eraypIE+mA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10656)
`protect data_block
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qdOFSMaHy3eaOtis4cG1o8CBNp902QN7qJhb6EdWMU6Exoqu6uFaUA/DgXdQS4R/AZyp5o2o
`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc347.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p15n01i00347ent IS
END c03s02b01x00p15n01i00347ent;
ARCHITECTURE c03s02b01x00p15n01i00347arch OF c03s02b01x00p15n01i00347ent IS
type MEM is array(5 downto 0) of BIT; -- No_failure_here
signal S1 : MEM := "000000";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(S1(4 downto 3) = "00")
report "***PASSED TEST: c03s02b01x00p15n01i00347"
severity NOTE;
assert (S1(4 downto 3) = "00")
report "***FAILED TEST: c03s02b01x00p15n01i00347 - The direction of the discrete range is the same as the direction of the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p15n01i00347arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc347.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p15n01i00347ent IS
END c03s02b01x00p15n01i00347ent;
ARCHITECTURE c03s02b01x00p15n01i00347arch OF c03s02b01x00p15n01i00347ent IS
type MEM is array(5 downto 0) of BIT; -- No_failure_here
signal S1 : MEM := "000000";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(S1(4 downto 3) = "00")
report "***PASSED TEST: c03s02b01x00p15n01i00347"
severity NOTE;
assert (S1(4 downto 3) = "00")
report "***FAILED TEST: c03s02b01x00p15n01i00347 - The direction of the discrete range is the same as the direction of the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p15n01i00347arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc347.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p15n01i00347ent IS
END c03s02b01x00p15n01i00347ent;
ARCHITECTURE c03s02b01x00p15n01i00347arch OF c03s02b01x00p15n01i00347ent IS
type MEM is array(5 downto 0) of BIT; -- No_failure_here
signal S1 : MEM := "000000";
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(S1(4 downto 3) = "00")
report "***PASSED TEST: c03s02b01x00p15n01i00347"
severity NOTE;
assert (S1(4 downto 3) = "00")
report "***FAILED TEST: c03s02b01x00p15n01i00347 - The direction of the discrete range is the same as the direction of the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p15n01i00347arch;
|
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Wrapper for everything USB
-------------------------------------------------------------------------------------
--Communicates over an USB UART port
--Implements a simple request-response protocol
--The commands from the PC -> response from token
--
--*I -> *IHEJ (ID)
--*W[64 byte] -> *D if successful, *T if timeout, *B if device busy with other task
--*R -> *M[64 byte] if data ready, *B if device busy with other task
--
-------------------------------------------------------------------------------------
entity USB_TOP is
generic ( data_addr_width : integer := 6;
BAUD_RATE : integer := 115200; --baud of 115200
CLOCK_RATE : integer := 100_000_000; --100MHz
OVERSAMPLES : integer := 4);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TXD : out STD_LOGIC;
RXD : in STD_LOGIC;
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0);
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
RAM_WE : out STD_LOGIC;
READY_FOR_DATA : in STD_LOGIC;
RSA_DONE : in STD_LOGIC;
DATA_READY : out STD_LOGIC);
end USB_TOP;
architecture Behavioral of USB_TOP is
component FIFO_TXD IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component TXD_Controller is
Generic (BAUD_RATE : integer := BAUD_RATE; --baud of 115200
CLOCK_RATE : integer := CLOCK_RATE; --100MHz
OVERSAMPLES : integer := OVERSAMPLES);
Port ( CLK : in STD_LOGIC; --Global clock
RESET : in STD_LOGIC; --reset signal (synchronous)
TXD_PIN : out STD_LOGIC; --data pin
FIFO_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); --byte from FIFO
FIFO_READ : out STD_LOGIC; --Read next signal to the FIFO
FIFO_EMPTY : in STD_LOGIC); --Flag from FIFO to signal if the FIFO is empty or not
end component;
component RXD_Controller is
Generic (Baud_Rate : integer := BAUD_RATE; --Baud of 115200
CLOCK_RATE : integer := CLOCK_RATE; --100MHz
OVERSAMPLES : integer := OVERSAMPLES);
Port(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RXD_PIN : in STD_LOGIC;
RXD_BYTE : out STD_LOGIC_VECTOR(7 downto 0);
VALID_DATA_IN : out STD_LOGIC);
end component;
component USB_CMD_PARSER is
generic ( data_addr_width : integer := data_addr_width;
Frequency : integer := CLOCK_RATE);
Port ( RXD_BYTE : in STD_LOGIC_VECTOR (7 downto 0); --Input byte from the serial-to-parallell translator
TXD_BYTE : out STD_LOGIC_VECTOR (7 downto 0); --Output byte to the parallell-to-serial translator
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0); --RAM ADDR where the RSA (signed) message is
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); --DATA from the active RAM cell
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0); --DATA to be written to active RAM cell if WE is high
VALID_DATA_IN : in STD_LOGIC; --Flag to the parallell-to-serial translator to tell it that there's a new byte on the bus
VALID_DATA_OUT : out STD_LOGIC; --Flag from the serial-to-parallell translator to tell that there's a new byte on the bus
RAM_WE : out STD_LOGIC; --RAM Write Enable flag
RSA_DONE : in STD_LOGIC; --Flag from RSA module that the values in RAM are the signed message
READY_FOR_DATA : in STD_LOGIC; --Flag from RSA module that it is ready to recive a new message to sign
RESET : in STD_LOGIC; --Reset for module. When high all registers and counters resets at next high flank of the clock
CLK : in STD_LOGIC; --Global clock signal
DATA_READY : out STD_LOGIC;
FIFO_EMPTY : in STD_LOGIC);
end component;
signal RXD_BYTE, TXD_BYTE, FIFO_DATA_OUT, FIFO_DATA_IN : STD_LOGIC_VECTOR(7 downto 0);
signal VALID_DATA_IN, VALID_DATA_OUT, FIFO_READ, FIFO_EMPTY : STD_LOGIC;
begin
TXD_CONTRL: TXD_Controller port map(
CLK => CLK,
RESET => RESET,
TXD_PIN => TXD,
FIFO_DATA_IN => FIFO_DATA_OUT, --confusing name. DATA is OUT from FIFO and is IN to TXD
FIFO_READ => FIFO_READ,
FIFO_EMPTY => FIFO_EMPTY
);
RXD_CONTRL: RXD_Controller port map(
CLK => CLK,
RESET => RESET,
RXD_PIN => RXD,
RXD_BYTE => RXD_BYTE,
VALID_DATA_IN => VALID_DATA_IN);
CMD_PARSER: USB_CMD_PARSER port map(
RXD_BYTE => RXD_BYTE,
TXD_BYTE => TXD_BYTE,
RAM_ADDR => RAM_ADDR,
RAM_DATA_IN => RAM_DATA_IN,
RAM_DATA_OUT => RAM_DATA_OUT,
VALID_DATA_IN => VALID_DATA_IN,
VALID_DATA_OUT => VALID_DATA_OUT,
RAM_WE => RAM_WE,
RSA_DONE => RSA_DONE,
READY_FOR_DATA => READY_FOR_DATA,
DATA_READY => DATA_READY,
RESET => RESET,
CLK => CLK,
FIFO_EMPTY => FIFO_EMPTY);
FIFO: FIFO_TXD PORT MAP(
clk => CLK,
rst => RESET,
din => TXD_BYTE,
wr_en => VALID_DATA_OUT,
rd_en => FIFO_READ,
dout => FIFO_DATA_OUT,
full => open,
empty => FIFO_EMPTY
);
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity battery is
port ( terminal plus, minus : electrical );
end entity battery;
architecture wrong of battery is
constant v_nominal : real := 9.0;
quantity v across plus to minus;
begin
v == v_nominal;
end architecture wrong;
--
architecture correct of battery is
constant v_nominal : real := 9.0;
quantity v across i through plus to minus;
begin
v == v_nominal;
end architecture correct;
-- end code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
signal clamp : bit;
quantity v1, v2 : real;
begin
-- code from book
if clamp = '1' use
v1 == 5.0;
v2 == 0.0;
else
v1 == v2;
end use;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity battery is
port ( terminal plus, minus : electrical );
end entity battery;
architecture wrong of battery is
constant v_nominal : real := 9.0;
quantity v across plus to minus;
begin
v == v_nominal;
end architecture wrong;
--
architecture correct of battery is
constant v_nominal : real := 9.0;
quantity v across i through plus to minus;
begin
v == v_nominal;
end architecture correct;
-- end code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
signal clamp : bit;
quantity v1, v2 : real;
begin
-- code from book
if clamp = '1' use
v1 == 5.0;
v2 == 0.0;
else
v1 == v2;
end use;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
-- code from book
entity battery is
port ( terminal plus, minus : electrical );
end entity battery;
architecture wrong of battery is
constant v_nominal : real := 9.0;
quantity v across plus to minus;
begin
v == v_nominal;
end architecture wrong;
--
architecture correct of battery is
constant v_nominal : real := 9.0;
quantity v across i through plus to minus;
begin
v == v_nominal;
end architecture correct;
-- end code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_04a is
end entity inline_04a;
architecture test of inline_04a is
signal clamp : bit;
quantity v1, v2 : real;
begin
-- code from book
if clamp = '1' use
v1 == 5.0;
v2 == 0.0;
else
v1 == v2;
end use;
-- end code from book
end architecture test;
|
-- NEED RESULT: ARCH00501: Aggregates in attribute specifications (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00501
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (9)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00501(ARCH00501)
-- ENT00501_Test_Bench(ARCH00501_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00501 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
constant a11 : boolean := false ;
constant a12 : boolean := true ;
constant a21 : integer := 1 ;
constant a22 : integer := 5 ;
constant b11 : integer := 0 ;
constant b12 : integer := 0 ;
constant b21 : integer := -5 ;
constant b22 : integer := -3 ;
constant c1 : integer := 0 ;
constant c2 : integer := 4 ;
constant d1 : integer := 3 ;
constant d2 : integer := 5 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - r1 to r1 ;
-- f2 : rec_arr (-r1 to r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-r1 to r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range a11 to a12 ;
subtype arange2 is integer range a21 to a22 ;
subtype brange1 is integer range b11 to b12 ;
subtype brange2 is integer range b21 to b22 ;
subtype crange is integer range c1 to c2 ;
subtype drange is integer range d1 to d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00501 ;
--
architecture ARCH00501 of ENT00501 is
begin
B1 :
block
--
begin
process
type dummy is ( d1 , d2 ) ;
attribute a_arr_1 : st_arr_1 ;
attribute a_time_matrix : st_time_matrix ;
attribute a_bit_vector : st_bit_vector ;
attribute a_rec_1 : rec_1 ;
attribute a_string : st_string ;
attribute a_arr_1 of all : type is
( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
attribute a_time_matrix of all : type is
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
attribute a_bit_vector of all : type is
( 0 => '1', 2 => '1', others => '0' ) ;
attribute a_string of all : type is
( 3 => 'a', 4 => 'b', others => '0' ) ;
attribute a_rec_1 of all : type is
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
variable bool : boolean := true ;
--
begin
bool := bool and dummy'a_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and dummy'a_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and dummy'a_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and dummy'a_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and dummy'a_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and dummy'a_bit_vector = B"10100" ;
--
bool := bool and dummy'a_string = "ab0" ;
--
bool := bool and dummy'a_rec_1.f1 = 0 and dummy'a_rec_1.f4 = 0
and dummy'a_rec_1.f3 = 1 ;
-- bool := bool and dummy'a_rec_1.f2(1) = true
-- and dummy'a_rec_1.f2(0) = false and
-- dummy'a_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00501" ,
"Aggregates in attribute specifications"
& " (locally static)" ,
bool ) ;
wait ;
end process ;
end block B1 ;
end ARCH00501 ;
--
entity ENT00501_Test_Bench is
end ENT00501_Test_Bench ;
--
architecture ARCH00501_Test_Bench of ENT00501_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00501 ( ARCH00501 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00501_Test_Bench ;
|
--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
q_invert_mask <= X"80" when q_invert = '1' else X"7f";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
dac_data_o <= (data_from_host_i xor X"7f") & "11";
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity n_register is
generic (
width:integer := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end n_register;
architecture arch of n_register is
signal data : std_logic_vector(width-1 downto 0);
begin
output <= data;
latch: process (clk,input,rst)
begin
if (rst = '1') then
data <= (others=>'0');
else if (clk'event and clk = '1') then
data <= input;
end if;
end if;
end process ;
end arch;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
begin -- process doit
assert( k1 = tboolean'left ) report "TEST FAILED" severity failure;
assert( k2 = tbit'left ) report "TEST FAILED" severity FAILURE;
assert( k3 = tcharacter'left ) report "TEST FAILED" severity FAILURE;
assert( k4 = tseverity_level'left ) report "TEST FAILED" severity FAILURE;
assert( k5 = tinteger'left ) report "TEST FAILED" severity FAILURE;
assert( k6 = treal'left ) report "TEST FAILED" severity FAILURE;
assert( k7 = ttime'left ) report "TEST FAILED" severity FAILURE;
assert( k8 = tnatural'left ) report "TEST FAILED" severity FAILURE;
assert( k9 = tpositive'left ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
begin -- process doit
assert( k1 = tboolean'left ) report "TEST FAILED" severity failure;
assert( k2 = tbit'left ) report "TEST FAILED" severity FAILURE;
assert( k3 = tcharacter'left ) report "TEST FAILED" severity FAILURE;
assert( k4 = tseverity_level'left ) report "TEST FAILED" severity FAILURE;
assert( k5 = tinteger'left ) report "TEST FAILED" severity FAILURE;
assert( k6 = treal'left ) report "TEST FAILED" severity FAILURE;
assert( k7 = ttime'left ) report "TEST FAILED" severity FAILURE;
assert( k8 = tnatural'left ) report "TEST FAILED" severity FAILURE;
assert( k9 = tpositive'left ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
subtype tboolean is boolean range FALSE to TRUE;
subtype tbit is bit range '0' to '1';
subtype tcharacter is character range 'A' to 'Z';
subtype tseverity_level is severity_level range NOTE to ERROR;
subtype tinteger is integer range 1111 to 2222;
subtype treal is real range 1.11 to 2.22;
subtype ttime is time range 1 ns to 1 hr;
subtype tnatural is natural range 100 to 200;
subtype tpositive is positive range 1000 to 2000;
variable k1 : tboolean;
variable k2 : tbit;
variable k3 : tcharacter;
variable k4 : tseverity_level;
variable k5 : tinteger;
variable k6 : treal;
variable k7 : ttime;
variable k8 : tnatural;
variable k9 : tpositive;
begin -- process doit
assert( k1 = tboolean'left ) report "TEST FAILED" severity failure;
assert( k2 = tbit'left ) report "TEST FAILED" severity FAILURE;
assert( k3 = tcharacter'left ) report "TEST FAILED" severity FAILURE;
assert( k4 = tseverity_level'left ) report "TEST FAILED" severity FAILURE;
assert( k5 = tinteger'left ) report "TEST FAILED" severity FAILURE;
assert( k6 = treal'left ) report "TEST FAILED" severity FAILURE;
assert( k7 = ttime'left ) report "TEST FAILED" severity FAILURE;
assert( k8 = tnatural'left ) report "TEST FAILED" severity FAILURE;
assert( k9 = tpositive'left ) report "TEST FAILED" severity FAILURE;
report "TEST PASSED";
wait;
end process doit;
end only;
|
-- DDR2 memory interface
-- Andrew Read, March 2016
-- This project is based on a working DDR2 interface very kindly donated by a friend
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
entity fpga_top is port(
clk : in std_logic;
nrst : in std_logic;
led : out std_logic_vector(1 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0);
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_CKE : out std_logic;
SDRAM_CK : out std_logic;
SDRAM_nCK : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQS : inout std_logic_vector(1 downto 0);
--SDRAM_nDQS : inout std_logic_vector(1 downto 0);
SDRAM_UDQM : out std_logic;
SDRAM_LDQM : out std_logic;
SDRAM_nCAS : out std_logic;
SDRAM_nCS : out std_logic;
SDRAM_nRAS : out std_logic;
SDRAM_nWE : out std_logic;
SDRAM_ODT : out std_logic);
end fpga_top;
architecture RTL of fpga_top is
component ByteHEXdisplay is
Port (
clk : in STD_LOGIC;
ssData : in STD_LOGIC_VECTOR (31 downto 0);
sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
anode : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component SDRAM_CTRL is
port (
CLK : in std_logic;
CLK_130 : in std_logic;
reset : in std_logic;
wrrd_ba_add : in std_logic_vector(2 downto 0);
wrrd_ras_add : in std_logic_vector(12 downto 0);
wrrd_cas_add : in std_logic_vector(8 downto 0);
wr_we : in std_logic_vector(3 downto 0);
wr_add : in std_logic_vector(25 downto 0);
wr_dat : in std_logic_vector(31 downto 0);
wr_ack : out std_logic;
rd_re : in std_logic;
rd_add : in std_logic_vector(25 downto 0);
rd_dat : out std_logic_vector(31 downto 0);
rd_ack : out std_logic;
rd_valid : out std_logic;
SDRAM_A : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(2 downto 0);
SDRAM_CKE : out std_logic;
SDRAM_CK : out std_logic;
SDRAM_nCK : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQS : inout std_logic_vector(1 downto 0);
--SDRAM_nDQS : inout std_logic_vector(1 downto 0);
SDRAM_DM : out std_logic_vector(1 downto 0);
SDRAM_nCAS : out std_logic;
SDRAM_nCS : out std_logic;
SDRAM_nRAS : out std_logic;
SDRAM_nWE : out std_logic);
end component;
component clk_manager
Port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC
-- resetn : in STD_LOGIC;
-- locked : out STD_LOGIC
);
end component;
type fsm_type is (init,
write_0_0, write_0_1,
write_1_0, write_1_1, write_1_2, write_1_3,
write_2_0, write_2_1, write_2_2, write_2_3, write_2_4, write_2_5,
write_3_0, write_3_1,
write_4_0, write_4_1,
read_0_0, read_0_1, read_0_2,
read_1_0, read_1_1, read_1_2, read_1_3, read_1_4, read_1_5,
read_2_0, read_2_1, read_2_2, read_2_3, read_2_4, read_2_5, read_2_6, read_2_7, read_2_8, read_2_9, read_2_10, read_2_11,
read_3_0, read_3_1, read_3_2,
read_4_0, read_4_1, read_4_2,
refreshWait);
signal wrrd_ba_add : std_logic_vector(2 downto 0);
signal wrrd_ras_add : std_logic_vector(12 downto 0);
signal wrrd_cas_add : std_logic_vector(8 downto 0);
signal wr_we : std_logic_vector(3 downto 0);
signal wr_add : std_logic_vector(25 downto 0);
signal wr_dat : std_logic_vector(31 downto 0);
signal wr_ack : std_logic;
signal rd_re : std_logic;
signal rd_add : std_logic_vector(25 downto 0);
signal rd_dat, rd_dat_reg, rd_dat_reg0 : std_logic_vector(31 downto 0);
signal rd_ack : std_logic;
signal rd_valid : std_logic;
signal bug_found : std_logic;
signal SDRAM_DM : std_logic_vector(1 downto 0);
signal clk_int : std_logic;
signal clk_int_130 : std_logic;
signal nrst_reg : std_logic;
signal state : fsm_type;
signal counter : integer range 0 to 32768;
signal time_cnt1 : integer range 0 to 65535;
signal time_cnt2 : integer range 0 to 4095;
signal led_toggle : std_logic;
signal ssdata : std_logic_vector(31 downto 0);
signal reset : std_logic := '1';
signal reset_counter : integer range 0 to 4095 := 0;
begin
SDRAM_ODT <= '0';
-----------------------------------------------------
-- clk
-----------------------------------------------------
-- reset process
process
begin
wait until rising_edge(clk_int);
if nrst = '0' then
reset_counter <= 0;
reset <= '1';
elsif reset_counter = 2000 then
reset <= '0';
else
reset_counter <= reset_counter + 1;
end if;
end process;
CLOCKMANAGER: clk_manager
port map
(-- Clock in ports
clk_in1 => clk,
clk_out1 => clk_int,
clk_out2 => clk_int_130
--resetn => nrst,
--locked => locked
);
----------------------------------------------
-- nrst_reg
----------------------------------------------
--nrst_reg_proc : process (clk_int, nrst) begin
--if (clk_int = '1' and clk_int'event) then
-- nrst_reg <= '0';
-- if (nrst = '1') then
-- nrst_reg <= '1';
-- end if;
--end if;
--end process;
-----------------------------------------------------
-- For relaxing the timing: rd_dat gets registered
-----------------------------------------------------
rd_dat_reg_gen : process (clk_int, reset)
begin
if (reset='1') then
rd_dat_reg <= conv_std_logic_vector(0, rd_dat_reg'length);
-- rd_dat_reg0 <= conv_std_logic_vector(0, rd_dat_reg0'length);
elsif (clk_int'event and clk_int='1') then
rd_dat_reg <= rd_dat_reg0; -- one cycle delay for some reason
end if;
end process;
-- rd_dat is already registered by PHYIO
rd_dat_reg0 <= rd_dat;
-----------------------------------------------------
-- FSM
-----------------------------------------------------
gen_fsm : process (clk_int, reset)
variable counter_bus : std_logic_vector(15 downto 0);
begin
if (reset='1') then
wrrd_ba_add <= conv_std_logic_vector(0, wrrd_ba_add'length);
wrrd_ras_add <= conv_std_logic_vector(0, wrrd_ras_add'length);
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
led <= "00";
state <= init;
wr_add <= conv_std_logic_vector(0, wr_add'length);
wr_dat <= conv_std_logic_vector(0, wr_dat'length);
wr_we <= "0000";
rd_re <= '0';
rd_add <= conv_std_logic_vector(0, rd_add'length);
counter <= 0;
bug_found <= '0';
time_cnt1 <= 0;
time_cnt2 <= 0;
led_toggle <= '0';
ssdata <= x"01234567";
elsif (clk_int'event and clk_int='1') then
case (state) is
-----------------------------------------------------
-- mode
-----------------------------------------------------
when init => state <= write_0_0;
-----------------------------------------------------
-- write bank: 0 page: 0 add: 0 data: 5555AAAA
-----------------------------------------------------
when write_0_0 =>
wr_we <= "1111";
wr_dat <= x"7755AACC";
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
state <= write_0_1;
when write_0_1 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= read_0_0;
rd_re <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFF0
-----------------------------------------------------
when read_0_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_0_1;
end if;
when read_0_1 =>
if (rd_valid = '1') then
state <= read_0_2;
end if;
when read_0_2 =>
--state <= write_4_0;
--counter <= 32768;
--------------------
state <= write_1_0;
ssdata <= rd_dat_reg;
if NOT (rd_dat_reg(31 downto 0) = x"7755AACC") then
--if NOT (rd_dat_reg(31 downto 0) = x"AAAA5555") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- write bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when write_1_0 =>
wr_we <= "1111";
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
wr_dat <= x"0000FFFF";
state <= write_1_1;
when write_1_1 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= write_1_2;
end if;
-----------------------------------------------------
-- write bank: 0 page: 0 add: 1 data: 0001FFFE
-----------------------------------------------------
when write_1_2 =>
wr_we <= "1111";
wrrd_cas_add <= conv_std_logic_vector(1, wrrd_cas_add'length);
wr_dat <= x"0001FFFE";
state <= write_1_3;
when write_1_3 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= read_1_0;
rd_re <= '1';
wrrd_cas_add <= conv_std_logic_vector(0, wrrd_cas_add'length);
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when read_1_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_1_1;
end if;
when read_1_1 =>
if (rd_valid = '1') then
state <= read_1_2;
end if;
when read_1_2 =>
state <= read_1_3;
rd_re <= '1';
wrrd_cas_add <= conv_std_logic_vector(1, wrrd_cas_add'length);
if NOT (rd_dat_reg(31 downto 0) = x"0000FFFF") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 1 data: 0001FFFE
-----------------------------------------------------
when read_1_3 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_1_4;
end if;
when read_1_4 =>
if (rd_valid = '1') then
state <= read_1_5;
end if;
when read_1_5 =>
state <= write_2_0;
if NOT (rd_dat_reg(31 downto 0) = x"0001FFFE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- write bank: 0 page: 1 add: 1 data: 0011FFEE
-----------------------------------------------------
when write_2_0 =>
wr_we <= "1111";
wrrd_cas_add <= conv_std_logic_vector(1, wrrd_cas_add'length);
wrrd_ras_add <= "0" & x"001";
wr_dat <= x"0011FFEE";
state <= write_2_1;
when write_2_1 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= write_2_2;
end if;
-----------------------------------------------------
-- write bank: 0 page: 2 add: 1 data: 0021FFDE
-----------------------------------------------------
when write_2_2 =>
wr_we <= "1111";
wrrd_ras_add <= "0" & x"002";
wr_dat <= x"0021FFDE";
state <= write_2_3;
when write_2_3 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= write_2_4;
end if;
-----------------------------------------------------
-- write bank: 1 page: 2 add: 1 data: 0121FEDE
-----------------------------------------------------
when write_2_4 =>
wr_we <= "1111";
wrrd_ba_add <= "001";
wr_dat <= x"0121FEDE";
state <= write_2_5;
when write_2_5 =>
if (wr_ack = '1') then
wr_we <= "0000";
state <= read_2_0;
rd_re <= '1';
wrrd_ba_add <= "000";
wrrd_ras_add <= "0" & x"000";
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 1 data: 0001FFFE
-----------------------------------------------------
when read_2_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_1;
end if;
when read_2_1 =>
if (rd_valid = '1') then
state <= read_2_2;
end if;
when read_2_2 =>
state <= read_2_3;
rd_re <= '1';
wrrd_ras_add <= "0" & x"001";
if NOT (rd_dat_reg(31 downto 0) = x"0001FFFE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 1 add: 1 data: 0011FFEE
-----------------------------------------------------
when read_2_3 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_4;
end if;
when read_2_4 =>
if (rd_valid = '1') then
state <= read_2_5;
end if;
when read_2_5 =>
state <= read_2_6;
rd_re <= '1';
wrrd_ras_add <= "0" & x"002";
if NOT (rd_dat_reg(31 downto 0) = x"0011FFEE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 0 page: 2 add: 1 data: 0021FFDE
-----------------------------------------------------
when read_2_6 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_7;
end if;
when read_2_7 =>
if (rd_valid = '1') then
state <= read_2_8;
end if;
when read_2_8 =>
state <= read_2_9;
rd_re <= '1';
wrrd_ba_add <= "001";
wrrd_ras_add <= "0" & x"002";
if NOT (rd_dat_reg(31 downto 0) = x"0021FFDE") then
bug_found <= '1';
end if;
-----------------------------------------------------
-- read bank: 1 page: 2 add: 1 data: 0121FEDE
-----------------------------------------------------
when read_2_9 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_2_10;
end if;
when read_2_10 =>
if (rd_valid = '1') then
state <= read_2_11;
end if;
when read_2_11 =>
state <= write_3_0;
if NOT (rd_dat_reg(31 downto 0) = x"0121FEDE") then
bug_found <= '1';
end if;
counter <= 256;
-----------------------------------------------------
-- write bank: 3 page: 3 add: 0..255 data: 0330<cas>
-----------------------------------------------------
when write_3_0 =>
wr_we <= "1111";
wrrd_ba_add <= "011";
wrrd_ras_add <= "0" & x"003";
wrrd_cas_add <= conv_std_logic_vector(counter, wrrd_cas_add'length);
wr_dat <= x"0330" & conv_std_logic_vector(counter, 16);
state <= write_3_1;
when write_3_1 =>
if (wr_ack = '1') then
if (counter = 0) then
wr_we <= "0000";
state <= read_3_0;
rd_re <= '1';
counter <= 256;
wrrd_cas_add <= conv_std_logic_vector(256, wrrd_cas_add'length);
else
counter <= counter / 2;
wrrd_cas_add <= conv_std_logic_vector(counter / 2, wrrd_cas_add'length);
wr_dat <= x"0330" & conv_std_logic_vector(counter / 2, 16);
end if;
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when read_3_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_3_1;
end if;
when read_3_1 =>
if (rd_valid = '1') then
state <= read_3_2;
end if;
when read_3_2 =>
if (counter = 0) then
state <= write_4_0;
counter <= 32768;
else
rd_re <= '1';
state <= read_3_0;
counter <= counter / 2;
wrrd_cas_add <= conv_std_logic_vector(counter / 2, wrrd_cas_add'length);
end if;
if (NOT (rd_dat_reg(31 downto 16) = x"0330")) OR
(NOT (rd_dat_reg(15 downto 9) = "0000000")) OR
(NOT (rd_dat_reg(8 downto 0) = conv_std_logic_vector(counter, wrrd_cas_add'length))) then
bug_found <= '1';
end if;
-----------------------------------------------------
-- write bank: 3 page: 3 add: 0..255 data: 0330<cas>
-----------------------------------------------------
when write_4_0 =>
wr_we <= "1111";
counter_bus := conv_std_logic_vector(counter, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
wrrd_cas_add <= conv_std_logic_vector(4, wrrd_cas_add'length);
wr_dat <= conv_std_logic_vector(counter + time_cnt2, 32);
state <= write_4_1;
when write_4_1 =>
if (wr_ack = '1') then
if (counter = 0) then
wr_we <= "0000";
state <= read_4_0;
rd_re <= '1';
counter <= 32768;
counter_bus := conv_std_logic_vector(32768, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
else
counter <= counter / 2;
counter_bus := conv_std_logic_vector(counter / 2, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
wr_dat <= conv_std_logic_vector((counter / 2) + time_cnt2, 32);
end if;
end if;
-----------------------------------------------------
-- read bank: 0 page: 0 add: 0 data: 0000FFFF
-----------------------------------------------------
when read_4_0 =>
if (rd_ack = '1') then
rd_re <= '0';
state <= read_4_1;
end if;
when read_4_1 =>
if (rd_valid = '1') then
state <= read_4_2;
end if;
when read_4_2 =>
if (counter = 0) then
state <= refreshWait;
counter <= 32768;
else
rd_re <= '1';
state <= read_4_0;
counter <= counter / 2;
counter_bus := conv_std_logic_vector(counter / 2, counter_bus'length);
wrrd_ba_add <= counter_bus(15 downto 13);
wrrd_ras_add <= counter_bus(12 downto 0);
end if;
if (NOT (rd_dat_reg(31 downto 0) = conv_std_logic_vector(counter + time_cnt2, 32))) then
bug_found <= '1';
end if;
-----------------------------------------------------
-- refreshWait
-----------------------------------------------------
when refreshWait =>
led(0) <= not led_toggle;
if (bug_found = '0') then
led(1) <= '1';
if (time_cnt1 = 4095) then
time_cnt1 <= 0;
if (time_cnt2 = 4095) then
state <= read_3_0;
rd_re <= '1';
counter <= 256;
wrrd_ba_add <= "011";
wrrd_ras_add <= "0" & x"003";
wrrd_cas_add <= conv_std_logic_vector(256, wrrd_cas_add'length);
time_cnt2 <= 0;
led_toggle <= not led_toggle;
else
state <= write_4_0;
time_cnt2 <= time_cnt2 + 1;
end if;
else
state <= write_4_0;
time_cnt1 <= time_cnt1 + 1;
end if;
else
led(1) <= '0';
if (time_cnt1 = 65535) then
time_cnt1 <= 0;
if (time_cnt2 = 511) then
time_cnt2 <= 0;
led_toggle <= not led_toggle;
else
time_cnt2 <= time_cnt2 + 1;
end if;
else
time_cnt1 <= time_cnt1 + 1;
end if;
end if;
when others =>
end case;
end if;
end process;
SDRAM_UDQM <= SDRAM_DM(1);
SDRAM_LDQM <= SDRAM_DM(0);
-----------------------------------------------------
-- SDRAM_CTRL
-----------------------------------------------------
SDRAM_CTRLi : SDRAM_CTRL
port map (
CLK => clk_int,
CLK_130 => clk_int_130,
reset => reset,
wrrd_ba_add => wrrd_ba_add,
wrrd_ras_add => wrrd_ras_add,
wrrd_cas_add => wrrd_cas_add,
wr_we => wr_we,
wr_add => wr_add,
wr_dat => wr_dat,
wr_ack => wr_ack,
rd_re => rd_re,
rd_add => rd_add,
rd_dat => rd_dat,
rd_ack => rd_ack,
rd_valid => rd_valid,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CK => SDRAM_CK,
SDRAM_nCK => SDRAM_nCK,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS,
--SDRAM_nDQS => SDRAM_nDQS,
SDRAM_DM => SDRAM_DM,
SDRAM_nCAS => SDRAM_nCAS,
SDRAM_nCS => SDRAM_nCS,
SDRAM_nRAS => SDRAM_nRAS,
SDRAM_nWE => SDRAM_nWE);
hex : ByteHEXdisplay
Port map (
clk => clk_int,
ssData => ssData,
sevenseg => sevenseg,
anode => anode
);
end RTL;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13424)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end pll_125;
architecture syn of pll_125 is
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
clk5_divide_by : NATURAL;
clk5_duty_cycle : NATURAL;
clk5_multiply_by : NATURAL;
clk5_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC ;
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
scanclk : IN STD_LOGIC
);
END COMPONENT;
signal sub_wire3 : std_logic_vector(1 downto 0);
signal sub_wire0 : std_logic_vector(9 downto 0);
begin
sub_wire3 <= '0' & inclk0;
c0 <= sub_wire0(0);
altpll_component : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 5,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 5,
clk3_phase_shift => "0",
clk4_divide_by => 2,
clk4_duty_cycle => 50,
clk4_multiply_by => 5,
clk4_phase_shift => "0",
clk5_divide_by => 2,
clk5_duty_cycle => 50,
clk5_multiply_by => 5,
clk5_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Stratix IV",
lpm_hint => "CBX_MODULE_PREFIX=pll_125",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
using_fbmimicbidir_port => "OFF",
self_reset_on_loss_lock => "OFF",
width_clock => 10
)
port map (
inclk => sub_wire3,
clk => sub_wire0,
areset => '0',
phasecounterselect => "1111",
phasestep => '1',
phaseupdown => '1',
scanclk => '0'
);
end architecture syn;
|
-------------------------------------------------------------------------------
-- Title : Title String
-------------------------------------------------------------------------------
-- Author : AUTHOR
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013, AUTHOR
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library work;
-- use work.<package_name>.all;
-------------------------------------------------------------------------------
entity entity_name is
generic (
PARAM : natural := 42
);
port (
clk : in std_logic
);
end entity_name;
-------------------------------------------------------------------------------
architecture behavioural of entity_name is
type entity_name_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1:
STATE2 -- State 2:
);
type entity_name_type is record
state : entity_name_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : entity_name_type := (state => IDLE);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(r)
variable v : entity_name_type;
begin
v := r;
case r.state is
when IDLE =>
null;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity rc4_initer is
generic (
width: integer := 8
);
port (
CLK: in std_logic;
GO: in std_logic;
KEYLEN: in std_logic_vector((width - 1) downto 0);
MEMINPUT: in std_logic_vector((width - 1) downto 0);
KEYINPUT: in std_logic_vector((width - 1) downto 0);
KEYINDEX: out std_logic_vector((width - 1) downto 0);
MEMCTRL: out std_logic;
MEMINDEX: out std_logic_vector((width - 1) downto 0);
MEMOUTPUT: out std_logic_vector((width - 1) downto 0);
DONE: out std_logic
);
end rc4_initer;
architecture Behavioral of rc4_initer is
constant permlength : integer := 256;
begin
process (clk)
type rc4_initer_state is (IDLE, INIT, SHUFFLE);
subtype rc4int is integer range 0 to 255;
variable state : rc4_initer_state := IDLE;
variable clk_ctr, ctr : integer := 0;
variable i, j, si, sj, k, tmp : rc4int := 0;
variable keylength : integer := 0;
begin
if rising_edge(clk) then
keylength := conv_integer(unsigned(keylen));
case state is
when IDLE =>
if go = '1' then
clk_ctr := 0;
ctr := 0;
done <= '0';
i := 0;
j := 0;
si := 0;
sj := 0;
state := INIT;
else
done <= '1';
state := IDLE;
end if;
when INIT =>
if ctr >= permlength then
clk_ctr := 0;
ctr := 0;
state := SHUFFLE;
else
if clk_ctr mod 2 = 0 then
-- nie rob nic (podtrzymaj ostatnia komende)
else
memctrl <= '1';
memindex <= conv_std_logic_vector(ctr, width);
memoutput <= conv_std_logic_vector(ctr, width);
ctr := ctr + 1;
end if;
clk_ctr := clk_ctr + 1;
end if;
when SHUFFLE =>
if i >= permlength then
clk_ctr := 0;
ctr := 0;
i := 0;
j := 0;
si := 0;
sj := 0;
memctrl <= '0';
done <= '1';
state := IDLE;
else
case clk_ctr is
when 0 =>
si := 0;
sj := 0;
k := 0;
memctrl <= '0';
memindex <= conv_std_logic_vector(i, width);
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 1 =>
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 2 =>
si := conv_integer(unsigned(meminput));
tmp := i mod keylength;
keyindex <= conv_std_logic_vector(tmp, width);
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 3 =>
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 4 =>
k := conv_integer(unsigned(keyinput));
j := (j + si + k) mod 256;
memctrl <= '0';
memindex <= conv_std_logic_vector(j, width);
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 5 =>
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 6 =>
sj := conv_integer(unsigned(meminput));
memoutput <= conv_std_logic_vector(si, width);
memctrl <= '1';
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 7 =>
memindex <= conv_std_logic_vector(i, width);
memoutput <= conv_std_logic_vector(sj, width);
memctrl <= '1';
clk_ctr := 0;
i := i + 1;
state := SHUFFLE;
when others =>
memindex <= "11111111";
memoutput <= "11111111";
memctrl <= '0';
state := SHUFFLE;
end case;
end if;
end case;
end if;
end process;
end Behavioral;
|
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
|
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
|
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2398.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n01i02398ent IS
END c07s03b02x00p08n01i02398ent;
ARCHITECTURE c07s03b02x00p08n01i02398arch OF c07s03b02x00p08n01i02398ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
end record;
type t22 is array (1 to 10) of integer;
variable v22 : t22;
BEGIN
v22 := (ele_1 => 22, others => 0); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n01i02398 - Element associations by an element simple name is allowed only in recordi aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n01i02398arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2398.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n01i02398ent IS
END c07s03b02x00p08n01i02398ent;
ARCHITECTURE c07s03b02x00p08n01i02398arch OF c07s03b02x00p08n01i02398ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
end record;
type t22 is array (1 to 10) of integer;
variable v22 : t22;
BEGIN
v22 := (ele_1 => 22, others => 0); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n01i02398 - Element associations by an element simple name is allowed only in recordi aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n01i02398arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2398.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n01i02398ent IS
END c07s03b02x00p08n01i02398ent;
ARCHITECTURE c07s03b02x00p08n01i02398arch OF c07s03b02x00p08n01i02398ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
end record;
type t22 is array (1 to 10) of integer;
variable v22 : t22;
BEGIN
v22 := (ele_1 => 22, others => 0); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n01i02398 - Element associations by an element simple name is allowed only in recordi aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n01i02398arch;
|
---------------------------------------------------------------------------
-- Project : FIR Filter
-- Author : James Gibbard (james@gibbard.me)
-- Date : 2017-03-25
-- File : mac_module.vhd
-- Module : mac_module
---------------------------------------------------------------------------
-- Description : Multiply accumulate unit.
-- Both multiply and sum results registered
---------------------------------------------------------------------------
-- Change Log
-- Version 0.0.1 : Initial version
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity mac_module is
generic (
--Max for Xilinx DSP48E1 slice is 25 x 18 multiply with 48bit accumulator
--Max for Cyclon/Arria V is 27 x 27 (or dual 18x19) multiply with 64bit accumulator
a_in_size : integer := 16;
b_in_size : integer := 16;
accumulator_size : integer := 48
);
port (
clk : in std_logic;
rst : in std_logic;
en_in : in std_logic;
a_in : in signed(a_in_size - 1 downto 0);
b_in : in signed(b_in_size - 1 downto 0);
accum_out : out signed(accumulator_size - 1 downto 0)
);
end mac_module;
architecture behavioural of mac_module is
signal accum : signed(accumulator_size - 1 downto 0);
signal multi_res : signed(a_in_size + b_in_size - 1 downto 0);
begin
mac_p : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
accum <= (others => '0');
multi_res <= (others => '0');
else
if en_in = '1' then
--Register multiply operation
multi_res <= a_in * b_in;
--Also register sum operation
accum <= accum + multi_res;
end if;
end if;
end if;
end process;
accum_out <= accum;
end behavioural;
|
-- File name: tb_bus_test.vhd
-- Created: 2009-02-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: bus_test tester
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_bus_test is
generic (
clk_per : time := 5 ns
);
end tb_bus_test;
architecture test of tb_bus_test is
component bus_test is
port (
clk : in std_logic;
nrst : in std_logic;
b : out unsigned(7 downto 0)
);
end component bus_test;
signal clk : std_logic := '0';
signal nrst : std_logic := '1';
signal stop : std_logic := '1';
signal b : unsigned(7 downto 0);
begin
dut : bus_test port map (
clk => clk, nrst => nrst, b => b
);
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
begin
nrst <= '0';
wait for clk_per*2;
nrst <= '1';
stop <= '0';
wait for clk_per*32;
stop <= '1';
wait for clk_per*4;
wait;
end process;
end test;
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:18:25 02/19/2014
-- Design Name:
-- Module Name: trigo - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity trigo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
sen : out STD_LOGIC_VECTOR (20 downto 0);
cos : out STD_LOGIC_VECTOR (20 downto 0));
end trigo;
architecture Behavioral of trigo is
begin
with valor select
sen <= "000000000000000000000" when "111111100000000000000",
"111111111111111111111" when "111111100010000000000",
"000000000000000000000" when "111111100100000000000",
"000000000000000000000" when "111111100110000000000",
"000000000000000000000" when "111111101000000000000",
"111111111111111111111" when "111111101010000000000",
"000000000000000000000" when "111111101100000000000",
"111111111111111111111" when "111111101110000000000",
"000000000000000000000" when "111111110000000000000",
"000000000010000000000" when "111111110001000000000",
"111111111111111111111" when "111111110010000000000",
"111111111110000000000" when "111111110011000000000",
"000000000000000000000" when "111111110100000000000",
"000000000010000000000" when "111111110101000000000",
"111111111111111111111" when "111111110110000000000",
"111111111110000000000" when "111111110111000000000",
"000000000000000000000" when "111111111000000000000",
"000000000001011010100" when "111111111000100000000",
"000000000010000000000" when "111111111001000000000",
"000000000001011010100" when "111111111001100000000",
"111111111111111111111" when "111111111010000000000",
"111111111110100101011" when "111111111010100000000",
"111111111110000000000" when "111111111011000000000",
"111111111110100101011" when "111111111011100000000",
"000000000000000000000" when "111111111100000000000",
"000000000000110000111" when "111111111100010000000",
"000000000001011010100" when "111111111100100000000",
"000000000001110110010" when "111111111100110000000",
"000000000010000000000" when "111111111101000000000",
"000000000001110110010" when "111111111101010000000",
"000000000001011010100" when "111111111101100000000",
"000000000000110000111" when "111111111101110000000",
"111111111111111111111" when "111111111110000000000",
"111111111111100111000" when "111111111110001000000",
"111111111111001111000" when "111111111110010000000",
"111111111110111000111" when "111111111110011000000",
"111111111110100101011" when "111111111110100000000",
"111111111110010101100" when "111111111110101000000",
"111111111110001001101" when "111111111110110000000",
"111111111110000010011" when "111111111110111000000",
"111111111110000000000" when "111111111111000000000",
"111111111110000010011" when "111111111111001000000",
"111111111110001001101" when "111111111111010000000",
"111111111110010101100" when "111111111111011000000",
"111111111110100101011" when "111111111111100000000",
"111111111110111000111" when "111111111111101000000",
"111111111111001111000" when "111111111111110000000",
"111111111111100111000" when "111111111111111000000",
"000000000000000000000" when "000000000000000000000",
"000000000000001100100" when "000000000000000100000",
"000000000000011000111" when "000000000000001000000",
"000000000000100101001" when "000000000000001100000",
"000000000000110000111" when "000000000000010000000",
"000000000000111100010" when "000000000000010100000",
"000000000001000111000" when "000000000000011000000",
"000000000001010001001" when "000000000000011100000",
"000000000001011010100" when "000000000000100000000",
"000000000001100010111" when "000000000000100100000",
"000000000001101010011" when "000000000000101000000",
"000000000001110000111" when "000000000000101100000",
"000000000001110110010" when "000000000000110000000",
"000000000001111010011" when "000000000000110100000",
"000000000001111101100" when "000000000000111000000",
"000000000001111111011" when "000000000000111100000",
"000000000010000000000" when "000000000001000000000",
"000000000001111111011" when "000000000001000100000",
"000000000001111101100" when "000000000001001000000",
"000000000001111010011" when "000000000001001100000",
"000000000001110110010" when "000000000001010000000",
"000000000001110000111" when "000000000001010100000",
"000000000001101010011" when "000000000001011000000",
"000000000001100010111" when "000000000001011100000",
"000000000001011010100" when "000000000001100000000",
"000000000001010001001" when "000000000001100100000",
"000000000001000111000" when "000000000001101000000",
"000000000000111100010" when "000000000001101100000",
"000000000000110000111" when "000000000001110000000",
"000000000000100101001" when "000000000001110100000",
"000000000000011000111" when "000000000001111000000",
"000000000000001100100" when "000000000001111100000",
"000000000000000000000" when "000000000010000000000",
"111111111111100111000" when "000000000010001000000",
"111111111111001111000" when "000000000010010000000",
"111111111110111000111" when "000000000010011000000",
"111111111110100101011" when "000000000010100000000",
"111111111110010101100" when "000000000010101000000",
"111111111110001001101" when "000000000010110000000",
"111111111110000010011" when "000000000010111000000",
"111111111110000000000" when "000000000011000000000",
"111111111110000010011" when "000000000011001000000",
"111111111110001001101" when "000000000011010000000",
"111111111110010101100" when "000000000011011000000",
"111111111110100101011" when "000000000011100000000",
"111111111110111000111" when "000000000011101000000",
"111111111111001111000" when "000000000011110000000",
"111111111111100111000" when "000000000011111000000",
"111111111111111111111" when "000000000100000000000",
"000000000000110000111" when "000000000100010000000",
"000000000001011010100" when "000000000100100000000",
"000000000001110110010" when "000000000100110000000",
"000000000010000000000" when "000000000101000000000",
"000000000001110110010" when "000000000101010000000",
"000000000001011010100" when "000000000101100000000",
"000000000000110000111" when "000000000101110000000",
"000000000000000000000" when "000000000110000000000",
"111111111111001111000" when "000000000110010000000",
"111111111110100101011" when "000000000110100000000",
"111111111110001001101" when "000000000110110000000",
"111111111110000000000" when "000000000111000000000",
"111111111110001001101" when "000000000111010000000",
"111111111110100101011" when "000000000111100000000",
"111111111111001111000" when "000000000111110000000",
"111111111111111111111" when "000000001000000000000",
"000000000001011010100" when "000000001000100000000",
"000000000010000000000" when "000000001001000000000",
"000000000001011010100" when "000000001001100000000",
"000000000000000000000" when "000000001010000000000",
"111111111110100101011" when "000000001010100000000",
"111111111110000000000" when "000000001011000000000",
"111111111110100101011" when "000000001011100000000",
"111111111111111111111" when "000000001100000000000",
"000000000001011010100" when "000000001100100000000",
"000000000010000000000" when "000000001101000000000",
"000000000001011010100" when "000000001101100000000",
"000000000000000000000" when "000000001110000000000",
"111111111110100101011" when "000000001110100000000",
"111111111110000000000" when "000000001111000000000",
"111111111110100101011" when "000000001111100000000",
"111111111111111111111" when "000000010000000000000",
"000000000010000000000" when "000000010001000000000",
"000000000000000000000" when "000000010010000000000",
"111111111110000000000" when "000000010011000000000",
"111111111111111111111" when "000000010100000000000",
"000000000010000000000" when "000000010101000000000",
"000000000000000000000" when "000000010110000000000",
"111111111110000000000" when "000000010111000000000",
"111111111111111111111" when "000000011000000000000",
"000000000010000000000" when "000000011001000000000",
"111111111111111111111" when "000000011010000000000",
"111111111110000000000" when "000000011011000000000",
"111111111111111111111" when "000000011100000000000",
"000000000010000000000" when "000000011101000000000",
"000000000000000000000" when "000000011110000000000",
"111111111110000000000" when "000000011111000000000",
"111111111111111111111" when "000000100000000000000",
"000000000000000000000" when others;
with valor select
cos <= "000000000010000000000" when "111111100000000000000",
"111111111110000000000" when "111111100010000000000",
"000000000010000000000" when "111111100100000000000",
"111111111110000000000" when "111111100110000000000",
"000000000010000000000" when "111111101000000000000",
"111111111110000000000" when "111111101010000000000",
"000000000010000000000" when "111111101100000000000",
"111111111110000000000" when "111111101110000000000",
"000000000010000000000" when "111111110000000000000",
"111111111111111111111" when "111111110001000000000",
"111111111110000000000" when "111111110010000000000",
"111111111111111111111" when "111111110011000000000",
"000000000010000000000" when "111111110100000000000",
"111111111111111111111" when "111111110101000000000",
"111111111110000000000" when "111111110110000000000",
"000000000000000000000" when "111111110111000000000",
"000000000010000000000" when "111111111000000000000",
"000000000001011010100" when "111111111000100000000",
"111111111111111111111" when "111111111001000000000",
"111111111110100101011" when "111111111001100000000",
"111111111110000000000" when "111111111010000000000",
"111111111110100101011" when "111111111010100000000",
"000000000000000000000" when "111111111011000000000",
"000000000001011010100" when "111111111011100000000",
"000000000010000000000" when "111111111100000000000",
"000000000001110110010" when "111111111100010000000",
"000000000001011010100" when "111111111100100000000",
"000000000000110000111" when "111111111100110000000",
"111111111111111111111" when "111111111101000000000",
"111111111111001111000" when "111111111101010000000",
"111111111110100101011" when "111111111101100000000",
"111111111110001001101" when "111111111101110000000",
"111111111110000000000" when "111111111110000000000",
"111111111110000010011" when "111111111110001000000",
"111111111110001001101" when "111111111110010000000",
"111111111110010101100" when "111111111110011000000",
"111111111110100101011" when "111111111110100000000",
"111111111110111000111" when "111111111110101000000",
"111111111111001111000" when "111111111110110000000",
"111111111111100111000" when "111111111110111000000",
"000000000000000000000" when "111111111111000000000",
"000000000000011000111" when "111111111111001000000",
"000000000000110000111" when "111111111111010000000",
"000000000001000111000" when "111111111111011000000",
"000000000001011010100" when "111111111111100000000",
"000000000001101010011" when "111111111111101000000",
"000000000001110110010" when "111111111111110000000",
"000000000001111101100" when "111111111111111000000",
"000000000010000000000" when "000000000000000000000",
"000000000001111111011" when "000000000000000100000",
"000000000001111101100" when "000000000000001000000",
"000000000001111010011" when "000000000000001100000",
"000000000001110110010" when "000000000000010000000",
"000000000001110000111" when "000000000000010100000",
"000000000001101010011" when "000000000000011000000",
"000000000001100010111" when "000000000000011100000",
"000000000001011010100" when "000000000000100000000",
"000000000001010001001" when "000000000000100100000",
"000000000001000111000" when "000000000000101000000",
"000000000000111100010" when "000000000000101100000",
"000000000000110000111" when "000000000000110000000",
"000000000000100101001" when "000000000000110100000",
"000000000000011000111" when "000000000000111000000",
"000000000000001100100" when "000000000000111100000",
"000000000000000000000" when "000000000001000000000",
"111111111111110011011" when "000000000001000100000",
"111111111111100111000" when "000000000001001000000",
"111111111111011010110" when "000000000001001100000",
"111111111111001111000" when "000000000001010000000",
"111111111111000011101" when "000000000001010100000",
"111111111110111000111" when "000000000001011000000",
"111111111110101110110" when "000000000001011100000",
"111111111110100101011" when "000000000001100000000",
"111111111110011101000" when "000000000001100100000",
"111111111110010101100" when "000000000001101000000",
"111111111110001111000" when "000000000001101100000",
"111111111110001001101" when "000000000001110000000",
"111111111110000101100" when "000000000001110100000",
"111111111110000010011" when "000000000001111000000",
"111111111110000000100" when "000000000001111100000",
"111111111110000000000" when "000000000010000000000",
"111111111110000010011" when "000000000010001000000",
"111111111110001001101" when "000000000010010000000",
"111111111110010101100" when "000000000010011000000",
"111111111110100101011" when "000000000010100000000",
"111111111110111000111" when "000000000010101000000",
"111111111111001111000" when "000000000010110000000",
"111111111111100111000" when "000000000010111000000",
"111111111111111111111" when "000000000011000000000",
"000000000000011000111" when "000000000011001000000",
"000000000000110000111" when "000000000011010000000",
"000000000001000111000" when "000000000011011000000",
"000000000001011010100" when "000000000011100000000",
"000000000001101010011" when "000000000011101000000",
"000000000001110110010" when "000000000011110000000",
"000000000001111101100" when "000000000011111000000",
"000000000010000000000" when "000000000100000000000",
"000000000001110110010" when "000000000100010000000",
"000000000001011010100" when "000000000100100000000",
"000000000000110000111" when "000000000100110000000",
"000000000000000000000" when "000000000101000000000",
"111111111111001111000" when "000000000101010000000",
"111111111110100101011" when "000000000101100000000",
"111111111110001001101" when "000000000101110000000",
"111111111110000000000" when "000000000110000000000",
"111111111110001001101" when "000000000110010000000",
"111111111110100101011" when "000000000110100000000",
"111111111111001111000" when "000000000110110000000",
"111111111111111111111" when "000000000111000000000",
"000000000000110000111" when "000000000111010000000",
"000000000001011010100" when "000000000111100000000",
"000000000001110110010" when "000000000111110000000",
"000000000010000000000" when "000000001000000000000",
"000000000001011010100" when "000000001000100000000",
"000000000000000000000" when "000000001001000000000",
"111111111110100101011" when "000000001001100000000",
"111111111110000000000" when "000000001010000000000",
"111111111110100101011" when "000000001010100000000",
"111111111111111111111" when "000000001011000000000",
"000000000001011010100" when "000000001011100000000",
"000000000010000000000" when "000000001100000000000",
"000000000001011010100" when "000000001100100000000",
"111111111111111111111" when "000000001101000000000",
"111111111110100101011" when "000000001101100000000",
"111111111110000000000" when "000000001110000000000",
"111111111110100101011" when "000000001110100000000",
"111111111111111111111" when "000000001111000000000",
"000000000001011010100" when "000000001111100000000",
"000000000010000000000" when "000000010000000000000",
"111111111111111111111" when "000000010001000000000",
"111111111110000000000" when "000000010010000000000",
"111111111111111111111" when "000000010011000000000",
"000000000010000000000" when "000000010100000000000",
"111111111111111111111" when "000000010101000000000",
"111111111110000000000" when "000000010110000000000",
"111111111111111111111" when "000000010111000000000",
"000000000010000000000" when "000000011000000000000",
"111111111111111111111" when "000000011001000000000",
"111111111110000000000" when "000000011010000000000",
"111111111111111111111" when "000000011011000000000",
"000000000010000000000" when "000000011100000000000",
"111111111111111111111" when "000000011101000000000",
"111111111110000000000" when "000000011110000000000",
"111111111111111111111" when "000000011111000000000",
"000000000010000000000" when "000000100000000000000",
"000000000000000000000" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: Nameless2
-- Engineer: Ana María Martínez Gómez, Aitor Alonso Lorenzo, Víctor Adolfo Gallego Alcalá
--
-- Create Date: 13:18:25 02/19/2014
-- Design Name:
-- Module Name: trigo - Behavioral
-- Project Name: Representación gráfica de funciones
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity trigo is
Port ( valor : in STD_LOGIC_VECTOR (20 downto 0);
sen : out STD_LOGIC_VECTOR (20 downto 0);
cos : out STD_LOGIC_VECTOR (20 downto 0));
end trigo;
architecture Behavioral of trigo is
begin
with valor select
sen <= "000000000000000000000" when "111111100000000000000",
"111111111111111111111" when "111111100010000000000",
"000000000000000000000" when "111111100100000000000",
"000000000000000000000" when "111111100110000000000",
"000000000000000000000" when "111111101000000000000",
"111111111111111111111" when "111111101010000000000",
"000000000000000000000" when "111111101100000000000",
"111111111111111111111" when "111111101110000000000",
"000000000000000000000" when "111111110000000000000",
"000000000010000000000" when "111111110001000000000",
"111111111111111111111" when "111111110010000000000",
"111111111110000000000" when "111111110011000000000",
"000000000000000000000" when "111111110100000000000",
"000000000010000000000" when "111111110101000000000",
"111111111111111111111" when "111111110110000000000",
"111111111110000000000" when "111111110111000000000",
"000000000000000000000" when "111111111000000000000",
"000000000001011010100" when "111111111000100000000",
"000000000010000000000" when "111111111001000000000",
"000000000001011010100" when "111111111001100000000",
"111111111111111111111" when "111111111010000000000",
"111111111110100101011" when "111111111010100000000",
"111111111110000000000" when "111111111011000000000",
"111111111110100101011" when "111111111011100000000",
"000000000000000000000" when "111111111100000000000",
"000000000000110000111" when "111111111100010000000",
"000000000001011010100" when "111111111100100000000",
"000000000001110110010" when "111111111100110000000",
"000000000010000000000" when "111111111101000000000",
"000000000001110110010" when "111111111101010000000",
"000000000001011010100" when "111111111101100000000",
"000000000000110000111" when "111111111101110000000",
"111111111111111111111" when "111111111110000000000",
"111111111111100111000" when "111111111110001000000",
"111111111111001111000" when "111111111110010000000",
"111111111110111000111" when "111111111110011000000",
"111111111110100101011" when "111111111110100000000",
"111111111110010101100" when "111111111110101000000",
"111111111110001001101" when "111111111110110000000",
"111111111110000010011" when "111111111110111000000",
"111111111110000000000" when "111111111111000000000",
"111111111110000010011" when "111111111111001000000",
"111111111110001001101" when "111111111111010000000",
"111111111110010101100" when "111111111111011000000",
"111111111110100101011" when "111111111111100000000",
"111111111110111000111" when "111111111111101000000",
"111111111111001111000" when "111111111111110000000",
"111111111111100111000" when "111111111111111000000",
"000000000000000000000" when "000000000000000000000",
"000000000000001100100" when "000000000000000100000",
"000000000000011000111" when "000000000000001000000",
"000000000000100101001" when "000000000000001100000",
"000000000000110000111" when "000000000000010000000",
"000000000000111100010" when "000000000000010100000",
"000000000001000111000" when "000000000000011000000",
"000000000001010001001" when "000000000000011100000",
"000000000001011010100" when "000000000000100000000",
"000000000001100010111" when "000000000000100100000",
"000000000001101010011" when "000000000000101000000",
"000000000001110000111" when "000000000000101100000",
"000000000001110110010" when "000000000000110000000",
"000000000001111010011" when "000000000000110100000",
"000000000001111101100" when "000000000000111000000",
"000000000001111111011" when "000000000000111100000",
"000000000010000000000" when "000000000001000000000",
"000000000001111111011" when "000000000001000100000",
"000000000001111101100" when "000000000001001000000",
"000000000001111010011" when "000000000001001100000",
"000000000001110110010" when "000000000001010000000",
"000000000001110000111" when "000000000001010100000",
"000000000001101010011" when "000000000001011000000",
"000000000001100010111" when "000000000001011100000",
"000000000001011010100" when "000000000001100000000",
"000000000001010001001" when "000000000001100100000",
"000000000001000111000" when "000000000001101000000",
"000000000000111100010" when "000000000001101100000",
"000000000000110000111" when "000000000001110000000",
"000000000000100101001" when "000000000001110100000",
"000000000000011000111" when "000000000001111000000",
"000000000000001100100" when "000000000001111100000",
"000000000000000000000" when "000000000010000000000",
"111111111111100111000" when "000000000010001000000",
"111111111111001111000" when "000000000010010000000",
"111111111110111000111" when "000000000010011000000",
"111111111110100101011" when "000000000010100000000",
"111111111110010101100" when "000000000010101000000",
"111111111110001001101" when "000000000010110000000",
"111111111110000010011" when "000000000010111000000",
"111111111110000000000" when "000000000011000000000",
"111111111110000010011" when "000000000011001000000",
"111111111110001001101" when "000000000011010000000",
"111111111110010101100" when "000000000011011000000",
"111111111110100101011" when "000000000011100000000",
"111111111110111000111" when "000000000011101000000",
"111111111111001111000" when "000000000011110000000",
"111111111111100111000" when "000000000011111000000",
"111111111111111111111" when "000000000100000000000",
"000000000000110000111" when "000000000100010000000",
"000000000001011010100" when "000000000100100000000",
"000000000001110110010" when "000000000100110000000",
"000000000010000000000" when "000000000101000000000",
"000000000001110110010" when "000000000101010000000",
"000000000001011010100" when "000000000101100000000",
"000000000000110000111" when "000000000101110000000",
"000000000000000000000" when "000000000110000000000",
"111111111111001111000" when "000000000110010000000",
"111111111110100101011" when "000000000110100000000",
"111111111110001001101" when "000000000110110000000",
"111111111110000000000" when "000000000111000000000",
"111111111110001001101" when "000000000111010000000",
"111111111110100101011" when "000000000111100000000",
"111111111111001111000" when "000000000111110000000",
"111111111111111111111" when "000000001000000000000",
"000000000001011010100" when "000000001000100000000",
"000000000010000000000" when "000000001001000000000",
"000000000001011010100" when "000000001001100000000",
"000000000000000000000" when "000000001010000000000",
"111111111110100101011" when "000000001010100000000",
"111111111110000000000" when "000000001011000000000",
"111111111110100101011" when "000000001011100000000",
"111111111111111111111" when "000000001100000000000",
"000000000001011010100" when "000000001100100000000",
"000000000010000000000" when "000000001101000000000",
"000000000001011010100" when "000000001101100000000",
"000000000000000000000" when "000000001110000000000",
"111111111110100101011" when "000000001110100000000",
"111111111110000000000" when "000000001111000000000",
"111111111110100101011" when "000000001111100000000",
"111111111111111111111" when "000000010000000000000",
"000000000010000000000" when "000000010001000000000",
"000000000000000000000" when "000000010010000000000",
"111111111110000000000" when "000000010011000000000",
"111111111111111111111" when "000000010100000000000",
"000000000010000000000" when "000000010101000000000",
"000000000000000000000" when "000000010110000000000",
"111111111110000000000" when "000000010111000000000",
"111111111111111111111" when "000000011000000000000",
"000000000010000000000" when "000000011001000000000",
"111111111111111111111" when "000000011010000000000",
"111111111110000000000" when "000000011011000000000",
"111111111111111111111" when "000000011100000000000",
"000000000010000000000" when "000000011101000000000",
"000000000000000000000" when "000000011110000000000",
"111111111110000000000" when "000000011111000000000",
"111111111111111111111" when "000000100000000000000",
"000000000000000000000" when others;
with valor select
cos <= "000000000010000000000" when "111111100000000000000",
"111111111110000000000" when "111111100010000000000",
"000000000010000000000" when "111111100100000000000",
"111111111110000000000" when "111111100110000000000",
"000000000010000000000" when "111111101000000000000",
"111111111110000000000" when "111111101010000000000",
"000000000010000000000" when "111111101100000000000",
"111111111110000000000" when "111111101110000000000",
"000000000010000000000" when "111111110000000000000",
"111111111111111111111" when "111111110001000000000",
"111111111110000000000" when "111111110010000000000",
"111111111111111111111" when "111111110011000000000",
"000000000010000000000" when "111111110100000000000",
"111111111111111111111" when "111111110101000000000",
"111111111110000000000" when "111111110110000000000",
"000000000000000000000" when "111111110111000000000",
"000000000010000000000" when "111111111000000000000",
"000000000001011010100" when "111111111000100000000",
"111111111111111111111" when "111111111001000000000",
"111111111110100101011" when "111111111001100000000",
"111111111110000000000" when "111111111010000000000",
"111111111110100101011" when "111111111010100000000",
"000000000000000000000" when "111111111011000000000",
"000000000001011010100" when "111111111011100000000",
"000000000010000000000" when "111111111100000000000",
"000000000001110110010" when "111111111100010000000",
"000000000001011010100" when "111111111100100000000",
"000000000000110000111" when "111111111100110000000",
"111111111111111111111" when "111111111101000000000",
"111111111111001111000" when "111111111101010000000",
"111111111110100101011" when "111111111101100000000",
"111111111110001001101" when "111111111101110000000",
"111111111110000000000" when "111111111110000000000",
"111111111110000010011" when "111111111110001000000",
"111111111110001001101" when "111111111110010000000",
"111111111110010101100" when "111111111110011000000",
"111111111110100101011" when "111111111110100000000",
"111111111110111000111" when "111111111110101000000",
"111111111111001111000" when "111111111110110000000",
"111111111111100111000" when "111111111110111000000",
"000000000000000000000" when "111111111111000000000",
"000000000000011000111" when "111111111111001000000",
"000000000000110000111" when "111111111111010000000",
"000000000001000111000" when "111111111111011000000",
"000000000001011010100" when "111111111111100000000",
"000000000001101010011" when "111111111111101000000",
"000000000001110110010" when "111111111111110000000",
"000000000001111101100" when "111111111111111000000",
"000000000010000000000" when "000000000000000000000",
"000000000001111111011" when "000000000000000100000",
"000000000001111101100" when "000000000000001000000",
"000000000001111010011" when "000000000000001100000",
"000000000001110110010" when "000000000000010000000",
"000000000001110000111" when "000000000000010100000",
"000000000001101010011" when "000000000000011000000",
"000000000001100010111" when "000000000000011100000",
"000000000001011010100" when "000000000000100000000",
"000000000001010001001" when "000000000000100100000",
"000000000001000111000" when "000000000000101000000",
"000000000000111100010" when "000000000000101100000",
"000000000000110000111" when "000000000000110000000",
"000000000000100101001" when "000000000000110100000",
"000000000000011000111" when "000000000000111000000",
"000000000000001100100" when "000000000000111100000",
"000000000000000000000" when "000000000001000000000",
"111111111111110011011" when "000000000001000100000",
"111111111111100111000" when "000000000001001000000",
"111111111111011010110" when "000000000001001100000",
"111111111111001111000" when "000000000001010000000",
"111111111111000011101" when "000000000001010100000",
"111111111110111000111" when "000000000001011000000",
"111111111110101110110" when "000000000001011100000",
"111111111110100101011" when "000000000001100000000",
"111111111110011101000" when "000000000001100100000",
"111111111110010101100" when "000000000001101000000",
"111111111110001111000" when "000000000001101100000",
"111111111110001001101" when "000000000001110000000",
"111111111110000101100" when "000000000001110100000",
"111111111110000010011" when "000000000001111000000",
"111111111110000000100" when "000000000001111100000",
"111111111110000000000" when "000000000010000000000",
"111111111110000010011" when "000000000010001000000",
"111111111110001001101" when "000000000010010000000",
"111111111110010101100" when "000000000010011000000",
"111111111110100101011" when "000000000010100000000",
"111111111110111000111" when "000000000010101000000",
"111111111111001111000" when "000000000010110000000",
"111111111111100111000" when "000000000010111000000",
"111111111111111111111" when "000000000011000000000",
"000000000000011000111" when "000000000011001000000",
"000000000000110000111" when "000000000011010000000",
"000000000001000111000" when "000000000011011000000",
"000000000001011010100" when "000000000011100000000",
"000000000001101010011" when "000000000011101000000",
"000000000001110110010" when "000000000011110000000",
"000000000001111101100" when "000000000011111000000",
"000000000010000000000" when "000000000100000000000",
"000000000001110110010" when "000000000100010000000",
"000000000001011010100" when "000000000100100000000",
"000000000000110000111" when "000000000100110000000",
"000000000000000000000" when "000000000101000000000",
"111111111111001111000" when "000000000101010000000",
"111111111110100101011" when "000000000101100000000",
"111111111110001001101" when "000000000101110000000",
"111111111110000000000" when "000000000110000000000",
"111111111110001001101" when "000000000110010000000",
"111111111110100101011" when "000000000110100000000",
"111111111111001111000" when "000000000110110000000",
"111111111111111111111" when "000000000111000000000",
"000000000000110000111" when "000000000111010000000",
"000000000001011010100" when "000000000111100000000",
"000000000001110110010" when "000000000111110000000",
"000000000010000000000" when "000000001000000000000",
"000000000001011010100" when "000000001000100000000",
"000000000000000000000" when "000000001001000000000",
"111111111110100101011" when "000000001001100000000",
"111111111110000000000" when "000000001010000000000",
"111111111110100101011" when "000000001010100000000",
"111111111111111111111" when "000000001011000000000",
"000000000001011010100" when "000000001011100000000",
"000000000010000000000" when "000000001100000000000",
"000000000001011010100" when "000000001100100000000",
"111111111111111111111" when "000000001101000000000",
"111111111110100101011" when "000000001101100000000",
"111111111110000000000" when "000000001110000000000",
"111111111110100101011" when "000000001110100000000",
"111111111111111111111" when "000000001111000000000",
"000000000001011010100" when "000000001111100000000",
"000000000010000000000" when "000000010000000000000",
"111111111111111111111" when "000000010001000000000",
"111111111110000000000" when "000000010010000000000",
"111111111111111111111" when "000000010011000000000",
"000000000010000000000" when "000000010100000000000",
"111111111111111111111" when "000000010101000000000",
"111111111110000000000" when "000000010110000000000",
"111111111111111111111" when "000000010111000000000",
"000000000010000000000" when "000000011000000000000",
"111111111111111111111" when "000000011001000000000",
"111111111110000000000" when "000000011010000000000",
"111111111111111111111" when "000000011011000000000",
"000000000010000000000" when "000000011100000000000",
"111111111111111111111" when "000000011101000000000",
"111111111110000000000" when "000000011110000000000",
"111111111111111111111" when "000000011111000000000",
"000000000010000000000" when "000000100000000000000",
"000000000000000000000" when others;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY clr_mux IS
PORT
(
color : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
portb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
out_r : OUT STD_LOGIC;
out_g : OUT STD_LOGIC;
out_b : OUT STD_LOGIC
);
END clr_mux;
ARCHITECTURE bdf_type OF clr_mux IS
signal i0 : std_logic;
signal i1 : std_logic;
signal i2 : std_logic;
signal i3 : std_logic;
signal D591 : std_logic;
signal D592 : std_logic;
signal D593 : std_logic;
signal D594 : std_logic;
signal D601 : std_logic;
signal D602 : std_logic;
signal D603 : std_logic;
signal D604 : std_logic;
signal D611 : std_logic;
signal D612 : std_logic;
signal D613 : std_logic;
BEGIN
i0 <= color(1) or color(0);
i1 <= color(1) or not color(0);
i2 <= not color(1) or color(0);
i3 <= not color(1) or not color(0);
D591 <= portb(0) or i1;
D592 <= portb(1) or i3;
D593 <= portb(2) or i0;
D594 <= portb(3) or i0;
D601 <= D604 and i3;
D602 <= D592 and i2;
D603 <= D593 and i1;
D604 <= D591 and D594;
D611 <= portb(4) xor D601;
D612 <= portb(5) xor D602;
D613 <= portb(6) xor D603;
out_r <= not D611;
out_g <= not D612;
out_b <= not D613;
END bdf_type; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY clr_mux IS
PORT
(
color : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
portb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
out_r : OUT STD_LOGIC;
out_g : OUT STD_LOGIC;
out_b : OUT STD_LOGIC
);
END clr_mux;
ARCHITECTURE bdf_type OF clr_mux IS
signal i0 : std_logic;
signal i1 : std_logic;
signal i2 : std_logic;
signal i3 : std_logic;
signal D591 : std_logic;
signal D592 : std_logic;
signal D593 : std_logic;
signal D594 : std_logic;
signal D601 : std_logic;
signal D602 : std_logic;
signal D603 : std_logic;
signal D604 : std_logic;
signal D611 : std_logic;
signal D612 : std_logic;
signal D613 : std_logic;
BEGIN
i0 <= color(1) or color(0);
i1 <= color(1) or not color(0);
i2 <= not color(1) or color(0);
i3 <= not color(1) or not color(0);
D591 <= portb(0) or i1;
D592 <= portb(1) or i3;
D593 <= portb(2) or i0;
D594 <= portb(3) or i0;
D601 <= D604 and i3;
D602 <= D592 and i2;
D603 <= D593 and i1;
D604 <= D591 and D594;
D611 <= portb(4) xor D601;
D612 <= portb(5) xor D602;
D613 <= portb(6) xor D603;
out_r <= not D611;
out_g <= not D612;
out_b <= not D613;
END bdf_type; |
others => x"00000000"
);
begin
busy_o <= re_i; -- we're done on the cycle after we serve the read request
do_ram:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(addr_i)) <= write_i;
end if;
addr_r <= addr_i;
end if;
end process do_ram;
read_o <= ram(to_integer(addr_r));
end architecture Xilinx; -- Entity: SinglePortRAM
|
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
return y_temp(0);
end func;
begin
end architecture;
|
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
return y_temp(0);
end func;
begin
end architecture;
|
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
return y_temp(0);
end func;
begin
end architecture;
|
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
return y_temp(0);
end func;
begin
end architecture;
|
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
return y_temp(0);
end func;
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.01.2016 18:07:39
-- Design Name:
-- Module Name: debouncer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debouncer is
Port (
resetin : in std_logic;
resetout : out std_logic;
resetout_n : out std_logic
);
end debouncer;
architecture Behavioral of debouncer is
signal reset_internal: std_logic;
begin
-- reset button is normally high
reset_internal <= resetin;
resetout <= NOT reset_internal;
resetout_n <= reset_internal;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.01.2016 18:07:39
-- Design Name:
-- Module Name: debouncer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity debouncer is
Port (
resetin : in std_logic;
resetout : out std_logic;
resetout_n : out std_logic
);
end debouncer;
architecture Behavioral of debouncer is
signal reset_internal: std_logic;
begin
-- reset button is normally high
reset_internal <= resetin;
resetout <= NOT reset_internal;
resetout_n <= reset_internal;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Add_Frame_example is
end entity;
architecture rtl of tb_Add_Frame_example is
component tb_Add_Frame
end component;
begin
tb_Add_Frame_instance :
component tb_Add_Frame
port map();
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Add_Frame_example is
end entity;
architecture rtl of tb_Add_Frame_example is
component tb_Add_Frame
end component;
begin
tb_Add_Frame_instance :
component tb_Add_Frame
port map();
end architecture rtl;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: clock_gen_test-bench.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:29:43 $
--
--------------------------------------------------------------------------
--
-- Architecture for test bench for clock generator
--
architecture bench of clock_gen_test is
component clock_gen
port (phi1, phi2 : out bit;
reset : out bit);
end component;
for cg : clock_gen
use entity work.clock_gen(behaviour)
generic map (Tpw => 8 ns, Tps => 2 ns);
signal p1, p2, reset : bit;
begin
cg : clock_gen
port map (p1, p2, reset);
end bench;
|
-- Author: Osama Gamal M. Attia
-- email: ogamal [at] iastate dot edu
-- Description:
-- Process 3:
-- Read nodes from p2 response queue, request node CSR/Info
-- NOTE: (P2 response queue = P3 request queue + graphInfo)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity process3 is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
started : in std_logic;
-- Process 3 information
p3_done : out std_logic;
p3_count : out unsigned(31 downto 0);
-- Input Graph Pointers (Represented in Custom CSR)
graphInfo : in std_logic_vector(63 downto 0);
-- Process 2 information
p2_done : in std_logic;
p2_count_2 : in unsigned(31 downto 0);
-- Process 3 req queue signals
p3_req_q_almost_full : in std_logic;
p3_req_q_wr_en : out std_logic;
p3_req_q_din : out std_logic_vector(63 downto 0);
p3_req_q_full : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0)
);
end entity ; -- process3
architecture arch of process3 is
signal count : unsigned (31 downto 0);
begin
p3_count <= count;
p3 : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
p3_done <= '0';
count <= (others => '0');
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
else
if (started = '1') then
-- Got process 2 response
if (p3_req_q_almost_full = '0' and mc_rsp_push = '1' and mc_rsp_rdctl(7 downto 0) = x"02") then
-- request graphInfo + Neigh ID
p3_req_q_wr_en <= '1';
p3_req_q_din <= std_logic_vector(resize(8 * unsigned(mc_rsp_data(31 downto 0)) + unsigned(graphInfo), 64));
count <= count + 1;
else
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
end if;
-- Process 3 is done if process 2 is done and count = p2_count_2
if (p2_done = '1' and count = p2_count_2) then
p3_done <= '1';
end if;
else
p3_done <= '0';
count <= (others => '0');
p3_req_q_wr_en <= '0';
p3_req_q_din <= (others => '0');
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- process 3
end architecture; -- arch |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port (a, b : in std_logic_vector(7 downto 0);
o, p : out std_logic);
end test;
architecture behav of test is
begin
o <= or a;
p <= and b;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:03:07 11/04/2014
-- Design Name:
-- Module Name: modulo_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity modulo_display is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
entrada_s : in STD_LOGIC_VECTOR (15 downto 0);
saida_8segmentos : out STD_LOGIC_VECTOR (7 downto 0);
disp_sel_o : out STD_LOGIC_VECTOR (3 downto 0));
end modulo_display;
architecture Behavioral of modulo_display is
signal display_s : STD_LOGIC_VECTOR (15 downto 0);
begin
bcd2hex_p : entity work.hex2bcd
port map ( clk => clock,
sw0 => entrada_s(3 downto 0),
sw1 => entrada_s(7 downto 4),
sw2 => entrada_s(11 downto 8),
sw3 => entrada_s(15 downto 12),
bcd0 => display_s(3 downto 0),
bcd1 => display_s(7 downto 4),
bcd2 => display_s(11 downto 8),
bcd3 => display_s(15 downto 12));
display1 : entity work.disp7segx4
port map ( entrada => display_s,
clock => clock,
reset => reset,
saida_8segmentos => saida_8segmentos,
disp_sel_o => disp_sel_o );
end Behavioral;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: components
-- Date: 23:15 10/12/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package gpibComponents is
component if_func_AH is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rdy : in std_logic; -- ready for next message
tcs : in std_logic; -- take control synchronously
-- state inputs
LACS : in std_logic; -- listener active state
LADS : in std_logic; -- listener addressed state
-- interface inputs
ATN : in std_logic; -- attention
DAV : in std_logic; -- data accepted
-- interface outputs
RFD : out std_logic; -- ready for data
DAC : out std_logic; -- data accepted
-- reported state
ANRS : out std_logic; -- acceptor not ready state
ACDS : out std_logic -- accept data state
);
end component;
component if_func_SH is
port(
-- device inputs
clk : in std_logic; -- clock
-- settingd
T1 : in std_logic_vector (7 downto 0);
-- local commands
pon : in std_logic; -- power on
nba : in std_logic; -- new byte available
-- state inputs
TACS : in std_logic; -- talker active state
SPAS : in std_logic; -- seriall poll active state
CACS : in std_logic; -- controller active state
CTRS : in std_logic; -- controller transfer state
-- interface inputs
ATN : in std_logic; -- attention
DAC : in std_logic; -- data accepted
RFD : in std_logic; -- ready for data
-- remote instructions
DAV : out std_logic; -- data address valid
-- device outputs
wnc : out std_logic; -- wait for new cycle
-- reported states
STRS : out std_logic; -- source transfer state
SDYS : out std_logic -- source delay state
);
end component;
component if_func_L_LE is
port(
-- clock
clk : in std_logic; -- clock
-- function settings
isLE : in std_logic;
-- local commands
pon : in std_logic; -- power on
ltn : in std_logic; -- listen
lun : in std_logic; -- local unlisten
lon : in std_logic; -- listen only
-- state inputs
ACDS : in std_logic; -- accept data state (AH)
CACS : in std_logic; -- controller active state (C)
TPAS : in std_logic; -- talker primary address state (T)
-- remote commands
ATN : in std_logic; -- attention
IFC : in std_logic; -- interface clear
MLA : in std_logic; -- my listen address
MTA : in std_logic; -- my talk address
UNL : in std_logic; -- unlisten
PCG : in std_logic; -- primary command group
MSA : in std_logic; -- my secondary address
-- reported states
LACS : out std_logic; -- listener active state
LADS : out std_logic; -- listener addressed state
LPAS : out std_logic -- listener primary addressed state
;debug1 : out std_logic
);
end component;
component if_func_T_TE is
port(
-- clock
clk : in std_logic; -- clock
-- function settings
isTE : in std_logic;
-- local instruction inputs
pon : in std_logic; -- power on
ton : in std_logic; -- talk only
endOf : in std_logic; -- end of byte string
-- state inputs
ACDS : in std_logic; -- accept data state (AH)
APRS : in std_logic; -- affirmative poll response
LPAS : in std_logic; -- listener primary state (LE)
-- remote instruction inputs
ATN : in std_logic; -- attention
IFC : in std_logic; -- interface clear
SPE : in std_logic; -- serial poll enable
SPD : in std_logic; -- serial poll disable
MTA : in std_logic; -- my talk address
OTA : in std_logic; -- other talk address
MLA : in std_logic; -- my listen address
OSA : in std_logic; -- other secondary address
MSA : in std_logic; -- my secondary address
PCG : in std_logic; -- primary command group
-- remote instruction outputs
END_OF : out std_logic; -- end of data
RQS : out std_logic; -- data accepted
DAB : out std_logic; -- data byte
EOS : out std_logic; -- end of string
STB : out std_logic; -- status byte
-- local instruction outputs
tac : out std_logic; -- talker active
-- reported states
SPAS : out std_logic; -- serial poll active state
TPAS : out std_logic; -- transmitter active state
TADS : out std_logic; -- talker addressed state
TACS : out std_logic -- talker active state
);
end component;
component if_func_C is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
gts : in std_logic; -- go to standby
rpp : in std_logic; -- request parallel poll
tcs : in std_logic; -- take control synchronously
tca : in std_logic; -- take control asynchronously
sic : in std_logic; -- send interface clear
rsc : in std_logic; -- request system control
sre : in std_logic; -- send remote enable
-- state inputs
TADS : in std_logic; -- talker addressed state (T or TE)
ACDS : in std_logic; -- accept data state (AH)
ANRS : in std_logic; -- acceptor not ready state (AH)
STRS : in std_logic; -- source transfer state (SH)
SDYS : in std_logic; -- source delay state (SH)
-- command inputs
ATN_in : in std_logic; -- attention
IFC_in : in std_logic; -- interface clear
TCT_in : in std_logic; -- take control
SRQ_in : in std_logic; -- service request
-- command outputs
ATN_out : out std_logic; -- attention
IFC_out : out std_logic; -- interface clear
TCT_out : out std_logic; -- take control
IDY_out : out std_logic; -- identify
REN_out : out std_logic; -- remote enable
-- reported states
CACS : out std_logic; -- controller active state
CTRS : out std_logic; -- controller transfer state
CSBS : out std_logic; -- controller standby state
CPPS : out std_logic; -- controller parallel poll state
CSRS : out std_logic; -- controller service requested state
SACS : out std_logic -- system control active state
);
end component;
component if_func_DC is
port(
-- device inputs
clk : in std_logic; -- clock
-- state inputs
LADS : in std_logic; -- listener addressed state (L or LE)
ACDS : in std_logic; -- accept data state (AH)
-- instructions
DCL : in std_logic; -- my listen address
SDC : in std_logic; -- unlisten
-- local instructions
clr : out std_logic -- clear device
);
end component;
component if_func_DT is
port(
-- device inputs
clk : in std_logic; -- clock
-- state inputs
LADS : in std_logic; -- listener addressed state (L or LE)
ACDS : in std_logic; -- accept data state (AH)
-- instructions
GET : in std_logic; -- group execute trigger
-- local instructions
trg : out std_logic -- trigger
);
end component;
component if_func_PP is
port(
-- device inputs
clk : in std_logic; -- clock
-- settings
lpeUsed : std_logic;
fixedPpLine : in std_logic_vector (2 downto 0);
-- local commands
pon : in std_logic; -- power on
lpe : in std_logic; -- local poll enable
ist : in std_logic; -- individual status
-- state inputs
ACDS : in std_logic; -- accept data state
LADS : in std_logic; -- listener address state (L or LE)
-- data input
dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
-- remote command inputs
IDY : in std_logic; -- identify
PPE : in std_logic; -- parallel poll enable
PPD : in std_logic; -- parallel poll disable
PPC : in std_logic; -- parallel poll configure
PPU : in std_logic; -- parallel poll unconfigure
PCG : in std_logic; -- primary command group
-- remote command outputs
PPR : out std_logic; -- paralel poll response
-- PPR command data
ppBitValue : out std_logic; -- bit value
ppLineNumber : out std_logic_vector (2 downto 0);
-- reported states
PPAS : out std_logic -- parallel poll active state
);
end component;
component if_func_RL is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rtl : in std_logic; -- return to local
-- state inputs
ACDS : in std_logic; -- listener active state (AH)
LADS : in std_logic; -- listener addressed state (L or LE)
-- instructions
REN : in std_logic; -- remote enable
LLO : in std_logic; -- local lockout
MLA : in std_logic; -- my listen address
GTL : in std_logic; -- go to local
-- reported state
LOCS : out std_logic; -- local state
LWLS : out std_logic -- local with lockout state
);
end component;
component if_func_SR is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rsv : in std_logic; -- service request
-- state inputs
SPAS : in std_logic; -- serial poll active state (T or TE)
-- output instructions
SRQ : out std_logic; -- service request
-- reported states
APRS : out std_logic -- affirmative poll response state
);
end component;
component commandEcoder is
port (
-- data
data : in std_logic_vector (7 downto 0);
-- status byte
status_byte : in std_logic_vector (7 downto 0);
-- PPR command data
ppBitValue : in std_logic;
ppLineNumber : in std_logic_vector (2 downto 0);
-- func states
APRS : in std_logic; -- affirmative poll response state
CACS : in std_logic; -- controller active state (C)
-- commands
ATN : in std_logic;
END_OF : in std_logic;
IDY : in std_logic;
DAC : in std_logic;
RFD : in std_logic;
DAV : in std_logic;
IFC : in std_logic;
REN : in std_logic;
SRQ : in std_logic; -- request for service
DAB : in std_logic;
EOS : in std_logic;
RQS : in std_logic; -- part of STB
STB : in std_logic;
TCT : in std_logic;
PPR : in std_logic;
-------------------------------------------
-- data lines -----------------------------
-------------------------------------------
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-------------------------------------------
-- control lines --------------------------
-------------------------------------------
-- DAV line
DAV_line : out std_logic;
-- NRFD line
NRFD_line : out std_logic;
-- NDAC line
NDAC_line : out std_logic;
-- ATN line
ATN_line : out std_logic;
-- EOI line
EOI_line : out std_logic;
-- SRQ line
SRQ_line : out std_logic;
-- IFC line
IFC_line : out std_logic;
-- REN line
REN_line : out std_logic
);
end component;
component commandDecoder is
port (
-------------------------------------------
-- data lines -----------------------------
-------------------------------------------
DI : in std_logic_vector (7 downto 0);
-------------------------------------------
-- control lines --------------------------
-------------------------------------------
-- DAV line
DAV_line : in std_logic;
-- NRFD line
NRFD_line : in std_logic;
-- NDAC line
NDAC_line : in std_logic;
-- ATN line
ATN_line : in std_logic;
-- EOI line
EOI_line : in std_logic;
-- SRQ line
SRQ_line : in std_logic;
-- IFC line
IFC_line : in std_logic;
-- REN line
REN_line : in std_logic;
-------------------------------------------
-- internal settiongs ---------------------
-------------------------------------------
-- eos mark
eosMark : in std_logic_vector (7 downto 0);
-- eos used
eosUsed : in std_logic;
-- my listen address
myListAddr : in std_logic_vector (4 downto 0);
-- my talk address
myTalkAddr : in std_logic_vector (4 downto 0);
-- secondary address detected
secAddrDetected : in std_logic;
-------------------------------------------
-- internal states ------------------------
-------------------------------------------
-- serial poll active state (T or TE)
SPAS : in std_logic;
-------------------------------------------
-- single line commands -------------------
-------------------------------------------
-- attention
ATN : out std_logic;
-- data accepted
DAC : out std_logic;
-- data valid
DAV : out std_logic;
-- end
END_c : out std_logic;
-- identify
IDY : out std_logic;
-- interface clear
IFC : out std_logic;
-- remote enable
REN : out std_logic;
-- ready for data
RFD : out std_logic;
-- service request
SRQ : out std_logic;
-------------------------------------------
-- multi line commands --------------------
-------------------------------------------
-- addressed command group
ACG : out std_logic;
-- data byte
DAB : out std_logic;
-- device clear
DCL : out std_logic;
-- end of string
EOS : out std_logic;
-- group execute trigger
GET : out std_logic;
-- go to local
GTL : out std_logic;
-- listen address group
LAG : out std_logic;
-- local lockout
LLO : out std_logic;
-- my listen address
MLA : out std_logic;
-- my talk address
MTA : out std_logic;
-- my secondary address
MSA : out std_logic;
-- null byte
NUL : out std_logic;
-- other secondary address
OSA : out std_logic;
-- other talk address
OTA : out std_logic;
-- primary command group
PCG : out std_logic;
-- parallel poll configure
PPC : out std_logic;
-- parallel poll enable
PPE : out std_logic;
-- parallel poll disable
PPD : out std_logic;
-- parallel poll response
PPR : out std_logic;
-- parallel poll unconfigure
PPU : out std_logic;
-- request service
RQS : out std_logic;
-- secondary command group
SCG : out std_logic;
-- selected device clear
SDC : out std_logic;
-- serial poll disable
SPD : out std_logic;
-- serial poll enable
SPE : out std_logic;
-- status byte
STB : out std_logic;
-- talk address group
TAG : out std_logic;
-- take control
TCT : out std_logic;
-- universal command group
UCG : out std_logic;
-- unlisten
UNL : out std_logic;
-- untalk
UNT : out std_logic
);
end component;
component SecondaryAddressDecoder is
port (
-- secondary address mask
secAddrMask : in std_logic_vector (31 downto 0);
-- data input
DI : in std_logic_vector (4 downto 0);
-- secondary address detected
secAddrDetected : out std_logic
);
end component;
component SecAddrSaver is
port (
reset : in std_logic;
------------------- gpib ----------------------
TADS : in std_logic;
TPAS : in std_logic;
LADS : in std_logic;
LPAS : in std_logic;
MSA_Dec : in std_logic;
DI : in std_logic_vector(4 downto 0);
currentSecAddr : out std_logic_vector(4 downto 0)
);
end component;
component gpibInterface is port (
clk : in std_logic;
reset : std_logic;
-- application interface
isLE : in std_logic;
isTE : in std_logic;
lpeUsed : in std_logic;
fixedPpLine : in std_logic_vector (2 downto 0);
eosUsed : in std_logic;
eosMark : in std_logic_vector (7 downto 0);
myListAddr : in std_logic_vector (4 downto 0);
myTalkAddr : in std_logic_vector (4 downto 0);
secAddrMask : in std_logic_vector (31 downto 0);
data : in std_logic_vector (7 downto 0);
status_byte : in std_logic_vector (7 downto 0);
T1 : in std_logic_vector (7 downto 0);
-- local commands to interface
rdy : in std_logic; -- ready for next message (AH)
nba : in std_logic; -- new byte available (SH)
ltn : in std_logic; -- listen (L, LE)
lun : in std_logic; -- local unlisten (L, LE)
lon : in std_logic; -- listen only (L, LE)
ton : in std_logic; -- talk only (T, TE)
endOf : in std_logic; -- end of byte string (T, TE)
gts : in std_logic; -- go to standby (C)
rpp : in std_logic; -- request parallel poll (C)
tcs : in std_logic; -- take control synchronously (C, AH)
tca : in std_logic; -- take control asynchronously (C)
sic : in std_logic; -- send interface clear (C)
rsc : in std_logic; -- request system control (C)
sre : in std_logic; -- send remote enable (C)
rtl : in std_logic; -- return to local (RL)
rsv : in std_logic; -- request service (SR)
ist : in std_logic; -- individual status (PP)
lpe : in std_logic; -- local poll enable (PP)
-- local commands from interface
dvd : out std_logic; -- data valid (AH)
wnc : out std_logic; -- wait for new cycle (SH)
tac : out std_logic; -- talker active (T, TE)
lac : out std_logic; -- listener active (L, LE)
cwrc : out std_logic; -- controller write commands
cwrd : out std_logic; -- controller write data
clr : out std_logic; -- clear device (DC)
trg : out std_logic; -- trigger device (DT)
atl : out std_logic; -- addressed to listen (T or TE)
att : out std_logic; -- addressed to talk(L or LE)
mla : out std_logic; -- my listen addres decoded (L or LE)
lsb : out std_logic; -- last byte
spa : out std_logic; -- seriall poll active
ppr : out std_logic; -- parallel poll ready
sreq : out std_logic; -- service requested
isLocal : out std_logic; -- device is local controlled
currentSecAddr : out std_logic_vector (4 downto 0); -- current sec addr
-- interface signals
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-- attention
ATN_in : in std_logic;
ATN_out : out std_logic;
-- data valid
DAV_in : in std_logic;
DAV_out : out std_logic;
-- not ready for data
NRFD_in : in std_logic;
NRFD_out : out std_logic;
-- no data accepted
NDAC_in : in std_logic;
NDAC_out : out std_logic;
-- end or identify
EOI_in : in std_logic;
EOI_out : out std_logic;
-- service request
SRQ_in : in std_logic;
SRQ_out : out std_logic;
-- interface clear
IFC_in : in std_logic;
IFC_out : out std_logic;
-- remote enable
REN_in : in std_logic;
REN_out : out std_logic
;debug1 : out std_logic
);
end component;
end gpibComponents; |
library ieee;
use ieee.std_logic_1164.all;
-- Simulates the A and B signal of the rotatory key encoder
entity rotKeyGen is
port (
A: out std_logic;
B: out std_logic;
Push : out std_logic
);
end entity rotKeyGen;
architecture RTL of rotKeyGen is
begin
-- This process generates the A and B signals
-- YOU may modify this for your own test cases !
process
begin
while TRUE loop
A<='0';
B<='0';
wait for 300 ns;
A<='1';
B<='0';
wait for 10 ns;
A<='0';
B<='0';
wait for 10 ns;
A<='1';
B<='0';
wait for 200 ns;
A<='1';
B<='1';
wait for 10 ns;
A<='1';
B<='0';
wait for 10 ns;
A<='1';
B<='1';
wait for 1 us;
A<='0';
B<='1';
wait for 10 ns;
A<='1';
B<='1';
wait for 10 ns;
A<='0';
B<='1';
wait for 200 ns;
A<='0';
B<='0';
wait for 10 ns;
A<='0';
B<='1';
wait for 10 ns;
A<='0';
B<='0';
wait for 500 ns;
wait for 200 ns;
A<='0';
B<='1';
wait for 200 ns;
A<='1';
B<='1';
wait for 1 us;
A<='1';
B<='0';
wait for 200 ns;
A<='0';
B<='0';
wait for 100 ms;
end loop;
end process;
end architecture RTL;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
hackVector : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, hackVector);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
hackVector : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, hackVector);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block2.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block2
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block2 IS
-- Signals
SIGNAL dout_6_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_6_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_7_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_7_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_6_re_signed <= signed(dout_6_re);
dout_6_im_signed <= signed(dout_6_im);
dout_8_re_signed <= signed(dout_8_re);
dout_8_im_signed <= signed(dout_8_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_6_re_signed, dout_6_im_signed,
dout_8_re_signed, dout_8_im_signed, dout_1_vld, rotate_7)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_7 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_6_re_signed, 17);
add_cast_2 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_6_re_signed, 17);
sub_cast_2 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_6_im_signed, 17);
add_cast_6 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_6_im_signed, 17);
sub_cast_6 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_6_re_signed, 17);
add_cast_0 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_6_re_signed, 17);
sub_cast_0 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_6_im_signed, 17);
add_cast_4 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_6_im_signed, 17);
sub_cast_4 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_7_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_7_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_8_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_8_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re_1 <= std_logic_vector(dout_8_re_tmp);
dout_8_im_1 <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:18 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_1/bram_2048_1_stub.vhdl
-- Design : bram_2048_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bram_2048_1 is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end bram_2048_1;
architecture stub of bram_2048_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:18 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_1/bram_2048_1_stub.vhdl
-- Design : bram_2048_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bram_2048_1 is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end bram_2048_1;
architecture stub of bram_2048_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
------------------------------------------------------------------------------
-- hw_acc - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hw_acc
-- Version: 1.00.a
-- Description: Example Axi Streaming core (VHDL).
-- Date: Mon Sep 15 15:41:21 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- ACLK : Synchronous clock
-- ARESETN : System reset, active low
-- S_AXIS_TREADY : Ready to accept data in
-- S_AXIS_TDATA : Data in
-- S_AXIS_TLAST : Optional data in qualifier
-- S_AXIS_TVALID : Data in is valid
-- M_AXIS_TVALID : Data out is valid
-- M_AXIS_TDATA : Data Out
-- M_AXIS_TLAST : Optional data out qualifier
-- M_AXIS_TREADY : Connected slave device is ready to accept data out
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity myip_v1_0 is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "Clk";
end myip_v1_0;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENTITY hw_acc
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output stream NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY hw_acc to implement your coprocessor
architecture EXAMPLE of myip_v1_0 is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 2;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 2;
type STATE_TYPE is (Idle, Read_Input1, Read_Input2, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold product of inputs read at any point in time
signal product : unsigned(63 downto 0);
signal product_vector : std_logic_vector(63 downto 0);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
begin
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's hw_acc.c file
S_AXIS_TREADY <= '1' when (state = Read_Input1 or state = Read_Input2) else '0';
M_AXIS_TVALID <= '1' when state = Write_Outputs else '0';
M_AXIS_TLAST <= '1' when (state = Write_Outputs and nr_of_writes = 0) else '0';
--Output MSB first
product_vector <= std_logic_vector(product);
M_AXIS_TDATA <= product_vector(63 downto 32);
The_SW_accelerator : process (ACLK) is
begin -- process The_SW_accelerator
if ACLK'event and ACLK = '1' then -- Rising clock edge
if ARESETN = '0' then -- Synchronous reset (active low)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
product <= (others => '0');
else
case state is
when Idle =>
if (S_AXIS_TVALID = '1') then
state <= Read_Input1;
--Subtract 2 because the first input word is always directly copied to the product.
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
product <= (others => '0');
end if;
when Read_Input1 =>
if (S_AXIS_TVALID = '1') then
--The first number is always stored in the product.
product <= resize(unsigned(S_AXIS_TDATA), product'length);
state <= Read_Input2;
nr_of_reads <= nr_of_reads - 1;
end if;
when Read_Input2 =>
if(S_AXIS_TVALID = '1') then
--Subsequent numbers multiply the existing product.
product <= resize(product*unsigned(S_AXIS_TDATA), product'length);
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when Write_Outputs =>
if (M_AXIS_TREADY = '1') then
if (nr_of_writes = 0) then
state <= Idle;
else
nr_of_writes <= nr_of_writes - 1;
--Shift the product one whole word to the left.
product <= shift_left(product, 32);
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mcore
-- File: mcore.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: Module containing the processor, caches, memory controller
-- and standard peripherals
------------------------------------------------------------------------------
-- 29.01.02 added signals for DDM
-- 13.03.02 mdct dummy core added LA
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.ambacomp.all;
use work.mdctlib.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity mcore is
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
ddmi : in ddm_in_type; --LA
ddmo : out ddm_out_type; --LA
test : in std_logic
);
end;
architecture rtl of mcore is
component clkgen
port (
clk : in std_logic;
pciclk : in std_logic;
clki : in clkgen_in_type;
clko : out clkgen_out_type
);
end component;
component rstgen
port (
resetn : in std_logic;
pcirst : in std_logic;
clk : in clk_type;
rst : out rst_type
);
end component;
signal rst : rst_type;
signal clko : clkgen_out_type;
signal clki : clkgen_in_type;
signal iui : iu_in_type;
signal iuo : iu_out_type;
signal ahbsto: ahbstat_out_type;
signal mctrlo: mctrl_out_type;
signal wpo : wprot_out_type;
signal apbi : apb_slv_in_vector(0 to APB_SLV_MAX-1);
signal apbo : apb_slv_out_vector(0 to APB_SLV_MAX-1);
signal ahbmi : ahb_mst_in_vector(0 to AHB_MST_MAX-1);
signal ahbmo : ahb_mst_out_vector(0 to AHB_MST_MAX-1);
signal ahbsi : ahb_slv_in_vector(0 to AHB_SLV_MAX-1);
signal ahbso : ahb_slv_out_vector(0 to AHB_SLV_MAX-1);
signal pciresetn, pciirq : std_logic;
signal irqi : irq_in_type;
signal irqo : irq_out_type;
signal irq2i : irq2_in_type;
signal irq2o : irq2_out_type;
signal timo : timers_out_type;
signal pioo : pio_out_type;
signal uart1i, uart2i : uart_in_type;
signal uart1o, uart2o : uart_out_type;
signal ddmirq : std_logic; -- LA
signal mdctirq : std_logic; -- LA
begin
-- reset generator
reset0 : rstgen port map (resetn, pciresetn, clko.clk, rst);
-- clock generator
clkgen0 : clkgen port map (clk, pcii.pci_clk_in, clki, clko);
----------------------------------------------------------------------
-- AHB bus --
----------------------------------------------------------------------
-- AHB arbiter/decoder
ahb0 : ahbarb
generic map (masters => AHB_MASTERS, defmast => AHB_DEFMST)
port map (rst.syncrst, clko.clk, ahbmi(0 to AHB_MASTERS-1),
ahbmo(0 to AHB_MASTERS-1), ahbsi, ahbso);
-- AHB/APB bridge
apb0 : apbmst
port map (rst.syncrst, clko.clk, ahbsi(1), ahbso(1), apbi, apbo);
-- processor and cache sub-system
proc0 : proc port map (
rst.syncrst, clki, clko, apbi(2), apbo(2), ahbmi(0), ahbmo(0), iui, iuo);
-- memory controller
mctrl0 : mctrl port map (
rst => rst, clk=> clko.clk, memi => memi, memo => memo,
ahbsi => ahbsi(0), ahbso => ahbso(0), apbi => apbi(0), apbo => apbo(0),
pioo => pioo, wpo => wpo, mctrlo => mctrlo);
-- AHB write protection
wp0 : if WPROTEN generate
wpm : wprot port map (
rst => rst, clk => clko.clk, wpo => wpo, ahbsi => ahbsi(0),
apbi => apbi(3), apbo => apbo(3));
end generate;
wp1 : if not WPROTEN generate apbo(3).prdata <= (others => '0'); end generate;
-- AHB status register
as0 : if AHBSTATEN generate
asm : ahbstat port map (
rst => rst, clk => clko.clk, ahbmi => ahbmi(0), ahbsi => ahbsi(0),
apbi => apbi(1), apbo => apbo(1), ahbsto => ahbsto);
end generate;
as1 : if not AHBSTATEN generate
apbo(1).prdata <= (others => '0'); ahbsto.ahberr <= '0';
end generate;
-- AHB test module
ahbt : if PCICORE = ahbtst generate
a0 : ahbtest port map ( rst => rst.syncrst, clk => clko.clk,
ahbi => ahbsi(2), ahbo => ahbso(2)
);
pci0 : pci_is
port map (
rst_n => rst.syncrst, app_clk => clko.clk, pci_clk => clko.pciclk,
pbi => apbi(10), pbo => apbo(10), irq => pciirq,
TargetMasterOut => ahbmo(1), TargetMasterIn => ahbmi(1),
pci_in => pcii, pci_out => pcio,
InitSlaveOut => ahbso(3), InitSlaveIn => ahbsi(3),
InitMasterOut => ahbmo(2), InitMasterIn => ahbmi(2)
);
pciresetn <= '1';
end generate;
-- Optional InSilicon PCI core
pci_is0 : if PCICORE = insilicon generate
pci0 : pci_is
port map (
rst_n => rst.syncrst, app_clk => clko.clk, pci_clk => clko.pciclk,
pbi => apbi(10), pbo => apbo(10), irq => pciirq,
TargetMasterOut => ahbmo(1), TargetMasterIn => ahbmi(1),
pci_in => pcii, pci_out => pcio,
InitSlaveOut => ahbso(2), InitSlaveIn => ahbsi(2),
InitMasterOut => ahbmo(2), InitMasterIn => ahbmi(2)
);
pciresetn <= pcii.pci_rst_in_n;
end generate;
-- Optional ESA PCI core
pci_esa0 : if PCICORE = esa generate
pci0 : pci_esa
port map (
resetn => rst.syncrst, app_clk => clko.clk,
pci_in => pcii, pci_out => pcio,
ahbmasterin => ahbmi(1), ahbmasterout => ahbmo(1),
ahbslavein => ahbsi(2), ahbslaveout => ahbso(2),
apbslavein => apbi(10), apbslaveout => apbo(10), irq => pciirq
);
pciresetn <= pcii.pci_rst_in_n;
end generate;
pr0 : if not PCIEN generate pciirq <= '0'; pciresetn <= '0'; end generate;
-- drive unused part of the AHB bus to stop some stupid synthesis tools
-- from inserting tri-state buffers (!)
ahbdrv : for i in 0 to AHB_SLV_MAX-1 generate
u0 : if not AHB_SLVTABLE(i).enable generate
ahbso(i).hready <= '-'; ahbso(i).hresp <= "--";
ahbso(i).hrdata <= (others => '-');
ahbso(i).hsplit <= (others => '-');
end generate;
end generate;
----------------------------------------------------------------------
-- APB bus --
----------------------------------------------------------------------
pci_arb0 : if PCIARBEN generate
pciarb : pci_arb
port map (
clk => pcii.pci_clk_in, rst_n => rst.syncrst,
req_n => ioi.pci_arb_req_n, frame_n => pcii.pci_frame_in_n,
gnt_n => ioo.pci_arb_gnt_n, pclk => clko.clk,
prst_n => pcii.pci_rst_in_n, pbi => apbi(11), pbo => apbo(11)
);
end generate;
-- LEON configuration register
lc0 : if CFGREG generate
lcm : lconf port map (rst => rst, apbo => apbo(4));
end generate;
-- timers (and watchdog)
timers0 : timers
port map (rst => rst.syncrst, clk => clko.clk, apbi => apbi(5),
apbo => apbo(5), timo => timo);
-- UARTS
-- This stupidity exists because synopsys DC is not capable of
-- handling record elements in port maps. Sad really ...
uart1i.rxd <= pioo.rxd(0); uart1i.ctsn <= pioo.ctsn(0);
uart2i.rxd <= pioo.rxd(1); uart2i.ctsn <= pioo.ctsn(1);
uart1i.scaler <= pioo.io8lsb; uart2i.scaler <= pioo.io8lsb;
uart1 : uart port map (
rst => rst.syncrst, clk => clko.clk, apbi => apbi(6), apbo => apbo(6),
uarti => uart1i, uarto => uart1o);
uart2 : uart port map (
rst => rst.syncrst, clk => clko.clk, apbi => apbi(7), apbo => apbo(7),
uarti => uart2i, uarto => uart2o);
-- interrupt controller
irqctrl0 : irqctrl
port map (rst => rst.syncrst, clk => clko.clk, apbi => apbi(8),
apbo => apbo(8), irqi => irqi, irqo => irqo);
irqi.intack <= iuo.intack; irqi.irl <= iuo.irqvec; iui.irl <= irqo.irl;
-- optional secondary interrupt controller
i2 : if IRQ2EN generate
irqctrl1 : irqctrl2
port map (rst => rst.syncrst, clk => clko.clk, apbi => apbi(10),
apbo => apbo(10), irqi => irq2i, irqo => irq2o);
end generate;
-- parallel I/O port
ioport0 : ioport
port map (rst => rst, clk => clko.clk, apbi => apbi(9), apbo => apbo(9),
uart1o => uart1o, uart2o => uart2o, mctrlo => mctrlo,
ioi => ioi, pioo => pioo);
-- ddm
ddm0 : ddm
port map (rst => rst.syncrst, clk => clk, apbi => apbi(11), apbo => apbo(11),
ahbi => ahbmi(1), ahbo => ahbmo(1), ddmo => ddmo, ddmi => ddmi,
irq => ddmirq ); -- LA
-- mdct
mdct0 : mdct
port map (rst => rst.syncrst, clk => clk, apbi => apbi(12), apbo => apbo(12),
ahbi => ahbmi(2), ahbo => ahbmo(2), irq => mdctirq ); -- LA
-- drive unused part of the APB bus to stop some stupid synthesis tools
-- from inserting tri-state buffers (!)
apbdrv : for i in 0 to APB_SLV_MAX-1 generate
u0 : if not APB_TABLE(i).enable generate
apbo(i).prdata <= (others => '-');
end generate;
end generate;
-- IRQ assignments, add you mapping below
irqi.irq(15) <= '0'; -- unmaskable irq
irqi.irq(14) <= pciirq;
irqi.irq(13) <= ddmirq; -- LA
irqi.irq(12) <= mdctirq; -- LA
irqi.irq(11 downto 10) <= (others => '0'); -- unassigned irqs
-- irqi.irq(10) <= irq2o.irq when IRQ2EN else '0';
irqi.irq(9) <= timo.irq(1); -- timer 2
irqi.irq(8) <= timo.irq(0); -- timer 1
irqi.irq(7 downto 4) <= pioo.irq; -- I/O port interrupts
irqi.irq(3) <= uart1o.irq; -- UART 1
irqi.irq(2) <= uart2o.irq; -- UART 2
irqi.irq(1) <= ahbsto.ahberr; -- AHB error
-- additional 32 interrupts for secondary interrupt controller
irq2i.irq <= (others => '0');
-- drive outputs
ioo.piol <= pioo.piol(15 downto 0);
ioo.piodir <= pioo.piodir(15 downto 0);
ioo.wdog <= timo.wdog;
ioo.errorn <= iuo.error;
-- disassambler
-- pragma translate_off
trace0 : trace(iuo.debug, (test = '1'));
-- pragma translate_on
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
port
(
nibble1, nibble2 : in unsigned(3 downto 0);
sum : out unsigned(3 downto 0);
carry_out : out std_logic
);
end entity adder;
architecture behavioral of adder is
signal temp : unsigned(4 downto 0);
begin
temp <= ("0" & nibble1) + nibble2;
sum <= temp(3 downto 0);
carry_out <= temp(4);
end architecture behavioral;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_rnd;
architecture behaviour of ex2_rnd is
constant s1: std_logic_vector(4 downto 0) := "11101";
constant s2: std_logic_vector(4 downto 0) := "00010";
constant s4: std_logic_vector(4 downto 0) := "11011";
constant s0: std_logic_vector(4 downto 0) := "11110";
constant s3: std_logic_vector(4 downto 0) := "11111";
constant s6: std_logic_vector(4 downto 0) := "10001";
constant s9: std_logic_vector(4 downto 0) := "10110";
constant s7: std_logic_vector(4 downto 0) := "01011";
constant s8: std_logic_vector(4 downto 0) := "01111";
constant s5: std_logic_vector(4 downto 0) := "00001";
constant s10: std_logic_vector(4 downto 0) := "10000";
constant s11: std_logic_vector(4 downto 0) := "11010";
constant s13: std_logic_vector(4 downto 0) := "11000";
constant s12: std_logic_vector(4 downto 0) := "01000";
constant s15: std_logic_vector(4 downto 0) := "00100";
constant s18: std_logic_vector(4 downto 0) := "01001";
constant s16: std_logic_vector(4 downto 0) := "00110";
constant s17: std_logic_vector(4 downto 0) := "11100";
constant s14: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s3; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s7; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "11";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s10 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s13; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s12; output <= "--";
end if;
when s11 =>
if std_match(input, "00") then next_state <= s15; output <= "--";
elsif std_match(input, "01") then next_state <= s18; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s12 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s16; output <= "--";
elsif std_match(input, "11") then next_state <= s17; output <= "--";
end if;
when s13 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s10; output <= "00";
elsif std_match(input, "10") then next_state <= s15; output <= "--";
elsif std_match(input, "11") then next_state <= s14; output <= "--";
end if;
when s14 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s15; output <= "--";
end if;
when s15 =>
if std_match(input, "00") then next_state <= s10; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s11; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s16 =>
if std_match(input, "00") then next_state <= s14; output <= "11";
elsif std_match(input, "01") then next_state <= s11; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s17 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s10; output <= "00";
end if;
when s18 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s12; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
|
------------------------------------------------------------------------------
-- Title : DSP48E1-based MAC and data registered data propagation (1 stage)
------------------------------------------------------------------------------
-- Author : Daniel Tavares
-- Company : CNPEM LNLS-DIG
-- Created : 2019-11-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Elementary mulitply-accumulate block for systolic FIR filter
-- implementation. Use 1 pipeline stage at the input data.
-- Reference: "DSP: Designing for Optimal Results"
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-11-23 1.0 daniel.tavares Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity mac1reg is
port
(
clk_i : in std_logic;
data_i : in std_logic_vector (17 downto 0);
coef_i : in std_logic_vector (24 downto 0);
data_o : out std_logic_vector (17 downto 0);
mac_o : out std_logic_vector (47 downto 0);
casc_o : out std_logic_vector (47 downto 0)
);
end mac1reg;
architecture rtl of mac1reg is
signal coef : std_logic_vector(29 downto 0);
begin
DSP48E1_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT",
B_INPUT => "DIRECT",
USE_DPORT => FALSE,
USE_MULT => "MULTIPLY",
USE_SIMD => "ONE48",
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET",
MASK => X"3fffffffffff",
PATTERN => X"000000000000",
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_PATTERN_DETECT => "NO_PATDET",
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MREG => 1,
OPMODEREG => 0,
PREG => 1
)
port map (
CLK => clk_i,
A => coef,
B => data_i,
BCOUT => data_o,
PCOUT => casc_o,
P => mac_o,
BCIN => (others => '0'),
PCIN => (others => '0'),
INMODE => "10001",
OPMODE => "0000101",
ALUMODE => "0000",
-- Reset/Clock Enable Inputs
CEA1 => '1',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '0',
CECARRYIN => '0',
CECTRL => '1',
CED => '0',
CEINMODE => '0',
CEM => '1',
CEP => '1',
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
-- Unused port
ACOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => open,
UNDERFLOW => open,
CARRYOUT => open,
ACIN => (others => '0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
CARRYINSEL => "000",
C => (others => '0'),
CARRYIN => '0',
D => (others => '0')
);
-- Sign extension - DSP48E1 expects 30 bits on port A but multiplier uses only 25 bits
coef(24 downto 0) <= coef_i;
coef(29 downto 25) <= (others => coef_i(24));
end rtl;
|
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : SRAM-Model (a very very very simple model) for Simulation
-- Last update : 02.12.2013
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.iac_pkg.all;
entity sram_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FULL_DEBUG : natural := 0;
-- file for preload of sram
FILE_NAME_PRELOAD : string := "preload.txt";
-- file for dump at end of simulation
FILE_NAME_DUMP : string := "dump.txt";
-- number of addressable words in sram (size of sram)
GV_SRAM_SIZE : natural := 2**20
);
port(
-- global signals
end_simulation : in std_ulogic;
-- sram connections
sram_ce_n : in std_ulogic;
sram_oe_n : in std_ulogic;
sram_we_n : in std_ulogic;
sram_ub_n : in std_ulogic;
sram_lb_n : in std_ulogic;
sram_addr : in std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0)
);
end sram_model;
architecture sim of sram_model is
constant DUMP_WORDS_PER_LINE : natural := 8;
-- files
file file_preload : text open read_mode is FILE_NAME_PRELOAD;
file file_dump : text open write_mode is FILE_NAME_DUMP;
-- internal representation of sram (data-array)
type sram_data_t is array (0 to GV_SRAM_SIZE-1) of std_ulogic_vector(sram_dq'length-1 downto 0);
signal sram_data : sram_data_t;
begin
-- set outgoing signals
sram_dq <= std_logic_vector(sram_data(to_integer(unsigned(sram_addr)))) when (sram_ce_n = '0' and sram_we_n = '1') else
(others => 'Z');
process
variable active_line : line;
variable neol : boolean := false;
variable data_value : integer := 0;
variable cnt : natural := 0;
begin
-- preload data from file
-- prefill array with undefined
sram_data <= (others => (others => 'U'));
-- read preload file
while not endfile(file_preload) loop
-- read line
readline(file_preload, active_line);
-- loop until end of line
loop
-- read integer from line
read(active_line, data_value, neol);
-- exit when line has ended
exit when not neol;
-- chancel when sram is already full
exit when cnt = GV_SRAM_SIZE-1;
-- write data to array
sram_data(cnt) <= std_ulogic_vector(to_signed(data_value, sram_dq'length));
-- increment counter
cnt := cnt + 1;
end loop;
end loop;
file_close(file_preload);
loop
-- stop when simulation has ended
exit when end_simulation = '1';
-- chip enable detected
if sram_ce_n = '0' then
-- write (read outside the process)
if sram_we_n = '0' then
-- write data to array
sram_data(to_integer(unsigned(sram_addr))) <= std_ulogic_vector(sram_dq);
if FULL_DEBUG = 1 then
write(active_line, string'("[SRAM] Write "));
write(active_line, to_integer(unsigned(sram_dq)));
write(active_line, string'(" ("));
write(active_line, to_bitvector(sram_dq));
write(active_line, string'(") to Addr "));
write(active_line, to_integer(unsigned(sram_addr)));
write(active_line, string'("."));
writeline(output, active_line);
end if;
-- read
else
if FULL_DEBUG = 1 then
write(active_line, string'("[SRAM] Read "));
write(active_line, to_integer(unsigned(sram_data(to_integer(unsigned(sram_addr))))));
write(active_line, string'(" ("));
write(active_line, to_bitvector(sram_data(to_integer(unsigned(sram_addr)))));
write(active_line, string'(") from Addr "));
write(active_line, to_integer(unsigned(sram_addr)));
write(active_line, string'("."));
writeline(output, active_line);
end if;
end if;
end if;
-- wait for one cycle
wait for SYSTEM_CYCLE_TIME;
end loop;
-- dump data to file after simulation was ended
-- loop over sram-size, with 4 words per line
for i in 0 to (GV_SRAM_SIZE/DUMP_WORDS_PER_LINE)-1 loop
--write(active_line, hex(std_ulogic_vector(to_unsigned(i*DUMP_WORDS_PER_LINE,to_log16(GV_SRAM_SIZE)*4))) & ": ");
for j in 0 to DUMP_WORDS_PER_LINE-1 loop
--write(active_line, hex(sram_data(i*DUMP_WORDS_PER_LINE+j)));
if j /= DUMP_WORDS_PER_LINE-1 then
if (((j+1) mod 4) = 0) then
write(active_line, string'(" "));
else
write(active_line, string'(" "));
end if;
end if;
end loop;
writeline(file_dump, active_line);
end loop;
file_close(file_dump);
-- wait forever
wait;
end process;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
package pkg is
constant mask : std_logic_vector (7 downto 0) := x"0f";
end pkg;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:37:46 11/22/2015
-- Design Name:
-- Module Name: Z:/Downloads/VMware Shared Files/ComputerOrganization/MadeCPUin21days/CPU_TEST.vhd
-- Project Name: MadeCPUin21days
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CPU_TOP
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CPU_TEST IS
END CPU_TEST;
ARCHITECTURE behavior OF CPU_TEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CPU_TOP
PORT(
clock : IN std_logic;
reset : IN std_logic;
RAM1ADDR : OUT std_logic_vector(17 downto 0);
RAM1DATA : INOUT std_logic_vector(15 downto 0);
RAM1EN : OUT std_logic;
RAM1OE : OUT std_logic;
RAM1RW : OUT std_logic;
RAM2ADDR : OUT std_logic_vector(17 downto 0);
RAM2DATA : INOUT std_logic_vector(15 downto 0);
RAM2EN : OUT std_logic;
RAM2OE : OUT std_logic;
RAM2RW : OUT std_logic;
SERIAL_DATA_READY : IN std_logic;
SERIAL_RDN : OUT std_logic;
SERIAL_TBRE : IN std_logic;
SERIAL_TSRE : IN std_logic;
SERIAL_WRN : OUT std_logic;
SW : IN std_logic_vector (15 downto 0);
LED : OUT std_logic_vector(15 downto 0);
DLED_RIGHT : out STD_LOGIC_VECTOR (6 downto 0)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal SERIAL_DATA_READY : std_logic := '0';
signal SERIAL_TBRE : std_logic := '1';
signal SERIAL_TSRE : std_logic := '1';
--BiDirs
signal RAM1DATA : std_logic_vector(15 downto 0);
signal RAM2DATA : std_logic_vector(15 downto 0);
--Outputs
signal RAM1ADDR : std_logic_vector(17 downto 0);
signal RAM1EN : std_logic;
signal RAM1OE : std_logic;
signal RAM1RW : std_logic;
signal RAM2ADDR : std_logic_vector(17 downto 0);
signal RAM2EN : std_logic;
signal RAM2OE : std_logic;
signal RAM2RW : std_logic;
signal SERIAL_RDN : std_logic;
signal SERIAL_WRN : std_logic;
signal LED : std_logic_vector(15 downto 0);
signal SW : std_logic_vector (15 downto 0);
signal DLED_RIGHT : std_logic_vector (6 downto 0);
-- Clock period definitions
constant clock_period : time := 20 ns;
constant clock_2t_period : time := 40 ns;
constant clock_4t_period : time := 80 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CPU_TOP PORT MAP (
clock => clock,
reset => reset,
RAM1ADDR => RAM1ADDR,
RAM1DATA => RAM1DATA,
RAM1EN => RAM1EN,
RAM1OE => RAM1OE,
RAM1RW => RAM1RW,
RAM2ADDR => RAM2ADDR,
RAM2DATA => RAM2DATA,
RAM2EN => RAM2EN,
RAM2OE => RAM2OE,
RAM2RW => RAM2RW,
SERIAL_DATA_READY => SERIAL_DATA_READY,
SERIAL_RDN => SERIAL_RDN,
SERIAL_TBRE => SERIAL_TBRE,
SERIAL_TSRE => SERIAL_TSRE,
SERIAL_WRN => SERIAL_WRN,
SW => SW,
LED => LED,
DLED_RIGHT => DLED_RIGHT
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state.
reset <= '0';
sw <= "0000000001000111";
wait for 10 ns;
reset <= '1';
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
RAM2DATA <= x"6D40";
wait for clock_4t_period;
RAM2DATA <= x"35A0";
wait for clock_4t_period;
RAM2DATA <= x"6880";
wait for clock_4t_period;
RAM2DATA <= x"3000";
wait for clock_4t_period;
RAM2DATA <= x"DD00";
wait for clock_4t_period;
RAM2DATA <= x"68EF";
wait for clock_4t_period;
RAM2DATA <= (others => 'Z');
wait for clock_4t_period;
RAM2DATA <= x"3000";
wait for clock_4t_period;
RAM2DATA <= x"DD01";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
RAM2DATA <= x"0800";
wait for clock_4t_period;
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
-- B 0x31
RAM2DATA <= "0001000001100001";
wait for clock_4t_period;
-- R0 <= x"FF"
RAM2DATA <= "0110100011111111";
wait for clock_4t_period;
-- SW R0 R1 1
RAM2DATA <= "1101100000100001";
wait for clock_4t_period;
-- SLL R0 R0
RAM2DATA <= "0011000000000000";
wait for clock_4t_period;
-- R1 <= x"0F"
RAM2DATA <= "0110100000001111";
wait for clock_4t_period;
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
-- SW R0 R1 1
RAM2DATA <= "1101100000100001";
wait for clock_4t_period;
-- SLL R0 R0
RAM2DATA <= "0011000000000000";
-- ADDU R0 R1 R2
RAM2DATA <= "1110000000101001";
wait for clock_4t_period;
-- NOP
RAM2DATA <= "0000100000000000";
wait for clock_4t_period;
-- SW R0 R1 0
RAM2DATA <= "1101100000100000";
wait for clock_4t_period;
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: RickWare
--
-- Create Date: 11:42:22 11/04/2015
-- Design Name:
-- Module Name: Ultrasonic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: Parallax Ultrasonic Sensor controller
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Ultrasonic is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Tx : out STD_LOGIC;
LEDs : out STD_LOGIC_VECTOR(7 downto 0));
end Ultrasonic;
architecture Behavioral of Ultrasonic is
-- State definition
type state_values is (StartPulse,WaitForResponse,UltrasonicResponse,WaitForNewStart);
signal pres_state, next_state : state_values;
-- Define the State duration times for the variable time duration FSM
-- All times are expressed in micro-seconds
constant tStartPulse : integer := 5;
constant tWaitForNewStart : integer := 1_000_000;
-- Define signals used by frequency divider
constant Fosc : integer := 100_000_000; --Frecuencia del oscilador de Nexys3
constant Fdiv : integer := 1_000_000; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
signal Cont : integer range 0 to CtaMax;
signal TimeBase : STD_LOGIC;
-- Define a second counter, used to determine how much
-- time has been spent in a State
signal SecondCount : integer range 0 to tWaitForNewStart;
-- Define a signal that gives the amount of time
-- to be spent in a State
signal StateDuration : integer range 0 to tWaitForNewStart;
begin
--Regla calcular distancia
-- x = tin * 300 / 18500
-- Generate a TimeBase of one second
freqdiv: process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
TimeBase <= '1';
else
Cont <= Cont + 1;
TimeBase <= '0';
end if;
end if;
end process freqdiv;
statereg : process(Clk,TimeBase,Rst)
begin
if Rst = '1' then
pres_state <= StartPulse;
SecondCount <= 0;
elsif (rising_edge(Clk) and TimeBase = '1') then
if SecondCount = StateDuration-1 then
pres_state <= next_state;
SecondCount <= 0;
else
SecondCount <= SecondCount + 1;
end if;
end if;
end process statereg;
fsm : process (pres_state)
begin
case (pres_state) is
-- ST0
when StartPulse =>
next_state <= WaitForResponse;
StateDuration <= tStartPulse;
-- ST1
when WaitForResponse =>
next_state <= UltraSonicResponse;
StateDuration <= 1;
-- ST2
when UltraSonicResponse =>
next_state <= WaitForNewStart;
StateDuration <= 1;
-- ST3
when WaitForNewStart =>
next_state <= StartPulse;
StateDuration <= tWaitForNewStart;
when others =>
next_state <= WaitForResponse;
StateDuration <= tStartPulse;
end case;
end process fsm;
output : process (pres_state)
begin
case (pres_state) is
when StartPulse => Tx <= '1';
when WaitForResponse => Tx <= '0';
when UltraSonicResponse => Tx <= '0';
when WaitForNewStart => Tx <= '0';
when others => Tx <= '1';
end case;
end process output;
end Behavioral;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity syncram_banked_1r1w is
generic (
addr_bits : natural := 1;
word_bits : natural := 1;
log2_banks : natural := 0;
write_first : boolean := true
);
port (
clk : in std_ulogic;
we : in std_ulogic;
wbanken : in std_ulogic_vector(2**log2_banks-1 downto 0);
waddr : in std_ulogic_vector(addr_bits-1 downto 0);
wdata : in std_ulogic_vector2(2**log2_banks-1 downto 0, word_bits-1 downto 0);
re : in std_ulogic;
rbanken : in std_ulogic_vector(2**log2_banks-1 downto 0);
raddr : in std_ulogic_vector(addr_bits-1 downto 0);
rdata : out std_ulogic_vector2(2**log2_banks-1 downto 0, word_bits-1 downto 0)
);
end;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file FIFO.vhd when simulating
-- the core, FIFO. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY FIFO IS
port (
din: IN std_logic_VECTOR(15 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END FIFO;
ARCHITECTURE FIFO_a OF FIFO IS
-- synthesis translate_off
component wrapped_FIFO
port (
din: IN std_logic_VECTOR(15 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_FIFO use entity XilinxCoreLib.fifo_generator_v5_1(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 16,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 16,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 14,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_thresh_assert_val => 4,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 15,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_FIFO
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full);
-- synthesis translate_on
END FIFO_a;
|
------------------------------------------------------------------------------
-- LEON Demonstration design test bench
-- Copyright (C) 2004 - 2015 Cobham Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := '1';
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic := '0'
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb, scb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1, cts1, rts1 : std_ulogic;
signal txd2, rxd2, cts2, rts2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_logic := '0';
signal emdintn : std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal led_cfg: std_logic_vector(2 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
led_cfg<="000"; --put the phy in base10h mode
can_rxd <= (others => 'H'); bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
pci_arb_req <= "HHHH";
-- spacewire loop-back
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sdclk, error, wdogn, address(27 downto 0), data,
cb(7 downto 0), sa, sd,
-- scb(7 downto 0),
sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, rts1, cts1, txd2, rxd2, rts2, cts2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emdintn,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_int, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd,
spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp,
spw_txdn, spw_txsp, spw_txsn
);
-- optional sdram
sd0 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0)) or ((CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 0)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) or ((CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
sd64 : if (CFG_MCTRL_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
pWvKnka42+vKiKbBP4Oia4Z1OWZ9K/yekn5poPXnfPRqp/OnPiYdhEOGoi2DX//NxFFUBRvN7IQ7
wfX+6TH/Jg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ezEs3AfBG0l9aWY2OjK+dHBh4TYxtmE9uajSlqrTTj5jhKLR57/28ifPN7gjBi/1LU0E+YVW3gjw
S/Xz82ckOKLIak1k4Vz4h0kce9TWYNYUvIDvI50CyftikirmV28lQcmaPwLZ0nxY8gK0QrW4J3db
gge2IVsrnHlt8MHD9Mc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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MSC9NRGm+33xTjR2EGyXh26PuyJIM8OdDqytBA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kEhjZ8AsBsfuyd2+1ISeUtBu8qUbZ6iBovK2AYRZCxXwav/+nG63AvwvUe1oX8VO1EKUJ3O5iAny
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YyMGQ/hXQuGYgdMmDCs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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q+nDbI09F+r6oTCi5gEtD/XE764lFeblJr4Ryg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21632)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21632)
`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
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