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-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
-- 03.08.2015 Bahri Enis Demirtel created
library IEEE;
use IEEE.std_logic_1164.ALL;
library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library WORK;
use WORK.all;
entity instruction_fetch is
port(
clk : in std_logic;
rst : in std_logic;
PC : in std_logic_vector(31 downto 0); --PC : in std_logic_vector(CPU_ADDR_WIDTH-1 downto 0); --PC(32 bit)
InstrData : in std_logic_vector(31 downto 0); --InstrData : in std_logic_vector(CPU_DATA_WIDTH-1 downto 0); --InstrData, Adress information comes from Memory(32 bit)
--StallData : in std_logic;
IR : out std_logic_vector(31 downto 0); --IR : out std_logic_vector(CPU_ADDR_WIDTH-1 downto 0); --IR, Next PC goes to Execution Stage(32 bit)
InstrAddr: out std_logic_vector(31 downto 0); --InstrAddr: out std_logic_vector(CPU_ADDR_WIDTH-1 downto 0); --InstrAddr, PC goes to Memory(32 bit)
Instr : out std_logic_vector(31 downto 0) --Instr : out std_logic_vector(CPU_DATA_WIDTH-1 downto 0); --Instr, Adress information from Memory goes to Instruction Decoder(32 bit)
);
end entity instruction_fetch;
architecture behavioral of instruction_fetch is
begin
process (rst, clk, PC, InstrData) is
begin
if(rst = '1') then
InstrAddr <= X"0000_0000"; --If reset comes PC goes to the beginning, its value is 0000_0000
IR <= X"0000_0000"; --If reset all coming signals are 0000_0000
Instr <= X"0000_0000"; --If reset all coming signals are 0000_0000
else
--elsif (rising_edge(clk)) then
--if(StallData='0') then
InstrAddr <= PC; --We can the value of PC to the memory adress
IR <= PC + X"0000_0004"; --IR value is always PC+4;
Instr <= InstrData; --Instr value is always equal to InstrData value
end if;
end process ;
end architecture behavioral;
|
entity case7 is
end entity;
architecture test of case7 is
constant C1 : bit_vector(3 downto 0) := X"1";
constant C2 : bit_vector(3 downto 0) := X"2";
alias C3 : bit_vector(3 downto 0) is C1;
signal x : bit_vector(7 downto 0);
signal y : integer;
begin
testp: process (x) is
begin
case x is
when C1 & X"0" =>
y <= 5;
when C1 & X"8" =>
y <= 6;
when C2 & X"2" =>
y <= 10;
when C3 & X"3" =>
y <= 5;
when others =>
y <= 0;
end case;
end process;
end architecture;
|
component usb_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
keycode_export : out std_logic_vector(7 downto 0); -- export
usb_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_RD_N : out std_logic; -- RD_N
usb_WR_N : out std_logic; -- WR_N
usb_CS_N : out std_logic; -- CS_N
usb_RST_N : out std_logic; -- RST_N
usb_INT : in std_logic := 'X'; -- INT
sdram_out_clk_clk : out std_logic; -- clk
usb_out_clk_clk : out std_logic -- clk
);
end component usb_system;
u0 : component usb_system
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
keycode_export => CONNECTED_TO_keycode_export, -- keycode.export
usb_DATA => CONNECTED_TO_usb_DATA, -- usb.DATA
usb_ADDR => CONNECTED_TO_usb_ADDR, -- .ADDR
usb_RD_N => CONNECTED_TO_usb_RD_N, -- .RD_N
usb_WR_N => CONNECTED_TO_usb_WR_N, -- .WR_N
usb_CS_N => CONNECTED_TO_usb_CS_N, -- .CS_N
usb_RST_N => CONNECTED_TO_usb_RST_N, -- .RST_N
usb_INT => CONNECTED_TO_usb_INT, -- .INT
sdram_out_clk_clk => CONNECTED_TO_sdram_out_clk_clk, -- sdram_out_clk.clk
usb_out_clk_clk => CONNECTED_TO_usb_out_clk_clk -- usb_out_clk.clk
);
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of vgca
--
-- Generated
-- by: wig
-- on: Thu Jul 6 16:43:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca-struct-a.vhd,v 1.3 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: vgca-struct-a.vhd,v $
-- Revision 1.3 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of vgca
--
architecture struct of vgca is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component adc
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component bsr
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component clkgen
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component dac
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component padframe
-- No Generated Generics
port (
-- Generated Port for Entity padframe
mix_logic0_0 : in std_ulogic; -- padin
mix_logic0_bus_4 : in std_ulogic_vector(31 downto 0); -- padin
ramd_i : in std_ulogic_vector(31 downto 0); -- padin
ramd_i2 : in std_ulogic_vector(31 downto 0); -- padin
ramd_o : out std_ulogic_vector(31 downto 0); -- padout
ramd_o2 : out std_ulogic_vector(31 downto 0); -- padout
ramd_o3 : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity padframe
);
end component;
-- ---------
component tap_con
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_cpu
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_di
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_dp
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_fe
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_mm
-- No Generated Generics
port (
-- Generated Port for Entity vgca_mm
ramd_i : in std_ulogic_vector(31 downto 0);
ramd_i2 : in std_ulogic_vector(31 downto 0);
ramd_i3 : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity vgca_mm
);
end component;
-- ---------
component vgca_rc
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal mix_logic0_bus_4 : std_ulogic_vector(31 downto 0);
signal mm_ramd : std_ulogic_vector(31 downto 0);
signal mm_ramd2 : std_ulogic_vector(31 downto 0);
signal mm_ramd3 : std_ulogic_vector(31 downto 0);
-- __I_NODRV_I signal ramd_i : std_ulogic_vector(31 downto 0);
-- __I_NODRV_I signal ramd_i2 : std_ulogic_vector(31 downto 0);
-- __I_OUT_OPEN signal ramd_o : std_ulogic_vector(31 downto 0);
-- __I_OUT_OPEN signal ramd_o2 : std_ulogic_vector(31 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
mix_logic0_bus_4 <= ( others => '0' );
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for i_adc
i_adc: adc
;
-- End of Generated Instance Port Map for i_adc
-- Generated Instance Port Map for i_bsr
i_bsr: bsr
;
-- End of Generated Instance Port Map for i_bsr
-- Generated Instance Port Map for i_clkgen
i_clkgen: clkgen
;
-- End of Generated Instance Port Map for i_clkgen
-- Generated Instance Port Map for i_dac
i_dac: dac
;
-- End of Generated Instance Port Map for i_dac
-- Generated Instance Port Map for i_padframe
i_padframe: padframe
port map (
mix_logic0_0 => mix_logic0_0, -- padin
mix_logic0_bus_4 => mix_logic0_bus_4, -- padin
-- __I_NODRV_I -- __I_NODRV_I ramd_i => __nodrv__/ramd_i2/ramd_i, -- padin (X4)
-- __I_NODRV_I ramd_i2 => __nodrv__/ramd_i2, -- padin (X4)
ramd_o => mm_ramd,
-- __I_RECONN -- __I_RECONN ramd_o => open, -- padout (X4) -- __I_OUT_OPEN
ramd_o2 => mm_ramd2,
-- __I_RECONN ramd_o2 => open, -- padout (X4) -- __I_OUT_OPEN
ramd_o3 => mm_ramd3
);
-- End of Generated Instance Port Map for i_padframe
-- Generated Instance Port Map for i_tap_con
i_tap_con: tap_con
;
-- End of Generated Instance Port Map for i_tap_con
-- Generated Instance Port Map for i_vgca_cpu
i_vgca_cpu: vgca_cpu
;
-- End of Generated Instance Port Map for i_vgca_cpu
-- Generated Instance Port Map for i_vgca_di
i_vgca_di: vgca_di
;
-- End of Generated Instance Port Map for i_vgca_di
-- Generated Instance Port Map for i_vgca_dp
i_vgca_dp: vgca_dp
;
-- End of Generated Instance Port Map for i_vgca_dp
-- Generated Instance Port Map for i_vgca_fe
i_vgca_fe: vgca_fe
;
-- End of Generated Instance Port Map for i_vgca_fe
-- Generated Instance Port Map for i_vgca_mm
i_vgca_mm: vgca_mm
port map (
ramd_i => mm_ramd,
ramd_i2 => mm_ramd2,
ramd_i3 => mm_ramd3
);
-- End of Generated Instance Port Map for i_vgca_mm
-- Generated Instance Port Map for i_vgca_rc
i_vgca_rc: vgca_rc
;
-- End of Generated Instance Port Map for i_vgca_rc
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
sel : in std_logic_vector(3 downto 0);
value : in std_logic;
spi_sdo : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
begin
-- no problem if the "not" is taken out
spi_sdo <= not or_reduce(sel);
end bug3_syn;
|
-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
sel : in std_logic_vector(3 downto 0);
value : in std_logic;
spi_sdo : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
begin
-- no problem if the "not" is taken out
spi_sdo <= not or_reduce(sel);
end bug3_syn;
|
-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
sel : in std_logic_vector(3 downto 0);
value : in std_logic;
spi_sdo : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
begin
-- no problem if the "not" is taken out
spi_sdo <= not or_reduce(sel);
end bug3_syn;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc559.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:30 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:27 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00559ent IS
END c03s04b01x00p01n01i00559ent;
ARCHITECTURE c03s04b01x00p01n01i00559arch OF c03s04b01x00p01n01i00559ent IS
type natural_vector is array (natural range <>) of natural;
type natural_vector_file is file of natural_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_vector_file open read_mode is "iofile.25";
variable v : natural_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00559"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00559 - File reading operation (natural_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00559arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc559.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:30 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:27 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00559ent IS
END c03s04b01x00p01n01i00559ent;
ARCHITECTURE c03s04b01x00p01n01i00559arch OF c03s04b01x00p01n01i00559ent IS
type natural_vector is array (natural range <>) of natural;
type natural_vector_file is file of natural_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_vector_file open read_mode is "iofile.25";
variable v : natural_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00559"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00559 - File reading operation (natural_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00559arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc559.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:30 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:27 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:03 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00559ent IS
END c03s04b01x00p01n01i00559ent;
ARCHITECTURE c03s04b01x00p01n01i00559arch OF c03s04b01x00p01n01i00559ent IS
type natural_vector is array (natural range <>) of natural;
type natural_vector_file is file of natural_vector;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : natural_vector_file open read_mode is "iofile.25";
variable v : natural_vector(0 to 3);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 4) report "wrong length passed during read operation";
if (v /= (1,2,3,4)) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00559"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00559 - File reading operation (natural_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00559arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8+8*CFG_MCTRL_RAM16BIT; -- rom data width (8/16)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal flash_d : std_logic_vector(15 downto 0);
signal romsn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_ulogic;
signal ereset : std_logic;
signal led : std_logic_vector(8 downto 1);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal ba : std_logic_vector(3 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal pb_sw : std_logic_vector(4 downto 1);
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_rs : std_ulogic;
signal lcd_rw : std_ulogic;
signal lcd_en : std_ulogic;
signal lcd_backl: std_ulogic;
signal can_txd : std_ulogic;
signal can_rxd : std_ulogic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal smsc_addr : std_logic_vector(21 downto 0);
signal smsc_data : std_logic_vector(31 downto 0);
signal smsc_nbe : std_logic_vector(3 downto 0);
signal smsc_resetn : std_ulogic;
signal smsc_ardy : std_ulogic;
signal smsc_intr : std_ulogic;
signal smsc_nldev : std_ulogic;
signal smsc_nrd : std_ulogic;
signal smsc_nwr : std_ulogic;
signal smsc_ncs : std_ulogic;
signal smsc_aen : std_ulogic;
signal smsc_lclk : std_ulogic;
signal smsc_wnr : std_ulogic;
signal smsc_rdyrtn : std_ulogic;
signal smsc_cycle : std_ulogic;
signal smsc_nads : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= '1'; error <= led(8); sa(14 downto 12) <= "000";
pb_sw <= rst & "00" & dsubre;
cpu : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (pb_sw, clk, led, address(21 downto 1), flash_d,
sa(11 downto 0), sd, ba, sddqm, sdclk, sdcke, sdcsn, sdwen, sdrasn,
sdcasn, txd1, rxd1, open, gnd, dsutx, dsurx, open, gnd,
oen, writen, romsn, open, vcc, open, open,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, emdc, gnd, ereset, gpio,
-- lcd_data, lcd_rs, lcd_rw, lcd_en, lcd_backl,
can_txd, can_rxd,
smsc_addr(14 downto 0), smsc_data, smsc_nbe, smsc_resetn, smsc_ardy,-- smsc_intr,
smsc_nldev, smsc_nrd, smsc_nwr, smsc_ncs, smsc_aen, smsc_lclk,
smsc_wnr, smsc_rdyrtn, smsc_cycle, smsc_nads);
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => ba(1 downto 0), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => ba(3 downto 2), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
rom8 : if romwidth /= 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= flash_d(15);
end generate;
rom16 : if romwidth = 16 generate
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), flash_d(15 downto 0), gnd, gnd,
romsn, writen, oen);
address(0) <= '0';
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
flash_d <= buskeep(flash_d) after 5 ns;
sd <= buskeep(sd) after 5 ns;
smsc_data <= buskeep(smsc_data) after 5 ns;
smsc_addr(21 downto 15) <= (others => '0');
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), smsc_data,
smsc_ncs, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_173 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_173;
architecture augh of add_173 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_173 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_173;
architecture augh of add_173 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc11.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p02n01i00011ent IS
END c04s02b00x00p02n01i00011ent;
ARCHITECTURE c04s02b00x00p02n01i00011arch OF c04s02b00x00p02n01i00011ent IS
-- Failure_here: Missing 'is':
subtype GROUND BIT range '0' to '0';
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s02b00x00p02n01i00011 - The reserved word is is misssing."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p02n01i00011arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc11.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p02n01i00011ent IS
END c04s02b00x00p02n01i00011ent;
ARCHITECTURE c04s02b00x00p02n01i00011arch OF c04s02b00x00p02n01i00011ent IS
-- Failure_here: Missing 'is':
subtype GROUND BIT range '0' to '0';
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s02b00x00p02n01i00011 - The reserved word is is misssing."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p02n01i00011arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc11.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p02n01i00011ent IS
END c04s02b00x00p02n01i00011ent;
ARCHITECTURE c04s02b00x00p02n01i00011arch OF c04s02b00x00p02n01i00011ent IS
-- Failure_here: Missing 'is':
subtype GROUND BIT range '0' to '0';
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s02b00x00p02n01i00011 - The reserved word is is misssing."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p02n01i00011arch;
|
architecture RTL of FIFO is
begin
-- Simple form
a <= b;
-- Simple form
a <= b when 'a' else
c when 'b' else
d;
-- Basic version
with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
--+-------------------
--| Add labels:
--+-------------------
-- Simple form
simple_label : a <= b;
-- Simple form
conditional_label : a <= b when 'a' else
c when 'b' else
d;
-- Basic version
select_label : with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
--+-------------------
--| Add postponed keyword
--+-------------------
-- Simple form
simple_label : postponed a <= b;
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
-- Basic version
select_label : postponed with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
--+-------------------
--| With only postponed keyword
--+-------------------
-- Simple form
postponed a <= b;
-- Simple form
postponed a <= b when 'a' else
c when 'b' else
d;
-- Basic version
postponed with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
--+-------------------
--| Test parenthesis
--+-------------------
a <= std_logic(to_unsigned(b, 4));
end architecture RTL;
|
--------------------------------------------------------------------------------
-- company:
-- engineer:
--
-- vhdl test bench created by ise for module: random_number
--
-- dependencies:
--
-- revision:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_generic_Detect_Edge is
end tb_generic_Detect_Edge;
architecture arch_tb_generic_Detect_Edge of tb_generic_Detect_Edge is
constant detect_type : string := "Rising"; -- Rising or Falling
constant Input_width_g : natural := 4;
-- clock period definitions
constant clk_period : time := 10 ns;
-- component declaration for the unit under test (uut)
component generic_Detect_Edge is
generic(
detect_type : string := "Rising"; -- Rising or Falling
Input_width_g : natural := 1
);
port(
---- Global Inputs
Clk : in std_logic; -- main clock
Reset_n : in std_logic; -- reset synchrone, enable on LOW level
---- Inputs
Input_Data : in std_logic_vector((Input_width_g-1) downto 0); --Input
---- Outputs
Output_Data : out std_logic_vector((Input_width_g-1) downto 0) -- At 1 just one cycle of clock
);
end component generic_Detect_Edge;
--component generic_One_Detect_Edge is
-- generic (
-- detect_type : string := "Rising" -- Rising or Falling
-- );
-- port(
-- ---- Global Inputs
-- Clk : in std_logic; -- main clock
-- Reset_n : in std_logic; -- reset synchrone, enable on LOW level
--
-- ---- Inputs
-- Input_Data : in std_logic; --Input
--
-- ---- Outputs
-- Output_Data : out std_logic -- At 1 just one cycle of clock
-- );
--end component generic_One_Detect_Edge;
--inputs
signal clk : std_logic ;
signal reset_n : std_logic ;
signal Input_Data : std_logic_vector((Input_width_g-1) downto 0);
signal Output_Data : std_logic_vector((Input_width_g-1) downto 0);
begin
-- instantiate the unit under test (uut)
uut: generic_Detect_Edge
generic map (
detect_type => detect_type,
Input_width_g => Input_width_g
)
port map(
---- Global Inputs
Clk => Clk, -- Main clock
Reset_n => Reset_n, -- Reset synchrone on LOW level
---- Inputs
Input_Data => Input_Data, --Input
---- Outputs
Output_Data => Output_Data -- At 1 just one cycle of clock
);
-- instantiate the unit under test (uut)
-- uut: generic_One_Detect_Edge
-- generic map (
-- detect_type => detect_type
-- )
-- port map(
-- ---- Global Inputs
-- Clk => Clk, -- Main clock
-- Reset_n => Reset_n, -- Reset synchrone on LOW level
--
-- ---- Inputs
-- Input_Data => Input_Data(0), --Input
--
-- ---- Outputs
-- Output_Data => Output_Data(0) -- At 1 just one cycle of clock
-- );
--
-- clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- reset process
reset_proc: process
begin
reset_n <= '0';
wait for clk_period;
reset_n<='1';
wait;
end process;
-- Input_Data process
Input_Data_proc: process
begin
for I in 0 to 15 loop
Input_Data <= std_logic_vector(to_unsigned(I,Input_Data'length));
wait for 7.5*clk_period;
end loop;
end process;
end arch_tb_generic_Detect_Edge;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:33:05 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/mul8_16_stub.vhdl
-- Design : mul8_16
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mul8_16 is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end mul8_16;
architecture stub of mul8_16 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[7:0],B[15:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:33:05 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/mul8_16_stub.vhdl
-- Design : mul8_16
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mul8_16 is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end mul8_16;
architecture stub of mul8_16 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[7:0],B[15:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity simplespi is
generic (
buswidth : integer
);
port (
clk : in std_logic;
ibus : in std_logic_vector(buswidth-1 downto 0);
obus : out std_logic_vector(buswidth-1 downto 0);
loadbitcount : in std_logic;
loadbitrate : in std_logic;
loaddata : in std_logic;
readdata : in std_logic;
readbitcount : in std_logic;
readbitrate : in std_logic;
spiclk : out std_logic;
spiin : in std_logic;
spiout: out std_logic;
spiframe: out std_logic;
davout: out std_logic
);
end simplespi;
architecture behavioral of simplespi is
constant DivWidth: integer := 8;
-- ssi interface related signals
signal RateDivReg : std_logic_vector(DivWidth -1 downto 0);
signal RateDiv : std_logic_vector(DivWidth -1 downto 0);
signal ModeReg : std_logic_vector(8 downto 0);
alias BitcountReg : std_logic_vector(5 downto 0) is ModeReg(5 downto 0);
alias CPOL : std_logic is ModeReg(6);
alias CPHA : std_logic is ModeReg(7);
alias DontClearFrame : std_logic is ModeReg(8);
signal BitCount : std_logic_vector(5 downto 0);
signal ClockFF: std_logic;
signal SPISreg: std_logic_vector(buswidth-1 downto 0);
signal Frame: std_logic;
signal EFrame: std_logic;
signal Dav: std_logic;
signal SPIInLatch: std_logic;
signal FirstLeadingEdge: std_logic;
begin
aspiinterface: process (clk, readdata, ModeReg, ClockFF, Frame,
SPISreg, readbitcount, BitcountReg,
Dav, readbitrate, RateDivReg)
begin
if rising_edge(clk) then
if loaddata = '1' then
SPISreg <= ibus;
BitCount <= BitCountReg;
Frame <= '1';
EFrame <= '1';
Dav <= '0';
ClockFF <= '0';
FirstLeadingEdge <= '1';
RateDiv <= RateDivReg;
end if;
if Frame = '1' then
if RateDiv = 0 then
RateDiv <= RateDivReg;
SPIInLatch <= spiin;
if ClockFF = '0' then
if BitCount(5) = '1' then
Frame <= '0'; -- frame cleared 1/2 SPI clock after GO
if DontClearFrame = '0' then
EFrame <= '0';
end if;
Dav <= '1';
else
ClockFF <= '1';
end if;
if CPHA = '1' and FirstLeadingEdge = '0' then -- shift out on leading edge for CPHA = 1 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
FirstLeadingEdge <= '0';
else
ClockFF <= '0';
BitCount <= BitCount -1;
if CPHA = '0' then -- shift out on trailing edge for CPHA = 0 case
SPISreg <= SPISreg(30 downto 0) & (SPIInLatch);
end if;
end if;
else
RateDiv <= RateDiv -1;
end if;
end if;
if loadbitcount = '1' then
ModeReg <= ibus(8 downto 0);
end if;
if loadbitrate = '1' then
RateDivReg <= ibus(DivWidth -1 downto 0);
end if;
end if; -- clk
obus <= (others => 'Z');
if readdata = '1' then
obus <= SPISReg;
end if;
if readbitcount = '1' then
obus(8 downto 0) <= ModeReg;
obus(buswidth -1) <= Dav;
end if;
if readbitrate = '1' then
obus(DivWidth-1 downto 0) <= RateDivReg;
end if;
spiclk <= ClockFF xor CPOL;
spiframe <= not EFrame;
davout <= Dav;
-- for i in 0 to buswidth -1 loop
-- if i = BitCountReg then
-- spiout <= SPISReg(i);
-- end if;
-- end loop;
spiout <= SPISReg(conv_integer(BitCountReg(4 downto 0))); -- select the MSB of the current size
end process aspiinterface;
end Behavioral;
|
-------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_50_c;
use microblaze_v8_50_c.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_BASE_VECTORS : std_logic_vector;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "virtex5",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_BASE_VECTORS => X"00000000",
C_DPLB_DWIDTH => 64,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 64,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_AWDOMAIN => M_AXI_IC_AWDOMAIN,
M_AXI_IC_AWSNOOP => M_AXI_IC_AWSNOOP,
M_AXI_IC_AWBAR => M_AXI_IC_AWBAR,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_WACK => M_AXI_IC_WACK,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_ARDOMAIN => M_AXI_IC_ARDOMAIN,
M_AXI_IC_ARSNOOP => M_AXI_IC_ARSNOOP,
M_AXI_IC_ARBAR => M_AXI_IC_ARBAR,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_IC_RACK => M_AXI_IC_RACK,
M_AXI_IC_ACVALID => M_AXI_IC_ACVALID,
M_AXI_IC_ACADDR => M_AXI_IC_ACADDR,
M_AXI_IC_ACSNOOP => M_AXI_IC_ACSNOOP,
M_AXI_IC_ACPROT => M_AXI_IC_ACPROT,
M_AXI_IC_ACREADY => M_AXI_IC_ACREADY,
M_AXI_IC_CRREADY => M_AXI_IC_CRREADY,
M_AXI_IC_CRVALID => M_AXI_IC_CRVALID,
M_AXI_IC_CRRESP => M_AXI_IC_CRRESP,
M_AXI_IC_CDVALID => M_AXI_IC_CDVALID,
M_AXI_IC_CDREADY => M_AXI_IC_CDREADY,
M_AXI_IC_CDDATA => M_AXI_IC_CDDATA,
M_AXI_IC_CDLAST => M_AXI_IC_CDLAST,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_AWDOMAIN => M_AXI_DC_AWDOMAIN,
M_AXI_DC_AWSNOOP => M_AXI_DC_AWSNOOP,
M_AXI_DC_AWBAR => M_AXI_DC_AWBAR,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_WACK => M_AXI_DC_WACK,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_ARDOMAIN => M_AXI_DC_ARDOMAIN,
M_AXI_DC_ARSNOOP => M_AXI_DC_ARSNOOP,
M_AXI_DC_ARBAR => M_AXI_DC_ARBAR,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
M_AXI_DC_RACK => M_AXI_DC_RACK,
M_AXI_DC_ACVALID => M_AXI_DC_ACVALID,
M_AXI_DC_ACADDR => M_AXI_DC_ACADDR,
M_AXI_DC_ACSNOOP => M_AXI_DC_ACSNOOP,
M_AXI_DC_ACPROT => M_AXI_DC_ACPROT,
M_AXI_DC_ACREADY => M_AXI_DC_ACREADY,
M_AXI_DC_CRREADY => M_AXI_DC_CRREADY,
M_AXI_DC_CRVALID => M_AXI_DC_CRVALID,
M_AXI_DC_CRRESP => M_AXI_DC_CRRESP,
M_AXI_DC_CDVALID => M_AXI_DC_CDVALID,
M_AXI_DC_CDREADY => M_AXI_DC_CDREADY,
M_AXI_DC_CDDATA => M_AXI_DC_CDDATA,
M_AXI_DC_CDLAST => M_AXI_DC_CDLAST,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- Title : Signal Delay Left and Right
-- Author : Michael Wurm <michael.wurm@students.fh-hagenberg.at>
-------------------------------------------------------------------------------
-- Description : Unit delays left and right channel independent. Each channel's
-- delay can be configured separately.
-------------------------------------------------------------------------------
architecture Rtl of Template is
---------------------------------------------------------------------------
-- Wires
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
type aConfigReg is array (0 to 1) of unsigned(31 downto 0);
signal ConfigReg : aConfigReg := (others => (others => '0'));
begin
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
aso_left_data <= asi_left_data;
aso_left_valid <= asi_left_valid;
aso_right_data <= asi_right_data;
aso_right_valid <= asi_right_valid;
---------------------------------------------------------------------------
-- Signal assignments
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Logic
---------------------------------------------------------------------------
-- MM INTERFACE for configuration
SetConfigReg : process (csi_clk) is
begin
if rising_edge(csi_clk) then
if avs_s0_write = '1' then
ConfigReg(to_integer(unsigned(avs_s0_address)))
<= unsigned(avs_s0_writedata);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Instantiations
---------------------------------------------------------------------------
end architecture Rtl;
|
-- NEED RESULT: ARCH00372.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00372: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00372: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00372
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00372(ARCH00372)
-- ENT00372_Test_Bench(ARCH00372_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00372 is
end ENT00372 ;
--
--
architecture ARCH00372 of ENT00372 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= transport
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00372.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= transport
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <= transport
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00372" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00372" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00372" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f3(lowb,true)(lowb to highb-1) <= transport
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns ;
--
end ARCH00372 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00372_Test_Bench is
end ENT00372_Test_Bench ;
--
--
architecture ARCH00372_Test_Bench of ENT00372_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00372 ( ARCH00372 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00372_Test_Bench ;
|
---------------------------------------------------------
-- Здес код, который может использовать все утсройства --
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity user_code is
port(
buttons: in std_logic_vector(7 downto 0);
led: out std_logic_vector(7 downto 0);
web_output_write_o: out std_logic;
web_output_data_o: out std_logic_vector(7 downto 0);
web_output_ready_i: in std_logic;
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
-- PS/2
web_ps2_kbd_data: inout std_logic;
web_ps2_kbd_clk: inout std_logic;
ps2_data1: inout std_logic;
ps2_clk1: inout std_logic;
ps2_data2: inout std_logic;
ps2_clk2: inout std_logic;
reset_o: out std_logic;
-- 50 Mhz
clk: in std_logic
);
end user_code;
architecture Behavioral of user_code is
signal reset : std_logic := '1';
type state is (s_wait, s_data, s_done);
signal ps2d_out, ps2c_out,
ps2d_i, ps2c_i,
idle, rx_done,
tx_wr_ps2, tx_done: std_logic;
signal rx_data, tx_data: std_logic_vector(7 downto 0);
type state_type is (send_ED, rec_ack, send_lock, wait_send);
signal s : state_type := send_ED;
signal led_kbd, led_shift: std_logic_vector(7 downto 0) := (others => '0');
begin
reset_o <= reset;
reset_proc: process(clk)
variable counter: unsigned(1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if counter = "11" then
reset <= '0';
else
reset <= '1';
counter := counter + 1;
end if;
end if;
end process;
web_ps2_kbd_data <= '0' when ps2d_out = '0' else 'Z';
web_ps2_kbd_clk <= '0' when ps2c_out = '0' else 'Z';
ps2d_i <= '0' when web_ps2_kbd_data = '0' else '1';
ps2c_i <= '0' when web_ps2_kbd_clk = '0' else '1';
---- ![не проходит один такт, проверить на физ клавиатуре]! --
inst_ps2_rx: entity work.ps2_rx
port map (
clk => clk,
reset => reset,
ps2d => ps2d_i,
ps2c => ps2c_i,
rx_en => idle,
rx_done => rx_done,
dout => rx_data
);
inst_ps2_tx: entity work.ps2_tx
port map (
clk => clk,
reset => reset,
ps2d_out => ps2d_out,
ps2c_out => ps2c_out,
ps2d_in => ps2d_i,
ps2c_in => ps2c_i,
tx_idle => idle,
din => tx_data,
wr_ps2 => tx_wr_ps2,
tx_done => tx_done
);
proc_out: process(reset, clk)
begin
if reset = '1' then
web_output_write_o <= '0';
elsif rising_edge(clk) then
web_output_write_o <= '0';
if rx_done = '1' then
web_output_data_o <= rx_data;
web_output_write_o <= '1';
end if;
end if;
end process;
led <= led_shift;
proc_rx: process(reset, clk)
variable realesed, ext_code: boolean;
begin
if reset = '1' then
led_kbd <= (others => '0');
realesed := false;
ext_code := false;
led_shift <= (others => '0');
elsif rising_edge(clk) then
tx_wr_ps2 <= '0';
case s is
when send_ED =>
if rot_center = '1' then
tx_data <= X"F4";
tx_wr_ps2 <= '1';
s <= rec_ack;
elsif buttons(4) = '1' then
tx_data <= X"AA";
tx_wr_ps2 <= '1';
s <= rec_ack;
elsif rx_done='1' then
if realesed then
realesed := false;
elsif ext_code then
case rx_data is
-- left
when X"6B" =>
led_shift <= led_shift(6 downto 0) & '1';
-- right
when X"74" =>
led_shift <= '0' & led_shift(7 downto 1);
when others => null;
end case;
ext_code := false;
else
case rx_data is
when X"77" =>
led_kbd(1) <= not led_kbd(1);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"7E" =>
led_kbd(0) <= not led_kbd(0);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"58" =>
led_kbd(2) <= not led_kbd(2);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"5A" =>
tx_data <= X"EE";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"76" =>
tx_data <= X"FF";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"05" =>
tx_data <= X"FE";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"E0" =>
ext_code := true;
when X"F0" =>
realesed := true;
when others => null;
end case;
end if;
end if;
when rec_ack =>
if rx_done = '1' then
if tx_data = X"ED" and rx_data = X"FA" then
s <= send_lock;
else
s <= send_ED;
end if;
end if;
when send_lock =>
tx_data <= led_kbd;
tx_wr_ps2 <= '1';
s <= wait_send;
when wait_send =>
if tx_done = '1' then
s <= send_ED;
end if;
end case;
end if;
end process;
-- proc_rx: process(reset, ps2c_i)
-- variable counter: unsigned(2 downto 0);
-- begin
-- if reset = '1' then
-- rx_done <= '0';
-- rx_data <= (others => '0');
-- elsif rising_edge(ps2c_i) then
-- rx_done <= '0';
-- if idle = '1' then
-- case s is
-- when s_wait =>
-- if ps2d_i = '0' then
-- s <= s_data;
-- counter := "111";
-- end if;
-- when s_data =>
-- rx_data <= ps2d_i & rx_data(7 downto 1);
-- if counter = "000" then
-- s <= s_done;
-- else
-- counter := counter - "001";
-- end if;
-- when s_done =>
-- rx_done <= '1';
-- --led <= rx_data;
-- s <= s_wait;
-- end case;
-- end if;
-- end if;
-- end process;
-- proc_tx: process(reset, ps2c_i)
-- variable counter: unsigned(3 downto 0);
-- begin
-- if reset = '1' then
-- idle <= '1';
-- s_tx <= s_wait;
-- state_send <= s_wait;
-- ps2d_out <= 'Z';
-- ps2c_out <= 'Z';
-- led <= (others => '0');
-- elsif rising_edge(ps2c_i) then
-- web_output_write_o <= '0';
-- case s_tx is
-- when s_wait =>
-- idle <= '1';
-- if rx_done = '1' then
-- s_tx <= s_data;
-- tx_data <= rx_data;
-- counter := "0000";
-- idle <= '0';
-- ps2c_out <= '0';
-- state_send <= s_wait;
-- end if;
-- when s_data =>
-- if counter = "0001" then
-- ps2c_out <= 'Z';
-- ps2d_out <= '0';
-- elsif counter > "0001" and counter < "1010" then
-- ps2d_out <= tx_data(0);
-- tx_data <= '0' & tx_data(7 downto 1);
-- elsif counter = "1010" then
-- if ps2d_i = '0' then
-- web_output_data_o <= "00000001";
-- web_output_write_o <= '1';
-- end if;
-- s_tx <= s_done;
-- end if;
-- counter := counter + 1;
-- when s_done =>
-- ps2d_out <= 'Z';
-- ps2c_out <= 'Z';
-- s_tx <= s_wait;
-- end case;
-- end if;
-- end process;
end Behavioral; |
-- VHDL Entity R6502_TC.R6502_TC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity R6502_TC is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end R6502_TC ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Top Level
-- Path: R6502_TC/R6502_TC/struct
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library R6502_TC;
architecture struct of R6502_TC is
-- Architecture declarations
-- Internal signal declarations
-- Component Declarations
component Core
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : Core use entity R6502_TC.Core;
-- pragma synthesis_on
begin
-- Instance port mappings.
U_0 : Core
port map (
clk_clk_i => clk_clk_i,
d_i => d_i,
irq_n_i => irq_n_i,
nmi_n_i => nmi_n_i,
rdy_i => rdy_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
d_o => d_o,
rd_o => rd_o,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
end struct;
|
-- VHDL Entity R6502_TC.R6502_TC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity R6502_TC is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end R6502_TC ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Top Level
-- Path: R6502_TC/R6502_TC/struct
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library R6502_TC;
architecture struct of R6502_TC is
-- Architecture declarations
-- Internal signal declarations
-- Component Declarations
component Core
port (
clk_clk_i : in std_logic ;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic ;
nmi_n_i : in std_logic ;
rdy_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : Core use entity R6502_TC.Core;
-- pragma synthesis_on
begin
-- Instance port mappings.
U_0 : Core
port map (
clk_clk_i => clk_clk_i,
d_i => d_i,
irq_n_i => irq_n_i,
nmi_n_i => nmi_n_i,
rdy_i => rdy_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
d_o => d_o,
rd_o => rd_o,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
end struct;
|
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ng==
`protect end_protected
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.numeric_pkg.all;
entity decoder is
generic (
output_bits : natural := 2
);
port (
datain : in std_ulogic_vector(bitsize(output_bits-1)-1 downto 0);
dataout : out std_ulogic_vector(output_bits-1 downto 0)
);
end;
|
package util is
function log2(x : in integer) return integer;
end package;
package body util is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.util.all;
entity memory is
generic (
WIDTH : integer;
DEPTH : integer );
port (
clk : in bit;
addr : in bit_vector(log2(DEPTH) - 1 downto 0);
din : in bit_vector(WIDTH - 1 downto 0);
dout : out bit_vector(WIDTH - 1 downto 0);
we : in bit );
end entity;
architecture rtl of memory is
type ram_t is array (0 to DEPTH - 1) of bit_vector(WIDTH - 1 downto 0);
signal addr_r : bit_vector(log2(DEPTH) - 1 downto 0); -- Should be folded
signal ram : ram_t;
begin
end architecture;
-------------------------------------------------------------------------------
use work.util.all;
entity bigram is
end entity;
architecture test of bigram is
constant ITERS : integer := 100;
constant WIDTH : integer := 1024;
constant DEPTH : integer := 1024;
signal clk : bit := '0';
signal addr : bit_vector(log2(DEPTH) - 1 downto 0); -- Should be folded
signal din : bit_vector(WIDTH - 1 downto 0);
signal dout : bit_vector(WIDTH - 1 downto 0);
signal we : bit := '1';
signal running : boolean := true;
begin
clk <= not clk after 5 ns when running else '0';
uut: entity work.memory
generic map (
WIDTH => WIDTH,
DEPTH => DEPTH )
port map (
clk => clk,
addr => addr,
din => din,
dout => dout,
we => we );
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2285.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02285ent IS
END c07s02b06x00p14n01i02285ent;
ARCHITECTURE c07s02b06x00p14n01i02285arch OF c07s02b06x00p14n01i02285ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
constant a : phys := 2 p3;
constant b : phys := 10 p2;
constant d : integer := a / b;
BEGIN
assert NOT(d = 1)
report "***PASSED TEST: c07s02b06x00p14n01i02285"
severity NOTE;
assert (d = 1)
report "***FAILED TEST: c07s02b06x00p14n01i02285 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02285arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2285.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02285ent IS
END c07s02b06x00p14n01i02285ent;
ARCHITECTURE c07s02b06x00p14n01i02285arch OF c07s02b06x00p14n01i02285ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
constant a : phys := 2 p3;
constant b : phys := 10 p2;
constant d : integer := a / b;
BEGIN
assert NOT(d = 1)
report "***PASSED TEST: c07s02b06x00p14n01i02285"
severity NOTE;
assert (d = 1)
report "***FAILED TEST: c07s02b06x00p14n01i02285 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02285arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2285.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02285ent IS
END c07s02b06x00p14n01i02285ent;
ARCHITECTURE c07s02b06x00p14n01i02285arch OF c07s02b06x00p14n01i02285ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
constant a : phys := 2 p3;
constant b : phys := 10 p2;
constant d : integer := a / b;
BEGIN
assert NOT(d = 1)
report "***PASSED TEST: c07s02b06x00p14n01i02285"
severity NOTE;
assert (d = 1)
report "***FAILED TEST: c07s02b06x00p14n01i02285 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02285arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomonDecoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0: in std_logic_vector(2 downto 0);
Dsyn1: out std_logic_vector(2 downto 0);
Dsyn2: out std_logic_vector(2 downto 0));
end ReedSolomonDecoder;
architecture Behavioral of ReedSolomonDecoder is
component flipflop is
Port ( D: in std_logic_vector(2 downto 0);
Clock : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector(2 downto 0));
end component;
component AdderXor is
Port ( a: in std_logic_vector(2 downto 0);
b: in std_logic_vector(2 downto 0);
c: out std_logic_vector(2 downto 0)) ;
end component;
component Mult is
port(uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0));
end component;
signal alpha3 : std_logic_vector(2 downto 0);
signal alpha4 : std_logic_vector(2 downto 0);
signal D1 : std_logic_vector(2 downto 0);
signal D2 : std_logic_vector(2 downto 0);
signal Q1 : std_logic_vector(2 downto 0);
signal Q2 : std_logic_vector(2 downto 0);
signal C0 : std_logic_vector(2 downto 0);
signal multa1 : std_logic_vector(2 downto 0);
signal multa2 : std_logic_vector(2 downto 0);
begin
alpha3(0) <= '0'; alpha3(1) <= '1'; alpha3(2) <= '1';
alpha4(0) <= '1'; alpha4(1) <= '1'; alpha4(2) <= '0';
add1 : AdderXor port map (multa1, Qs0, C0);
D1 <= C0;
ff1 : flipflop port map (D1,Clock,Count7,Q1);
add2 : AdderXor port map(Q1, multa2, D2);
ff2 : flipflop port map (D2,Clock,Count7,Q2);
mult1 : Mult port map (Q2, alpha3, multa1);
mult2 : Mult port map (Q2, alpha4, multa2);
Dsyn1 <= D1;
Dsyn2 <= D2;
end Behavioral;
|
-------------------------------------------------------------------------------
--! @project Unrolled (2) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ascon_StateUpdate_control is
port(
Clk : in std_logic; -- Clock
Reset : in std_logic; -- Reset (synchronous)
-- Control signals
RoundNr : out std_logic_vector(2 downto 0); -- biggest round is 12
sel1,sel2,sel3,sel4 : out std_logic_vector(1 downto 0);
sel0 : out std_logic_vector(2 downto 0);
selout : out std_logic;
Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : out std_logic;
ActivateGen : out std_logic;
GenSize : out std_logic_vector(2 downto 0);
-- External control signals
Start : in std_logic;
Mode : in std_logic_vector(3 downto 0);
Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption
Busy : out std_logic
);
end entity Ascon_StateUpdate_control;
architecture structural of Ascon_StateUpdate_control is
begin
-----------------------------------------
------ The Finite state machine --------
-----------------------------------------
-- Modes: initialization, associative data, encryption, decryption, tag generation, final encryption, final decryption, seperation constant
-- 0010 0000 0110 0100 0001 0111 0101, 0011
-- case1 1000, case2 1001
fsm: process(Clk, Reset) is
type state_type is (IDLE,LOADNEW,CRYPT,TAG);
variable CurrState : state_type := IDLE;
variable RoundNrVar : std_logic_vector(2 downto 0);
begin
if Clk'event and Clk = '1' then
-- default values
sel0 <= "000";
sel1 <= "00";
sel2 <= "00";
sel3 <= "00";
sel4 <= "00";
selout <= '0';
Reg0En <= '0';
Reg1En <= '0';
Reg2En <= '0';
Reg3En <= '0';
Reg4En <= '0';
RegOutEn <= '0';
ActivateGen <= '0';
GenSize <= "000";
Busy <= '0';
if Reset = '1' then -- synchronous reset active high
-- registers used by fsm:
RoundNrVar := "000";
CurrState := IDLE;
else
FSMlogic : case CurrState is
when IDLE =>
if Start = '1' then
Busy <= '1';
if Mode = "0000" then -- AD mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Xor with DataIn)
sel0 <= "010";
Reg0En <= '1';
CurrState := CRYPT;
elsif Mode = "0100" then -- Decryption mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0110" then -- Encryption
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := CRYPT;
elsif Mode = "0001" then -- Tag mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (XOR middle with key)
sel1 <= "10";
sel2 <= "11";
Reg1En <= '1';
Reg2En <= '1';
CurrState := TAG;
elsif Mode = "0111" then -- Last block encryption
-- set Sel and Enables signal (Generate output and xor state)
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0101" then -- Last block decryption
-- set Sel and Enables signal (Generate output and xor state)
ActivateGen <= '1';
GenSize <= Size;
sel0 <= "010";
Reg0En <= '1';
RegOutEn <= '1';
CurrState := IDLE;
elsif Mode = "0011" then -- Seperation constant
sel4 <= "11";
Reg4En <= '1';
CurrState := IDLE;
elsif Mode = "0010" then -- Initialization mode
RoundNrVar := "111"; -- so starts at 0 next cycle
-- set Sel and Enables signal (Load in key and IV)
sel0 <= "001";
sel1 <= "01";
sel2 <= "01";
sel3 <= "01";
sel4 <= "01";
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
elsif Mode = "1000" then -- case1
sel0 <= "100";
Reg0En <= '1';
CurrState := IDLE;
else -- case2
sel0 <= "100";
Reg0En <= '1';
RoundNrVar := "111"; -- so starts at 0 next cycle
CurrState := CRYPT;
end if;
else
Busy <= '0';
CurrState := IDLE;
end if;
when LOADNEW =>
if RoundNrVar = "101" then -- RoundNrVar = 11
-- set Sel and Enables signal (Xor at the end)
sel3 <= "10";
sel4 <= "10";
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := LOADNEW;
Busy <= '1';
end if;
when CRYPT =>
if RoundNrVar = "001" then -- RoundNrVar = 4
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := CRYPT;
Busy <= '1';
end if;
when TAG =>
if RoundNrVar = "101" then -- RoundNrVar = 11
-- set Sel and Enables signal (connect tag to output)
selout <= '1';
RegOutEn <= '1';
CurrState := IDLE;
Busy <= '0';
else
RoundNrVar := std_logic_vector(unsigned(RoundNrVar) + 1);
-- set Sel and Enables signal (execute a round)
Reg0En <= '1';
Reg1En <= '1';
Reg2En <= '1';
Reg3En <= '1';
Reg4En <= '1';
CurrState := TAG;
Busy <= '1';
end if;
end case FSMlogic;
RoundNr <= RoundNrVar;
end if;
end if;
end process fsm;
end architecture structural;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.trfsmparts.all;
use work.tb_trfsmpkg.all;
use work.tbfuncs.all;
entity tb_transitionrow is
end tb_transitionrow;
architecture behavior of tb_transitionrow is
constant TotalInputWidth : integer := 10;
constant MyInputWidth : integer := 5;
constant StateWidth : integer := 5;
constant OutputWidth : integer := 7;
constant ConfigLength : integer := CalcTRConfigLength(StateWidth,TotalInputWidth,MyInputWidth,OutputWidth);
-- Attention: don't make symmetric values because otherwise we can't find
-- problems with the order
constant CfgOurState : std_logic_vector(StateWidth-1 downto 0) := "10111";
-- constant CfgInputSelect : std_logic_vector(TotalInputWidth-1 downto 0) := "1001110010";
-- constant CfgInputPattern : std_logic_vector(2**MyInputWidth-1 downto 0) := "00000010000010000000000000000000";
constant CfgNextState : std_logic_vector(StateWidth-1 downto 0) := "01011";
constant CfgOutput : std_logic_vector(OutputWidth-1 downto 0) := "1100110";
constant ConfigBitStream : std_logic_vector(ConfigLength-1 downto 0)
:= GenTRConfigBitStream(StateWidth,TotalInputWidth,MyInputWidth,OutputWidth,
"1xx001xx1x,1xx100xx1x",CfgOurState,CfgNextState,CfgOutput);
constant CfgClkHalfPeriode : time := 100 ns;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal Reset_n_i : std_logic;
signal Input_i : std_logic_vector(TotalInputWidth-1 downto 0);
signal State_i : std_logic_vector(StateWidth-1 downto 0);
signal Match_o : std_logic;
signal NextState_o : std_logic_vector(StateWidth-1 downto 0);
signal Output_o : std_logic_vector(OutputWidth-1 downto 0);
signal CfgMode_i : std_logic;
signal CfgClk_i : std_logic;
signal CfgShift_i : std_logic;
signal CfgDataIn_i : std_logic;
signal CfgDataOut_o : std_logic;
-- purpose: Set inputs and check outputs
procedure CheckTransitionRow (
constant Input : in std_logic_vector(TotalInputWidth-1 downto 0);
constant State : in std_logic_vector(StateWidth-1 downto 0);
constant Match : in std_logic;
constant NextState : in std_logic_vector(StateWidth-1 downto 0);
constant Output : in std_logic_vector(OutputWidth-1 downto 0);
signal Input_i : out std_logic_vector(TotalInputWidth-1 downto 0);
signal State_i : out std_logic_vector(StateWidth-1 downto 0);
signal Match_o : in std_logic;
signal NextState_o : in std_logic_vector(StateWidth-1 downto 0);
signal Output_o : in std_logic_vector(OutputWidth-1 downto 0)
) is
variable l : line;
begin -- CheckTransitionRow
Input_i <= Input;
State_i <= State;
write(l,string'("Input = "));
write(l,Input);
write(l,string'(", State = "));
write(l,State);
wait for CheckOutputDelay;
if CheckStdLogic (Match_o, Match, "Match") and
CheckStdLogicVector(NextState_o,NextState,"NextState") and
CheckStdLogicVector(Output_o, Output, "Output") then
write(l,string'(": OK!"));
end if;
writeline(std.textio.output,l);
wait for SetupNextInputDelay;
end CheckTransitionRow;
begin -- behavior
TransitionRow_1: TransitionRow
generic map (
TotalInputWidth => TotalInputWidth,
MyInputWidth => MyInputWidth,
StateWidth => StateWidth,
OutputWidth => OutputWidth)
port map (
Reset_n_i => Reset_n_i,
Input_i => Input_i,
State_i => State_i,
Match_o => Match_o,
NextState_o => NextState_o,
Output_o => Output_o,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
Check: process
begin -- process Check
Input_i <= (others => '0');
State_i <= (others => '0');
CfgMode_i <= '0';
CfgClk_i <= '0';
CfgShift_i <= '0';
CfgDataIn_i <= '0';
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
Reset_n_i <= '0';
wait for 1 us;
Reset_n_i <= '1';
wait for 1 ns;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- shift in the config bit stream with LSB first, the ConfigRegister will
-- shift this from right to left (=MSB to LSB), so after everything is
-- shifted, the bits have the same order as setup above and as visible at
-- the screen.
CfgMode_i <= '1';
CfgShift_i <= '1';
for i in 0 to ConfigLength-1 loop
CfgDataIn_i <= ConfigBitStream(i);
wait for SetupNextInputDelay;
CfgClk_i <= '1';
wait for CfgClkHalfPeriode;
CfgClk_i <= '0';
wait for CfgClkHalfPeriode-SetupNextInputDelay;
end loop; -- i
CfgMode_i <= '0';
CfgShift_i <= '0';
---------------------------------------------------------------------------
-- Action
---------------------------------------------------------------------------
-- CfgInputSelect = "1001110010" -> 1,4,5,6,9 are sensitive
-- CfgInputPattern = "00000010000010000000000000000000"; -> 19 = 10011, 25 = 11001
-- -> 1xx001xx1x, 1xx100xx1x
-- Test with wrong current states and wrong inputs
for i in 0 to 2**StateWidth-1 loop
if i /= conv_integer(CfgOurState) then
CheckTransitionRow("0000000000",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1111111111",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1000010011",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1101000010",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
end if;
end loop; -- i
-- Test matching state but wrong inputs
CheckTransitionRow("0000000000",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1111111111",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1000110010",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001100010",CfgOurState,'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
-- Test wrong current states but matching inputs
CheckTransitionRow("1000010010","00000",'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001000010","00000",'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
for i in 0 to 2**StateWidth-1 loop
if i /= conv_integer(CfgOurState) then
CheckTransitionRow("1000010010",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001000010",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1110011111",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1111001111",conv_std_logic_vector(i,StateWidth),'0',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
end if;
end loop; -- i
-- Test matching state and inputs
CheckTransitionRow("1000010010",CfgOurState,'1',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
CheckTransitionRow("1001000010",CfgOurState,'1',CfgNextState,CfgOutput,Input_i,State_i,Match_o,NextState_o,Output_o);
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert 0 = 1
report " simulation is finished "
severity failure ;
end process Check;
end behavior;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_1r1w is
begin
syncram : entity work.syncram_1r1w_inferred(rtl)
generic map (
addr_bits => addr_bits,
data_bits => data_bits,
write_first => write_first
)
port map (
clk => clk,
we => we,
waddr => waddr,
wdata => wdata,
re => re,
raddr => raddr,
rdata => rdata
);
end;
|
package pack1 is
type rec is record
x : integer;
y : integer;
z : integer;
end record;
constant r : rec;
end package;
package body pack1 is
constant r : rec := (1, 2, 3);
end package body;
-------------------------------------------------------------------------------
package pack2 is
function sum_fields return integer;
end package;
use work.pack1.all;
package body pack2 is
function sum_fields return integer is
begin
return r.x + r.y + r.z;
end function;
end package body;
|
----------------------------------------------------------------------------------
--
-- Author: Adam Howard - ahowar31@utk.edu, Ben Olson - molson5@utk.edu
-- ECE-351: Course Project - Greenhouse Monitor
-- Notes: Driver for reading data from the Ambient Light Sensor
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity als_driver is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
cs : out STD_LOGIC;
scl : out STD_LOGIC;
sda : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end als_driver;
architecture als_driver_arch of als_driver is
component clk_divider is
Port (
rst: in std_logic;
clk_in : in std_logic;
clk_out : out std_logic;
const : in INTEGER
);
end component clk_divider;
signal cs_sig, sclk : std_logic := '1';
signal w_counter : integer := 15;
signal data_buffer : std_logic_vector (15 downto 0) := "0000000000000000";
begin
scl <= sclk;
cs <= cs_sig;
data_out <= data_buffer(11 downto 4);
-- Divides clock down to 2MHz
CLK_DIV: clk_divider port map(
rst => rst,
clk_in => clk,
clk_out => sclk,
const => 24
);
SPI_READ: process(sclk, rst) is
begin
if (rst = '1') then
cs_sig <= '1';
data_buffer <= "0000000000000000";
w_counter <= 15;
elsif rising_edge(sclk) then
if w_counter = 15 then
cs_sig <= '0';
w_counter <= w_counter - 1;
elsif w_counter > 0 then
data_buffer(w_counter) <= sda;
w_counter <= w_counter - 1;
else
data_buffer(w_counter) <= sda;
cs_sig <= '1';
w_counter <= 15;
end if;
end if;
end process SPI_READ;
end als_driver_arch;
|
--------------------------------------------------------------------------------
--
-- File: Synchronizer.vhd
-- Author: Rob Baummer
--
-- Description: Synchronizes I to clock using 2 flip flops
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nbit_synchronizer is
generic (
N : integer);
port (
clk : in std_logic;
reset : in std_logic;
I : in std_logic_vector(N-1 downto 0);
O : out std_logic_vector(N-1 downto 0)
);
end nbit_synchronizer;
architecture behavioral of nbit_synchronizer is
signal dff1 : std_logic_vector(N-1 downto 0);
signal dff2 : std_logic_vector(N-1 downto 0);
begin
--Dual synchronization registers
process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
dff1 <= (others => '0');
dff2 <= (others => '0');
else
dff1 <= I;
dff2 <= dff1;
end if;
end if;
end process;
--Synchronized output
O <= dff2;
end behavioral;
|
library verilog;
use verilog.vl_types.all;
entity Roll_Sum_vlg_check_tst is
port(
hex0 : in vl_logic_vector(2 downto 0);
hex1 : in vl_logic_vector(2 downto 0);
Sum : in vl_logic_vector(3 downto 0);
sampler_rx : in vl_logic
);
end Roll_Sum_vlg_check_tst;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
end block;
BLOCK_LABEL : block is
begin
end block;
end architecture RTL;
|
-- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_std_logic_vector_delay is
generic
(
WIDTH : integer := 1;
DELAY : integer := 0
);
port
(
-- clock, enable and reset
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
-- input and output
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
end entity;
architecture rtl of alt_vipvfr131_common_std_logic_vector_delay is
begin
-- check generics
assert WIDTH > 0
report "Generic WIDTH must be greater than zero"
severity ERROR;
assert DELAY >= 0
report "Generic DELAY must greater than or equal to zero"
severity ERROR;
-- if zero delay is requested, just combinationally pass through
no_delay_gen :
if DELAY = 0 generate
begin
q <= data;
end generate;
-- if one or more cycles of delay have been requested, build a simple
-- shift register and do the delaying
some_delay_gen :
if DELAY > 0 generate
-- shift register, to do the required delaying
type shift_register_type is array(integer range <>) of std_logic_vector(WIDTH - 1 downto 0);
signal shift_register : shift_register_type(DELAY - 1 downto 0);
begin
-- clocked process to update shift register
shift_reg : process (clock, reset)
begin
if reset = '1' then
shift_register <= (others => (others => '0'));
elsif clock'EVENT and clock = '1' then
if ena = '1' then
for i in 0 to DELAY - 2 loop
shift_register(i) <= shift_register(i + 1);
end loop;
shift_register(DELAY - 1) <= data;
end if;
end if;
end process;
-- assign output from end of shift register
q <= shift_register(0);
end generate;
end ;
|
-- Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.alt_vipvfr131_common_package.all;
entity alt_vipvfr131_common_std_logic_vector_delay is
generic
(
WIDTH : integer := 1;
DELAY : integer := 0
);
port
(
-- clock, enable and reset
clock : in std_logic;
reset : in std_logic;
ena : in std_logic := '1';
-- input and output
data : in std_logic_vector(WIDTH - 1 downto 0);
q : out std_logic_vector(WIDTH - 1 downto 0)
);
end entity;
architecture rtl of alt_vipvfr131_common_std_logic_vector_delay is
begin
-- check generics
assert WIDTH > 0
report "Generic WIDTH must be greater than zero"
severity ERROR;
assert DELAY >= 0
report "Generic DELAY must greater than or equal to zero"
severity ERROR;
-- if zero delay is requested, just combinationally pass through
no_delay_gen :
if DELAY = 0 generate
begin
q <= data;
end generate;
-- if one or more cycles of delay have been requested, build a simple
-- shift register and do the delaying
some_delay_gen :
if DELAY > 0 generate
-- shift register, to do the required delaying
type shift_register_type is array(integer range <>) of std_logic_vector(WIDTH - 1 downto 0);
signal shift_register : shift_register_type(DELAY - 1 downto 0);
begin
-- clocked process to update shift register
shift_reg : process (clock, reset)
begin
if reset = '1' then
shift_register <= (others => (others => '0'));
elsif clock'EVENT and clock = '1' then
if ena = '1' then
for i in 0 to DELAY - 2 loop
shift_register(i) <= shift_register(i + 1);
end loop;
shift_register(DELAY - 1) <= data;
end if;
end if;
end process;
-- assign output from end of shift register
q <= shift_register(0);
end generate;
end ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1549.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01549ent IS
END c08s09b00x00p10n01i01549ent;
ARCHITECTURE c08s09b00x00p10n01i01549arch OF c08s09b00x00p10n01i01549ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
-- local variables
variable EXECUTED_ONCE : BOOLEAN;
variable COUNT : INTEGER;
variable k : integer := 0;
BEGIN
-- 1. These for-loops should only execute one time.
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH to INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in first loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW to INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in second loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH downto INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in third loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW downto INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fourth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH to COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fifth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW to COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in sixth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH downto COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in seventh loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW downto COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in eighth loop.";
EXECUTED_ONCE := TRUE;
end loop;
-- 2. These for-loops should be executed COUNT number of times.
COUNT := 0;
for I in 3 to 13 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 9th loop.";
COUNT := 0;
for I in 13 downto 3 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 10th loop.";
COUNT := 0;
for I in COLORS'LOW to COLORS'HIGH loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 11th loop.";
COUNT := 0;
for I in COLORS'HIGH downto COLORS'LOW loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 12th loop.";
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01549"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01549 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01549arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1549.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01549ent IS
END c08s09b00x00p10n01i01549ent;
ARCHITECTURE c08s09b00x00p10n01i01549arch OF c08s09b00x00p10n01i01549ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
-- local variables
variable EXECUTED_ONCE : BOOLEAN;
variable COUNT : INTEGER;
variable k : integer := 0;
BEGIN
-- 1. These for-loops should only execute one time.
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH to INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in first loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW to INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in second loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH downto INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in third loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW downto INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fourth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH to COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fifth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW to COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in sixth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH downto COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in seventh loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW downto COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in eighth loop.";
EXECUTED_ONCE := TRUE;
end loop;
-- 2. These for-loops should be executed COUNT number of times.
COUNT := 0;
for I in 3 to 13 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 9th loop.";
COUNT := 0;
for I in 13 downto 3 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 10th loop.";
COUNT := 0;
for I in COLORS'LOW to COLORS'HIGH loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 11th loop.";
COUNT := 0;
for I in COLORS'HIGH downto COLORS'LOW loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 12th loop.";
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01549"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01549 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01549arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1549.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01549ent IS
END c08s09b00x00p10n01i01549ent;
ARCHITECTURE c08s09b00x00p10n01i01549arch OF c08s09b00x00p10n01i01549ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type COLORS is (RED, GREEN, BLUE);
-- local variables
variable EXECUTED_ONCE : BOOLEAN;
variable COUNT : INTEGER;
variable k : integer := 0;
BEGIN
-- 1. These for-loops should only execute one time.
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH to INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in first loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW to INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in second loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'HIGH downto INTEGER'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in third loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in INTEGER'LOW downto INTEGER'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fourth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH to COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in fifth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW to COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in sixth loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'HIGH downto COLORS'HIGH loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in seventh loop.";
EXECUTED_ONCE := TRUE;
end loop;
EXECUTED_ONCE := FALSE;
for I in COLORS'LOW downto COLORS'LOW loop
if (EXECUTED_ONCE) then
k := 1;
end if;
assert (not( EXECUTED_ONCE ))
report "Failing in eighth loop.";
EXECUTED_ONCE := TRUE;
end loop;
-- 2. These for-loops should be executed COUNT number of times.
COUNT := 0;
for I in 3 to 13 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 9th loop.";
COUNT := 0;
for I in 13 downto 3 loop
COUNT := COUNT + 1;
end loop;
if (count /= 11) then
k := 1;
end if;
assert (COUNT = 11)
report "Failing in 10th loop.";
COUNT := 0;
for I in COLORS'LOW to COLORS'HIGH loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 11th loop.";
COUNT := 0;
for I in COLORS'HIGH downto COLORS'LOW loop
COUNT := COUNT + 1;
end loop;
if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
k := 1;
end if;
assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
report "Failing in 12th loop.";
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p10n01i01549"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p10n01i01549 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01549arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
library IEEE;
use ieee.std_logic_1164.all;
entity one_to_thirty_two_demux is
port(
input : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(4 downto 0);
a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u ,v, w, x, y, z, out27, out28, out29, out30, out31, out32 : out std_logic_vector(31 downto 0);
ce0, ce1, ce2, ce3, ce4, ce5, ce6, ce7, ce8, ce9, ce10, ce11, ce12, ce13, ce14, ce15, ce16, ce17, ce18, ce19, ce20, ce21, ce22, ce23, ce24, ce25, ce26, ce27, ce28, ce29, ce30, ce31 : out std_logic
);
end one_to_thirty_two_demux;
architecture behav of one_to_thirty_two_demux is
begin
a <= input when sel="00000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
b <= input when sel="00001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
c <= input when sel="00010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
d <= input when sel="00011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
e <= input when sel="00100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
f <= input when sel="00101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
g <= input when sel="00110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
h <= input when sel="00111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
i <= input when sel="01000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
j <= input when sel="01001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
k <= input when sel="01010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
l <= input when sel="01011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
m <= input when sel="01100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
n <= input when sel="01101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
o <= input when sel="01110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
p <= input when sel="01111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
q <= input when sel="10000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
r <= input when sel="10001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
s <= input when sel="10010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
t <= input when sel="10011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
u <= input when sel="10100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
v <= input when sel="10101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
w <= input when sel="10110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
x <= input when sel="10111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
y <= input when sel="11000" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
z <= input when sel="11001" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out27 <= input when sel="11010" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out28 <= input when sel="11011" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out29 <= input when sel="11100" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out30 <= input when sel="11101" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out31 <= input when sel="11110" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
out32 <= input when sel="11111" else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
ce0 <= '1' when sel="00000" else '0';
ce1 <= '1' when sel="00001" else '0';
ce2 <= '1' when sel="00010" else '0';
ce3 <= '1' when sel="00011" else '0';
ce4 <= '1' when sel="00100" else '0';
ce5 <= '1' when sel="00101" else '0';
ce6 <= '1' when sel="00110" else '0';
ce7 <= '1' when sel="00111" else '0';
ce8 <= '1' when sel="01000" else '0';
ce9 <= '1' when sel="01001" else '0';
ce10 <= '1' when sel="01010" else '0';
ce11 <= '1' when sel="01011" else '0';
ce12 <= '1' when sel="01100" else '0';
ce13 <= '1' when sel="01101" else '0';
ce14 <= '1' when sel="01110" else '0';
ce15 <= '1' when sel="01111" else '0';
ce16 <= '1' when sel="10000" else '0';
ce17 <= '1' when sel="10001" else '0';
ce18 <= '1' when sel="10010" else '0';
ce19 <= '1' when sel="10011" else '0';
ce20 <= '1' when sel="10100" else '0';
ce21 <= '1' when sel="10101" else '0';
ce22 <= '1' when sel="10110" else '0';
ce23 <= '1' when sel="10111" else '0';
ce24 <= '1' when sel="11000" else '0';
ce25 <= '1' when sel="11001" else '0';
ce26 <= '1' when sel="11010" else '0';
ce27 <= '1' when sel="11011" else '0';
ce28 <= '1' when sel="11100" else '0';
ce29 <= '1' when sel="11101" else '0';
ce30 <= '1' when sel="11110" else '0';
ce31 <= '1' when sel="11111" else '0';
end behav; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all;
entity sink is
generic ( name : string;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_type;
info_detail : in info_detail_type );
end sink;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all;
entity sink is
generic ( name : string;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_type;
info_detail : in info_detail_type );
end sink;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all;
entity sink is
generic ( name : string;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_type;
info_detail : in info_detail_type );
end sink;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1387.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01387ent IS
END c08s05b00x00p04n01i01387ent;
ARCHITECTURE c08s05b00x00p04n01i01387arch OF c08s05b00x00p04n01i01387ent IS
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 3) := ('0','0','0','0');
BEGIN
NUM1 := ('0', '0', '1', '1');
assert NOT( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' )
report "***PASSED TEST: c08s05b00x00p04n01i01387"
severity NOTE;
assert ( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' )
report "***FAILED TEST: c08s05b00x00p04n01i01387 - Assigning to an aggregate variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01387arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1387.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01387ent IS
END c08s05b00x00p04n01i01387ent;
ARCHITECTURE c08s05b00x00p04n01i01387arch OF c08s05b00x00p04n01i01387ent IS
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 3) := ('0','0','0','0');
BEGIN
NUM1 := ('0', '0', '1', '1');
assert NOT( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' )
report "***PASSED TEST: c08s05b00x00p04n01i01387"
severity NOTE;
assert ( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' )
report "***FAILED TEST: c08s05b00x00p04n01i01387 - Assigning to an aggregate variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01387arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1387.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01387ent IS
END c08s05b00x00p04n01i01387ent;
ARCHITECTURE c08s05b00x00p04n01i01387arch OF c08s05b00x00p04n01i01387ent IS
BEGIN
TESTING: PROCESS
variable NUM1 : BIT_VECTOR(0 to 3) := ('0','0','0','0');
BEGIN
NUM1 := ('0', '0', '1', '1');
assert NOT( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' )
report "***PASSED TEST: c08s05b00x00p04n01i01387"
severity NOTE;
assert ( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' )
report "***FAILED TEST: c08s05b00x00p04n01i01387 - Assigning to an aggregate variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01387arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2467.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02467ent IS
END c07s03b02x02p03n02i02467ent;
ARCHITECTURE c07s03b02x02p03n02i02467arch OF c07s03b02x02p03n02i02467ent IS
type UN_ARR is array (integer range <>) of character;
subtype CON_ARR is UN_ARR( 1 to 5 );
attribute LOCN : CON_ARR ;
signal S : Integer ;
attribute LOCN of S : signal is ('A', others => 'Z'); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
report "***PASSED TEST: c07s03b02x02p03n02i02467"
severity NOTE;
assert ( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
report "***FAILED TEST: c07s03b02x02p03n02i02467 - An array aggregate with an others choice may appear as the expression defining the value of an attribute in an attribute specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02467arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2467.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02467ent IS
END c07s03b02x02p03n02i02467ent;
ARCHITECTURE c07s03b02x02p03n02i02467arch OF c07s03b02x02p03n02i02467ent IS
type UN_ARR is array (integer range <>) of character;
subtype CON_ARR is UN_ARR( 1 to 5 );
attribute LOCN : CON_ARR ;
signal S : Integer ;
attribute LOCN of S : signal is ('A', others => 'Z'); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
report "***PASSED TEST: c07s03b02x02p03n02i02467"
severity NOTE;
assert ( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
report "***FAILED TEST: c07s03b02x02p03n02i02467 - An array aggregate with an others choice may appear as the expression defining the value of an attribute in an attribute specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02467arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2467.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02467ent IS
END c07s03b02x02p03n02i02467ent;
ARCHITECTURE c07s03b02x02p03n02i02467arch OF c07s03b02x02p03n02i02467ent IS
type UN_ARR is array (integer range <>) of character;
subtype CON_ARR is UN_ARR( 1 to 5 );
attribute LOCN : CON_ARR ;
signal S : Integer ;
attribute LOCN of S : signal is ('A', others => 'Z'); -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
report "***PASSED TEST: c07s03b02x02p03n02i02467"
severity NOTE;
assert ( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
report "***FAILED TEST: c07s03b02x02p03n02i02467 - An array aggregate with an others choice may appear as the expression defining the value of an attribute in an attribute specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02467arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY RegisterFile_tb IS
END RegisterFile_tb;
ARCHITECTURE behavior OF RegisterFile_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegisterFile
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DtoWrite : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
crs1 : OUT std_logic_vector(31 downto 0);
crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(5 downto 0) := (others => '0');
signal rs2 : std_logic_vector(5 downto 0) := (others => '0');
signal rd : std_logic_vector(5 downto 0) := (others => '0');
signal DtoWrite : std_logic_vector(31 downto 0) := (others => '0');
signal crs1 : std_logic_vector(31 downto 0) := (others => '0');
signal crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegisterFile PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
DtoWrite => DtoWrite,
rst => rst,
crs1 => crs1,
crs2 => crs2
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rs1 <= "000000";
rs2 <="000000";
rd <="000001";
dToWrite <= "00000000000000000000000000000001";
wait for 15 ns;
rd <="000010";
dToWrite <= "00000000000000000000000000000010";
wait for 15 ns;
rd <="000011";
dToWrite <= "00000000000000000000000000000011";
wait for 15 ns;
rst <= '1';
-- rd <="00100";
-- dToWrite <= "00000000000000000000000000000100";
--
-- wait for 15 ns;
-- rd <="00101";
-- dToWrite <= "00000000000000000000000000000101";
wait for 15 ns;
rd <= "000000";
wait for 15 ns;
rs1 <= "000000";
rs2 <= "000001";
wait for 15 ns;
rs1 <= "000001";
rs2 <= "000010";
wait for 15 ns;
rs1 <= "000010";
rs2 <= "000011";
wait for 15 ns;
rs1 <= "000011";
rs2 <= "000100";
wait for 15 ns;
rs1 <= "000100";
rs2 <= "000101";
wait for 15 ns;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity sdram_ctrl is
generic (
HIGH_BIT: integer := 24
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
dbg: out memory_debug_type;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24;
MHZ: integer := 96;
REFRESH_CYCLES: integer := 4096;
ADDRESS_BITS: integer := 13
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0);
tag_in : in std_logic_vector(31 downto 0);
tag_out : out std_logic_vector(31 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (HIGH_BIT downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_tag : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => HIGH_BIT,
ADDRESS_BITS => 12
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask,
tag_in => wb_tag_i,
tag_out => sdr_tag
);
sdr_address(HIGH_BIT downto 2) <= wb_adr_i(HIGH_BIT downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
resync: if true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
else
wb_ack_o <= sdr_data_out_valid;
end if;
wb_dat_o <= sdr_data_out;
wb_tag_o <= sdr_tag;
end if;
end process;
end generate;
noresync: if false generate
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
wb_tag_o <= sdr_tag;
end generate;
dbg.strobe <= ( not pending ) and wb_stb_i and wb_cyc_i;
dbg.write <= wb_we_i;
dbg.address <= unsigned(wb_adr_i);
dbg.data <= unsigned(wb_dat_i);
dbg.pc <= x"deadbeef";
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1642.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p06n01i01642pkg is
procedure procI;
function funcI return INTEGER;
end c08s12b00x00p06n01i01642pkg;
package body c08s12b00x00p06n01i01642pkg is
procedure procI is
begin
-- Return.
return;
-- Statement should NEVER be executed.
assert (FALSE)
report "Statement in procedure was executed in error.";
end procI;
function funcI return INTEGER is
begin
-- Return from the function.
return( 4 );
-- Statement should NEVER be executed.
assert (FALSE)
report "Statement in function was executed in error.";
end funcI;
end c08s12b00x00p06n01i01642pkg;
use work.c08s12b00x00p06n01i01642pkg.all;
ENTITY c08s12b00x00p06n01i01642ent IS
END c08s12b00x00p06n01i01642ent;
ARCHITECTURE c08s12b00x00p06n01i01642arch OF c08s12b00x00p06n01i01642ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Execute the procedure.
procI;
-- Execute the function.
assert NOT(funcI = 4)
report "***PASSED TEST: c08s12b00x00p06n01i01642"
severity NOTE;
assert (funcI = 4)
report "***FAILED TEST: c08s12b00x00p06n01i01642 - The execution of the return statement completes if the type of the expression is of teh result subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01642arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1642.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p06n01i01642pkg is
procedure procI;
function funcI return INTEGER;
end c08s12b00x00p06n01i01642pkg;
package body c08s12b00x00p06n01i01642pkg is
procedure procI is
begin
-- Return.
return;
-- Statement should NEVER be executed.
assert (FALSE)
report "Statement in procedure was executed in error.";
end procI;
function funcI return INTEGER is
begin
-- Return from the function.
return( 4 );
-- Statement should NEVER be executed.
assert (FALSE)
report "Statement in function was executed in error.";
end funcI;
end c08s12b00x00p06n01i01642pkg;
use work.c08s12b00x00p06n01i01642pkg.all;
ENTITY c08s12b00x00p06n01i01642ent IS
END c08s12b00x00p06n01i01642ent;
ARCHITECTURE c08s12b00x00p06n01i01642arch OF c08s12b00x00p06n01i01642ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Execute the procedure.
procI;
-- Execute the function.
assert NOT(funcI = 4)
report "***PASSED TEST: c08s12b00x00p06n01i01642"
severity NOTE;
assert (funcI = 4)
report "***FAILED TEST: c08s12b00x00p06n01i01642 - The execution of the return statement completes if the type of the expression is of teh result subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01642arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1642.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p06n01i01642pkg is
procedure procI;
function funcI return INTEGER;
end c08s12b00x00p06n01i01642pkg;
package body c08s12b00x00p06n01i01642pkg is
procedure procI is
begin
-- Return.
return;
-- Statement should NEVER be executed.
assert (FALSE)
report "Statement in procedure was executed in error.";
end procI;
function funcI return INTEGER is
begin
-- Return from the function.
return( 4 );
-- Statement should NEVER be executed.
assert (FALSE)
report "Statement in function was executed in error.";
end funcI;
end c08s12b00x00p06n01i01642pkg;
use work.c08s12b00x00p06n01i01642pkg.all;
ENTITY c08s12b00x00p06n01i01642ent IS
END c08s12b00x00p06n01i01642ent;
ARCHITECTURE c08s12b00x00p06n01i01642arch OF c08s12b00x00p06n01i01642ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Execute the procedure.
procI;
-- Execute the function.
assert NOT(funcI = 4)
report "***PASSED TEST: c08s12b00x00p06n01i01642"
severity NOTE;
assert (funcI = 4)
report "***FAILED TEST: c08s12b00x00p06n01i01642 - The execution of the return statement completes if the type of the expression is of teh result subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p06n01i01642arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2148.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02148ent IS
END c07s02b04x00p21n01i02148ent;
ARCHITECTURE c07s02b04x00p21n01i02148arch OF c07s02b04x00p21n01i02148ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_1 is time_v (1 to 1);
SUBTYPE time_null is time_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : time_1;
variable l_operand : time_null;
variable r_operand : time := 78 ns ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1) = 78 ns)
report "***PASSED TEST: c07s02b04x00p21n01i02148"
severity NOTE;
assert (result(1) = 78 ns)
report "***FAILED TEST: c07s02b04x00p21n01i02148 - Concatenation of null and TIME element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02148arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2148.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02148ent IS
END c07s02b04x00p21n01i02148ent;
ARCHITECTURE c07s02b04x00p21n01i02148arch OF c07s02b04x00p21n01i02148ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_1 is time_v (1 to 1);
SUBTYPE time_null is time_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : time_1;
variable l_operand : time_null;
variable r_operand : time := 78 ns ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1) = 78 ns)
report "***PASSED TEST: c07s02b04x00p21n01i02148"
severity NOTE;
assert (result(1) = 78 ns)
report "***FAILED TEST: c07s02b04x00p21n01i02148 - Concatenation of null and TIME element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02148arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2148.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02148ent IS
END c07s02b04x00p21n01i02148ent;
ARCHITECTURE c07s02b04x00p21n01i02148arch OF c07s02b04x00p21n01i02148ent IS
TYPE time_v is array (integer range <>) of time;
SUBTYPE time_1 is time_v (1 to 1);
SUBTYPE time_null is time_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : time_1;
variable l_operand : time_null;
variable r_operand : time := 78 ns ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1) = 78 ns)
report "***PASSED TEST: c07s02b04x00p21n01i02148"
severity NOTE;
assert (result(1) = 78 ns)
report "***FAILED TEST: c07s02b04x00p21n01i02148 - Concatenation of null and TIME element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02148arch;
|
-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Table driven, cycle exact 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture fast of cpu65xx is
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInE : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- E = Accu | 0xEE (for ANE, LXA)
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInE : unsigned(0 to 7) := "01000000";
constant aluInEXT : unsigned(0 to 7) := "01100100";
constant aluInET : unsigned(0 to 7) := "01000100";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInXH : unsigned(0 to 7) := "00100010";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInYH : unsigned(0 to 7) := "00010010";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInAX : unsigned(0 to 7) := "10100000";
constant aluInAXH : unsigned(0 to 7) := "10100010";
constant aluInAT : unsigned(0 to 7) := "10000100";
constant aluInXT : unsigned(0 to 7) := "00100100";
constant aluInST : unsigned(0 to 7) := "00001100";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
-- 1100
-- 1101
-- 1110
constant aluModeAnc : aluMode1 := "1111";
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeArr : aluMode2 := "111";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---";
constant aluSre : aluMode := aluModeLsr & aluModeEor & "---";
constant aluRra : aluMode := aluModeRor & aluModeAdc & "---";
constant aluRla : aluMode := aluModeRol & aluModeAnd & "---";
constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100";
constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---";
constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---";
constant aluArr : aluMode := aluModeRor & aluModeArr & "---";
constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x)
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM ***
"1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu
"1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM ***
"1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied
"1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM ***
"1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x)
"0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
"0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x)
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM ***
"0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
"0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y
"0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x)
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM ***
"1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
"0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM ***
"0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied
"0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
"1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x)
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc)
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM ***
"1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y
"0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied
"1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y
"0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal C: std_logic; -- Carry
signal Z: std_logic; -- Zero flag
signal I: std_logic; -- Interrupt flag
signal D: std_logic; -- Decimal mode
signal V: std_logic; -- Overflow
signal N: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Pipeline registers
signal aluInputReg : unsigned(7 downto 0);
signal aluCmpInputReg : unsigned(7 downto 0);
signal aluRmwReg : unsigned(7 downto 0);
signal aluNineReg : unsigned(7 downto 0);
signal aluCReg : std_logic;
signal aluZReg : std_logic;
signal aluVReg : std_logic;
signal aluNReg : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInE) = '1' then
temp := temp and (A or X"EE");
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
if rising_edge(clk) then
aluInputReg <= temp;
end if;
aluInput <= temp;
if pipelineAluMux then
aluInput <= aluInputReg;
end if;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
if rising_edge(clk) then
aluCmpInputReg <= temp;
end if;
aluCmpInput <= temp;
if pipelineAluMux then
aluCmpInput <= aluCmpInputReg;
end if;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
varV := aluInput(6); -- Default for BIT / PLP / RTI
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp =>
rmwBits := C & aluInput;
when aluModeP =>
rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C;
when aluModeInc =>
rmwBits := C & (aluInput + 1);
when aluModeDec =>
rmwBits := C & (aluInput - 1);
when aluModeAsl =>
rmwBits := aluInput & "0";
when aluModeFlg =>
rmwBits := aluInput(0) & aluInput;
when aluModeLsr =>
rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol =>
rmwBits := aluInput & C;
when aluModeRoR =>
rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when aluModeAnc =>
rmwBits := (aluInput(7) and A(7)) & aluInput;
when others =>
rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc =>
lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp =>
ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd =>
ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor =>
ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra =>
ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when others =>
ninebits := rmwBits;
end case;
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others =>
null;
end case;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
varC := aluInput(7);
varV := aluInput(7) xor aluInput(6);
end if;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when aluModeArr =>
if D = '1' then
if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
end if;
if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
else
varC := '0';
end if;
end if;
when others =>
null;
end case;
if rising_edge(clk) then
aluRmwReg <= rmwBits(7 downto 0);
aluNineReg <= ninebits(7 downto 0);
aluCReg <= varC;
aluZReg <= varZ;
aluVReg <= varV;
aluNReg <= varN;
end if;
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
if pipelineAluOut then
aluRmwOut <= aluRmwReg;
aluRegisterOut <= aluNineReg;
aluC <= aluCReg;
aluZ <= aluZReg;
aluV <= aluVReg;
aluN <= aluNReg;
end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4
or reset = '1' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken
and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '1' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
process(clk)
begin
if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
end if;
end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '1') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
if pipelineOpcode then
opcInfo <= nextOpcInfoReg;
end if;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
debugOpcode <= theOpcode;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '1' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch =>
nextCpuCycle <= cycle2;
when cycle2 =>
if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then
-- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1'
and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1')
or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect =>
nextCpuCycle <= cycleIndirect;
when cycleIndirect =>
nextCpuCycle <= cycle3;
when cycleBranchTaken =>
if indexOut(8) /= T(7) then
-- Page boundary crossing during branch.
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead =>
if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
-- Page boundary crossing while indexed addressing.
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1'
or opcInfo(indexY) = '1' then
-- 6510 needs extra cycle for indexed addressing
-- combined with RMW indexing
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 =>
if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw =>
nextCpuCycle <= cycleWrite;
when cyclePreWrite =>
nextCpuCycle <= cycleWrite;
when cycleStack1 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 =>
nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0'
and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0'
or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 =>
nextCpuCycle <= cycleRead;
when cycleJump =>
if opcInfo(opcIncrAfter) = '1' then
-- Insert extra cycle
nextCpuCycle <= cycleEnd;
end if;
when others =>
null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 =>
T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
-- Read from stack
T <= di;
end if;
when cycleIndirect | cycleRead | cycleRead2 =>
T <= di;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
if enable = '1' then
if soReg = '1' and so_n = '0' then
V <= '1';
end if;
soReg <= so_n;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1')
or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 =>
updateFlag := true;
when cycleStack3 =>
updateFlag := true;
when cycleStack4 =>
updateFlag := true;
when cycleRead =>
if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite =>
if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others =>
null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
calcDo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= aluRmwOut;
if opcInfo(opcInH) = '1' then
-- For illegal opcodes SHA, SHX, SHY, SHS
doReg <= aluRmwOut and myAddrIncrH;
end if;
case nextCpuCycle is
when cycleStack2 =>
if opcInfo(opcIRQ) = '1'
and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 =>
doReg <= PC(7 downto 0);
when cycleRmw =>
-- do <= T; -- Read-modify-write write old value first.
doReg <= di; -- Read-modify-write write old value first.
when others => null;
end case;
end if;
end if;
end process;
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= '0';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0'
and ((opcInfo(opcStackAddr) = '0')
or (opcInfo(opcStackData) = '1')) then
theWe <= '1';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '1';
end if;
when cycleRmw =>
theWe <= '1';
when cycleWrite =>
theWe <= '1';
when others =>
null;
end case;
end if;
end if;
end process;
we <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch =>
PC <= myAddr;
when cycle2 =>
if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 =>
if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
debugPc <= PC;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 =>
if opcInfo(opcStackAddr) = '1'
or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 =>
if (opcInfo(opcIndirect) = '1')
and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect =>
nextAddr <= nextAddrZPIndexed;
when cycleIndirect =>
nextAddr <= nextAddrIncrL;
when cycleBranchTaken =>
nextAddr <= nextAddrRelative;
when cycleBranchPage =>
if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead =>
nextAddr <= nextAddrZPIndexed;
when cycleRead =>
nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 =>
nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw =>
nextAddr <= nextAddrHold;
when cyclePreWrite =>
nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite =>
nextAddr <= nextAddrPc;
when cycleStack1 =>
nextAddr <= nextAddrStack;
when cycleStack2 =>
nextAddr <= nextAddrStack;
when cycleStack3 =>
nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 =>
nextAddr <= nextAddrIrq;
when cycleJump =>
nextAddr <= nextAddrAbs;
when others =>
null;
end case;
if reset = '1' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr;
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddr <= PC;
when nextAddrIrq =>
myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset => myAddr <= X"FFFC";
when nextAddrAbs => myAddr <= di & T;
when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0);
when nextAddrZeroPage => myAddr <= "00000000" & di;
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddr <= "00000001" & S;
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
debugA <= A;
debugX <= X;
debugY <= Y;
debugS <= S;
end architecture;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
-- NEED RESULT: ARCH00524.B1: Selected name overcomes hiding by homograph passed
-- NEED RESULT: ARCH00524.B2: Selected name overcomes hiding by homograph passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00524
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (3)
-- 10.3 (5)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00524_1
-- PKG00524_2
-- E00000(ARCH00524)
-- ENT00524_Test_Bench(ARCH00524_Test_Bench)
--
-- REVISION HISTORY:
--
-- 14-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
package PKG00524_1 is
type A is range 1 to 5;
type B is range 1.0 to 10.0;
type C is (C1, C2, C3) ;
end PKG00524_1;
package PKG00524_2 is
subtype A is CHARACTER range '1' to '5';
constant C : A := '4';
end PKG00524_2;
use WORK.STANDARD_TYPES.all, WORK.PKG00524_1.all, WORK.PKG00524_2.all;
architecture ARCH00524 of E00000 is
begin
B1 :
block
constant F : boolean := true;
begin
process
variable B : integer := 5;
variable D : WORK.PKG00524_1.B := 2.3;
-- selected name overcomes hiding by homograph
constant Q : WORK.PKG00524_1.C := C2;
begin
test_report ( "ARCH00524.B1" ,
"Selected name overcomes hiding by homograph" ,
(B = 5) and
(D = 2.3) and
(Q = c2) ) ;
wait ;
end process;
B2 :
block
constant F : bit := '1';
constant G : boolean := B1.F;
-- selected name overcomes hiding by homograph
constant H : WORK.PKG00524_2.A := WORK.PKG00524_2.C;
-- selected name overcomes hiding by homograph
signal S : WORK.PKG00524_1.A := 3 ;
-- selected name overcomes hiding by homograph
begin
process
begin
test_report ( "ARCH00524.B2" ,
"Selected name overcomes hiding by homograph" ,
(F = '1') and G and
(H = '4') and
(S = 3) ) ;
wait ;
end process;
end block B2 ;
end block B1 ;
end ARCH00524 ;
entity ENT00524_Test_Bench is
end ENT00524_Test_Bench ;
architecture ARCH00524_Test_Bench of ENT00524_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00524 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00524_Test_Bench ;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
-- THz = 1000 GHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
-- TiB = 1024 GiB;
end units;
--
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- TODO
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function min(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function min(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function max(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function max(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function min(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function min(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function min(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function min(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function max(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function max(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function max(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function max(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
-- QUESTION: some sum functions are not meaningful -> orthogonal function/type system
function sum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function sum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function sum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function sum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : NATURAL) return TIME;
function ps2Time(t_ps : NATURAL) return TIME;
function ns2Time(t_ns : NATURAL) return TIME;
function us2Time(t_us : NATURAL) return TIME;
function ms2Time(t_ms : NATURAL) return TIME;
function sec2Time(t_sec : NATURAL) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
-- function THz2Time(f_THz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- function THz2Time(f_THz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
-- function THz2Freq(f_THz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- function THz2Freq(f_THz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
begin
if (a < 1 us) then
return real(a / MTRIS) / real(b / MTRIS);
elsif (a < 1 ms) then
return real(a / (1000 * MTRIS)) / real(b / MTRIS) * 1000.0;
elsif (a < 1 sec) then
return real(a / (1000000 * MTRIS)) / real(b / MTRIS) * 1000000.0;
else
return real(a / (1000000000 * MTRIS)) / real(b / MTRIS) * 1000000000.0;
end if;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
if (f < 1 kHz) then res := div(1 Hz, f) * 1 sec;
elsif (f < 1 MHz) then res := div(1 kHz, f) * 1 ms;
elsif (f < 1 GHz) then res := div(1 MHz, f) * 1 us;
-- elsif (f < 1 THz) then res := div(1 GHz, f) * 1 ns;
else res := div(1 GHz, f) * 1 ns;
-- else res := div(1 THz, f) * 1 ps;
end if;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
-- if (p < 1 ps) then res := div(1 fs, p) * 1 THz;
if (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
-- elsif (p < 1 ns) then res := div(1 ps, p) * 1 GHz;
elsif (p < 1 us) then res := div(1 ns, p) * 1 MHz;
elsif (p < 1 ms) then res := div(1 us, p) * 1 kHz;
elsif (p < 1 sec) then res := div(1 ms, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
if (br < 1 kBd) then res := div(br, 1 Bd) * 1 Hz;
elsif (br < 1 MBd) then res := div(br, 1 kBd) * 1 kHz;
elsif (br < 1 GBd) then res := div(br, 1 MBd) * 1 MHz;
else res := div(br, 1 GBd) * 1 GHz;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function min(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function min(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function min(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function min(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function max(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function max(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function max(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function max(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function min(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function min(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function min(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function min(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function max(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function max(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function max(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function max(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function sum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function sum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function sum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function sum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : NATURAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : NATURAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : NATURAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : NATURAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : NATURAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : NATURAL) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : NATURAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- function THz2Time(f_THz : REAL) return TIME is
-- begin
-- return 1 ps / f_THz;
-- end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : NATURAL) return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- function THz2Freq(f_THz : REAL )return FREQ is
-- begin
-- return f_THz * 1 THz;
-- end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
-- elsif (scale = 1 TiB) then return div(mem, 1 TiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (1.0 - div(res_time, Timing)) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
-- if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
-- report "TimingToCycles (timing deviation report): " & CR &
-- " timing to achieve: " & to_string(Timing) & CR &
-- " calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
-- " resulting timing: " & to_string(res_time) & CR &
-- " deviation: " & to_string(Timing - res_time) & " (" & str_format(res_dev, 2) & "%)"
-- severity note;
-- end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (t < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(t, 1 fs);
elsif (t < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(t, 1 ps);
elsif (t < 1 us) then
unit(1 to 2) := "ns";
value := to_real(t, 1 ns);
elsif (t < 1 ms) then
unit(1 to 2) := "us";
value := to_real(t, 1 us);
elsif (t < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(t, 1 ms);
else
unit := "sec";
value := to_real(t, 1 sec);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else --if (f < 1 THz) then
unit := "GHz";
value := to_real(f, 1 GHz);
-- else
-- unit := "THz";
-- value := to_real(f, 1 THz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else --if (mem < 1 TiB) then
unit := "GiB";
value := to_real(mem, 1 GiB);
-- else
-- unit := "TiB";
-- value := to_real(mem, 1 TiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
|
architecture RTL of FIFO is
signal sig1 : std_logic_vector(3 downto 0) ;
constant c_cons1 : integer := 200 ;
constant c_cons2 : integer := 200;
begin
end architecture RTL ;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XNORGATE IS
PORT(A,B:IN STD_LOGIC;
C:OUT STD_LOGIC);
END XNORGATE;
ARCHITECTURE XNORG OF XNORGATE IS
BEGIN
C <= A XNOR B;
END XNORG;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01945pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- ----------------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01945pkg.all;
ENTITY vests27 IS
END vests27;
ARCHITECTURE c07s02b01x00p01n02i01945arch OF vests27 IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
--
-- Test AND operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01945"
severity NOTE;
assert ( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01945arch;
|
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